Lines Matching refs:control_reg
126 u32 control_reg;
156 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
157 err = write_control_reg(chip, control_reg, true);
166 u32 control_reg, clock;
184 control_reg = le32_to_cpu(chip->comm_page->control_register);
185 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
200 if (control_reg & GML_SPDIF_PRO_MODE)
225 control_reg |= clock;
231 return write_control_reg(chip, control_reg, false);
238 u32 control_reg, clocks_from_dsp;
242 control_reg = le32_to_cpu(chip->comm_page->control_register) &
253 control_reg |= GML_SPDIF_CLOCK;
255 control_reg |= GML_DOUBLE_SPEED_MODE;
257 control_reg &= ~GML_DOUBLE_SPEED_MODE;
262 control_reg |= GML_ADAT_CLOCK;
263 control_reg &= ~GML_DOUBLE_SPEED_MODE;
266 control_reg |= GML_ESYNC_CLOCK;
267 control_reg &= ~GML_DOUBLE_SPEED_MODE;
270 control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
279 return write_control_reg(chip, control_reg, true);
286 u32 control_reg;
316 control_reg = le32_to_cpu(chip->comm_page->control_register);
317 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
322 control_reg |= GML_SPDIF_OPTICAL_MODE;
327 control_reg |= GML_SPDIF_CDROM_MODE;
333 control_reg |= GML_ADAT_MODE;
334 control_reg &= ~GML_DOUBLE_SPEED_MODE;
338 err = write_control_reg(chip, control_reg, true);