/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/ |
H A D | power.cpp | 33 write32(info, 0x6204, (1L << 29)); 36 write32(info, 0x42020, (1L << 28) | (1L << 7) | (1L << 5)); 39 write32(info, 0x42020, (1L << 28)); 42 write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28)); 45 write32(info, 0x42020, (1L << 7) | (1L << 5)); 48 write32(info, 0x6204, 0); 49 write32(info, 0x6208, (1L << 9) | (1L << 7) | (1L << 6)); 50 write32(info, 0x6210, 0); 57 write32(info, 0x6200, gateValue); 60 write32(inf [all...] |
H A D | intel_extreme.cpp | 97 write32(info, regIdentity, ~0); 98 write32(info, regEnabled, value); 99 write32(info, regMask, ~value); 106 write32(info, GEN11_GFX_MSTR_IRQ, enable ? GEN11_MASTER_IRQ : 0); 114 write32(info, PCH_MASTER_INT_CTL_BDW, enable ? PCH_MASTER_INT_CTL_GLOBAL_BDW : 0); 132 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW); 143 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW); 154 write32(info, regIdentity, identity | PCH_INTERRUPT_VBLANK_BDW); 164 write32(info, GEN8_DE_PORT_IIR, iir); 174 write32(inf [all...] |
H A D | driver.h | 71 write32(intel_info &info, uint32 encodedRegister, uint32 value) function
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/haiku/src/add-ons/accelerants/intel_extreme/ |
H A D | cursor.cpp | 23 write32(INTEL_CURSOR_CONTROL, 0); 48 write32(INTEL_CURSOR_PALETTE + 0, 0x00ffffff); 49 write32(INTEL_CURSOR_PALETTE + 4, 0); 53 write32(INTEL_CURSOR_CONTROL, 55 write32(INTEL_CURSOR_SIZE, height << 12 | width); 57 write32(INTEL_CURSOR_BASE, 98 write32(INTEL_CURSOR_POSITION, (y << 16) | x); 108 write32(INTEL_CURSOR_CONTROL, (isVisible ? CURSOR_ENABLED : 0) 110 write32(INTEL_CURSOR_BASE,
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H A D | FlexibleDisplayInterface.cpp | 64 write32(targetRegister, value | FDI_TX_ENABLE); 77 write32(targetRegister, value & ~FDI_TX_ENABLE); 107 write32(targetRegister, value); 110 write32(targetRegister, value | FDI_TX_PLL_ENABLED); 126 write32(targetRegister, read32(targetRegister) & ~FDI_TX_PLL_ENABLED); 154 write32(targetRegister, value | FDI_RX_ENABLE); 167 write32(targetRegister, value & ~FDI_RX_ENABLE); 202 write32(targetRegister, value); 205 write32(targetRegister, value | FDI_RX_PLL_ENABLED); 216 write32(targetRegiste [all...] |
H A D | dpms.cpp | 61 write32(controlRegister, control | PANEL_CONTROL_POWER_TARGET_ON 72 write32(controlRegister, (control & ~PANEL_CONTROL_POWER_TARGET_ON) 95 write32(INTEL_DISPLAY_A_PLL, pll); 98 write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED); 101 write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED); 109 write32(INTEL_DISPLAY_B_PLL, pll); 112 write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED); 115 write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED); 142 write32(INTEL_ANALOG_PORT, (read32(INTEL_ANALOG_PORT) 150 write32(INTEL_DIGITAL_PORT_ [all...] |
H A D | Pipes.cpp | 42 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 45 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 49 write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) 52 write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) 147 write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl); 154 write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); 168 write32(INTEL_TRANSCODER_A_HTOTAL + fPipeOffset, 171 write32(INTEL_TRANSCODER_A_HBLANK + fPipeOffset, 174 write32(INTEL_TRANSCODER_A_HSYNC + fPipeOffset, 178 write32(INTEL_TRANSCODER_A_VTOTA [all...] |
H A D | PanelFitter.cpp | 62 write32(fRegisterBase + PCH_PANEL_FITTER_CONTROL, fitCtl); 91 write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, (timing.h_display << 16) | timing.v_display); 101 write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, 0); 109 write32(targetRegister, (read32(targetRegister) & ~PANEL_FITTER_ENABLED)
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H A D | engine.cpp | 54 write32(fRingBuffer.register_base + RING_BUFFER_TAIL, fRingBuffer.position); 161 write32(ringBuffer.register_base + RING_BUFFER_CONTROL, 0); 181 write32(ring + RING_BUFFER_TAIL, 0); 182 write32(ring + RING_BUFFER_START, ringBuffer.offset); 183 write32(ring + RING_BUFFER_CONTROL,
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H A D | mode.cpp | 145 write32(INTEL_DISPLAY_A_OFFSET_HAS + offset, 150 write32(INTEL_DISPLAY_A_BASE + offset, 155 write32(INTEL_DISPLAY_A_SURFACE + offset, sharedInfo.frame_buffer_offset); 158 write32(INTEL_DISPLAY_A_BASE + offset, sharedInfo.frame_buffer_offset 475 write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED); 505 write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow >> 6); 506 write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow >> 6); 508 write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow); 509 write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow); 627 write32(intel_get_backlight_registe [all...] |
H A D | accelerant.h | 93 write32(uint32 encodedRegister, uint32 value) function
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H A D | Ports.cpp | 175 write32(portRegister, portState | PORT_TRANS_B_SEL_CPT); 178 write32(portRegister, portState | PORT_TRANS_C_SEL_CPT); 181 write32(portRegister, portState | PORT_TRANS_A_SEL_CPT); 187 write32(portRegister, portState & ~DISPLAY_MONITOR_PIPE_B); 189 write32(portRegister, portState | DISPLAY_MONITOR_PIPE_B); 409 write32(ioRegister, value); 604 write32(ICL_PWR_WELL_CTL_AUX2, value | HSW_PWR_WELL_CTL_REQ(0)); 903 write32(channelData[index], data); 905 write32(channelControl, sendControl); 913 write32(channelContro [all...] |
H A D | accelerant.cpp | 276 write32(INTEL_DSPCLK_GATE_D, 280 write32(INTEL_GEN9_CLKGATE_DIS_4, 284 write32(INTEL_GMBUS0, 0); //reset, idle 285 write32(INTEL_GMBUS4, 0); //block interrupts
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/haiku/src/add-ons/kernel/drivers/graphics/radeon_hd/ |
H A D | radeon_hd.cpp | 336 write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 338 write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control 341 write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control 344 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, 347 write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 382 write32(info.registers + R600_BUS_CNTL, bus_cntl); 383 write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control); 384 write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control); 385 write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control); 386 write32(inf [all...] |
H A D | driver.h | 30 #define write32(address, data) (*((volatile uint32*)(address)) = (data)) macro
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H A D | device.cpp | 89 write32(info.registers + reg, value);
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/haiku/src/add-ons/kernel/drivers/network/ether/wb840/ |
H A D | device.h | 18 # define write32(address,value) (*gPci->write_io_32)((address),(value)) macro 28 # define write32(address,data) (*((volatile uint32 *)(address)) = (data)) macro
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H A D | interface.c | 46 write32(device->reg_base + WB_SIO, \ 50 write32(device->reg_base + WB_SIO, \ 108 write32(device->reg_base + WB_SIO, 0); 329 write32(device->reg_base + WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 334 write32(device->reg_base + WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 345 write32(device->reg_base + WB_SIO, 0);
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H A D | wb840.c | 80 write32(device->reg_base + WB_IMR, WB_INTRS); 81 write32(device->reg_base + WB_ISR, 0xFFFFFFFF); 88 write32(device->reg_base + WB_IMR, 0L); 89 write32(device->reg_base + WB_ISR, 0L); 190 write32(device->reg_base + WB_BUSCTL, 194 write32(device->reg_base + WB_BUSCTL_SKIPLEN, WB_SKIPLEN_4LONG); 212 write32(device->reg_base + WB_NETCFG, 0L); 213 write32(device->reg_base + WB_BUSCTL, 0L); 214 write32(device->reg_base + WB_TXADDR, 0L); 215 write32(devic [all...] |
H A D | device.c | 112 write32(data->reg_base + WB_RXSTART, 0xFFFFFFFF); 228 write32(device->reg_base + WB_TXSTART, 0xFFFFFFFF); 265 write32(device->reg_base + WB_TXSTART, 0xFFFFFFFF); 347 write32(device->reg_base + WB_TXADDR, 0x00000000); 348 write32(device->reg_base + WB_RXADDR, 0x00000000);
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H A D | wb840.h | 486 #define WB_SETBIT(reg, x) write32(reg, read32(reg) | x) 487 #define WB_CLRBIT(reg, x) write32(reg, read32(reg) & ~x)
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/haiku/src/add-ons/kernel/busses/i2c/pch/ |
H A D | pch_i2c.cpp | 30 write32(bus->registers + PCH_IC_ENABLE, status); 52 write32(bus->registers + PCH_IC_CLR_RX_UNDER, 0); 54 write32(bus->registers + PCH_IC_CLR_RX_OVER, 0); 56 write32(bus->registers + PCH_IC_CLR_TX_OVER, 0); 58 write32(bus->registers + PCH_IC_CLR_RD_REQ, 0); 60 write32(bus->registers + PCH_IC_CLR_TX_ABRT, 0); 62 write32(bus->registers + PCH_IC_CLR_RX_DONE, 0); 64 write32(bus->registers + PCH_IC_CLR_ACTIVITY, 0); 66 write32(bus->registers + PCH_IC_CLR_STOP_DET, 0); 68 write32(bu [all...] |
H A D | pch_i2c.h | 36 #define write32(address, data) \ macro
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/haiku/src/system/boot/loader/file_systems/fat/ |
H A D | fatfs.h | 29 #define write32(buffer, off, value) \ macro
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H A D | Volume.cpp | 388 write32(buffer, 0x1e8, freeClusters - 1); 391 write32(buffer, 0x1ec, cluster);
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