1/* 2 * Copyright 2020, J��r��me Duval, jerome.duval@gmail.com. 3 * 4 * Distributed under the terms of the MIT License. 5 */ 6#ifndef _PCH_I2C_H 7#define _PCH_I2C_H 8 9 10#include "pch_i2c_hardware.h" 11 12extern "C" { 13# include "acpi.h" 14} 15 16#include <i2c.h> 17#include <lock.h> 18 19 20//#define TRACE_PCH_I2C 21#ifdef TRACE_PCH_I2C 22# define TRACE(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 23#else 24# define TRACE(x...) ; 25#endif 26#define TRACE_ALWAYS(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 27#define ERROR(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 28#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 29 30 31#define PCH_I2C_ACPI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/acpi/driver_v1" 32#define PCH_I2C_PCI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/pci/driver_v1" 33#define PCH_I2C_SIM_MODULE_NAME "busses/i2c/pch_i2c/device/v1" 34 35 36#define write32(address, data) \ 37 (*((volatile uint32*)(address)) = (data)) 38#define read32(address) \ 39 (*((volatile uint32*)(address))) 40 41 42 43extern device_manager_info* gDeviceManager; 44extern i2c_for_controller_interface* gI2c; 45extern acpi_module_info* gACPI; 46extern driver_module_info gPchI2cAcpiDevice; 47extern driver_module_info gPchI2cPciDevice; 48 49 50acpi_status pch_i2c_scan_bus_callback(acpi_handle object, uint32 nestingLevel, 51 void *context, void** returnValue); 52 53 54struct pch_i2c_crs { 55 uint16 i2c_addr; 56 uint32 irq; 57 uint8 irq_triggering; 58 uint8 irq_polarity; 59 uint8 irq_shareable; 60 61 uint32 addr_bas; 62 uint32 addr_len; 63}; 64 65 66typedef enum { 67 PCH_I2C_IRQ_LEGACY, 68 PCH_I2C_IRQ_MSI, 69 PCH_I2C_IRQ_MSI_X_SHARED 70} pch_i2c_irq_type; 71 72 73typedef struct { 74 phys_addr_t base_addr; 75 uint64 map_size; 76 uint32 irq; 77 i2c_bus sim; 78 79 device_node* node; 80 device_node* driver_node; 81 82 area_id registersArea; 83 addr_t registers; 84 uint32 capabilities; 85 86 uint16 ss_hcnt; 87 uint16 ss_lcnt; 88 uint16 fs_hcnt; 89 uint16 fs_lcnt; 90 uint16 hs_hcnt; 91 uint16 hs_lcnt; 92 uint32 sda_hold_time; 93 94 uint8 tx_fifo_depth; 95 uint8 rx_fifo_depth; 96 97 uint32 masterConfig; 98 99 // transfer 100 int32 busy; 101 bool readwait; 102 bool writewait; 103 i2c_op op; 104 void* buffer; 105 size_t length; 106 uint32 flags; 107 int32 error; 108 109 mutex lock; 110 status_t (*scan_bus)(i2c_bus_cookie cookie); 111} pch_i2c_sim_info; 112 113 114#endif // _PCH_I2C_H 115