intel_extreme: hook dp_aux channel to the i2c common ddc for DigitalDisplayInterface ports

This assumes a Gen9 or Gen11 configuration, and aux channel 0. As a result, the same EDID will
be found for every DDI port. The mapping should be found in the VBT.

Tested on KabyLake and JasperLake

Change-Id: I27f5ac8ec8e6ba519fbe9aaf745e78a7361175b9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5175
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: added more pipeC support, fixes for eDP on DDI systems

intel_extreme: Sandy/IvyBridge fix 4 lanes DP detect, fully pgm eDP link

intel_extreme: decoupled PIPE/eDP link programming from FDI train, fixed eDP pgm error.

intel_extreme:DP links on sky- upto/incl coffeelake are now done (refclk detection added)

intel_extreme: skylake PLL works, all outputs fully functional.

intel_extreme: add haswell/skylake PLL calcs, no functional change yet.

intel_extreme: skylake/DDI improvements. no resolution changing possible yet (missing DPLL code yet)

intel_extreme: haswell and skylake DDI EDID support added, modesetting not finished yet.

intel_extreme: fix regression introduced in hrev55419.

Apparently my comment about the width and height being swapped in this
register was not visible enough, so I make it a bit more obvious by
adding some uppercase.

Change-Id: I27621032d071ed09f82aa109f37482178351db04
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4664
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

intel extreme: skylake sets color, base and address, no resolution and refresh yet

intel_extreme: Fixed virtualscreen setup, ticket #17261

intel_extreme: displayport now scales to BIOS set mode.

intel_extreme: don't pgm pipes, follow BIOS for now. Two screens on now i.e.

intel driver: added panelfitter pgmming.

Intel_extreme: fixed hrev55115 regression and added FDI data/link M/N programming.

Intel_extreme: fixed DPLL pgming (Sandy+), prevent black display by not killing PIPE (Ivy+). Chkd GMA(Q33G/Q45) OK. Added defines.

intel_extreme: Do not early-enable the pipe on pre-SandyBridge

Should fix #15861.

intel_extreme: some minor fixes

- Cleanup HEAD_MODE constants. These should be completely removed, now
that we have a proper notion of pipes and displays. But the DPMS code
still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
missing a +1 to show the actual videomode values

intel_extreme: fix panel fitting code

This could also help with VGA output, a logic error in the pipe code
would lead to never configuring the pipe resolution. May help with VGA
output on SandyBridge and IvyBridge (but I get DPMS off on my laptop for
now, so I think something isn't quite right yet).

intel_extreme: program the DPLL_SEL register on SandyBridge

We need to assign PLLs to pipes and transcoders. The assignments on
previous generations were fixed, but now it's up to us to set it up.

Do the simplest thing for now: assign PLL1 to pipe A and PLL2 to pipe B.

intel_extreme: fix pipe selection for Ivy Bridge and later

Should fix #15661 and #15662.

intel_extreme: set the "image size" register on generation 4 and below

This is undocumented, but required for GMA 945 and probably earlier
devices as well. The register is reserved in later generation 4 devices,
and not mentionned at all in later versions.

Fixes #15655.

intel_extreme: disable pipe configuration

This code just sets nonsensical things in the pipe control register, so
disable it and add FIXMEs if someone wants to get it to work someday
(but it's not needed for modesetting an already up and running display).

Also remove some other places where we write to non-existing registers.

Fixes #15628 (for real, this time).

intel_extreme: fix pipe and plane size registers

- The name for the registers were swapped
- The width and height were also swapped in one of them
- Remove some old #if 0 code that touched these registers but has been
disabled for a while.

intel_extreme: use the panel fitter for generation 4 devices

LVDS panels must really be driven at their native resolution, otherwise
they will simply not work. This means we should basically never touch
the video timings on that side. We need to only set the source size in
the pipe configuration, and let the panel fitter figure out the scaling.

On my G45 laptop, this allows me to use non-native resolutions on the
laptop display. This also means when booting with a VGA display
connected, I do get a valid display on the internal panel (using the VGA
resolution). VGA still gets "out of range", so we're still not setting
up something there.

If I switch to VGA display in the BIOS, I get a working picture there
and garbage on the internal display, which is progress (before I would
get a black screen on the internal display)

Fixes #12723.

intel_extreme: set image size on both pipes.

This was hardcoded to pipe A on my laptop, but it's better to set both
pipes so it work in more cases.

Eventually I should see why my SandyBridge laptop is failing to move its
LVDS panel to pipe B...

This fixes miqlas Thinpad X200s and possibly some other machines. Thanks
for letting me experiment with the hardware!

More SandyBridge fixes and cleanups

Modesetting
===========

My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:

- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed

DPMS
====

It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.

Remaining hacks
===============

I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.

This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.

Fix SandyBridge support.

This reverts commit 4f2b258c32efeab97f043519b7f2d4e22819d431.
This reverts commit c86f3dba238a44a8fcf7b1452c46f1cab68f525a.
This reverts commit 61fbdb0667c57f6d3d11d33bce6c01bdd625aaec.
This reverts commit b3f14fb7c715cf95b374ee749dcafd5537d1b017.

intel_extreme: Implement Ilk PCH FDI link training

* IronLake tested and FDI says it trains successfully
* Still no LVDS video on Ilk

intel_extreme: Improve PCH detection

* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.

intel_extreme: Rework PLL calculation

* More like linux, improved G4x calculations
* Reduce un-needed pll limit complexity
* Improved pll limits on ports based on type

intel_extreme: Extend DDI port probing to A-E

* The Linux code made this a bit hard to figure out via
complex define functions, however there can be up to
5 DDI ports (A-E)

intel_extreme: Add general pipe configuration and adjust color space

intel_extreme: Move rest of pipe control into pipe class

intel_extreme: Fix pll divisors on gen 3 cards

* Likely a regression from my card generation rework

intel_extreme: Fix i965 LVDS panel programming

* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965

pll: Cleanup PLL post dividers, add VLV and CHV limits

intel_extreme: Rework PLL and id PineView as PIN

intel_extreme: program both pll divisors

intel_extreme: Don't store pipes within ports

* Store pipes within accelerant, and tell ports
about them.
* Rebrand DisplayPipe class to Pipe