intel_extreme: disable digital dpms monitor shutoff, it's faulty and incomplete (ticket #12964)

intel_extreme: only access ports pipe if it has one assigned.

More SandyBridge fixes and cleanups

Modesetting
===========

My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:

- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed

DPMS
====

It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.

Remaining hacks
===============

I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.

This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.

Fix SandyBridge support.

This reverts commit 4f2b258c32efeab97f043519b7f2d4e22819d431.
This reverts commit c86f3dba238a44a8fcf7b1452c46f1cab68f525a.
This reverts commit 61fbdb0667c57f6d3d11d33bce6c01bdd625aaec.
This reverts commit b3f14fb7c715cf95b374ee749dcafd5537d1b017.

intel_extreme: Improve PCH detection

* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.

intel_extreme: Move rest of pipe control into pipe class

intel_extreme: tracing cleanup; no functional change

intel_extreme: LVDS cleanup and fixes for later gens

intel_extreme: Rebase and refactor mmlr's work from 2013

* New port storage classes and cleaner logic

intel_extreme: Improve accelerant tracing and debug output

* Several messages to syslog weren't tagged with
intel_extreme making troubleshooting difficult
* Fix a few typesize printf issues with B_PRI macro

Make some more SandyBridge specifics into Platform Control Hub (PCH) specifics.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42868 a95241bf-73f2-0310-859d-f6bbb57e9c96

Style cleanups only, no functional change.
* Make the pointer style consistent accross all components, which should make it
easier when working all over the place.
* 80 char limits.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Rework how registers are accessed. Most registers are now grouped into
register blocks and we encode their block into the register definition. On
register access these blocks are then translated into the final address.
* Set up the register blocks for (G)MCH and PCH variants.
* Remove most SandyBridge code that was actually PCH specific and is now taken
care of automatically.
* This will temporarily break SandyBridge support again until the right
transcoders are actually programmed.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42857 a95241bf-73f2-0310-859d-f6bbb57e9c96

Attempt at panel control for SandyBridge, still disabled though as it doesn't
work yet.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42856 a95241bf-73f2-0310-859d-f6bbb57e9c96

More SandyBridge specifics: Use the proper registers for display detection and
DPMS. Still needs to be reworked...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42846 a95241bf-73f2-0310-859d-f6bbb57e9c96

* The DPMS code tried to enable the LVDS panel already if a digital display
was detected; however, it should only do so when there is an actual LVDS panel
detected.
* This should fix one part of ticket #3149 - looks like there are two different
issues. Thanks to Robert J. Gebis for providing me remote access to his
system.
* Minor debug output improvements.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36941 a95241bf-73f2-0310-859d-f6bbb57e9c96

Patch by Christopher Plymire, style-reworked by myself:
* first steps of supporting LVDS panels.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25975 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96

* No longer switch between divisor register set 0 and 1; it doesn't really
make any sense.
* "pll" might have been set incorrectly on i8xx chips.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22253 a95241bf-73f2-0310-859d-f6bbb57e9c96

* B_MOVE_DISPLAY and B_SET_INDEXED_COLORS should now work for the digital
output as well.
* Obviously got the register for INTEL_DISPLAY_B_DIGITAL_PORT wrong - it's
not 0x61000 but 0x61140, maybe that can explain the fun we had at BeGeistert :)
* Renamed the analog display registers to better fit the digital ones, ie.
replaced DISPLAY with DISPLAY_A - although this might be not really correct
as it seems that the pipes can be selected arbitrarily.
* Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17566 a95241bf-73f2-0310-859d-f6bbb57e9c96

Some work to support output on the digital interface like laptop panels.
Need to clean this up, though. It even sort of worked on tic's IBM X40
on BeGeistert - if you weren't irritated by the fact some parts of the
screen were just black, that is :-)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17565 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Now using Thomas memory manager to manage the graphics memory; allocation
of graphics memory is now possible.
* Changed driver name to start with "intel_extreme" to have a nicer device
name.
* Renamed frame_buffer* stuff to graphics_memory* as the frame buffer just
happens to be located somewhere in the graphics memory.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17224 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added some debug output - the driver is actually working under R5 as well, I just
didn't test it correctly last time...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16873 a95241bf-73f2-0310-859d-f6bbb57e9c96

Very basic driver for the "Intel Extreme Graphics 2" chips, only supports i865G for now.
Only mode switches do work, doesn't yet make sure the mode is valid, though.
At this point, this driver only works on Haiku, the R5 app_server is crashing for some
reason I need to investigate some day (maybe tomorrow :)).


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16872 a95241bf-73f2-0310-859d-f6bbb57e9c96

intel_extreme: Improve accelerant tracing and debug output

* Several messages to syslog weren't tagged with
intel_extreme making troubleshooting difficult
* Fix a few typesize printf issues with B_PRI macro

Make some more SandyBridge specifics into Platform Control Hub (PCH) specifics.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42868 a95241bf-73f2-0310-859d-f6bbb57e9c96

Style cleanups only, no functional change.
* Make the pointer style consistent accross all components, which should make it
easier when working all over the place.
* 80 char limits.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Rework how registers are accessed. Most registers are now grouped into
register blocks and we encode their block into the register definition. On
register access these blocks are then translated into the final address.
* Set up the register blocks for (G)MCH and PCH variants.
* Remove most SandyBridge code that was actually PCH specific and is now taken
care of automatically.
* This will temporarily break SandyBridge support again until the right
transcoders are actually programmed.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42857 a95241bf-73f2-0310-859d-f6bbb57e9c96

Attempt at panel control for SandyBridge, still disabled though as it doesn't
work yet.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42856 a95241bf-73f2-0310-859d-f6bbb57e9c96

More SandyBridge specifics: Use the proper registers for display detection and
DPMS. Still needs to be reworked...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42846 a95241bf-73f2-0310-859d-f6bbb57e9c96

* The DPMS code tried to enable the LVDS panel already if a digital display
was detected; however, it should only do so when there is an actual LVDS panel
detected.
* This should fix one part of ticket #3149 - looks like there are two different
issues. Thanks to Robert J. Gebis for providing me remote access to his
system.
* Minor debug output improvements.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36941 a95241bf-73f2-0310-859d-f6bbb57e9c96

Patch by Christopher Plymire, style-reworked by myself:
* first steps of supporting LVDS panels.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25975 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did
not take the VCO limits into account; both could (and would during testing) create invalid
frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
is used in the X driver to create comparable output (our error computation is based on float,
though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
is now only used for the view offset. Instead of setting the base manually here and there,
there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
my i965 system, I'm now greeted by a black screen after startup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96

* No longer switch between divisor register set 0 and 1; it doesn't really
make any sense.
* "pll" might have been set incorrectly on i8xx chips.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22253 a95241bf-73f2-0310-859d-f6bbb57e9c96

* B_MOVE_DISPLAY and B_SET_INDEXED_COLORS should now work for the digital
output as well.
* Obviously got the register for INTEL_DISPLAY_B_DIGITAL_PORT wrong - it's
not 0x61000 but 0x61140, maybe that can explain the fun we had at BeGeistert :)
* Renamed the analog display registers to better fit the digital ones, ie.
replaced DISPLAY with DISPLAY_A - although this might be not really correct
as it seems that the pipes can be selected arbitrarily.
* Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17566 a95241bf-73f2-0310-859d-f6bbb57e9c96

Some work to support output on the digital interface like laptop panels.
Need to clean this up, though. It even sort of worked on tic's IBM X40
on BeGeistert - if you weren't irritated by the fact some parts of the
screen were just black, that is :-)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17565 a95241bf-73f2-0310-859d-f6bbb57e9c96

* Now using Thomas memory manager to manage the graphics memory; allocation
of graphics memory is now possible.
* Changed driver name to start with "intel_extreme" to have a nicer device
name.
* Renamed frame_buffer* stuff to graphics_memory* as the frame buffer just
happens to be located somewhere in the graphics memory.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17224 a95241bf-73f2-0310-859d-f6bbb57e9c96

Added some debug output - the driver is actually working under R5 as well, I just
didn't test it correctly last time...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16873 a95241bf-73f2-0310-859d-f6bbb57e9c96

Very basic driver for the "Intel Extreme Graphics 2" chips, only supports i865G for now.
Only mode switches do work, doesn't yet make sure the mode is valid, though.
At this point, this driver only works on Haiku, the R5 app_server is crashing for some
reason I need to investigate some day (maybe tomorrow :)).


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16872 a95241bf-73f2-0310-859d-f6bbb57e9c96