intel_extreme: for DDI, map the ddc pin to the GPIO

add port G for Gen12

Change-Id: I70bba2d6d2ec0fbad8bdbec14412ea982690d563
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5626
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

intel_extreme: on gen12 PIPE_DDI_FUNC_CTL_EDP seems unreliable

this is only useful when connecting an external screen, and the laptop actually uses it on boot.
should help with #17706

Change-Id: Ia3434f76cf6210b743f17d5559d031c089cbcd85
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5518
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: improve DpAux support on HSW/SNB/IVB

hraw_clock is possibly dynamic, but for the usecase this seems good enough.
Tested on SandyBridge and Haswell laptops.

Change-Id: I045b3c03f6b37bbffb3d8688658ffaa2a97311ae
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5319
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: probe DP AUX or/and DDC on DDI ports

* the VBT tells whether DDI ports can have both DP and HDMI/DVI as outputs.
* tested on Dell Optiplex 9020 Gen7/Haswell with an HDMI/DP adapter on a DP connector.
* avoids enabling a down DDI port when an EDID is found: the display isn't setup by the BIOS.

Change-Id: I69487a2fcb74899d7c22d04e955e776b0e739151
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5317
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: when DDI A eDP port isn't enabled by the BIOS, don't enable

we might be connected with an external port (HDMI or DP) which would be later found.

Change-Id: Ibeab4abb651e5b37d7a0fa452286ee34dec7dfbd
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5306
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: the eDP port on DDI is mostly found on port A

* for eDP a displayport output should also be found als VBT device type.
* should help with #17730

Change-Id: I893bd2dabfd1730ab545336e2f9a5b15abc194a4
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5299
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: reuse DpAux code for DisplayPort

the code is moved in the Port class.

Change-Id: I3beb337e29b26ee4732224723c5b76b5f415a248
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5291
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: leverage VBT device type for internal panel

* also handle dp aux on PCH.
* tested on Gen7, should work from Gen6.

Change-Id: I8d99bcdc10c817e66441a6a644df490dd988a74d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5290
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme: parse VBT device configs, use this to skip unused ports

* BDB version from 111
* for DDI from Gen9
* for HDMI and DisplayPort from Gen6
* use the first port to create the mode list
* also probe DDI Port A
* the aux channel helps to select the correct dp aux registers.

Change-Id: I80549a6ec0477bed768cc5f388959b606d50c1b7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5286
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>

intel_extreme/DDI: _DpAuxTransfer(), check read buffer before copying to it

happens in #17713

Change-Id: I7a4214af70a9ebca8ee70c507a704771c194e92d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5223
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: check EDID for DDI interface E, not only the VBT

fix #17706

Change-Id: I23f260b179cdfabee391d9426a30ec636cafff8e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5212
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>

intel_extreme: hook dp_aux channel to the i2c common ddc for DigitalDisplayInterface ports

This assumes a Gen9 or Gen11 configuration, and aux channel 0. As a result, the same EDID will
be found for every DDI port. The mapping should be found in the VBT.

Tested on KabyLake and JasperLake

Change-Id: I27f5ac8ec8e6ba519fbe9aaf745e78a7361175b9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5175
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: change i2c_send_receive to a hook

common: i2c/ddc uses a 7-bit address for EDID.

Change-Id: Ic1bba2a23174c671bd7374104596c22433bd343a
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5171
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>

intel_extreme: added more pipeC support, fixes for eDP on DDI systems

intel_extreme: for eDP/laptops always use the panel's fixed native modeline, panel doesn't accept otherwise.

intel_extreme: eDP now works on Sandy/Ivy laptops: ticket #17350 i.e.

intel_extreme: log srcclk info, Sandy/Ivy eDP detect BIOS pipe setup and use that.

intel_extreme: eDP port width register read is OK after all (SandyBridge).

intel_extreme: eDP port width seems fixed at 4 on SandyBridge.

intel_extreme: Sandy/IvyBridge fix 4 lanes DP detect, fully pgm eDP link

intel_extreme: decoupled PIPE/eDP link programming from FDI train, fixed eDP pgm error.

intel_extreme: added EDID use for eDP laptop panels

intel_extreme: for Ivy/SandyBridge added eDP programming for laptops.

intel_extreme: sandy/ivybridge DP links to screens are now programmed to the actual mode if possible

intel_extreme: fixed small error, forgot to (re)set default refclk for DP.

intel_extreme:DP links on sky- upto/incl coffeelake are now done (refclk detection added)

intel_extreme: PLLs post skylake work differently again. Refclk update.

intel_extreme: for gen9.5 added new portF to DDI scan. add ID dump in kerneldriver.

intel_extreme: added DDI link colordepth detection, may fix ticket #17439

intel_extreme: fix 3 and 4 lanes DP connections (ticket #17439)

intel_extreme: add laptop panel detection and mode scaling for DDI systems

intel_extreme: always assume panel on eDP on laptops.

intel_extreme: enabled all known skylake gfx cards since they are pgm'd now

intel_extreme: skylake PLL works, all outputs fully functional.

intel_extreme: add haswell/skylake PLL calcs, no functional change yet.

intel_extreme: skylake/DDI improvements. no resolution changing possible yet (missing DPLL code yet)

intel_extreme: haswell and skylake DDI EDID support added, modesetting not finished yet.

intel_extreme: probe EDID again so DDI will fail restoring screen on some systems (workaround)

intel_extreme: reduce use of display_mode where display_timing is enough

In most cases we don't need to use the complete display_mode struct and
we just need the timings. This will avoid future confusion between the
virtual width/height and the actual display timings, if we implement
scrolling someday.

Change-Id: I6c4430b84130b956a47ea0a01afb0843f5a34fd2
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4665
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

intel_extreme: Fixed virtualscreen setup, ticket #17261

intel_extreme: gen4 displayport now sets modes, dualhead clone works.

intel_extreme:dualhead clone mode with displayport works on Sandy/Ivy Bridge.

intel_extreme: displayport now scales to BIOS set mode.

intel_extreme: haswell+ has DDI, no DP, so block scanning that for screens.

intel_extreme: don't pgm pipes, follow BIOS for now. Two screens on now i.e.

intel_extreme: only access ports pipe if it has one assigned.

intel_extreme: fixed DP/DDI clk init switch and link det, accept EDID still down.

intel driver: internal panels need HWtarget for link and fitter

intel driver: added panelfitter pgmming.

Intel_extreme: fixed hrev55115 regression and added FDI data/link M/N programming.

Intel_extreme: fixed Pipe config pgm fault, fixed PLL setup fault (non-analog ports).

intel_extreme: some minor fixes

- Cleanup HEAD_MODE constants. These should be completely removed, now
that we have a proper notion of pipes and displays. But the DPMS code
still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
missing a +1 to show the actual videomode values

intel_extreme: fix panel fitting code

This could also help with VGA output, a logic error in the pipe code
would lead to never configuring the pipe resolution. May help with VGA
output on SandyBridge and IvyBridge (but I get DPMS off on my laptop for
now, so I think something isn't quite right yet).

intel_extreme: fix pipe selection for Ivy Bridge and later

Should fix #15661 and #15662.

intel_extreme: Keep LVDS on its assigned pipe also for SandyBridge

We don't manage to change the transcoder there, either, so just keep
using the selected one (A if no other display is connected, and B if
there is one, it seems).

We were configuring pipe B but the LVDS panel would still display pipe
A. And, we were not configuring pipe B properly, even. The whole
modesetting only worked by occasionally setting some registers for pipe
A ("just in case", said comments).

Now we actually configure the pipe we are using, which makes more sense
and brings us a step closer to multi monitor support.

intel_extreme: do not reprogram transcoded/output mapping on ibex point

Another try to fix #15628

intel_extreme: do not change panel fitter registers in later devices

This code was accidentally re-enabled in hrev53690.

Should fix #15628.

intel_extreme: do configure the LVDS panel when we use native resolution

Should fix the remaining problem in #14066

intel_extreme: use panel fitter also for generation 3

Should help with #14066

intel_extreme: use the panel fitter for generation 4 devices

LVDS panels must really be driven at their native resolution, otherwise
they will simply not work. This means we should basically never touch
the video timings on that side. We need to only set the source size in
the pipe configuration, and let the panel fitter figure out the scaling.

On my G45 laptop, this allows me to use non-native resolutions on the
laptop display. This also means when booting with a VGA display
connected, I do get a valid display on the internal panel (using the VGA
resolution). VGA still gets "out of range", so we're still not setting
up something there.

If I switch to VGA display in the BIOS, I get a working picture there
and garbage on the internal display, which is progress (before I would
get a black screen on the internal display)

Fixes #12723.

intel_extreme: enable LVDS if a VESA panel information is found

This is useful for example on the eeePC 701, where the EDID/DDC lines
from the LCD display are not wired to the video card as expected (I
confirmed this by downloading the eeePC schematics, the LCD is somehow
wired to what would normally be a PS/2 port on the embedded controller).

In this case, there is no way we can get the EDID data from the usual
means, however, we still know the panel resolution by looking it up in
the VESA BIOS, and if we found it there, there has to be an LVDS panel,
so we can configure it.

Should fix #14066.

intel_extreme: disable FDI training for now.

It just deadlocks, so let's try to go without it and hope for the best?

Should fix #14301

Change-Id: I3cbd6e800a64da31f1fb1f1fb66b088e0298596e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1899
Reviewed-by: waddlesplash <waddlesplash@gmail.com>

More SandyBridge fixes and cleanups

Modesetting
===========

My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:

- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed

DPMS
====

It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.

Remaining hacks
===============

I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.

This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.

Fix SandyBridge support.

This reverts commit 4f2b258c32efeab97f043519b7f2d4e22819d431.
This reverts commit c86f3dba238a44a8fcf7b1452c46f1cab68f525a.
This reverts commit 61fbdb0667c57f6d3d11d33bce6c01bdd625aaec.
This reverts commit b3f14fb7c715cf95b374ee749dcafd5537d1b017.

intel_extreme: Implement Ilk PCH FDI link training

* IronLake tested and FDI says it trains successfully
* Still no LVDS video on Ilk

intel_extreme: Fix regression from hrev50410; #12855

intel_extreme: LVDS pipe only *has* to be B when gen < 4

intel_extreme: Improve PCH detection

* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.

intel_extreme: Rework PLL calculation

* More like linux, improved G4x calculations
* Reduce un-needed pll limit complexity
* Improved pll limits on ports based on type

intel_extreme: Tab cleanup; no functional change.

* It seems like the Atom editor has been injecting
spaces in strange spots.
* Clean up spaces. Should help gcc6 as well.
* Sorry for the mess! Atom is on probation.

Ports.cpp: fix gcc6 build

* Reindent source code, to fix gcc6
'-Werror=misleading-indentation' warnings.

intel_extreme: Extend DDI port probing to A-E

* The Linux code made this a bit hard to figure out via
complex define functions, however there can be up to
5 DDI ports (A-E)

intel_extreme: Improve LVDS panel detection robustness

* If older generation, check for mobile. If mobile GPU
is found, make an assumption that a LVDS panel exists
and attempt to leverage the vbios or VESA EDID.

intel_extreme: Fix blurry native LVDS mode

* Intel panel scaling was making native mode blury
* Resolutions < native result in a non-scaled screen for now.
* We should look into using the hardware scaler vs
doing fake scaling.
* Resolves #12716

intel_extreme: Power up DDI

intel_extreme: Add initial work for DDI ports

intel_extreme: Properly use VBIOS panel mode

* Move current_mode into the accelerant as the
driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
Mode set should notice that and fall back to panel_mode

intel_extrme: Better tracing, note when dp no-link

intel_extreme: Clean up DisplayPort Port class

* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd

intel_extreme: Add general pipe configuration and adjust color space

intel_extreme: Move rest of pipe control into pipe class

intel_extreme: Correct LVDS DPLL mode on gen 3

intel_extreme: Fix DPLL mode selection on gen 3

* Gen 3 chipsets also have this DPLL mode. 0 is reserved.

intel_extreme: Fix i965 LVDS panel programming

* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965

intel_extreme: Correct panel control register on non-pch

intel_extreme: Improve LVDS CLKB desire detection

intel_extreme: Don't store pipes within ports

* Store pipes within accelerant, and tell ports
about them.
* Rebrand DisplayPipe class to Pipe

intel_extreme: Fix LVDS polarity flags

intel_extreme: Improve LVDS panel control

* Disable panel before modification
* Properly wait for panel power

intel_extreme: More FDI training work

* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.

intel_extreme: First work at programming FDI

intel_extreme: Fix DP / HDMI gpu register location mixup on die

intel_extreme: Cleanup pipe enablement ordering

intel_extreme: Program more LVDS regs. Set +/- @ lvds port

intel_extreme: Store current display mode on each port

intel_extreme: Disable lvds panel_fitter for now

intel_extreme: Make sure we power up the panel after modesetting

intel_extreme: Program multiplier divisors

intel_extreme: tracing cleanup; no functional change

intel_extreme: Add initial TMDS modesetting code

intel_extreme: Set mode and pll via pipe-aware class functions

intel_extreme: Begin using new DisplayPipe class

intel_extreme: Add pipe selection for ports

intel_extreme: Correct generations based on some Intel help

intel_extreme: LVDS cleanup and fixes for later gens

intel_extreme: Rework card identification defines

* Be more verbose on flag type
* Add additional groups
* Add additional families
* Correctly assign later models

intel_extreme: Undo a suspect PLL change from mmlr's branch

intel_extreme: Start doing mode-setting at port level

* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
likely need broken apart.

intel_extreme: Fix regs, remove PCH for VLV, Expand Type

* Fix some incorrect HDMI reg locations
* PCH goes away on later Intel chips
* Add more mask room for Intel Groups

intel_extreme: Correct card identification, add gen4 hdmi regs

intel_extreme: Dump more info on ports found. Build fixes.

intel_extreme: Rebase and refactor mmlr's work from 2013

* New port storage classes and cleaner logic