Searched refs:vblank_end (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_crt.c706 u32 vblank, vblank_start, vblank_end; local
721 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
749 if (vblank_start <= vactive && vblank_end >= vtotal) {
756 VBLANK_END(vblank_end - 1));
760 if (vblank_start - vactive >= vtotal - vblank_end)
763 vsample = (vtotal + vblank_end) >> 1;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c856 unsigned int vblank_end = dst->vblank_end; local
979 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1080 <= vblank_end / 2.0)
1087 <= vblank_end)
1100 "WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1103 vblank_end);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c810 unsigned int vblank_end = dst->vblank_end; local
933 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1041 <= vblank_end / 2.0)
1048 <= vblank_end)
1060 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1063 vblank_end);
H A Ddisplay_rq_dlg_calc_20.c810 unsigned int vblank_end = dst->vblank_end; local
933 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1040 <= vblank_end / 2.0)
1047 <= vblank_end)
1059 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1062 vblank_end);
H A Ddcn20_fpu.c1391 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
/linux-master/drivers/video/fbdev/
H A Dgbefb.c522 timing->vblank_end = timing->vtotal;
561 SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end);
573 SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end);
581 temp = timing->vblank_start - timing->vblank_end - 1;
625 SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end);
/linux-master/include/video/
H A Dgbe.h298 short vblank_end; /* Vertical blank end */ member in struct:gbe_timing_info
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c232 unsigned int vblank_end = dst->vblank_end; local
277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c250 unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; local
259 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;
273 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;
H A Ddml_display_rq_dlg_calc.c214 dml_uint_t vblank_end = timing->VBlankEnd[plane_idx]; local
320 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c919 unsigned int vblank_end = dst->vblank_end; local
1047 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1138 <= vblank_end / 2.0)
1145 <= vblank_end)
1157 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1160 vblank_end);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c881 unsigned int vblank_end = dst->vblank_end; local
983 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1035 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
1040 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c966 unsigned int vblank_end = dst->vblank_end; local
1068 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
1122 if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
1127 if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_lib.c228 dml_print("DML PARAMS: vblank_end = %d\n", pipe_dest->vblank_end);
H A Ddisplay_mode_structs.h515 unsigned int vblank_end; member in struct:_vcs_dpi_display_pipe_dest_params_st
H A Ddml1_display_rq_dlg_calc.c1013 unsigned int vblank_end = e2e_pipe_param->pipe.dest.vblank_end; local
1160 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */
1259 "WARNING_DLG: %s: vblank_start=%d vblank_end=%d",
1262 vblank_end);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c440 input->dest.vblank_end = input->dest.vblank_start
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1258 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c132 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
/linux-master/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h1513 uint16_t vblank_end; member in struct:dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2::__anon65::__anon67
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c652 pipe_data->pipe_config.vblank_data.vblank_end =
/linux-master/drivers/gpu/drm/i915/
H A Di915_reg.h1950 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))

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