1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "../display_mode_lib.h" 27#include "../display_mode_vba.h" 28#include "../dml_inline_defs.h" 29#include "display_rq_dlg_calc_30.h" 30#include "display_mode_vba_30.h" 31 32static bool is_dual_plane(enum source_format_class source_format) 33{ 34 bool ret_val = 0; 35 36 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha)) 37 ret_val = 1; 38 39 return ret_val; 40} 41 42static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, 43 double refclk_freq_in_mhz, 44 double pclk_freq_in_mhz, 45 unsigned int odm_combine, 46 unsigned int recout_width, 47 unsigned int hactive, 48 double vratio, 49 double hscale_pixel_rate, 50 unsigned int delivery_width, 51 unsigned int req_per_swath_ub) 52{ 53 double refcyc_per_delivery = 0.0; 54 55 if (vratio <= 1.0) { 56 if (odm_combine) 57 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) 58 * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) 59 / pclk_freq_in_mhz / (double)req_per_swath_ub; 60 else 61 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)recout_width 62 / pclk_freq_in_mhz / (double)req_per_swath_ub; 63 } else { 64 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)delivery_width 65 / (double)hscale_pixel_rate / (double)req_per_swath_ub; 66 } 67 68 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 69 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 70 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 71 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 72 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 73 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 74 75 return refcyc_per_delivery; 76 77} 78 79static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 80{ 81 if (tile_size == dm_256k_tile) 82 return (256 * 1024); 83 else if (tile_size == dm_64k_tile) 84 return (64 * 1024); 85 else 86 return (4 * 1024); 87} 88 89static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 90 display_data_rq_regs_st *rq_regs, 91 const display_data_rq_sizing_params_st *rq_sizing) 92{ 93 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 94 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 95 96 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; 97 98 if (rq_sizing->min_chunk_bytes == 0) 99 rq_regs->min_chunk_size = 0; 100 else 101 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; 102 103 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; 104 if (rq_sizing->min_meta_chunk_bytes == 0) 105 rq_regs->min_meta_chunk_size = 0; 106 else 107 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; 108 109 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; 110 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; 111} 112 113static void extract_rq_regs(struct display_mode_lib *mode_lib, 114 display_rq_regs_st *rq_regs, 115 const display_rq_params_st *rq_param) 116{ 117 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 118 unsigned int detile_buf_plane1_addr = 0; 119 120 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); 121 122 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), 123 1) - 3; 124 125 if (rq_param->yuv420) { 126 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); 127 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), 128 1) - 3; 129 } 130 131 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); 132 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); 133 134 // FIXME: take the max between luma, chroma chunk size? 135 // okay for now, as we are setting chunk_bytes to 8kb anyways 136 if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb 137 rq_regs->drq_expansion_mode = 0; 138 } else { 139 rq_regs->drq_expansion_mode = 2; 140 } 141 rq_regs->prq_expansion_mode = 1; 142 rq_regs->mrq_expansion_mode = 1; 143 rq_regs->crq_expansion_mode = 1; 144 145 if (rq_param->yuv420) { 146 if ((double)rq_param->misc.rq_l.stored_swath_bytes 147 / (double)rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { 148 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 149 } else { 150 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), 151 256, 152 0) / 64.0; // 2/3 to chroma 153 } 154 } 155 rq_regs->plane1_base_address = detile_buf_plane1_addr; 156} 157 158static void handle_det_buf_split(struct display_mode_lib *mode_lib, 159 display_rq_params_st *rq_param, 160 const display_pipe_source_params_st *pipe_src_param) 161{ 162 unsigned int total_swath_bytes = 0; 163 unsigned int swath_bytes_l = 0; 164 unsigned int swath_bytes_c = 0; 165 unsigned int full_swath_bytes_packed_l = 0; 166 unsigned int full_swath_bytes_packed_c = 0; 167 bool req128_l = false; 168 bool req128_c = false; 169 bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); 170 bool surf_vert = (pipe_src_param->source_scan == dm_vert); 171 unsigned int log2_swath_height_l = 0; 172 unsigned int log2_swath_height_c = 0; 173 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 174 175 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 176 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 177 178 if (rq_param->yuv420_10bpc) { 179 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 180 256, 181 1) + 256; 182 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 183 256, 184 1) + 256; 185 } 186 187 if (rq_param->yuv420) 188 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 189 else 190 total_swath_bytes = 2 * full_swath_bytes_packed_l; 191 192 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 193 req128_l = false; 194 req128_c = false; 195 swath_bytes_l = full_swath_bytes_packed_l; 196 swath_bytes_c = full_swath_bytes_packed_c; 197 } else if (!rq_param->yuv420) { 198 req128_l = true; 199 req128_c = false; 200 swath_bytes_c = full_swath_bytes_packed_c; 201 swath_bytes_l = full_swath_bytes_packed_l / 2; 202 } else if ((double)full_swath_bytes_packed_l / (double)full_swath_bytes_packed_c < 1.5) { 203 req128_l = false; 204 req128_c = true; 205 swath_bytes_l = full_swath_bytes_packed_l; 206 swath_bytes_c = full_swath_bytes_packed_c / 2; 207 208 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 209 210 if (total_swath_bytes > detile_buf_size_in_bytes) { 211 req128_l = true; 212 swath_bytes_l = full_swath_bytes_packed_l / 2; 213 } 214 } else { 215 req128_l = true; 216 req128_c = false; 217 swath_bytes_l = full_swath_bytes_packed_l/2; 218 swath_bytes_c = full_swath_bytes_packed_c; 219 220 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 221 222 if (total_swath_bytes > detile_buf_size_in_bytes) { 223 req128_c = true; 224 swath_bytes_c = full_swath_bytes_packed_c/2; 225 } 226 } 227 228 if (rq_param->yuv420) 229 total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; 230 else 231 total_swath_bytes = 2 * swath_bytes_l; 232 233 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 234 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 235 236 if (surf_linear) { 237 log2_swath_height_l = 0; 238 log2_swath_height_c = 0; 239 } else { 240 unsigned int swath_height_l; 241 unsigned int swath_height_c; 242 243 if (!surf_vert) { 244 swath_height_l = rq_param->misc.rq_l.blk256_height; 245 swath_height_c = rq_param->misc.rq_c.blk256_height; 246 } else { 247 swath_height_l = rq_param->misc.rq_l.blk256_width; 248 swath_height_c = rq_param->misc.rq_c.blk256_width; 249 } 250 251 if (swath_height_l > 0) 252 log2_swath_height_l = dml_log2(swath_height_l); 253 254 if (req128_l && log2_swath_height_l > 0) 255 log2_swath_height_l -= 1; 256 257 if (swath_height_c > 0) 258 log2_swath_height_c = dml_log2(swath_height_c); 259 260 if (req128_c && log2_swath_height_c > 0) 261 log2_swath_height_c -= 1; 262 } 263 264 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 265 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 266 267 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 268 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 269 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 270 __func__, 271 full_swath_bytes_packed_l); 272 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 273 __func__, 274 full_swath_bytes_packed_c); 275} 276 277static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, 278 display_data_rq_dlg_params_st *rq_dlg_param, 279 display_data_rq_misc_params_st *rq_misc_param, 280 display_data_rq_sizing_params_st *rq_sizing_param, 281 unsigned int vp_width, 282 unsigned int vp_height, 283 unsigned int data_pitch, 284 unsigned int meta_pitch, 285 unsigned int source_format, 286 unsigned int tiling, 287 unsigned int macro_tile_size, 288 unsigned int source_scan, 289 unsigned int hostvm_enable, 290 unsigned int is_chroma, 291 unsigned int surface_height) 292{ 293 bool surf_linear = (tiling == dm_sw_linear); 294 bool surf_vert = (source_scan == dm_vert); 295 296 unsigned int bytes_per_element = 0; 297 unsigned int bytes_per_element_y = 0; 298 unsigned int bytes_per_element_c = 0; 299 300 unsigned int blk256_width = 0; 301 unsigned int blk256_height = 0; 302 303 unsigned int blk256_width_y = 0; 304 unsigned int blk256_height_y = 0; 305 unsigned int blk256_width_c = 0; 306 unsigned int blk256_height_c = 0; 307 unsigned int log2_bytes_per_element = 0; 308 unsigned int log2_blk256_width = 0; 309 unsigned int log2_blk256_height = 0; 310 unsigned int blk_bytes = 0; 311 unsigned int log2_blk_bytes = 0; 312 unsigned int log2_blk_height = 0; 313 unsigned int log2_blk_width = 0; 314 unsigned int log2_meta_req_bytes = 0; 315 unsigned int log2_meta_req_height = 0; 316 unsigned int log2_meta_req_width = 0; 317 unsigned int meta_req_width = 0; 318 unsigned int meta_req_height = 0; 319 unsigned int log2_meta_row_height = 0; 320 unsigned int meta_row_width_ub = 0; 321 unsigned int log2_meta_chunk_bytes = 0; 322 unsigned int log2_meta_chunk_height = 0; 323 324 //full sized meta chunk width in unit of data elements 325 unsigned int log2_meta_chunk_width = 0; 326 unsigned int log2_min_meta_chunk_bytes = 0; 327 unsigned int min_meta_chunk_width = 0; 328 unsigned int meta_chunk_width = 0; 329 unsigned int meta_chunk_per_row_int = 0; 330 unsigned int meta_row_remainder = 0; 331 unsigned int meta_chunk_threshold = 0; 332 unsigned int meta_blk_bytes = 0; 333 unsigned int meta_blk_height = 0; 334 unsigned int meta_blk_width = 0; 335 unsigned int meta_surface_bytes = 0; 336 unsigned int vmpg_bytes = 0; 337 unsigned int meta_pte_req_per_frame_ub = 0; 338 unsigned int meta_pte_bytes_per_frame_ub = 0; 339 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes); 340 const bool dual_plane_en = is_dual_plane((enum source_format_class)(source_format)); 341 const unsigned int dpte_buf_in_pte_reqs = dual_plane_en ? 342 (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) 343 : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma); 344 345 unsigned int log2_vmpg_height = 0; 346 unsigned int log2_vmpg_width = 0; 347 unsigned int log2_dpte_req_height_ptes = 0; 348 unsigned int log2_dpte_req_height = 0; 349 unsigned int log2_dpte_req_width = 0; 350 unsigned int log2_dpte_row_height_linear = 0; 351 unsigned int log2_dpte_row_height = 0; 352 unsigned int log2_dpte_group_width = 0; 353 unsigned int dpte_row_width_ub = 0; 354 unsigned int dpte_req_height = 0; 355 unsigned int dpte_req_width = 0; 356 unsigned int dpte_group_width = 0; 357 unsigned int log2_dpte_group_bytes = 0; 358 unsigned int log2_dpte_group_length = 0; 359 double byte_per_pixel_det_y = 0; 360 double byte_per_pixel_det_c = 0; 361 362 dml30_CalculateBytePerPixelAnd256BBlockSizes((enum source_format_class)(source_format), 363 (enum dm_swizzle_mode)(tiling), 364 &bytes_per_element_y, 365 &bytes_per_element_c, 366 &byte_per_pixel_det_y, 367 &byte_per_pixel_det_c, 368 &blk256_height_y, 369 &blk256_height_c, 370 &blk256_width_y, 371 &blk256_width_c); 372 373 if (!is_chroma) { 374 blk256_width = blk256_width_y; 375 blk256_height = blk256_height_y; 376 bytes_per_element = bytes_per_element_y; 377 } else { 378 blk256_width = blk256_width_c; 379 blk256_height = blk256_height_c; 380 bytes_per_element = bytes_per_element_c; 381 } 382 383 log2_bytes_per_element = dml_log2(bytes_per_element); 384 385 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 386 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 387 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 388 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 389 390 log2_blk256_width = dml_log2((double)blk256_width); 391 log2_blk256_height = dml_log2((double)blk256_height); 392 blk_bytes = surf_linear ? 393 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 394 log2_blk_bytes = dml_log2((double)blk_bytes); 395 log2_blk_height = 0; 396 log2_blk_width = 0; 397 398 // remember log rule 399 // "+" in log is multiply 400 // "-" in log is divide 401 // "/2" is like square root 402 // blk is vertical biased 403 if (tiling != dm_sw_linear) 404 log2_blk_height = log2_blk256_height 405 + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); 406 else 407 log2_blk_height = 0; // blk height of 1 408 409 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 410 411 if (!surf_vert) { 412 int unsigned temp = 0; 413 414 temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width; 415 if (data_pitch < blk256_width) { 416 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width); 417 } else { 418 if (temp > data_pitch) { 419 if (data_pitch >= vp_width) 420 temp = data_pitch; 421 else 422 dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width); 423 } 424 } 425 rq_dlg_param->swath_width_ub = temp; 426 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width; 427 } else { 428 int unsigned temp = 0; 429 430 temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height; 431 if (surface_height < blk256_height) { 432 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height); 433 } else { 434 if (temp > surface_height) { 435 if (surface_height >= vp_height) 436 temp = surface_height; 437 else 438 dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height); 439 } 440 } 441 rq_dlg_param->swath_width_ub = temp; 442 rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height; 443 } 444 445 if (!surf_vert) 446 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 447 * bytes_per_element; 448 else 449 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 450 * bytes_per_element; 451 452 rq_misc_param->blk256_height = blk256_height; 453 rq_misc_param->blk256_width = blk256_width; 454 455 // ------- 456 // meta 457 // ------- 458 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 459 460 // each 64b meta request for dcn is 8x8 meta elements and 461 // a meta element covers one 256b block of the data surface. 462 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 463 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 464 - log2_meta_req_height; 465 meta_req_width = 1 << log2_meta_req_width; 466 meta_req_height = 1 << log2_meta_req_height; 467 log2_meta_row_height = 0; 468 meta_row_width_ub = 0; 469 470 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 471 // calculate upper bound of the meta_row_width 472 if (!surf_vert) { 473 log2_meta_row_height = log2_meta_req_height; 474 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 475 + meta_req_width; 476 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 477 } else { 478 log2_meta_row_height = log2_meta_req_width; 479 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 480 + meta_req_height; 481 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 482 } 483 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 484 485 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 486 487 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 488 log2_meta_chunk_height = log2_meta_row_height; 489 490 //full sized meta chunk width in unit of data elements 491 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 492 - log2_meta_chunk_height; 493 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 494 min_meta_chunk_width = 1 495 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 496 - log2_meta_chunk_height); 497 meta_chunk_width = 1 << log2_meta_chunk_width; 498 meta_chunk_per_row_int = (unsigned int)(meta_row_width_ub / meta_chunk_width); 499 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 500 meta_chunk_threshold = 0; 501 meta_blk_bytes = 4096; 502 meta_blk_height = blk256_height * 64; 503 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 504 meta_surface_bytes = meta_pitch 505 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) 506 * bytes_per_element / 256; 507 vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes; 508 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 509 8 * vmpg_bytes, 510 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 511 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 512 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 513 514 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 515 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 516 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 517 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 518 __func__, 519 meta_pte_req_per_frame_ub); 520 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 521 __func__, 522 meta_pte_bytes_per_frame_ub); 523 524 if (!surf_vert) 525 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 526 else 527 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 528 529 if (meta_row_remainder <= meta_chunk_threshold) 530 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 531 else 532 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 533 534 // ------ 535 // dpte 536 // ------ 537 if (surf_linear) { 538 log2_vmpg_height = 0; // one line high 539 } else { 540 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 541 } 542 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 543 544 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 545 if (surf_linear) { //one 64B PTE request returns 8 PTEs 546 log2_dpte_req_height_ptes = 0; 547 log2_dpte_req_width = log2_vmpg_width + 3; 548 log2_dpte_req_height = 0; 549 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 550 //one 64B req gives 8x1 PTEs for 4KB tile 551 log2_dpte_req_height_ptes = 0; 552 log2_dpte_req_width = log2_blk_width + 3; 553 log2_dpte_req_height = log2_blk_height + 0; 554 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 555 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 556 log2_dpte_req_height_ptes = 4; 557 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 558 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 559 } else { //64KB page size and must 64KB tile block 560 //one 64B req gives 8x1 PTEs for 64KB tile 561 log2_dpte_req_height_ptes = 0; 562 log2_dpte_req_width = log2_blk_width + 3; 563 log2_dpte_req_height = log2_blk_height + 0; 564 } 565 566 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 567 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 568 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 569 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 570 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 571 dpte_req_height = 1 << log2_dpte_req_height; 572 dpte_req_width = 1 << log2_dpte_req_width; 573 574 // calculate pitch dpte row buffer can hold 575 // round the result down to a power of two. 576 if (surf_linear) { 577 unsigned int dpte_row_height = 0; 578 579 log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); 580 581 dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma); 582 dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs); 583 dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear); 584 585 ASSERT(log2_dpte_row_height_linear >= 3); 586 587 if (log2_dpte_row_height_linear > 7) 588 log2_dpte_row_height_linear = 7; 589 590 log2_dpte_row_height = log2_dpte_row_height_linear; 591 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 592 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 593 dpte_row_height = 1 << log2_dpte_row_height; 594 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, 595 dpte_req_width, 596 1) + dpte_req_width; 597 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 598 } else { 599 // the upper bound of the dpte_row_width without dependency on viewport position follows. 600 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 601 if (!surf_vert) { 602 log2_dpte_row_height = log2_dpte_req_height; 603 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 604 + dpte_req_width; 605 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 606 } else { 607 log2_dpte_row_height = 608 (log2_blk_width < log2_dpte_req_width) ? 609 log2_blk_width : log2_dpte_req_width; 610 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 611 + dpte_req_height; 612 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 613 } 614 } 615 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 616 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 617 else 618 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 619 620 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 621 622 // the dpte_group_bytes is reduced for the specific case of vertical 623 // access of a tile surface that has dpte request of 8x1 ptes. 624 if (hostvm_enable) 625 rq_sizing_param->dpte_group_bytes = 512; 626 else { 627 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group 628 rq_sizing_param->dpte_group_bytes = 512; 629 else 630 rq_sizing_param->dpte_group_bytes = 2048; 631 } 632 633 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 634 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 635 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 636 637 // full sized data pte group width in elements 638 if (!surf_vert) 639 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 640 else 641 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 642 643 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 644 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 645 log2_dpte_group_width = log2_dpte_group_width - 1; 646 647 dpte_group_width = 1 << log2_dpte_group_width; 648 649 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 650 // the upper bound for the dpte groups per row is as follows. 651 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, 652 1); 653} 654 655static void get_surf_rq_param(struct display_mode_lib *mode_lib, 656 display_data_rq_sizing_params_st *rq_sizing_param, 657 display_data_rq_dlg_params_st *rq_dlg_param, 658 display_data_rq_misc_params_st *rq_misc_param, 659 const display_pipe_params_st *pipe_param, 660 bool is_chroma, 661 bool is_alpha) 662{ 663 bool mode_422 = 0; 664 unsigned int vp_width = 0; 665 unsigned int vp_height = 0; 666 unsigned int data_pitch = 0; 667 unsigned int meta_pitch = 0; 668 unsigned int surface_height = 0; 669 unsigned int ppe = mode_422 ? 2 : 1; 670 671 // FIXME check if ppe apply for both luma and chroma in 422 case 672 if (is_chroma | is_alpha) { 673 vp_width = pipe_param->src.viewport_width_c / ppe; 674 vp_height = pipe_param->src.viewport_height_c; 675 data_pitch = pipe_param->src.data_pitch_c; 676 meta_pitch = pipe_param->src.meta_pitch_c; 677 surface_height = pipe_param->src.surface_height_y / 2.0; 678 } else { 679 vp_width = pipe_param->src.viewport_width / ppe; 680 vp_height = pipe_param->src.viewport_height; 681 data_pitch = pipe_param->src.data_pitch; 682 meta_pitch = pipe_param->src.meta_pitch; 683 surface_height = pipe_param->src.surface_height_y; 684 } 685 686 if (pipe_param->dest.odm_combine) { 687 unsigned int access_dir = 0; 688 unsigned int full_src_vp_width = 0; 689 unsigned int hactive_odm = 0; 690 unsigned int src_hactive_odm = 0; 691 access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 692 hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2); 693 if (is_chroma) { 694 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; 695 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; 696 } else { 697 full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; 698 src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; 699 } 700 701 if (access_dir == 0) { 702 vp_width = dml_min(full_src_vp_width, src_hactive_odm); 703 dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width); 704 } else { 705 vp_height = dml_min(full_src_vp_width, src_hactive_odm); 706 dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height); 707 } 708 dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width); 709 dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm); 710 dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm); 711 } 712 713 rq_sizing_param->chunk_bytes = 8192; 714 715 if (is_alpha) { 716 rq_sizing_param->chunk_bytes = 4096; 717 } 718 719 if (rq_sizing_param->chunk_bytes == 64 * 1024) 720 rq_sizing_param->min_chunk_bytes = 0; 721 else 722 rq_sizing_param->min_chunk_bytes = 1024; 723 724 rq_sizing_param->meta_chunk_bytes = 2048; 725 rq_sizing_param->min_meta_chunk_bytes = 256; 726 727 if (pipe_param->src.hostvm) 728 rq_sizing_param->mpte_group_bytes = 512; 729 else 730 rq_sizing_param->mpte_group_bytes = 2048; 731 732 get_meta_and_pte_attr(mode_lib, 733 rq_dlg_param, 734 rq_misc_param, 735 rq_sizing_param, 736 vp_width, 737 vp_height, 738 data_pitch, 739 meta_pitch, 740 pipe_param->src.source_format, 741 pipe_param->src.sw_mode, 742 pipe_param->src.macro_tile_size, 743 pipe_param->src.source_scan, 744 pipe_param->src.hostvm, 745 is_chroma, 746 surface_height); 747} 748 749static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 750 display_rq_params_st *rq_param, 751 const display_pipe_params_st *pipe_param) 752{ 753 // get param for luma surface 754 rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 755 || pipe_param->src.source_format == dm_420_10 756 || pipe_param->src.source_format == dm_rgbe_alpha 757 || pipe_param->src.source_format == dm_420_12; 758 759 rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10; 760 761 rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha)?1:0; 762 763 get_surf_rq_param(mode_lib, 764 &(rq_param->sizing.rq_l), 765 &(rq_param->dlg.rq_l), 766 &(rq_param->misc.rq_l), 767 pipe_param, 768 0, 769 0); 770 771 if (is_dual_plane((enum source_format_class)(pipe_param->src.source_format))) { 772 // get param for chroma surface 773 get_surf_rq_param(mode_lib, 774 &(rq_param->sizing.rq_c), 775 &(rq_param->dlg.rq_c), 776 &(rq_param->misc.rq_c), 777 pipe_param, 778 1, 779 rq_param->rgbe_alpha); 780 } 781 782 // calculate how to split the det buffer space between luma and chroma 783 handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); 784 print__rq_params_st(mode_lib, rq_param); 785} 786 787void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 788 display_rq_regs_st *rq_regs, 789 const display_pipe_params_st *pipe_param) 790{ 791 display_rq_params_st rq_param = { 0 }; 792 793 memset(rq_regs, 0, sizeof(*rq_regs)); 794 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); 795 extract_rq_regs(mode_lib, rq_regs, &rq_param); 796 797 print__rq_regs_st(mode_lib, rq_regs); 798} 799 800static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 801 double *refcyc_per_req_delivery_pre_cur, 802 double *refcyc_per_req_delivery_cur, 803 double refclk_freq_in_mhz, 804 double ref_freq_to_pix_freq, 805 double hscale_pixel_rate_l, 806 double hscl_ratio, 807 double vratio_pre_l, 808 double vratio_l, 809 unsigned int cur_width, 810 enum cursor_bpp cur_bpp) 811{ 812 unsigned int cur_src_width = cur_width; 813 unsigned int cur_req_size = 0; 814 unsigned int cur_req_width = 0; 815 double cur_width_ub = 0.0; 816 double cur_req_per_width = 0.0; 817 double hactive_cur = 0.0; 818 819 ASSERT(cur_src_width <= 256); 820 821 *refcyc_per_req_delivery_pre_cur = 0.0; 822 *refcyc_per_req_delivery_cur = 0.0; 823 if (cur_src_width > 0) { 824 unsigned int cur_bit_per_pixel = 0; 825 826 if (cur_bpp == dm_cur_2bit) { 827 cur_req_size = 64; // byte 828 cur_bit_per_pixel = 2; 829 } else { // 32bit 830 cur_bit_per_pixel = 32; 831 if (cur_src_width >= 1 && cur_src_width <= 16) 832 cur_req_size = 64; 833 else if (cur_src_width >= 17 && cur_src_width <= 31) 834 cur_req_size = 128; 835 else 836 cur_req_size = 256; 837 } 838 839 cur_req_width = (double)cur_req_size / ((double)cur_bit_per_pixel / 8.0); 840 cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) 841 * (double)cur_req_width; 842 cur_req_per_width = cur_width_ub / (double)cur_req_width; 843 hactive_cur = (double)cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor 844 845 if (vratio_pre_l <= 1.0) { 846 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 847 / (double)cur_req_per_width; 848 } else { 849 *refcyc_per_req_delivery_pre_cur = (double)refclk_freq_in_mhz 850 * (double)cur_src_width / hscale_pixel_rate_l 851 / (double)cur_req_per_width; 852 } 853 854 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 855 856 if (vratio_l <= 1.0) { 857 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 858 / (double)cur_req_per_width; 859 } else { 860 *refcyc_per_req_delivery_cur = (double)refclk_freq_in_mhz 861 * (double)cur_src_width / hscale_pixel_rate_l 862 / (double)cur_req_per_width; 863 } 864 865 dml_print("DML_DLG: %s: cur_req_width = %d\n", 866 __func__, 867 cur_req_width); 868 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", 869 __func__, 870 cur_width_ub); 871 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", 872 __func__, 873 cur_req_per_width); 874 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", 875 __func__, 876 hactive_cur); 877 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 878 __func__, 879 *refcyc_per_req_delivery_pre_cur); 880 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 881 __func__, 882 *refcyc_per_req_delivery_cur); 883 884 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 885 } 886} 887 888// Note: currently taken in as is. 889// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 890static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 891 const display_e2e_pipe_params_st *e2e_pipe_param, 892 const unsigned int num_pipes, 893 const unsigned int pipe_idx, 894 display_dlg_regs_st *disp_dlg_regs, 895 display_ttu_regs_st *disp_ttu_regs, 896 const display_rq_dlg_params_st rq_dlg_param, 897 const display_dlg_sys_params_st dlg_sys_param, 898 const bool cstate_en, 899 const bool pstate_en, 900 const bool vm_en, 901 const bool ignore_viewport_pos, 902 const bool immediate_flip_support) 903{ 904 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 905 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 906 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 907 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 908 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 909 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 910 911 // ------------------------- 912 // Section 1.15.2.1: OTG dependent Params 913 // ------------------------- 914 // Timing 915 unsigned int htotal = dst->htotal; 916 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove 917 unsigned int hblank_end = dst->hblank_end; 918 unsigned int vblank_start = dst->vblank_start; 919 unsigned int vblank_end = dst->vblank_end; 920 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 921 922 double dppclk_freq_in_mhz = clks->dppclk_mhz; 923 double dispclk_freq_in_mhz = clks->dispclk_mhz; 924 double refclk_freq_in_mhz = clks->refclk_mhz; 925 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 926 bool interlaced = dst->interlaced; 927 928 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 929 930 double min_dcfclk_mhz = 0; 931 double t_calc_us = 0; 932 double min_ttu_vblank = 0; 933 934 double min_dst_y_ttu_vblank = 0; 935 unsigned int dlg_vblank_start = 0; 936 bool dual_plane = false; 937 bool mode_422 = false; 938 unsigned int access_dir = 0; 939 unsigned int vp_height_l = 0; 940 unsigned int vp_width_l = 0; 941 unsigned int vp_height_c = 0; 942 unsigned int vp_width_c = 0; 943 944 // Scaling 945 unsigned int htaps_l = 0; 946 unsigned int htaps_c = 0; 947 double hratio_l = 0; 948 double hratio_c = 0; 949 double vratio_l = 0; 950 double vratio_c = 0; 951 bool scl_enable = false; 952 953 double line_time_in_us = 0; 954 // double vinit_l; 955 // double vinit_c; 956 // double vinit_bot_l; 957 // double vinit_bot_c; 958 959 // unsigned int swath_height_l; 960 unsigned int swath_width_ub_l = 0; 961 // unsigned int dpte_bytes_per_row_ub_l; 962 unsigned int dpte_groups_per_row_ub_l = 0; 963 // unsigned int meta_pte_bytes_per_frame_ub_l; 964 // unsigned int meta_bytes_per_row_ub_l; 965 966 // unsigned int swath_height_c; 967 unsigned int swath_width_ub_c = 0; 968 // unsigned int dpte_bytes_per_row_ub_c; 969 unsigned int dpte_groups_per_row_ub_c = 0; 970 971 unsigned int meta_chunks_per_row_ub_l = 0; 972 unsigned int meta_chunks_per_row_ub_c = 0; 973 unsigned int vupdate_offset = 0; 974 unsigned int vupdate_width = 0; 975 unsigned int vready_offset = 0; 976 977 unsigned int dppclk_delay_subtotal = 0; 978 unsigned int dispclk_delay_subtotal = 0; 979 unsigned int pixel_rate_delay_subtotal = 0; 980 981 unsigned int vstartup_start = 0; 982 unsigned int dst_x_after_scaler = 0; 983 int dst_y_after_scaler = 0; 984 double line_wait = 0; 985 double dst_y_prefetch = 0; 986 double dst_y_per_vm_vblank = 0; 987 double dst_y_per_row_vblank = 0; 988 double dst_y_per_vm_flip = 0; 989 double dst_y_per_row_flip = 0; 990 double max_dst_y_per_vm_vblank = 0; 991 double max_dst_y_per_row_vblank = 0; 992 double lsw = 0; 993 double vratio_pre_l = 0; 994 double vratio_pre_c = 0; 995 unsigned int req_per_swath_ub_l = 0; 996 unsigned int req_per_swath_ub_c = 0; 997 unsigned int meta_row_height_l = 0; 998 unsigned int meta_row_height_c = 0; 999 unsigned int swath_width_pixels_ub_l = 0; 1000 unsigned int swath_width_pixels_ub_c = 0; 1001 unsigned int scaler_rec_in_width_l = 0; 1002 unsigned int scaler_rec_in_width_c = 0; 1003 unsigned int dpte_row_height_l = 0; 1004 unsigned int dpte_row_height_c = 0; 1005 double hscale_pixel_rate_l = 0; 1006 double hscale_pixel_rate_c = 0; 1007 double min_hratio_fact_l = 0; 1008 double min_hratio_fact_c = 0; 1009 double refcyc_per_line_delivery_pre_l = 0; 1010 double refcyc_per_line_delivery_pre_c = 0; 1011 double refcyc_per_line_delivery_l = 0; 1012 double refcyc_per_line_delivery_c = 0; 1013 1014 double refcyc_per_req_delivery_pre_l = 0; 1015 double refcyc_per_req_delivery_pre_c = 0; 1016 double refcyc_per_req_delivery_l = 0; 1017 double refcyc_per_req_delivery_c = 0; 1018 1019 unsigned int full_recout_width = 0; 1020 double refcyc_per_req_delivery_pre_cur0 = 0; 1021 double refcyc_per_req_delivery_cur0 = 0; 1022 double refcyc_per_req_delivery_pre_cur1 = 0; 1023 double refcyc_per_req_delivery_cur1 = 0; 1024 1025 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX] = { 0 }; 1026 1027 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 1028 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 1029 1030 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 1031 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 1032 dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en); 1033 dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos); 1034 dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support); 1035 1036 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 1037 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 1038 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 1039 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 1040 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 1041 ASSERT(ref_freq_to_pix_freq < 4.0); 1042 1043 disp_dlg_regs->ref_freq_to_pix_freq = 1044 (unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19)); 1045 disp_dlg_regs->refcyc_per_htotal = (unsigned int)(ref_freq_to_pix_freq * (double)htotal 1046 * dml_pow(2, 8)); 1047 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 1048 1049 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 1050 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 1051 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1052 1053 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; 1054 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 1055 1056 disp_dlg_regs->min_dst_y_next_start = (unsigned int)(((double)dlg_vblank_start 1057 ) * dml_pow(2, 2)); 1058 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1059 1060 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 1061 __func__, 1062 min_dcfclk_mhz); 1063 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", 1064 __func__, 1065 min_ttu_vblank); 1066 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 1067 __func__, 1068 min_dst_y_ttu_vblank); 1069 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", 1070 __func__, 1071 t_calc_us); 1072 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 1073 __func__, 1074 disp_dlg_regs->min_dst_y_next_start); 1075 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 1076 __func__, 1077 ref_freq_to_pix_freq); 1078 1079 // ------------------------- 1080 // Section 1.15.2.2: Prefetch, Active and TTU 1081 // ------------------------- 1082 // Prefetch Calc 1083 // Source 1084 // dcc_en = src.dcc; 1085 dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); 1086 mode_422 = false; // TODO 1087 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 1088 vp_height_l = src->viewport_height; 1089 vp_width_l = src->viewport_width; 1090 vp_height_c = src->viewport_height_c; 1091 vp_width_c = src->viewport_width_c; 1092 1093 // Scaling 1094 htaps_l = taps->htaps; 1095 htaps_c = taps->htaps_c; 1096 hratio_l = scl->hscl_ratio; 1097 hratio_c = scl->hscl_ratio_c; 1098 vratio_l = scl->vscl_ratio; 1099 vratio_c = scl->vscl_ratio_c; 1100 scl_enable = scl->scl_enable; 1101 1102 line_time_in_us = (htotal / pclk_freq_in_mhz); 1103 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 1104 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 1105 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1106 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1107 1108 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1109 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1110 vupdate_offset = dst->vupdate_offset; 1111 vupdate_width = dst->vupdate_width; 1112 vready_offset = dst->vready_offset; 1113 1114 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1115 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1116 1117 if (scl_enable) 1118 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1119 else 1120 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1121 1122 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1123 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1124 1125 if (dout->dsc_enable) { 1126 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1127 1128 dispclk_delay_subtotal += dsc_delay; 1129 } 1130 1131 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1132 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1133 1134 vstartup_start = dst->vstartup_start; 1135 if (interlaced) { 1136 if (vstartup_start / 2.0 1137 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal 1138 <= vblank_end / 2.0) 1139 disp_dlg_regs->vready_after_vcount0 = 1; 1140 else 1141 disp_dlg_regs->vready_after_vcount0 = 0; 1142 } else { 1143 if (vstartup_start 1144 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal 1145 <= vblank_end) 1146 disp_dlg_regs->vready_after_vcount0 = 1; 1147 else 1148 disp_dlg_regs->vready_after_vcount0 = 0; 1149 } 1150 1151 // TODO: Where is this coming from? 1152 if (interlaced) 1153 vstartup_start = vstartup_start / 2; 1154 1155 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1156 if (vstartup_start >= min_vblank) { 1157 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1158 __func__, 1159 vblank_start, 1160 vblank_end); 1161 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1162 __func__, 1163 vstartup_start, 1164 min_vblank); 1165 min_vblank = vstartup_start + 1; 1166 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1167 __func__, 1168 vstartup_start, 1169 min_vblank); 1170 } 1171 1172 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1173 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1174 if (dst_y_after_scaler < 0) 1175 dst_y_after_scaler = 0; 1176 1177 // do some adjustment on the dst_after scaler to account for odm combine mode 1178 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", 1179 __func__, 1180 dst_x_after_scaler); 1181 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", 1182 __func__, 1183 dst_y_after_scaler); 1184 1185 // need to figure out which side of odm combine we're in 1186 if (dst->odm_combine) { 1187 // figure out which pipes go together 1188 bool visited[DC__NUM_PIPES__MAX] = { false }; 1189 unsigned int i, j, k; 1190 1191 for (k = 0; k < num_pipes; ++k) { 1192 visited[k] = false; 1193 pipe_index_in_combine[k] = 0; 1194 } 1195 1196 for (i = 0; i < num_pipes; i++) { 1197 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { 1198 1199 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; 1200 unsigned int grp_idx = 0; 1201 1202 for (j = i; j < num_pipes; j++) { 1203 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp 1204 && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { 1205 pipe_index_in_combine[j] = grp_idx; 1206 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx); 1207 grp_idx++; 1208 visited[j] = true; 1209 } 1210 } 1211 } 1212 } 1213 1214 } 1215 1216 if (dst->odm_combine == dm_odm_combine_mode_disabled) { 1217 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double) hblank_end * ref_freq_to_pix_freq); 1218 } else { 1219 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 1220 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; 1221 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); 1222 } 1223 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 1224 1225 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1226 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1227 __func__, 1228 pixel_rate_delay_subtotal); 1229 dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n", 1230 __func__, 1231 pipe_idx, 1232 dst_x_after_scaler); 1233 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", 1234 __func__, 1235 pipe_idx, 1236 dst_y_after_scaler); 1237 1238 // Lwait 1239 // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? 1240 line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; 1241 if (cstate_en) 1242 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1243 if (pstate_en) 1244 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us 1245 + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? 1246 line_wait); 1247 line_wait = line_wait / line_time_in_us; 1248 1249 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1250 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1251 1252 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, 1253 e2e_pipe_param, 1254 num_pipes, 1255 pipe_idx); 1256 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, 1257 e2e_pipe_param, 1258 num_pipes, 1259 pipe_idx); 1260 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1261 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1262 1263 max_dst_y_per_vm_vblank = 32.0; //U5.2 1264 max_dst_y_per_row_vblank = 16.0; //U4.2 1265 1266 // magic! 1267 if (htotal <= 75) { 1268 min_vblank = 300; 1269 max_dst_y_per_vm_vblank = 100.0; 1270 max_dst_y_per_row_vblank = 100.0; 1271 } 1272 1273 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); 1274 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); 1275 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1276 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1277 1278 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); 1279 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); 1280 1281 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1282 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1283 1284 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1285 1286 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1287 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1288 1289 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1290 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1291 1292 // Active 1293 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1294 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1295 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1296 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1297 swath_width_pixels_ub_l = 0; 1298 swath_width_pixels_ub_c = 0; 1299 scaler_rec_in_width_l = 0; 1300 scaler_rec_in_width_c = 0; 1301 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1302 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1303 1304 if (mode_422) { 1305 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element 1306 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1307 } else { 1308 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1309 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1310 } 1311 1312 hscale_pixel_rate_l = 0.; 1313 hscale_pixel_rate_c = 0.; 1314 min_hratio_fact_l = 1.0; 1315 min_hratio_fact_c = 1.0; 1316 1317 if (hratio_l <= 1) 1318 min_hratio_fact_l = 2.0; 1319 else if (htaps_l <= 6) { 1320 if ((hratio_l * 2.0) > 4.0) 1321 min_hratio_fact_l = 4.0; 1322 else 1323 min_hratio_fact_l = hratio_l * 2.0; 1324 } else { 1325 if (hratio_l > 4.0) 1326 min_hratio_fact_l = 4.0; 1327 else 1328 min_hratio_fact_l = hratio_l; 1329 } 1330 1331 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1332 1333 if (hratio_c <= 1) 1334 min_hratio_fact_c = 2.0; 1335 else if (htaps_c <= 6) { 1336 if ((hratio_c * 2.0) > 4.0) 1337 min_hratio_fact_c = 4.0; 1338 else 1339 min_hratio_fact_c = hratio_c * 2.0; 1340 } else { 1341 if (hratio_c > 4.0) 1342 min_hratio_fact_c = 4.0; 1343 else 1344 min_hratio_fact_c = hratio_c; 1345 } 1346 1347 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1348 1349 refcyc_per_line_delivery_pre_l = 0.; 1350 refcyc_per_line_delivery_pre_c = 0.; 1351 refcyc_per_line_delivery_l = 0.; 1352 refcyc_per_line_delivery_c = 0.; 1353 1354 refcyc_per_req_delivery_pre_l = 0.; 1355 refcyc_per_req_delivery_pre_c = 0.; 1356 refcyc_per_req_delivery_l = 0.; 1357 refcyc_per_req_delivery_c = 0.; 1358 1359 full_recout_width = 0; 1360 // In ODM 1361 if (src->is_hsplit) { 1362 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1363 // combine, you MUST specify the full_recout_width...according to Oswin 1364 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1365 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1366 __func__); 1367 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1368 } else 1369 full_recout_width = dst->full_recout_width; 1370 } else 1371 full_recout_width = dst->recout_width; 1372 1373 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1374 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1375 refclk_freq_in_mhz, 1376 pclk_freq_in_mhz, 1377 dst->odm_combine, 1378 full_recout_width, 1379 dst->hactive, 1380 vratio_pre_l, 1381 hscale_pixel_rate_l, 1382 swath_width_pixels_ub_l, 1383 1); // per line 1384 1385 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, 1386 refclk_freq_in_mhz, 1387 pclk_freq_in_mhz, 1388 dst->odm_combine, 1389 full_recout_width, 1390 dst->hactive, 1391 vratio_l, 1392 hscale_pixel_rate_l, 1393 swath_width_pixels_ub_l, 1394 1); // per line 1395 1396 dml_print("DML_DLG: %s: full_recout_width = %d\n", 1397 __func__, 1398 full_recout_width); 1399 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1400 __func__, 1401 hscale_pixel_rate_l); 1402 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1403 __func__, 1404 refcyc_per_line_delivery_pre_l); 1405 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1406 __func__, 1407 refcyc_per_line_delivery_l); 1408 1409 if (dual_plane) { 1410 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1411 refclk_freq_in_mhz, 1412 pclk_freq_in_mhz, 1413 dst->odm_combine, 1414 full_recout_width, 1415 dst->hactive, 1416 vratio_pre_c, 1417 hscale_pixel_rate_c, 1418 swath_width_pixels_ub_c, 1419 1); // per line 1420 1421 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, 1422 refclk_freq_in_mhz, 1423 pclk_freq_in_mhz, 1424 dst->odm_combine, 1425 full_recout_width, 1426 dst->hactive, 1427 vratio_c, 1428 hscale_pixel_rate_c, 1429 swath_width_pixels_ub_c, 1430 1); // per line 1431 1432 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1433 __func__, 1434 refcyc_per_line_delivery_pre_c); 1435 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1436 __func__, 1437 refcyc_per_line_delivery_c); 1438 } 1439 1440 // smehta: this is a hack added until we get the real dml, sorry, need to make progress 1441 if (src->dynamic_metadata_enable && src->gpuvm) { 1442 unsigned int levels = mode_lib->ip.gpuvm_max_page_table_levels; 1443 double ref_cycles; 1444 1445 if (src->hostvm) 1446 levels = levels * (mode_lib->ip.hostvm_max_page_table_levels+1); 1447 1448 ref_cycles = (levels * mode_lib->soc.urgent_latency_vm_data_only_us) * refclk_freq_in_mhz; 1449 dml_print("BENyamin: dst_y_prefetch = %f %d %f %f \n", 1450 ref_cycles, levels, mode_lib->soc.urgent_latency_vm_data_only_us, refclk_freq_in_mhz); 1451 disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int) ref_cycles; 1452 } 1453 dml_print("BENyamin: dmdta_en vm = %d %d \n", 1454 src->dynamic_metadata_enable, src->vm); 1455 // TTU - Luma / Chroma 1456 if (access_dir) { // vertical access 1457 scaler_rec_in_width_l = vp_height_l; 1458 scaler_rec_in_width_c = vp_height_c; 1459 } else { 1460 scaler_rec_in_width_l = vp_width_l; 1461 scaler_rec_in_width_c = vp_width_c; 1462 } 1463 1464 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1465 refclk_freq_in_mhz, 1466 pclk_freq_in_mhz, 1467 dst->odm_combine, 1468 full_recout_width, 1469 dst->hactive, 1470 vratio_pre_l, 1471 hscale_pixel_rate_l, 1472 scaler_rec_in_width_l, 1473 req_per_swath_ub_l); // per req 1474 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, 1475 refclk_freq_in_mhz, 1476 pclk_freq_in_mhz, 1477 dst->odm_combine, 1478 full_recout_width, 1479 dst->hactive, 1480 vratio_l, 1481 hscale_pixel_rate_l, 1482 scaler_rec_in_width_l, 1483 req_per_swath_ub_l); // per req 1484 1485 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1486 __func__, 1487 refcyc_per_req_delivery_pre_l); 1488 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1489 __func__, 1490 refcyc_per_req_delivery_l); 1491 1492 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1493 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1494 1495 if (dual_plane) { 1496 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1497 refclk_freq_in_mhz, 1498 pclk_freq_in_mhz, 1499 dst->odm_combine, 1500 full_recout_width, 1501 dst->hactive, 1502 vratio_pre_c, 1503 hscale_pixel_rate_c, 1504 scaler_rec_in_width_c, 1505 req_per_swath_ub_c); // per req 1506 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, 1507 refclk_freq_in_mhz, 1508 pclk_freq_in_mhz, 1509 dst->odm_combine, 1510 full_recout_width, 1511 dst->hactive, 1512 vratio_c, 1513 hscale_pixel_rate_c, 1514 scaler_rec_in_width_c, 1515 req_per_swath_ub_c); // per req 1516 1517 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1518 __func__, 1519 refcyc_per_req_delivery_pre_c); 1520 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1521 __func__, 1522 refcyc_per_req_delivery_c); 1523 1524 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1525 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1526 } 1527 1528 // TTU - Cursor 1529 refcyc_per_req_delivery_pre_cur0 = 0.0; 1530 refcyc_per_req_delivery_cur0 = 0.0; 1531 if (src->num_cursors > 0) { 1532 calculate_ttu_cursor(mode_lib, 1533 &refcyc_per_req_delivery_pre_cur0, 1534 &refcyc_per_req_delivery_cur0, 1535 refclk_freq_in_mhz, 1536 ref_freq_to_pix_freq, 1537 hscale_pixel_rate_l, 1538 scl->hscl_ratio, 1539 vratio_pre_l, 1540 vratio_l, 1541 src->cur0_src_width, 1542 (enum cursor_bpp)(src->cur0_bpp)); 1543 } 1544 1545 refcyc_per_req_delivery_pre_cur1 = 0.0; 1546 refcyc_per_req_delivery_cur1 = 0.0; 1547 if (src->num_cursors > 1) { 1548 calculate_ttu_cursor(mode_lib, 1549 &refcyc_per_req_delivery_pre_cur1, 1550 &refcyc_per_req_delivery_cur1, 1551 refclk_freq_in_mhz, 1552 ref_freq_to_pix_freq, 1553 hscale_pixel_rate_l, 1554 scl->hscl_ratio, 1555 vratio_pre_l, 1556 vratio_l, 1557 src->cur1_src_width, 1558 (enum cursor_bpp)(src->cur1_bpp)); 1559 } 1560 1561 // TTU - Misc 1562 // all hard-coded 1563 1564 // Assignment to register structures 1565 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1566 ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); 1567 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1568 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); 1569 disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); 1570 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); 1571 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); 1572 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); 1573 disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); 1574 1575 disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); 1576 disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); 1577 1578 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank); 1579 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank); 1580 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip); 1581 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip); 1582 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1583 (unsigned int)(dst_y_per_row_vblank * (double)htotal 1584 * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l); 1585 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); 1586 1587 if (dual_plane) { 1588 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank 1589 * (double)htotal * ref_freq_to_pix_freq 1590 / (double)dpte_groups_per_row_ub_c); 1591 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1592 < (unsigned int)dml_pow(2, 13)); 1593 } 1594 1595 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1596 (unsigned int)(dst_y_per_row_vblank * (double)htotal 1597 * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_l); 1598 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); 1599 1600 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1601 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1602 1603 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)(dst_y_per_row_flip * htotal 1604 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1605 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)(dst_y_per_row_flip * htotal 1606 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1607 1608 if (dual_plane) { 1609 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)(dst_y_per_row_flip 1610 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1611 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)(dst_y_per_row_flip 1612 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1613 } 1614 1615 disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; 1616 disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; 1617 disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); 1618 disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); 1619 1620 // Clamp to max for now 1621 if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) 1622 disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; 1623 1624 if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) 1625 disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; 1626 1627 if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) 1628 disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; 1629 1630 if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) 1631 disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; 1632 1633 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)((double)dpte_row_height_l 1634 / (double)vratio_l * dml_pow(2, 2)); 1635 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); 1636 1637 if (dual_plane) { 1638 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)((double)dpte_row_height_c 1639 / (double)vratio_c * dml_pow(2, 2)); 1640 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int)dml_pow(2, 17)) { 1641 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1642 __func__, 1643 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1644 (unsigned int)dml_pow(2, 17) - 1); 1645 } 1646 } 1647 1648 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)((double)meta_row_height_l 1649 / (double)vratio_l * dml_pow(2, 2)); 1650 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); 1651 1652 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1653 1654 dml_print("DML: Trow: %fus\n", line_time_in_us * (double)dpte_row_height_l / (double)vratio_l); 1655 1656 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)((double)dpte_row_height_l 1657 / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq 1658 / (double)dpte_groups_per_row_ub_l); 1659 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23)) 1660 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1661 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)((double)meta_row_height_l 1662 / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq 1663 / (double)meta_chunks_per_row_ub_l); 1664 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23)) 1665 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1666 1667 if (dual_plane) { 1668 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1669 (unsigned int)((double)dpte_row_height_c / (double)vratio_c 1670 * (double)htotal * ref_freq_to_pix_freq 1671 / (double)dpte_groups_per_row_ub_c); 1672 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23)) 1673 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1674 1675 // TODO: Is this the right calculation? Does htotal need to be halved? 1676 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1677 (unsigned int)((double)meta_row_height_c / (double)vratio_c 1678 * (double)htotal * ref_freq_to_pix_freq 1679 / (double)meta_chunks_per_row_ub_c); 1680 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23)) 1681 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1682 } 1683 1684 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_l, 1685 1); 1686 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int)dml_floor(refcyc_per_line_delivery_l, 1687 1); 1688 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); 1689 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); 1690 1691 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_c, 1692 1); 1693 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int)dml_floor(refcyc_per_line_delivery_c, 1694 1); 1695 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); 1696 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); 1697 1698 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1699 disp_dlg_regs->dst_y_offset_cur0 = 0; 1700 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1701 disp_dlg_regs->dst_y_offset_cur1 = 0; 1702 1703 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1704 1705 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l 1706 * dml_pow(2, 10)); 1707 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l 1708 * dml_pow(2, 10)); 1709 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c 1710 * dml_pow(2, 10)); 1711 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c 1712 * dml_pow(2, 10)); 1713 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1714 (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1715 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 1716 * dml_pow(2, 10)); 1717 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1718 (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1719 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 1720 * dml_pow(2, 10)); 1721 disp_ttu_regs->qos_level_low_wm = 0; 1722 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1723 disp_ttu_regs->qos_level_high_wm = (unsigned int)(4.0 * (double)htotal 1724 * ref_freq_to_pix_freq); 1725 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 1726 1727 disp_ttu_regs->qos_level_flip = 14; 1728 disp_ttu_regs->qos_level_fixed_l = 8; 1729 disp_ttu_regs->qos_level_fixed_c = 8; 1730 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1731 disp_ttu_regs->qos_ramp_disable_l = 0; 1732 disp_ttu_regs->qos_ramp_disable_c = 0; 1733 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1734 1735 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1736 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1737 1738 print__ttu_regs_st(mode_lib, disp_ttu_regs); 1739 print__dlg_regs_st(mode_lib, disp_dlg_regs); 1740} 1741 1742void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 1743 display_dlg_regs_st *dlg_regs, 1744 display_ttu_regs_st *ttu_regs, 1745 const display_e2e_pipe_params_st *e2e_pipe_param, 1746 const unsigned int num_pipes, 1747 const unsigned int pipe_idx, 1748 const bool cstate_en, 1749 const bool pstate_en, 1750 const bool vm_en, 1751 const bool ignore_viewport_pos, 1752 const bool immediate_flip_support) 1753{ 1754 display_rq_params_st rq_param = { 0 }; 1755 display_dlg_sys_params_st dlg_sys_param = { 0 }; 1756 1757 // Get watermark and Tex. 1758 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1759 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, 1760 e2e_pipe_param, 1761 num_pipes); 1762 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1763 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1764 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1765 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1766 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, 1767 e2e_pipe_param, 1768 num_pipes); 1769 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, 1770 e2e_pipe_param, 1771 num_pipes); 1772 1773 print__dlg_sys_params_st(mode_lib, &dlg_sys_param); 1774 1775 // system parameter calculation done 1776 1777 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1778 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); 1779 dml_rq_dlg_get_dlg_params(mode_lib, 1780 e2e_pipe_param, 1781 num_pipes, 1782 pipe_idx, 1783 dlg_regs, 1784 ttu_regs, 1785 rq_param.dlg, 1786 dlg_sys_param, 1787 cstate_en, 1788 pstate_en, 1789 vm_en, 1790 ignore_viewport_pos, 1791 immediate_flip_support); 1792 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1793} 1794 1795