1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "../display_mode_lib.h" 28#include "../display_mode_vba.h" 29#include "../dml_inline_defs.h" 30#include "display_rq_dlg_calc_32.h" 31 32static bool is_dual_plane(enum source_format_class source_format) 33{ 34 bool ret_val = 0; 35 36 if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) 37 || (source_format == dm_rgbe_alpha)) 38 ret_val = 1; 39 40 return ret_val; 41} 42 43void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, 44 struct display_mode_lib *mode_lib, 45 const display_e2e_pipe_params_st *e2e_pipe_param, 46 const unsigned int num_pipes, 47 const unsigned int pipe_idx) 48{ 49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 50 bool dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 51 double stored_swath_l_bytes; 52 double stored_swath_c_bytes; 53 bool is_phantom_pipe; 54 uint32_t pixel_chunk_bytes = 0; 55 uint32_t min_pixel_chunk_bytes = 0; 56 uint32_t meta_chunk_bytes = 0; 57 uint32_t min_meta_chunk_bytes = 0; 58 uint32_t dpte_group_bytes = 0; 59 uint32_t mpte_group_bytes = 0; 60 61 uint32_t p1_pixel_chunk_bytes = 0; 62 uint32_t p1_min_pixel_chunk_bytes = 0; 63 uint32_t p1_meta_chunk_bytes = 0; 64 uint32_t p1_min_meta_chunk_bytes = 0; 65 uint32_t p1_dpte_group_bytes = 0; 66 uint32_t p1_mpte_group_bytes = 0; 67 68 unsigned int detile_buf_size_in_bytes; 69 unsigned int detile_buf_plane1_addr; 70 unsigned int pte_row_height_linear; 71 72 memset(rq_regs, 0, sizeof(*rq_regs)); 73 74 dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 75 76 pixel_chunk_bytes = get_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA 77 min_pixel_chunk_bytes = get_min_pixel_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA 78 79 if (pixel_chunk_bytes == 64 * 1024) 80 min_pixel_chunk_bytes = 0; 81 82 meta_chunk_bytes = get_meta_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; // From VBA 83 min_meta_chunk_bytes = get_min_meta_chunk_size_in_byte(mode_lib, e2e_pipe_param, num_pipes); // From VBA 84 85 dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 86 mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 87 88 p1_pixel_chunk_bytes = pixel_chunk_bytes; 89 p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; 90 p1_meta_chunk_bytes = meta_chunk_bytes; 91 p1_min_meta_chunk_bytes = min_meta_chunk_bytes; 92 p1_dpte_group_bytes = dpte_group_bytes; 93 p1_mpte_group_bytes = mpte_group_bytes; 94 95 if ((enum source_format_class) src->source_format == dm_rgbe_alpha) 96 p1_pixel_chunk_bytes = get_alpha_pixel_chunk_size_in_kbyte(mode_lib, e2e_pipe_param, num_pipes) * 1024; 97 98 rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; 99 rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; 100 101 if (min_pixel_chunk_bytes == 0) 102 rq_regs->rq_regs_l.min_chunk_size = 0; 103 else 104 rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1; 105 106 if (p1_min_pixel_chunk_bytes == 0) 107 rq_regs->rq_regs_c.min_chunk_size = 0; 108 else 109 rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; 110 111 rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; 112 rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; 113 114 if (min_meta_chunk_bytes == 0) 115 rq_regs->rq_regs_l.min_meta_chunk_size = 0; 116 else 117 rq_regs->rq_regs_l.min_meta_chunk_size = dml_log2(min_meta_chunk_bytes) - 6 + 1; 118 119 if (p1_min_meta_chunk_bytes == 0) 120 rq_regs->rq_regs_c.min_meta_chunk_size = 0; 121 else 122 rq_regs->rq_regs_c.min_meta_chunk_size = dml_log2(p1_min_meta_chunk_bytes) - 6 + 1; 123 124 rq_regs->rq_regs_l.dpte_group_size = dml_log2(dpte_group_bytes) - 6; 125 rq_regs->rq_regs_l.mpte_group_size = dml_log2(mpte_group_bytes) - 6; 126 rq_regs->rq_regs_c.dpte_group_size = dml_log2(p1_dpte_group_bytes) - 6; 127 rq_regs->rq_regs_c.mpte_group_size = dml_log2(p1_mpte_group_bytes) - 6; 128 129 detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; 130 detile_buf_plane1_addr = 0; 131 pte_row_height_linear = get_dpte_row_height_linear_l(mode_lib, e2e_pipe_param, num_pipes, 132 pipe_idx); 133 134 if (src->sw_mode == dm_sw_linear) 135 ASSERT(pte_row_height_linear >= 8); 136 137 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(pte_row_height_linear), 1) - 3; 138 139 if (dual_plane) { 140 unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, 141 num_pipes, pipe_idx); 142 ; 143 if (src->sw_mode == dm_sw_linear) 144 ASSERT(p1_pte_row_height_linear >= 8); 145 146 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(p1_pte_row_height_linear), 1) - 3; 147 } 148 149 rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 150 rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 151 152 // FIXME: take the max between luma, chroma chunk size? 153 // okay for now, as we are setting pixel_chunk_bytes to 8kb anyways 154 if (pixel_chunk_bytes >= 32 * 1024 || (dual_plane && p1_pixel_chunk_bytes >= 32 * 1024)) { //32kb 155 rq_regs->drq_expansion_mode = 0; 156 } else { 157 rq_regs->drq_expansion_mode = 2; 158 } 159 rq_regs->prq_expansion_mode = 1; 160 rq_regs->mrq_expansion_mode = 1; 161 rq_regs->crq_expansion_mode = 1; 162 163 stored_swath_l_bytes = get_det_stored_buffer_size_l_bytes(mode_lib, e2e_pipe_param, num_pipes, 164 pipe_idx); 165 stored_swath_c_bytes = get_det_stored_buffer_size_c_bytes(mode_lib, e2e_pipe_param, num_pipes, 166 pipe_idx); 167 is_phantom_pipe = get_is_phantom_pipe(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 168 169 // Note: detile_buf_plane1_addr is in unit of 1KB 170 if (dual_plane) { 171 if (is_phantom_pipe) { 172 detile_buf_plane1_addr = ((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma 173 } else { 174 if (stored_swath_l_bytes / stored_swath_c_bytes <= 1.5) { 175 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma 176#ifdef __DML_RQ_DLG_CALC_DEBUG__ 177 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", 178 __func__, detile_buf_plane1_addr); 179#endif 180 } else { 181 detile_buf_plane1_addr = 182 dml_round_to_multiple( 183 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 184 1024, 0) / 1024.0; // 2/3 to luma 185#ifdef __DML_RQ_DLG_CALC_DEBUG__ 186 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", 187 __func__, detile_buf_plane1_addr); 188#endif 189 } 190 } 191 } 192 rq_regs->plane1_base_address = detile_buf_plane1_addr; 193 194#ifdef __DML_RQ_DLG_CALC_DEBUG__ 195 dml_print("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe); 196 dml_print("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes); 197 dml_print("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes); 198 dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes); 199 dml_print("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr); 200 dml_print("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs->plane1_base_address); 201#endif 202 print__rq_regs_st(mode_lib, rq_regs); 203 dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 204} 205 206void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 207 display_dlg_regs_st *dlg_regs, 208 display_ttu_regs_st *ttu_regs, 209 display_e2e_pipe_params_st *e2e_pipe_param, 210 const unsigned int num_pipes, 211 const unsigned int pipe_idx) 212{ 213 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 214 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 215 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 216 double refcyc_per_req_delivery_pre_cur0 = 0.; 217 double refcyc_per_req_delivery_cur0 = 0.; 218 double refcyc_per_req_delivery_pre_c = 0.; 219 double refcyc_per_req_delivery_c = 0.; 220 double refcyc_per_req_delivery_pre_l; 221 double refcyc_per_req_delivery_l; 222 double refcyc_per_line_delivery_pre_c = 0.; 223 double refcyc_per_line_delivery_c = 0.; 224 double refcyc_per_line_delivery_pre_l; 225 double refcyc_per_line_delivery_l; 226 double min_ttu_vblank; 227 double vratio_pre_l; 228 double vratio_pre_c; 229 unsigned int min_dst_y_next_start; 230 unsigned int htotal = dst->htotal; 231 unsigned int hblank_end = dst->hblank_end; 232 unsigned int vblank_end = dst->vblank_end; 233 bool interlaced = dst->interlaced; 234 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 235 unsigned int vready_after_vcount0; 236 double refclk_freq_in_mhz = clks->refclk_mhz; 237 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 238 bool dual_plane = 0; 239 unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX]; 240 unsigned int dst_x_after_scaler; 241 unsigned int dst_y_after_scaler; 242 double dst_y_prefetch; 243 double dst_y_per_vm_vblank; 244 double dst_y_per_row_vblank; 245 double dst_y_per_vm_flip; 246 double dst_y_per_row_flip; 247 double max_dst_y_per_vm_vblank = 32.0; 248 double max_dst_y_per_row_vblank = 16.0; 249 double dst_y_per_pte_row_nom_l; 250 double dst_y_per_pte_row_nom_c; 251 double dst_y_per_meta_row_nom_l; 252 double dst_y_per_meta_row_nom_c; 253 double refcyc_per_pte_group_nom_l; 254 double refcyc_per_pte_group_nom_c; 255 double refcyc_per_pte_group_vblank_l; 256 double refcyc_per_pte_group_vblank_c; 257 double refcyc_per_pte_group_flip_l; 258 double refcyc_per_pte_group_flip_c; 259 double refcyc_per_meta_chunk_nom_l; 260 double refcyc_per_meta_chunk_nom_c; 261 double refcyc_per_meta_chunk_vblank_l; 262 double refcyc_per_meta_chunk_vblank_c; 263 double refcyc_per_meta_chunk_flip_l; 264 double refcyc_per_meta_chunk_flip_c; 265 266 memset(dlg_regs, 0, sizeof(*dlg_regs)); 267 memset(ttu_regs, 0, sizeof(*ttu_regs)); 268 dml_print("DML_DLG::%s: Calculation for pipe[%d] starts, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 269 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 270 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 271 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); 272 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 273 ASSERT(ref_freq_to_pix_freq < 4.0); 274 275 dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 276 dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 277 dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 278 279 min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 280 min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 281 282 dml_print("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, min_ttu_vblank); 283 dml_print("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, min_dst_y_next_start); 284 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, ref_freq_to_pix_freq); 285 286 dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); 287 288 vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, 289 pipe_idx); // From VBA 290 dlg_regs->vready_after_vcount0 = vready_after_vcount0; 291 292 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0); 293 294 dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); 295 dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1); 296 297 // do some adjustment on the dst_after scaler to account for odm combine mode 298 dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n", __func__, dst_x_after_scaler); 299 dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n", __func__, dst_y_after_scaler); 300 301 // need to figure out which side of odm combine we're in 302 if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { 303 // figure out which pipes go together 304 bool visited[DC__NUM_PIPES__MAX]; 305 unsigned int i, j, k; 306 307 for (k = 0; k < num_pipes; ++k) { 308 visited[k] = false; 309 pipe_index_in_combine[k] = 0; 310 } 311 312 for (i = 0; i < num_pipes; i++) { 313 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { 314 315 unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; 316 unsigned int grp_idx = 0; 317 318 for (j = i; j < num_pipes; j++) { 319 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp 320 && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { 321 pipe_index_in_combine[j] = grp_idx; 322 dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", 323 __func__, j, grp, grp_idx); 324 grp_idx++; 325 visited[j] = true; 326 } 327 } 328 } 329 } 330 } 331 332 if (dst->odm_combine == dm_odm_combine_mode_disabled) { 333 // FIXME how about ODM split?? 334 dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq); 335 } else { 336 if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) { 337 // TODO: We should really check that 4to1 is supported before setting it to 4 338 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); 339 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; 340 341 dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end 342 + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); 343 } 344 } 345 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 346 347 dml_print("DML_DLG: %s: htotal= %d\n", __func__, htotal); 348 dml_print("DML_DLG: %s: dst_x_after_scaler[%d]= %d\n", __func__, pipe_idx, dst_x_after_scaler); 349 dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n", __func__, pipe_idx, dst_y_after_scaler); 350 351 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 352 // From VBA 353 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 354 // From VBA 355 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 356 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 357 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 358 359 // magic! 360 if (htotal <= 75) { 361 max_dst_y_per_vm_vblank = 100.0; 362 max_dst_y_per_row_vblank = 100.0; 363 } 364 365 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 366 dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip); 367 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip); 368 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 369 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 370 371 ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); 372 ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank); 373 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 374 375 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 376 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 377 378 dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l); 379 dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c); 380 381 // Active 382 refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 383 refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 384 pipe_idx) * refclk_freq_in_mhz; // From VBA 385 386 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l); 387 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, refcyc_per_line_delivery_l); 388 389 if (dual_plane) { 390 refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, 391 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 392 refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 393 pipe_idx) * refclk_freq_in_mhz; // From VBA 394 395 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 396 __func__, refcyc_per_line_delivery_pre_c); 397 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 398 __func__, refcyc_per_line_delivery_c); 399 } 400 401 if (src->dynamic_metadata_enable && src->gpuvm) 402 dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, 403 pipe_idx) * refclk_freq_in_mhz; // From VBA 404 405 dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) 406 * refclk_freq_in_mhz; // From VBA 407 408 refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 409 refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 410 pipe_idx) * refclk_freq_in_mhz; // From VBA 411 412 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l); 413 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, refcyc_per_req_delivery_l); 414 415 if (dual_plane) { 416 refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, 417 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 418 refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 419 pipe_idx) * refclk_freq_in_mhz; // From VBA 420 421 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 422 __func__, refcyc_per_req_delivery_pre_c); 423 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, refcyc_per_req_delivery_c); 424 } 425 426 // TTU - Cursor 427 ASSERT(src->num_cursors <= 1); 428 if (src->num_cursors > 0) { 429 refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, 430 e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 431 refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, 432 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 433 434 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", 435 __func__, refcyc_per_req_delivery_pre_cur0); 436 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f\n", 437 __func__, refcyc_per_req_delivery_cur0); 438 } 439 440 // Assign to register structures 441 dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); 442 ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 443 444 dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 445 dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 446 dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 447 dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 448 dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 449 dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 450 dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 451 452 dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 453 dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 454 455 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_vblank); 456 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, dlg_regs->dst_y_per_row_vblank); 457 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_vm_flip); 458 dml_print("DML_DLG: %s: dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, dlg_regs->dst_y_per_row_flip); 459 460 dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, 461 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 462 dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, 463 pipe_idx) * refclk_freq_in_mhz; // From VBA 464 dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, 465 pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 466 dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, 467 pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA 468 469 // From VBA 470 dst_y_per_pte_row_nom_l = get_dst_y_per_pte_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 471 // From VBA 472 dst_y_per_pte_row_nom_c = get_dst_y_per_pte_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 473 // From VBA 474 dst_y_per_meta_row_nom_l = get_dst_y_per_meta_row_nom_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 475 // From VBA 476 dst_y_per_meta_row_nom_c = get_dst_y_per_meta_row_nom_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 477 478 refcyc_per_pte_group_nom_l = get_refcyc_per_pte_group_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 479 pipe_idx) * refclk_freq_in_mhz; // From VBA 480 refcyc_per_pte_group_nom_c = get_refcyc_per_pte_group_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 481 pipe_idx) * refclk_freq_in_mhz; // From VBA 482 refcyc_per_pte_group_vblank_l = get_refcyc_per_pte_group_vblank_l_in_us(mode_lib, e2e_pipe_param, 483 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 484 refcyc_per_pte_group_vblank_c = get_refcyc_per_pte_group_vblank_c_in_us(mode_lib, e2e_pipe_param, 485 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 486 refcyc_per_pte_group_flip_l = get_refcyc_per_pte_group_flip_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 487 pipe_idx) * refclk_freq_in_mhz; // From VBA 488 refcyc_per_pte_group_flip_c = get_refcyc_per_pte_group_flip_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 489 pipe_idx) * refclk_freq_in_mhz; // From VBA 490 491 refcyc_per_meta_chunk_nom_l = get_refcyc_per_meta_chunk_nom_l_in_us(mode_lib, e2e_pipe_param, num_pipes, 492 pipe_idx) * refclk_freq_in_mhz; // From VBA 493 refcyc_per_meta_chunk_nom_c = get_refcyc_per_meta_chunk_nom_c_in_us(mode_lib, e2e_pipe_param, num_pipes, 494 pipe_idx) * refclk_freq_in_mhz; // From VBA 495 refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param, 496 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 497 refcyc_per_meta_chunk_vblank_c = get_refcyc_per_meta_chunk_vblank_c_in_us(mode_lib, e2e_pipe_param, 498 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 499 refcyc_per_meta_chunk_flip_l = get_refcyc_per_meta_chunk_flip_l_in_us(mode_lib, e2e_pipe_param, 500 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 501 refcyc_per_meta_chunk_flip_c = get_refcyc_per_meta_chunk_flip_c_in_us(mode_lib, e2e_pipe_param, 502 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 503 504 dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2); 505 dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2); 506 dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2); 507 dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2); 508 dlg_regs->refcyc_per_pte_group_nom_l = refcyc_per_pte_group_nom_l; 509 dlg_regs->refcyc_per_pte_group_nom_c = refcyc_per_pte_group_nom_c; 510 dlg_regs->refcyc_per_pte_group_vblank_l = refcyc_per_pte_group_vblank_l; 511 dlg_regs->refcyc_per_pte_group_vblank_c = refcyc_per_pte_group_vblank_c; 512 dlg_regs->refcyc_per_pte_group_flip_l = refcyc_per_pte_group_flip_l; 513 dlg_regs->refcyc_per_pte_group_flip_c = refcyc_per_pte_group_flip_c; 514 dlg_regs->refcyc_per_meta_chunk_nom_l = refcyc_per_meta_chunk_nom_l; 515 dlg_regs->refcyc_per_meta_chunk_nom_c = refcyc_per_meta_chunk_nom_c; 516 dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; 517 dlg_regs->refcyc_per_meta_chunk_vblank_c = refcyc_per_meta_chunk_vblank_c; 518 dlg_regs->refcyc_per_meta_chunk_flip_l = refcyc_per_meta_chunk_flip_l; 519 dlg_regs->refcyc_per_meta_chunk_flip_c = refcyc_per_meta_chunk_flip_c; 520 dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1); 521 dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1); 522 dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1); 523 dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1); 524 525 dlg_regs->chunk_hdl_adjust_cur0 = 3; 526 dlg_regs->dst_y_offset_cur0 = 0; 527 dlg_regs->chunk_hdl_adjust_cur1 = 3; 528 dlg_regs->dst_y_offset_cur1 = 0; 529 530 dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 531 532 ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10)); 533 ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10)); 534 ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10)); 535 ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10)); 536 ttu_regs->refcyc_per_req_delivery_pre_cur0 = 537 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 538 ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10)); 539 ttu_regs->refcyc_per_req_delivery_pre_cur1 = 0; 540 ttu_regs->refcyc_per_req_delivery_cur1 = 0; 541 ttu_regs->qos_level_low_wm = 0; 542 543 ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq); 544 545 ttu_regs->qos_level_flip = 14; 546 ttu_regs->qos_level_fixed_l = 8; 547 ttu_regs->qos_level_fixed_c = 8; 548 ttu_regs->qos_level_fixed_cur0 = 8; 549 ttu_regs->qos_ramp_disable_l = 0; 550 ttu_regs->qos_ramp_disable_c = 0; 551 ttu_regs->qos_ramp_disable_cur0 = 0; 552 ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 553 554 // CHECK for HW registers' range, assert or clamp 555 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 556 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 557 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 558 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 559 if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23)) 560 dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; 561 562 if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23)) 563 dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; 564 565 if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23)) 566 dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; 567 568 if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23)) 569 dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; 570 571 ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); 572 ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)); 573 ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17)); 574 if (dual_plane) { 575 if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 576 // FIXME what so special about chroma, can we just assert? 577 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", 578 __func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1); 579 } 580 } 581 ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17)); 582 ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17)); 583 584 if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 585 dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 586 if (dual_plane) { 587 if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 588 dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 589 } 590 ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13)); 591 if (dual_plane) { 592 ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13)); 593 } 594 595 if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 596 dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 597 if (dual_plane) { 598 if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 599 dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 600 } 601 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); 602 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13)); 603 ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); 604 ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13)); 605 ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); 606 ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13)); 607 ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 608 ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14)); 609 ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 610 611 print__ttu_regs_st(mode_lib, ttu_regs); 612 print__dlg_regs_st(mode_lib, dlg_regs); 613 dml_print("DML_DLG::%s: Calculation for pipe[%d] done, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 614} 615 616