/linux-master/arch/x86/pci/ |
H A D | ce4100.c | 66 static void reg_write(struct sim_dev_reg *reg, u32 value) function 104 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) 105 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) 106 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) 107 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 108 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 109 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write) 110 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write) 111 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write) 112 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) [all...] |
/linux-master/drivers/firewire/ |
H A D | init_ohci1394_dma.c | 40 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) function 58 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); 75 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); 89 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 114 reg_write(ohci, OHCI1394_BusOptions, bus_options); 117 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); 120 reg_write(ohci, OHCI1394_HCControlSet, 124 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); 127 reg_write(ohci, OHCI1394_LinkControlSet, 131 reg_write(ohc [all...] |
H A D | nosy.c | 214 reg_write(struct pcilynx *lynx, int offset, u32 data) function 228 reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); 239 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20, pcl_bus); 240 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20, 257 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | 475 reg_write(lynx, LINK_INT_STATUS, link_int_status); 485 reg_write(lynx, PCI_INT_STATUS, pci_int_status); 506 reg_write(lynx, PCI_INT_ENABLE, 0); 603 reg_write(lynx, DMA0_CHAN_CTRL, 0); 604 reg_write(lyn [all...] |
H A D | ohci.c | 572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) function 599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 625 reg_write(ohci, OHCI1394_PhyControl, 717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 742 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1079 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1080 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1257 reg_write(ohci, COMMAND_PTR(ctx->regs), 1259 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1260 reg_write(ohc [all...] |
/linux-master/drivers/media/platform/st/stm32/dma2d/ |
H A D | dma2d-hw.c | 24 static inline void reg_write(void __iomem *base, u32 reg, u32 val) function 32 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); 58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); 75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr); 77 reg_write(d->regs, DMA2D_OCOLR_REG, 90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); 105 reg_write(d->regs, DMA2D_FGCOLR_REG, 114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); 129 reg_write( [all...] |
/linux-master/drivers/media/tuners/ |
H A D | qm1d1c0042.c | 64 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) function 107 return reg_write(state, 0x03, state->regs[0x03]); 117 ret = reg_write(state, 0x01, state->regs[0x01]); 119 ret = reg_write(state, 0x05, state->regs[0x05]); 205 ret = reg_write(state, 0x02, val); 213 ret = reg_write(state, 0x06, state->regs[0x06]); 219 ret = reg_write(state, 0x07, state->regs[0x07]); 230 ret = reg_write(state, 0x08, val); 251 ret = reg_write(state, 0x09, state->regs[0x09]); 253 ret = reg_write(stat [all...] |
/linux-master/drivers/media/i2c/ |
H A D | rj54n1cb0c.c | 446 static int reg_write(struct i2c_client *client, const u16 reg, function 472 return reg_write(client, reg, (ret & ~mask) | (data & mask)); 481 ret = reg_write(client, rv->reg, rv->val); 515 ret = reg_write(client, reg_xy, 520 ret = reg_write(client, reg_x, width & 0xff); 522 ret = reg_write(client, reg_y, height & 0xff); 533 int ret = reg_write(client, RJ54N1_INIT_START, 1); 536 ret = reg_write(client, RJ54N1_INIT_START, 0); 725 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff); 727 ret = reg_write(clien [all...] |
H A D | ak881x.c | 40 static int reg_write(struct i2c_client *client, const u8 reg, function 52 return reg_write(client, reg, (ret & ~mask) | (data & mask)); 86 if (reg_write(client, reg->reg, reg->val) < 0) 191 reg_write(client, AK881X_DAC_MODE, dac); 196 reg_write(client, AK881X_DAC_MODE, 0); 287 reg_write(client, AK881X_INTERFACE_MODE, ifmode | (20 << 3));
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/linux-master/drivers/media/pci/tw686x/ |
H A D | tw686x-core.c | 108 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); 109 reg_write(dev, DMA_CMD, dma_cmd); 133 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en); 134 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); 156 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask); 162 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); 300 reg_write(dev, SYS_SOFT_RST, 0x0f); 303 reg_write(dev, SRST[0], 0x3f); 305 reg_write(dev, SRST[1], 0x3f); 308 reg_write(de [all...] |
H A D | tw686x-video.c | 123 reg_write(dev, reg, vc->dma_descs[pb].phys); 168 reg_write(vc->dev, reg, phys); 288 reg_write(dev, reg, desc->phys); 407 reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], fps_map[i]); 599 reg_write(dev, BRIGHT[ch], ctrl->val & 0xff); 603 reg_write(dev, CONTRAST[ch], ctrl->val); 607 reg_write(dev, SAT_U[ch], ctrl->val); 608 reg_write(dev, SAT_V[ch], ctrl->val); 612 reg_write(dev, HUE[ch], ctrl->val & 0xff); 725 reg_write(v [all...] |
H A D | tw686x-audio.c | 74 reg_write(dev, reg, next->dma); 159 reg_write(dev, AUDIO_CONTROL2, reg); 170 reg_write(dev, AUDIO_CONTROL1, reg); 198 reg_write(dev, ADMA_P_ADDR[ac->ch], p_buf->dma); 199 reg_write(dev, ADMA_B_ADDR[ac->ch], b_buf->dma); 338 reg_write(dev, reg, ac->dma_descs[pb].phys); 352 reg_write(dev, DMA_CMD, dma_cmd & ~0xff00); 353 reg_write(dev, DMA_CHANNEL_ENABLE, dma_ch_mask & ~0xff00); 369 reg_write(dev, AUDIO_CONTROL1, BIT(0));
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/linux-master/drivers/base/regmap/ |
H A D | regmap-mmio.c | 25 void (*reg_write)(struct regmap_mmio_context *ctx, member in struct:regmap_mmio_context 162 ctx->reg_write(ctx, reg, val); 399 .reg_write = regmap_mmio_write, 451 ctx->reg_write = regmap_mmio_iowrite8; 454 ctx->reg_write = regmap_mmio_write8_relaxed; 457 ctx->reg_write = regmap_mmio_write8; 463 ctx->reg_write = regmap_mmio_iowrite16le; 466 ctx->reg_write = regmap_mmio_write16le_relaxed; 469 ctx->reg_write = regmap_mmio_write16le; 475 ctx->reg_write [all...] |
H A D | regmap-fsi.c | 36 .reg_write = regmap_fsi32_reg_write, 61 .reg_write = regmap_fsi32le_reg_write, 90 .reg_write = regmap_fsi16_reg_write, 119 .reg_write = regmap_fsi16le_reg_write, 148 .reg_write = regmap_fsi8_reg_write,
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H A D | regmap-mdio.c | 41 .reg_write = regmap_mdio_c22_write, 81 .reg_write = regmap_mdio_c45_write,
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/linux-master/drivers/net/dsa/ |
H A D | mv88e6060.c | 22 static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) function 63 ret = reg_write(priv, REG_PORT(i), PORT_CONTROL, 73 ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, 105 ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL, 112 return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, 129 ret = reg_write(priv, addr, PORT_CONTROL, 143 ret = reg_write(priv, addr, PORT_VLAN_MAP, 156 return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); 174 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); 178 ret = reg_write(pri [all...] |
/linux-master/drivers/media/dvb-frontends/ |
H A D | zd1301_demod.h | 17 * @reg_priv: First argument of reg_read and reg_write callbacks. 19 * @reg_write: Register write callback. 24 int (*reg_write)(void *, u16, u8); member in struct:zd1301_demod_platform_data
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/linux-master/drivers/net/dsa/realtek/ |
H A D | rtl83xx.h | 8 int (*reg_write)(void *ctx, u32 reg, u32 val); member in struct:realtek_interface_info
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/linux-master/drivers/soundwire/ |
H A D | qcom.c | 210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); member in struct:qcom_swrm_ctrl 455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); 495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); 512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 514 ctrl->reg_write(ctrl, 714 ctrl->reg_write(ctrl, 741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 757 ctrl->reg_write(ctrl, 767 ctrl->reg_write(ctr [all...] |
/linux-master/drivers/watchdog/ |
H A D | stm32_iwdg.c | 83 static inline void reg_write(void __iomem *base, u32 reg, u32 val) function 107 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); 110 reg_write(wdt->regs, IWDG_PR, iwdg_pr); 111 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr); 112 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE); 124 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); 136 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
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/linux-master/drivers/media/pci/sta2x11/ |
H A D | sta2x11_vip.c | 204 static inline void reg_write(struct sta2x11_vip *vip, unsigned int reg, u32 val) function 223 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) | DVP_CTL_ENA); 225 reg_write(vip, DVP_VTP, (u32)vip_buf->dma); 226 reg_write(vip, DVP_VBP, (u32)vip_buf->dma + offset); 338 reg_write(vip, DVP_ITM, DVP_IT_VSB | DVP_IT_VST); 354 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) & ~DVP_CTL_ENA); 356 reg_write(vip, DVP_ITM, 0); 681 reg_write(vip, DVP_TFO, 0); 683 reg_write(vip, DVP_BFO, 0); 685 reg_write(vi [all...] |
/linux-master/drivers/iio/dac/ |
H A D | ad5592r-base.c | 55 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 70 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 74 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 98 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 102 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 106 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 174 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); 253 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); 257 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); 262 ret = ops->reg_write(s [all...] |
/linux-master/drivers/nvmem/ |
H A D | internals.h | 31 nvmem_reg_write_t reg_write; member in struct:nvmem_device
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/linux-master/drivers/gpu/drm/i2c/ |
H A D | tda998x_drv.c | 651 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) function 695 reg_write(priv, reg, old_val | val); 705 reg_write(priv, reg, old_val & ~val); 712 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 714 reg_write(priv, REG_SOFTRESET, 0); 722 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 723 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 724 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 725 reg_write(priv, REG_SERIALIZER, 0x00); 726 reg_write(pri [all...] |
/linux-master/drivers/i2c/busses/ |
H A D | i2c-pasemi-core.c | 45 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) function 59 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) 69 reg_write(smbus, REG_CTL, val); 78 reg_write(smbus, REG_SMSTA, status); 88 reg_write(smbus, REG_IMASK, SMSTA_XEN | SMSTA_MTN); 90 reg_write(smbus, REG_IMASK, 0); 106 reg_write(smbus, REG_SMSTA, status); 111 reg_write(smbus, REG_SMSTA, SMSTA_XEN); 362 reg_write(smbus, REG_IMASK, 0); 378 reg_write(smbu [all...] |
/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_reg.c | 86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); 101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
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