Lines Matching refs:reg_write
123 reg_write(dev, reg, vc->dma_descs[pb].phys);
168 reg_write(vc->dev, reg, phys);
288 reg_write(dev, reg, desc->phys);
407 reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], fps_map[i]);
599 reg_write(dev, BRIGHT[ch], ctrl->val & 0xff);
603 reg_write(dev, CONTRAST[ch], ctrl->val);
607 reg_write(dev, SAT_U[ch], ctrl->val);
608 reg_write(dev, SAT_V[ch], ctrl->val);
612 reg_write(dev, HUE[ch], ctrl->val & 0xff);
725 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
732 reg_write(vc->dev, VDMA_WHP[vc->ch], val);
791 reg_write(vc->dev, SDT[vc->ch], val);
798 reg_write(vc->dev, VIDEO_CONTROL1, val);
846 reg_write(dev, SDT[vc->ch], 0x7);
847 reg_write(dev, SDT_EN[vc->ch], 0xff);
857 reg_write(dev, SDT[vc->ch], old_std);
988 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val);
1214 reg_write(dev, VDELAY_LO[ch], 0x14);
1215 reg_write(dev, HACTIVE_LO[ch], 0xd0);
1216 reg_write(dev, VIDEO_SIZE[ch], 0);
1294 reg_write(dev, PHASE_REF, val);
1296 reg_write(dev, MISC2[0], 0xe7);
1297 reg_write(dev, VCTRL1[0], 0xcc);
1298 reg_write(dev, LOOP[0], 0xa5);
1300 reg_write(dev, VCTRL1[1], 0xcc);
1301 reg_write(dev, LOOP[1], 0xa5);
1302 reg_write(dev, MISC2[1], 0xe7);