drivers/firewire/ohci.c

572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
599 	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
625 	reg_write(ohci, OHCI1394_PhyControl,
717 	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
742 		reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1079 	reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1080 	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1257 	reg_write(ohci, COMMAND_PTR(ctx->regs),
1259 	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1260 	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1307 	reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1454 		reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1617 	reg_write(ohci, OHCI1394_CSRData, lock_data);
1618 	reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1619 	reg_write(ohci, OHCI1394_CSRControl, sel);
1813 		reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1961 		reg_write(ohci, OHCI1394_LinkControlSet,
2066 	reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2068 		reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2097 		reg_write(ohci, OHCI1394_BusOptions,
2100 		reg_write(ohci, OHCI1394_ConfigROMhdr,
2105 		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2106 		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2137 	reg_write(ohci, OHCI1394_IntEventClear,
2141 		reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2160 		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2172 		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2188 		reg_write(ohci, OHCI1394_IntEventClear,
2197 		reg_write(ohci, OHCI1394_LinkControlSet,
2230 	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2296 	reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2299 	reg_write(ohci, OHCI1394_HCControlClear,
2353 	reg_write(ohci, OHCI1394_HCControlSet,
2379 	reg_write(ohci, OHCI1394_HCControlClear,
2382 	reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2383 	reg_write(ohci, OHCI1394_LinkControlSet,
2387 	reg_write(ohci, OHCI1394_ATRetries,
2397 			reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2402 		reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2408 	reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2410 	reg_write(ohci, OHCI1394_FairnessControl, 0);
2413 	reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2414 	reg_write(ohci, OHCI1394_IntEventClear, ~0);
2415 	reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2463 	reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2464 	reg_write(ohci, OHCI1394_BusOptions,
2466 	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2468 	reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2482 	reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2484 	reg_write(ohci, OHCI1394_HCControlSet,
2488 	reg_write(ohci, OHCI1394_LinkControlSet,
2568 	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2665 		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2667 		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2735 			reg_write(ohci, OHCI1394_LinkControlClear,
2745 			reg_write(ohci, OHCI1394_LinkControlSet,
2754 		reg_write(ohci, OHCI1394_NodeID, value >> 16);
2759 		reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2760 		reg_write(ohci, OHCI1394_IntEventSet,
2775 		reg_write(ohci, OHCI1394_ATRetries, value);
2780 		reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2989 	reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2990 	reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2991 	reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2992 	reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
3114 		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3115 		reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3130 		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3131 		reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3132 		reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3153 		reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3159 		reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3528 	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3724 	reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3727 	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3735 	reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3742 	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3799 		reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3855 		reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3856 		reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));