drm/i2c/tda998x_drv.c

651 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
695 		reg_write(priv, reg, old_val | val);
705 		reg_write(priv, reg, old_val & ~val);
712 	reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
714 	reg_write(priv, REG_SOFTRESET, 0);
722 	reg_write(priv, REG_PLL_SERIAL_1, 0x00);
723 	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
724 	reg_write(priv, REG_PLL_SERIAL_3, 0x00);
725 	reg_write(priv, REG_SERIALIZER,   0x00);
726 	reg_write(priv, REG_BUFFER_OUT,   0x00);
727 	reg_write(priv, REG_PLL_SCG1,     0x00);
728 	reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
729 	reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
730 	reg_write(priv, REG_PLL_SCGN1,    0xfa);
731 	reg_write(priv, REG_PLL_SCGN2,    0x00);
732 	reg_write(priv, REG_PLL_SCGR1,    0x5b);
733 	reg_write(priv, REG_PLL_SCGR2,    0x00);
734 	reg_write(priv, REG_PLL_SCG2,     0x10);
737 	reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
1017 	reg_write(priv, REG_ENA_AP, settings->ena_ap);
1018 	reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1019 	reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1020 	reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1021 	reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1024 	reg_write(priv, REG_CTS_N, settings->cts_n);
1025 	reg_write(priv, REG_AUDIO_DIV, adiv);
1131 	reg_write(priv, REG_ENA_AP, 0);
1230 	reg_write(priv, REG_DDC_ADDR, 0xa0);
1231 	reg_write(priv, REG_DDC_OFFS, offset);
1232 	reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1233 	reg_write(priv, REG_DDC_SEGM, segptr);
1237 	reg_write(priv, REG_EDID_CTRL, 0x1);
1240 	reg_write(priv, REG_EDID_CTRL, 0x0);
1407 		reg_write(priv, REG_ENA_VP_0, 0xff);
1408 		reg_write(priv, REG_ENA_VP_1, 0xff);
1409 		reg_write(priv, REG_ENA_VP_2, 0xff);
1411 		reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1412 		reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1413 		reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1425 		reg_write(priv, REG_ENA_VP_0, 0x00);
1426 		reg_write(priv, REG_ENA_VP_1, 0x00);
1427 		reg_write(priv, REG_ENA_VP_2, 0x00);
1550 	reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1552 	reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1555 	reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1558 	reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1559 	reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1565 	reg_write(priv, REG_SERIALIZER, 0);
1566 	reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1568 	reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1569 	reg_write(priv, REG_SEL_CLK, sel_clk);
1570 	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1588 		reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1594 	reg_write(priv, REG_ANA_GENERAL, 0x09);
1609 	reg_write(priv, REG_VIP_CNTRL_3, reg);
1611 	reg_write(priv, REG_VIDFORMAT, 0x00);
1635 		reg_write(priv, REG_ENABLE_SPACE, 0x00);
1647 	reg_write(priv, REG_TBG_CNTRL_1, reg);
1650 	reg_write(priv, REG_TBG_CNTRL_0, 0);
1668 		reg_write(priv, REG_TBG_CNTRL_1, reg);
1669 		reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1885 	reg_write(priv, REG_DDC_DISABLE, 0x00);
1888 	reg_write(priv, REG_TX3, 39);