drivers/soundwire/qcom.c

210 	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
455 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
495 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
512 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
514 				ctrl->reg_write(ctrl,
714 				ctrl->reg_write(ctrl,
741 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
750 				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
757 				ctrl->reg_write(ctrl,
767 				ctrl->reg_write(ctrl,
799 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
840 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
843 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
848 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
854 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
857 		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
858 		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
861 		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
862 		ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
865 		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
870 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
874 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
879 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
882 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
885 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
890 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
895 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
953 	return ctrl->reg_write(ctrl, reg, val);
962 	return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
983 	ret = ctrl->reg_write(ctrl, reg, value);
990 		ret = ctrl->reg_write(ctrl, reg, value);
998 		ret = ctrl->reg_write(ctrl, reg, value);
1006 		ret = ctrl->reg_write(ctrl, reg, value);
1015 		ret = ctrl->reg_write(ctrl, reg, value);
1019 		ret = ctrl->reg_write(ctrl, reg, value);
1027 		ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1049 	return ctrl->reg_write(ctrl, reg, val);
1501 		ctrl->reg_write = qcom_swrm_ahb_reg_write;
1507 		ctrl->reg_write = qcom_swrm_cpu_reg_write;
1663 		ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1681 			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1682 			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1685 			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1686 			ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1689 			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1691 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1696 			ctrl->reg_write(ctrl,
1699 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1724 			ctrl->reg_write(ctrl,
1727 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],