Searched refs:refclk (Results 1 - 25 of 79) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllgt215.c42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq;
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq;
50 N = tmp / info->refclk;
51 fN = tmp % info->refclk;
54 if (fN >= info->refclk / 2)
57 if (fN < info->refclk / 2)
59 fN = tmp - (N * info->refclk);
67 err = abs(freq - (info->refclk * N / M / *P));
75 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk;
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H A Dnv04.c38 pv->refclk = info->refclk;
/linux-master/drivers/gpu/drm/gma500/
H A Dgma_display.h44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
88 struct drm_crtc *crtc, int target, int refclk,
H A Doaktrail_crtc.c41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk)
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1);
128 int refclk, struct gma_clock_t *best_clock)
153 actual_freq = (refclk * clock.m) /
181 * Returns a set of divisors for the desired target clock with the given refclk,
186 int refclk, struc
83 mrst_limit(struct drm_crtc *crtc, int refclk) argument
126 mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) argument
184 mrst_lvds_find_best_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) argument
370 int refclk = 0; local
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H A Dcdv_intel_display.c25 int refclk, struct gma_clock_t *best_clock);
365 int refclk)
373 if (refclk == 96000)
379 if (refclk == 27000)
384 if (refclk == 27000)
393 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) argument
397 clock->vco = (refclk * clock->m) / clock->n;
403 int refclk,
411 switch (refclk) {
448 gma_crtc->clock_funcs->clock(refclk,
364 cdv_intel_limit(struct drm_crtc *crtc, int refclk) argument
401 cdv_intel_find_dp_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) argument
582 int refclk; local
826 i8xx_clock(int refclk, struct gma_clock_t *clock) argument
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/linux-master/drivers/phy/ti/
H A Dphy-dm816x-usb.c46 struct clk *refclk; member in struct:dm816x_usb_phy
76 if (clk_get_rate(phy->refclk) != 24000000)
77 dev_warn(phy->dev, "nonstandard phy refclk\n");
123 clk_disable(phy->refclk);
134 error = clk_enable(phy->refclk);
151 clk_disable(phy->refclk);
218 phy->refclk = devm_clk_get(phy->dev, "refclk");
219 if (IS_ERR(phy->refclk))
220 return PTR_ERR(phy->refclk);
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H A Dphy-ti-pipe3.c172 struct clk *refclk; member in struct:ti_pipe3
608 phy->refclk = devm_clk_get(dev, "refclk");
609 if (IS_ERR(phy->refclk)) {
610 dev_err(dev, "unable to get refclk\n");
611 /* older DTBs have missing refclk in SATA PHY
615 return PTR_ERR(phy->refclk);
817 * Prevent auto-disable of refclk for SATA PHY due to Errata i783
820 if (!IS_ERR(phy->refclk)) {
821 clk_prepare_enable(phy->refclk);
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/linux-master/drivers/net/ethernet/arc/
H A Demac_rockchip.c32 struct clk *refclk; member in struct:rockchip_priv_data
147 priv->refclk = devm_clk_get(dev, "macref");
148 if (IS_ERR(priv->refclk)) {
150 PTR_ERR(priv->refclk));
151 err = PTR_ERR(priv->refclk);
155 err = clk_prepare_enable(priv->refclk);
195 err = clk_set_rate(priv->refclk, 50000000);
241 clk_disable_unprepare(priv->refclk);
254 clk_disable_unprepare(priv->refclk);
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c1238 u16 refclk; member in struct:intel_cdclk_vals
1244 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1245 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1246 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1247 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1248 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1253 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1254 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1255 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1260 { .refclk
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H A Dintel_dpll.h23 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
40 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll.c236 /* LVDS 100mhz refclk limits. */
315 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) argument
321 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) argument
339 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
346 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) argument
352 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
359 int chv_calc_dpll_params(int refclk, struct dpll *clock) argument
365 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
398 int refclk local
489 int refclk = 100000; local
517 int refclk = 100000; local
616 i9xx_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, int target, int refclk, const struct dpll *match_clock, struct dpll *best_clock) argument
674 pnv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, int target, int refclk, const struct dpll *match_clock, struct dpll *best_clock) argument
730 g4x_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, int target, int refclk, const struct dpll *match_clock, struct dpll *best_clock) argument
824 vlv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, int target, int refclk, const struct dpll *match_clock, struct dpll *best_clock) argument
882 chv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, int target, int refclk, const struct dpll *match_clock, struct dpll *best_clock) argument
944 int refclk = 100000; local
1317 int refclk = 120000; local
1421 int refclk = 100000; local
1448 int refclk = 100000; local
1476 int refclk = 96000; local
1525 int refclk = 96000; local
1563 int refclk = 96000; local
1603 int refclk = 48000; local
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/linux-master/drivers/media/dvb-frontends/
H A Dstv6110x.h16 u32 refclk; member in struct:stv6110x_config
42 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
H A Dstv6110x_priv.h53 #define REFCLOCK_kHz (stv6110x->config->refclk / 1000)
54 #define REFCLOCK_MHz (stv6110x->config->refclk / 1000000)
H A Dstv090x.h90 int (*tuner_set_refclk)(struct dvb_frontend *fe, u32 refclk);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dpll.h20 int refclk; member in struct:nvkm_pll_vals
47 u32 refclk; member in struct:nvbios_pll
/linux-master/drivers/phy/
H A Dphy-pistachio-usb.c38 unsigned int refclk; member in struct:pistachio_usb_phy
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
160 ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
161 &p_phy->refclk);
/linux-master/drivers/phy/xilinx/
H A Dphy-zynqmp.c192 * @refclk: reference clock index
201 unsigned int refclk; member in struct:xpsgtr_phy
345 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
352 if (gtr_phy->refclk != gtr_phy->lane) {
355 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
778 unsigned int refclk; local
807 refclk = args->args[3];
808 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
809 !gtr_dev->refclk_sscs[refclk]) {
810 dev_err(dev, "Invalid reference clock number %u\n", refclk);
879 unsigned int refclk; local
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/linux-master/sound/soc/meson/
H A Daxg-spdifin.c55 struct clk *refclk; member in struct:axg_spdifin
165 ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
175 rate = clk_get_rate(priv->refclk);
229 ret = clk_prepare_enable(priv->refclk);
251 clk_disable_unprepare(priv->refclk);
470 priv->refclk = devm_clk_get(dev, "refclk");
471 if (IS_ERR(priv->refclk))
472 return dev_err_probe(dev, PTR_ERR(priv->refclk), "failed to get mclk\n");
/linux-master/drivers/spi/
H A Dspi-zynq-qspi.c124 * @refclk: Pointer to the peripheral clock
136 struct clk *refclk; member in struct:zynq_qspi
348 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
386 clk_enable(qspi->refclk);
662 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
663 if (IS_ERR(xqspi->refclk)) {
665 ret = PTR_ERR(xqspi->refclk);
675 ret = clk_prepare_enable(xqspi->refclk);
710 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
725 clk_disable_unprepare(xqspi->refclk);
[all...]
H A Dspi-zynqmp-gqspi.c172 * @refclk: Pointer to the peripheral clock
194 struct clk *refclk; member in struct:zynqmp_qspi
294 clk_rate = clk_get_rate(xqspi->refclk);
403 clk_rate = clk_get_rate(xqspi->refclk);
568 clk_rate = clk_get_rate(xqspi->refclk);
1001 clk_disable_unprepare(xqspi->refclk);
1026 ret = clk_prepare_enable(xqspi->refclk);
1253 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1254 if (IS_ERR(xqspi->refclk)) {
1256 ret = PTR_ERR(xqspi->refclk);
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/linux-master/drivers/net/ethernet/ti/
H A Dcpts.c559 err = clk_enable(cpts->refclk);
580 clk_disable(cpts->refclk);
600 clk_disable(cpts->refclk);
609 freq = clk_get_rate(cpts->refclk);
660 refclk_np = of_get_child_by_name(node, "cpts-refclk-mux");
662 /* refclk selection supported not for all SoCs */
767 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts");
768 if (IS_ERR(cpts->refclk))
770 cpts->refclk = devm_clk_get(dev, "cpts");
772 if (IS_ERR(cpts->refclk)) {
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dpll.c327 info->refclk = nvbios_rd32(bios, data + 31);
350 info->refclk = nvbios_rd32(bios, data + 28);
353 info->refclk = nvbios_rd16(bios, data + 9) * 1000;
368 info->refclk = nvbios_rd16(bios, data + 1) * 1000;
386 if (!info->refclk) {
387 info->refclk = device->crystal;
393 info->refclk = 200000;
395 info->refclk = 25000;
/linux-master/drivers/usb/cdns3/
H A Ddrd.h27 __le32 refclk; member in struct:cdns3_otg_regs
45 __le32 refclk; member in struct:cdns3_otg_legacy_regs
/linux-master/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb.h80 unsigned int refclk; /* disp. reference clock */ member in struct:mb862xxfb_par
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-visconti.c32 struct clk *refclk; member in struct:visconti_pcie
259 pcie->refclk = devm_clk_get(dev, "ref");
260 if (IS_ERR(pcie->refclk))
261 return dev_err_probe(dev, PTR_ERR(pcie->refclk),

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