Searched refs:pctl (Results 1 - 14 of 14) sorted by last modified time

/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_display.c3700 u32 pctl; local
3722 pctl = I915_READ(PFIT_CONTROL);
3723 if ((pctl & PFIT_ENABLE) &&
3724 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
/freebsd-11-stable/cddl/contrib/opensolaris/lib/libnvpair/
H A Dlibnvpair.c103 #define DFLTPRTOP(pctl, type) \
104 ((pctl)->nvprt_dfltops->print_##type.op)
106 #define DFLTPRTOPARG(pctl, type) \
107 ((pctl)->nvprt_dfltops->print_##type.arg)
109 #define CUSTPRTOP(pctl, type) \
110 ((pctl)->nvprt_custops->print_##type.op)
112 #define CUSTPRTOPARG(pctl, type) \
113 ((pctl)->nvprt_custops->print_##type.arg)
115 #define RENDER(pctl, type, nvl, name, val) \
118 if ((pctl)
154 indent(nvlist_prtctl_t pctl, int onemore) argument
258 nvprint_nvlist(nvlist_prtctl_t pctl, void *private, nvlist_t *nvl, const char *name, nvlist_t *value) argument
278 nvaprint_nvlist_array(nvlist_prtctl_t pctl, void *private, nvlist_t *nvl, const char *name, nvlist_t **valuep, uint_t count) argument
311 nvlist_prtctl_setdest(nvlist_prtctl_t pctl, FILE *fp) argument
317 nvlist_prtctl_getdest(nvlist_prtctl_t pctl) argument
324 nvlist_prtctl_setindent(nvlist_prtctl_t pctl, enum nvlist_indent_mode mode, int start, int inc) argument
342 nvlist_prtctl_doindent(nvlist_prtctl_t pctl, int onemore) argument
349 nvlist_prtctl_setfmt(nvlist_prtctl_t pctl, enum nvlist_prtctl_fmt which, const char *fmt) argument
382 nvlist_prtctl_dofmt(nvlist_prtctl_t pctl, enum nvlist_prtctl_fmt which, ...) argument
508 prtctl_defaults(FILE *fp, struct nvlist_prtctl *pctl, struct nvlist_printops *ops) argument
527 struct nvlist_prtctl *pctl; local
544 nvlist_prtctl_free(nvlist_prtctl_t pctl) argument
564 nvlist_print_with_indent(nvlist_t *nvl, nvlist_prtctl_t pctl) argument
764 nvlist_prt(nvlist_t *nvl, nvlist_prtctl_t pctl) argument
[all...]
/freebsd-11-stable/sys/contrib/octeon-sdk/
H A Dcvmx-agl-defs.h1372 uint64_t pctl : 5; /**< AGL PCTL */ member in struct:cvmx_agl_gmx_drv_ctl::cvmx_agl_gmx_drv_ctl_s
1378 uint64_t pctl : 5;
1397 uint64_t pctl : 5; /**< AGL PCTL */ member in struct:cvmx_agl_gmx_drv_ctl::cvmx_agl_gmx_drv_ctl_cn56xx
1403 uint64_t pctl : 5;
H A Dcvmx-asx0-defs.h89 uint64_t pctl : 5; /**< These bits control the driving strength of the dbg member in struct:cvmx_asx0_dbg_data_drv::cvmx_asx0_dbg_data_drv_s
95 uint64_t pctl : 5;
102 uint64_t pctl : 4; /**< These bits control the driving strength of the dbg member in struct:cvmx_asx0_dbg_data_drv::cvmx_asx0_dbg_data_drv_cn38xx
108 uint64_t pctl : 4;
H A Dcvmx-asxx-defs.h688 uint64_t pctl : 5; /**< PCTL Compensation Value member in struct:cvmx_asxx_rld_comp::cvmx_asxx_rld_comp_s
695 uint64_t pctl : 5;
702 uint64_t pctl : 4; /**< These bits reflect the computed compensation member in struct:cvmx_asxx_rld_comp::cvmx_asxx_rld_comp_cn38xx
708 uint64_t pctl : 4;
729 uint64_t pctl : 4; /**< These bits specify a driving strength (positive member in struct:cvmx_asxx_rld_data_drv::cvmx_asxx_rld_data_drv_s
737 uint64_t pctl : 4;
831 uint64_t pctl : 5; /**< Duke's drive control */ member in struct:cvmx_asxx_rld_pctl_strong::cvmx_asxx_rld_pctl_strong_s
833 uint64_t pctl : 5;
855 uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */ member in struct:cvmx_asxx_rld_pctl_weak::cvmx_asxx_rld_pctl_weak_s
857 uint64_t pctl
1178 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ member in struct:cvmx_asxx_tx_comp_byp::cvmx_asxx_tx_comp_byp_cn30xx
1191 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ member in struct:cvmx_asxx_tx_comp_byp::cvmx_asxx_tx_comp_byp_cn38xx
1205 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ member in struct:cvmx_asxx_tx_comp_byp::cvmx_asxx_tx_comp_byp_cn50xx
1220 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ member in struct:cvmx_asxx_tx_comp_byp::cvmx_asxx_tx_comp_byp_cn58xx
[all...]
H A Dcvmx-dfa-defs.h2025 uint64_t dfa__pctl : 4; /**< DFA DDR pctl from compensation circuit
5522 uint64_t pctl : 5; /**< Compensation control bits */ member in struct:cvmx_dfa_rodt_comp_ctl::cvmx_dfa_rodt_comp_ctl_s
5524 uint64_t pctl : 5;
H A Dcvmx-lmcx-defs.h3078 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
3184 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
3299 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
3430 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
3541 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
3655 uint64_t ddr__pctl : 4; /**< DDR pctl from compensation circuit
6518 uint64_t ddr__pctl : 5; /**< DDR pctl from compensation circuit */
6982 uint64_t pctl : 5; /**< Compensation control bits */ member in struct:cvmx_lmcx_rodt_comp_ctl::cvmx_lmcx_rodt_comp_ctl_s
6984 uint64_t pctl : 5;
H A Dcvmx-mgmt-port.c404 drv_ctl.s.pctl = 6;
H A Dcvmx-mio-defs.h1945 uint64_t pctl : 5; /**< Boot bus PCTL */ member in struct:cvmx_mio_boot_comp::cvmx_mio_boot_comp_cn50xx
1949 uint64_t pctl : 5;
1960 uint64_t pctl : 6; /**< Boot bus PCTL */ member in struct:cvmx_mio_boot_comp::cvmx_mio_boot_comp_cn61xx
1964 uint64_t pctl : 6;
4956 uint64_t pctl : 6; /**< GPIO bus PCTL */ member in struct:cvmx_mio_gpio_comp::cvmx_mio_gpio_comp_s
4960 uint64_t pctl : 6;
H A Dcvmx-npi-defs.h1277 uint64_t pctl : 5; /**< Bypass value for PCTL */ member in struct:cvmx_npi_comp_ctl::cvmx_npi_comp_ctl_s
1281 uint64_t pctl : 5;
H A Dcvmx-smi-defs.h78 uint64_t pctl : 6; /**< PCTL Drive strength control bits member in struct:cvmx_smi_drv_ctl::cvmx_smi_drv_ctl_s
90 uint64_t pctl : 6;
/freebsd-11-stable/sys/dev/sound/pci/
H A Dcsapcm.c73 u_long pctl; member in struct:csa_info
343 csa_writemem(resp, BA1_PCTL, ul | csa->pctl);
374 csa->pctl = ul & 0xffff0000;
789 * PCTL and CCTL can be stored into csa->pctl and csa->cctl,
/freebsd-11-stable/sys/dev/mii/
H A Dqsphy.c168 int bmsr, bmcr, pctl; local
188 pctl = PHY_READ(sc, MII_QSPHY_PCTL);
189 switch (pctl & PCTL_OPMASK) {
/freebsd-11-stable/sys/dev/bhnd/cores/pci/
H A Dbhnd_pci_hostb.c464 uint16_t pctl; local
466 pctl = BHND_PCI_MDIO_READ(sc, BHND_PCIE_PHY_SDR9_PLL,
469 pctl &= ~BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN;
471 BHND_PCIE_SDR9_PLL_CTRL, pctl);

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