1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-asxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon asxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_ASXX_DEFS_H__ 53232812Sjmallett#define __CVMX_ASXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 62215976Sjmallett cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id); 63215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000180ull); 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) 67215976Sjmallett#endif 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallettstatic inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id) 70215976Sjmallett{ 71215976Sjmallett if (!( 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 73215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 75215976Sjmallett cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 76215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000188ull); 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallettstatic inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id) 83215976Sjmallett{ 84215976Sjmallett if (!( 85215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 86215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 87215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 88215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 90215976Sjmallett cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id); 91215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull; 92215976Sjmallett} 93215976Sjmallett#else 94215976Sjmallett#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) 95215976Sjmallett#endif 96215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 97215976Sjmallettstatic inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id) 98215976Sjmallett{ 99215976Sjmallett if (!( 100215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 101215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 102215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 105215976Sjmallett cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id); 106215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull; 107215976Sjmallett} 108215976Sjmallett#else 109215976Sjmallett#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) 110215976Sjmallett#endif 111215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 112215976Sjmallettstatic inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id) 113215976Sjmallett{ 114215976Sjmallett if (!( 115215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 116215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 117215976Sjmallett cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 118215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000190ull); 119215976Sjmallett} 120215976Sjmallett#else 121215976Sjmallett#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) 122215976Sjmallett#endif 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallettstatic inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id) 125215976Sjmallett{ 126215976Sjmallett if (!( 127215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 128215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 129215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 130215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 132215976Sjmallett cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id); 133215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull; 134215976Sjmallett} 135215976Sjmallett#else 136215976Sjmallett#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) 137215976Sjmallett#endif 138215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id) 140215976Sjmallett{ 141215976Sjmallett if (!( 142215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 144215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id); 145215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull; 146215976Sjmallett} 147215976Sjmallett#else 148215976Sjmallett#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) 149215976Sjmallett#endif 150215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 151215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id) 152215976Sjmallett{ 153215976Sjmallett if (!( 154215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 156215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id); 157215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull; 158215976Sjmallett} 159215976Sjmallett#else 160215976Sjmallett#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) 161215976Sjmallett#endif 162215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 163215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id) 164215976Sjmallett{ 165215976Sjmallett if (!( 166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 168215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id); 169215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull; 170215976Sjmallett} 171215976Sjmallett#else 172215976Sjmallett#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) 173215976Sjmallett#endif 174215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id) 176215976Sjmallett{ 177215976Sjmallett if (!( 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 180215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id); 181215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull; 182215976Sjmallett} 183215976Sjmallett#else 184215976Sjmallett#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) 185215976Sjmallett#endif 186215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 187215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id) 188215976Sjmallett{ 189215976Sjmallett if (!( 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 191215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id); 192215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull; 193215976Sjmallett} 194215976Sjmallett#else 195215976Sjmallett#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) 196215976Sjmallett#endif 197215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id) 199215976Sjmallett{ 200215976Sjmallett if (!( 201215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 203215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull; 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id) 211215976Sjmallett{ 212215976Sjmallett if (!( 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 214215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 215215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id); 216215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull; 217215976Sjmallett} 218215976Sjmallett#else 219215976Sjmallett#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) 220215976Sjmallett#endif 221215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id) 223215976Sjmallett{ 224215976Sjmallett if (!( 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 227215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id); 228215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull; 229215976Sjmallett} 230215976Sjmallett#else 231215976Sjmallett#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) 232215976Sjmallett#endif 233215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id) 235215976Sjmallett{ 236215976Sjmallett if (!( 237215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 238215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 239215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id); 240215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull; 241215976Sjmallett} 242215976Sjmallett#else 243215976Sjmallett#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) 244215976Sjmallett#endif 245215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 246215976Sjmallettstatic inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id) 247215976Sjmallett{ 248215976Sjmallett if (!( 249215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 250215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 251215976Sjmallett cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id); 252215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull; 253215976Sjmallett} 254215976Sjmallett#else 255215976Sjmallett#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) 256215976Sjmallett#endif 257215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id) 259215976Sjmallett{ 260215976Sjmallett if (!( 261215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 262215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 265215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 266215976Sjmallett cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 267215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 268215976Sjmallett} 269215976Sjmallett#else 270215976Sjmallett#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 271215976Sjmallett#endif 272215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 273215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id) 274215976Sjmallett{ 275215976Sjmallett if (!( 276215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 277215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 278215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 279215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 280215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 281215976Sjmallett cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id); 282215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull; 283215976Sjmallett} 284215976Sjmallett#else 285215976Sjmallett#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) 286215976Sjmallett#endif 287215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id) 289215976Sjmallett{ 290215976Sjmallett if (!( 291215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 292215976Sjmallett cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id); 293215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull; 294215976Sjmallett} 295215976Sjmallett#else 296215976Sjmallett#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) 297215976Sjmallett#endif 298215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id) 300215976Sjmallett{ 301215976Sjmallett if (!( 302215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 303215976Sjmallett cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id); 304215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull; 305215976Sjmallett} 306215976Sjmallett#else 307215976Sjmallett#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) 308215976Sjmallett#endif 309215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 310215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id) 311215976Sjmallett{ 312215976Sjmallett if (!( 313215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 314215976Sjmallett cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id); 315215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull; 316215976Sjmallett} 317215976Sjmallett#else 318215976Sjmallett#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) 319215976Sjmallett#endif 320215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321215976Sjmallettstatic inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id) 322215976Sjmallett{ 323215976Sjmallett if (!( 324215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 325215976Sjmallett cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id); 326215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull; 327215976Sjmallett} 328215976Sjmallett#else 329215976Sjmallett#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) 330215976Sjmallett#endif 331215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332215976Sjmallettstatic inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id) 333215976Sjmallett{ 334215976Sjmallett if (!( 335215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 336215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 337215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 338215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 339215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 340215976Sjmallett cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 341215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 342215976Sjmallett} 343215976Sjmallett#else 344215976Sjmallett#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 345215976Sjmallett#endif 346215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 347215976Sjmallettstatic inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id) 348215976Sjmallett{ 349215976Sjmallett if (!( 350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 351215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 352215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 353215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 354215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 355215976Sjmallett cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id); 356215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull; 357215976Sjmallett} 358215976Sjmallett#else 359215976Sjmallett#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) 360215976Sjmallett#endif 361215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362215976Sjmallettstatic inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id) 363215976Sjmallett{ 364215976Sjmallett if (!( 365215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 366215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 367215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 368215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 369215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 370215976Sjmallett cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id); 371215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 372215976Sjmallett} 373215976Sjmallett#else 374215976Sjmallett#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 375215976Sjmallett#endif 376215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 377215976Sjmallettstatic inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id) 378215976Sjmallett{ 379215976Sjmallett if (!( 380215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 381215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 382215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 383215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 384215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 385215976Sjmallett cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id); 386215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull; 387215976Sjmallett} 388215976Sjmallett#else 389215976Sjmallett#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) 390215976Sjmallett#endif 391215976Sjmallett 392215976Sjmallett/** 393215976Sjmallett * cvmx_asx#_gmii_rx_clk_set 394215976Sjmallett * 395215976Sjmallett * ASX_GMII_RX_CLK_SET = GMII Clock delay setting 396215976Sjmallett * 397215976Sjmallett */ 398232812Sjmallettunion cvmx_asxx_gmii_rx_clk_set { 399215976Sjmallett uint64_t u64; 400232812Sjmallett struct cvmx_asxx_gmii_rx_clk_set_s { 401232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 402215976Sjmallett uint64_t reserved_5_63 : 59; 403215976Sjmallett uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk) 404215976Sjmallett delay line. The intrinsic delay can range from 405215976Sjmallett 50ps to 80ps per tap. */ 406215976Sjmallett#else 407215976Sjmallett uint64_t setting : 5; 408215976Sjmallett uint64_t reserved_5_63 : 59; 409215976Sjmallett#endif 410215976Sjmallett } s; 411215976Sjmallett struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 412215976Sjmallett struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 413215976Sjmallett struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 414215976Sjmallett}; 415215976Sjmalletttypedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t; 416215976Sjmallett 417215976Sjmallett/** 418215976Sjmallett * cvmx_asx#_gmii_rx_dat_set 419215976Sjmallett * 420215976Sjmallett * ASX_GMII_RX_DAT_SET = GMII Clock delay setting 421215976Sjmallett * 422215976Sjmallett */ 423232812Sjmallettunion cvmx_asxx_gmii_rx_dat_set { 424215976Sjmallett uint64_t u64; 425232812Sjmallett struct cvmx_asxx_gmii_rx_dat_set_s { 426232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 427215976Sjmallett uint64_t reserved_5_63 : 59; 428215976Sjmallett uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data) 429215976Sjmallett delay lines. The intrinsic delay can range from 430215976Sjmallett 50ps to 80ps per tap. */ 431215976Sjmallett#else 432215976Sjmallett uint64_t setting : 5; 433215976Sjmallett uint64_t reserved_5_63 : 59; 434215976Sjmallett#endif 435215976Sjmallett } s; 436215976Sjmallett struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 437215976Sjmallett struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 438215976Sjmallett struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 439215976Sjmallett}; 440215976Sjmalletttypedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t; 441215976Sjmallett 442215976Sjmallett/** 443215976Sjmallett * cvmx_asx#_int_en 444215976Sjmallett * 445215976Sjmallett * ASX_INT_EN = Interrupt Enable 446215976Sjmallett * 447215976Sjmallett */ 448232812Sjmallettunion cvmx_asxx_int_en { 449215976Sjmallett uint64_t u64; 450232812Sjmallett struct cvmx_asxx_int_en_s { 451232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 452215976Sjmallett uint64_t reserved_12_63 : 52; 453215976Sjmallett uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 454215976Sjmallett uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 455215976Sjmallett uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 456215976Sjmallett#else 457215976Sjmallett uint64_t ovrflw : 4; 458215976Sjmallett uint64_t txpop : 4; 459215976Sjmallett uint64_t txpsh : 4; 460215976Sjmallett uint64_t reserved_12_63 : 52; 461215976Sjmallett#endif 462215976Sjmallett } s; 463232812Sjmallett struct cvmx_asxx_int_en_cn30xx { 464232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 465215976Sjmallett uint64_t reserved_11_63 : 53; 466215976Sjmallett uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 467215976Sjmallett uint64_t reserved_7_7 : 1; 468215976Sjmallett uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 469215976Sjmallett uint64_t reserved_3_3 : 1; 470215976Sjmallett uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 471215976Sjmallett#else 472215976Sjmallett uint64_t ovrflw : 3; 473215976Sjmallett uint64_t reserved_3_3 : 1; 474215976Sjmallett uint64_t txpop : 3; 475215976Sjmallett uint64_t reserved_7_7 : 1; 476215976Sjmallett uint64_t txpsh : 3; 477215976Sjmallett uint64_t reserved_11_63 : 53; 478215976Sjmallett#endif 479215976Sjmallett } cn30xx; 480215976Sjmallett struct cvmx_asxx_int_en_cn30xx cn31xx; 481215976Sjmallett struct cvmx_asxx_int_en_s cn38xx; 482215976Sjmallett struct cvmx_asxx_int_en_s cn38xxp2; 483215976Sjmallett struct cvmx_asxx_int_en_cn30xx cn50xx; 484215976Sjmallett struct cvmx_asxx_int_en_s cn58xx; 485215976Sjmallett struct cvmx_asxx_int_en_s cn58xxp1; 486215976Sjmallett}; 487215976Sjmalletttypedef union cvmx_asxx_int_en cvmx_asxx_int_en_t; 488215976Sjmallett 489215976Sjmallett/** 490215976Sjmallett * cvmx_asx#_int_reg 491215976Sjmallett * 492215976Sjmallett * ASX_INT_REG = Interrupt Register 493215976Sjmallett * 494215976Sjmallett */ 495232812Sjmallettunion cvmx_asxx_int_reg { 496215976Sjmallett uint64_t u64; 497232812Sjmallett struct cvmx_asxx_int_reg_s { 498232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 499215976Sjmallett uint64_t reserved_12_63 : 52; 500215976Sjmallett uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 501215976Sjmallett uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 502215976Sjmallett uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 503215976Sjmallett#else 504215976Sjmallett uint64_t ovrflw : 4; 505215976Sjmallett uint64_t txpop : 4; 506215976Sjmallett uint64_t txpsh : 4; 507215976Sjmallett uint64_t reserved_12_63 : 52; 508215976Sjmallett#endif 509215976Sjmallett } s; 510232812Sjmallett struct cvmx_asxx_int_reg_cn30xx { 511232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 512215976Sjmallett uint64_t reserved_11_63 : 53; 513215976Sjmallett uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 514215976Sjmallett uint64_t reserved_7_7 : 1; 515215976Sjmallett uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 516215976Sjmallett uint64_t reserved_3_3 : 1; 517215976Sjmallett uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 518215976Sjmallett#else 519215976Sjmallett uint64_t ovrflw : 3; 520215976Sjmallett uint64_t reserved_3_3 : 1; 521215976Sjmallett uint64_t txpop : 3; 522215976Sjmallett uint64_t reserved_7_7 : 1; 523215976Sjmallett uint64_t txpsh : 3; 524215976Sjmallett uint64_t reserved_11_63 : 53; 525215976Sjmallett#endif 526215976Sjmallett } cn30xx; 527215976Sjmallett struct cvmx_asxx_int_reg_cn30xx cn31xx; 528215976Sjmallett struct cvmx_asxx_int_reg_s cn38xx; 529215976Sjmallett struct cvmx_asxx_int_reg_s cn38xxp2; 530215976Sjmallett struct cvmx_asxx_int_reg_cn30xx cn50xx; 531215976Sjmallett struct cvmx_asxx_int_reg_s cn58xx; 532215976Sjmallett struct cvmx_asxx_int_reg_s cn58xxp1; 533215976Sjmallett}; 534215976Sjmalletttypedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t; 535215976Sjmallett 536215976Sjmallett/** 537215976Sjmallett * cvmx_asx#_mii_rx_dat_set 538215976Sjmallett * 539215976Sjmallett * ASX_MII_RX_DAT_SET = GMII Clock delay setting 540215976Sjmallett * 541215976Sjmallett */ 542232812Sjmallettunion cvmx_asxx_mii_rx_dat_set { 543215976Sjmallett uint64_t u64; 544232812Sjmallett struct cvmx_asxx_mii_rx_dat_set_s { 545232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 546215976Sjmallett uint64_t reserved_5_63 : 59; 547215976Sjmallett uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data) 548215976Sjmallett delay lines. The intrinsic delay can range from 549215976Sjmallett 50ps to 80ps per tap. */ 550215976Sjmallett#else 551215976Sjmallett uint64_t setting : 5; 552215976Sjmallett uint64_t reserved_5_63 : 59; 553215976Sjmallett#endif 554215976Sjmallett } s; 555215976Sjmallett struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 556215976Sjmallett struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 557215976Sjmallett}; 558215976Sjmalletttypedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t; 559215976Sjmallett 560215976Sjmallett/** 561215976Sjmallett * cvmx_asx#_prt_loop 562215976Sjmallett * 563215976Sjmallett * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins) 564215976Sjmallett * 565215976Sjmallett */ 566232812Sjmallettunion cvmx_asxx_prt_loop { 567215976Sjmallett uint64_t u64; 568232812Sjmallett struct cvmx_asxx_prt_loop_s { 569232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 570215976Sjmallett uint64_t reserved_8_63 : 56; 571215976Sjmallett uint64_t ext_loop : 4; /**< External Loopback Enable 572215976Sjmallett 0 = No Loopback (TX FIFO is filled by RMGII) 573215976Sjmallett 1 = RX FIFO drives the TX FIFO 574215976Sjmallett - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 575215976Sjmallett - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 576215976Sjmallett - core clock > 250MHZ 577215976Sjmallett - rxc must not deviate from the +-50ppm 578215976Sjmallett - if txc>rxc, idle cycle may drop over time */ 579215976Sjmallett uint64_t int_loop : 4; /**< Internal Loopback Enable 580215976Sjmallett 0 = No Loopback (RX FIFO is filled by RMGII pins) 581215976Sjmallett 1 = TX FIFO drives the RX FIFO 582215976Sjmallett Note, in internal loop-back mode, the RGMII link 583215976Sjmallett status is not used (since there is no real PHY). 584215976Sjmallett Software cannot use the inband status. */ 585215976Sjmallett#else 586215976Sjmallett uint64_t int_loop : 4; 587215976Sjmallett uint64_t ext_loop : 4; 588215976Sjmallett uint64_t reserved_8_63 : 56; 589215976Sjmallett#endif 590215976Sjmallett } s; 591232812Sjmallett struct cvmx_asxx_prt_loop_cn30xx { 592232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 593215976Sjmallett uint64_t reserved_7_63 : 57; 594215976Sjmallett uint64_t ext_loop : 3; /**< External Loopback Enable 595215976Sjmallett 0 = No Loopback (TX FIFO is filled by RMGII) 596215976Sjmallett 1 = RX FIFO drives the TX FIFO 597215976Sjmallett - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 598215976Sjmallett - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 599215976Sjmallett - core clock > 250MHZ 600215976Sjmallett - rxc must not deviate from the +-50ppm 601215976Sjmallett - if txc>rxc, idle cycle may drop over time */ 602215976Sjmallett uint64_t reserved_3_3 : 1; 603215976Sjmallett uint64_t int_loop : 3; /**< Internal Loopback Enable 604215976Sjmallett 0 = No Loopback (RX FIFO is filled by RMGII pins) 605215976Sjmallett 1 = TX FIFO drives the RX FIFO 606215976Sjmallett - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 607215976Sjmallett - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 608215976Sjmallett - GMX_TX_CLK[CLK_CNT] must be 1 609215976Sjmallett Note, in internal loop-back mode, the RGMII link 610215976Sjmallett status is not used (since there is no real PHY). 611215976Sjmallett Software cannot use the inband status. */ 612215976Sjmallett#else 613215976Sjmallett uint64_t int_loop : 3; 614215976Sjmallett uint64_t reserved_3_3 : 1; 615215976Sjmallett uint64_t ext_loop : 3; 616215976Sjmallett uint64_t reserved_7_63 : 57; 617215976Sjmallett#endif 618215976Sjmallett } cn30xx; 619215976Sjmallett struct cvmx_asxx_prt_loop_cn30xx cn31xx; 620215976Sjmallett struct cvmx_asxx_prt_loop_s cn38xx; 621215976Sjmallett struct cvmx_asxx_prt_loop_s cn38xxp2; 622215976Sjmallett struct cvmx_asxx_prt_loop_cn30xx cn50xx; 623215976Sjmallett struct cvmx_asxx_prt_loop_s cn58xx; 624215976Sjmallett struct cvmx_asxx_prt_loop_s cn58xxp1; 625215976Sjmallett}; 626215976Sjmalletttypedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t; 627215976Sjmallett 628215976Sjmallett/** 629215976Sjmallett * cvmx_asx#_rld_bypass 630215976Sjmallett * 631215976Sjmallett * ASX_RLD_BYPASS 632215976Sjmallett * 633215976Sjmallett */ 634232812Sjmallettunion cvmx_asxx_rld_bypass { 635215976Sjmallett uint64_t u64; 636232812Sjmallett struct cvmx_asxx_rld_bypass_s { 637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 638215976Sjmallett uint64_t reserved_1_63 : 63; 639215976Sjmallett uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with 640215976Sjmallett ASX_RLD_BYPASS_SETTING */ 641215976Sjmallett#else 642215976Sjmallett uint64_t bypass : 1; 643215976Sjmallett uint64_t reserved_1_63 : 63; 644215976Sjmallett#endif 645215976Sjmallett } s; 646215976Sjmallett struct cvmx_asxx_rld_bypass_s cn38xx; 647215976Sjmallett struct cvmx_asxx_rld_bypass_s cn38xxp2; 648215976Sjmallett struct cvmx_asxx_rld_bypass_s cn58xx; 649215976Sjmallett struct cvmx_asxx_rld_bypass_s cn58xxp1; 650215976Sjmallett}; 651215976Sjmalletttypedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t; 652215976Sjmallett 653215976Sjmallett/** 654215976Sjmallett * cvmx_asx#_rld_bypass_setting 655215976Sjmallett * 656215976Sjmallett * ASX_RLD_BYPASS_SETTING 657215976Sjmallett * 658215976Sjmallett */ 659232812Sjmallettunion cvmx_asxx_rld_bypass_setting { 660215976Sjmallett uint64_t u64; 661232812Sjmallett struct cvmx_asxx_rld_bypass_setting_s { 662232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 663215976Sjmallett uint64_t reserved_5_63 : 59; 664215976Sjmallett uint64_t setting : 5; /**< The rld_dll setting bypass value */ 665215976Sjmallett#else 666215976Sjmallett uint64_t setting : 5; 667215976Sjmallett uint64_t reserved_5_63 : 59; 668215976Sjmallett#endif 669215976Sjmallett } s; 670215976Sjmallett struct cvmx_asxx_rld_bypass_setting_s cn38xx; 671215976Sjmallett struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 672215976Sjmallett struct cvmx_asxx_rld_bypass_setting_s cn58xx; 673215976Sjmallett struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 674215976Sjmallett}; 675215976Sjmalletttypedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t; 676215976Sjmallett 677215976Sjmallett/** 678215976Sjmallett * cvmx_asx#_rld_comp 679215976Sjmallett * 680215976Sjmallett * ASX_RLD_COMP 681215976Sjmallett * 682215976Sjmallett */ 683232812Sjmallettunion cvmx_asxx_rld_comp { 684215976Sjmallett uint64_t u64; 685232812Sjmallett struct cvmx_asxx_rld_comp_s { 686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 687215976Sjmallett uint64_t reserved_9_63 : 55; 688215976Sjmallett uint64_t pctl : 5; /**< PCTL Compensation Value 689215976Sjmallett These bits reflect the computed compensation 690215976Sjmallett values from the built-in compensation circuit. */ 691215976Sjmallett uint64_t nctl : 4; /**< These bits reflect the computed compensation 692215976Sjmallett values from the built-in compensation circuit. */ 693215976Sjmallett#else 694215976Sjmallett uint64_t nctl : 4; 695215976Sjmallett uint64_t pctl : 5; 696215976Sjmallett uint64_t reserved_9_63 : 55; 697215976Sjmallett#endif 698215976Sjmallett } s; 699232812Sjmallett struct cvmx_asxx_rld_comp_cn38xx { 700232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 701215976Sjmallett uint64_t reserved_8_63 : 56; 702215976Sjmallett uint64_t pctl : 4; /**< These bits reflect the computed compensation 703215976Sjmallett values from the built-in compensation circuit. */ 704215976Sjmallett uint64_t nctl : 4; /**< These bits reflect the computed compensation 705215976Sjmallett values from the built-in compensation circuit. */ 706215976Sjmallett#else 707215976Sjmallett uint64_t nctl : 4; 708215976Sjmallett uint64_t pctl : 4; 709215976Sjmallett uint64_t reserved_8_63 : 56; 710215976Sjmallett#endif 711215976Sjmallett } cn38xx; 712215976Sjmallett struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 713215976Sjmallett struct cvmx_asxx_rld_comp_s cn58xx; 714215976Sjmallett struct cvmx_asxx_rld_comp_s cn58xxp1; 715215976Sjmallett}; 716215976Sjmalletttypedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t; 717215976Sjmallett 718215976Sjmallett/** 719215976Sjmallett * cvmx_asx#_rld_data_drv 720215976Sjmallett * 721215976Sjmallett * ASX_RLD_DATA_DRV 722215976Sjmallett * 723215976Sjmallett */ 724232812Sjmallettunion cvmx_asxx_rld_data_drv { 725215976Sjmallett uint64_t u64; 726232812Sjmallett struct cvmx_asxx_rld_data_drv_s { 727232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 728215976Sjmallett uint64_t reserved_8_63 : 56; 729215976Sjmallett uint64_t pctl : 4; /**< These bits specify a driving strength (positive 730215976Sjmallett integer) for the RLD I/Os when the built-in 731215976Sjmallett compensation circuit is bypassed. */ 732215976Sjmallett uint64_t nctl : 4; /**< These bits specify a driving strength (positive 733215976Sjmallett integer) for the RLD I/Os when the built-in 734215976Sjmallett compensation circuit is bypassed. */ 735215976Sjmallett#else 736215976Sjmallett uint64_t nctl : 4; 737215976Sjmallett uint64_t pctl : 4; 738215976Sjmallett uint64_t reserved_8_63 : 56; 739215976Sjmallett#endif 740215976Sjmallett } s; 741215976Sjmallett struct cvmx_asxx_rld_data_drv_s cn38xx; 742215976Sjmallett struct cvmx_asxx_rld_data_drv_s cn38xxp2; 743215976Sjmallett struct cvmx_asxx_rld_data_drv_s cn58xx; 744215976Sjmallett struct cvmx_asxx_rld_data_drv_s cn58xxp1; 745215976Sjmallett}; 746215976Sjmalletttypedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t; 747215976Sjmallett 748215976Sjmallett/** 749215976Sjmallett * cvmx_asx#_rld_fcram_mode 750215976Sjmallett * 751215976Sjmallett * ASX_RLD_FCRAM_MODE 752215976Sjmallett * 753215976Sjmallett */ 754232812Sjmallettunion cvmx_asxx_rld_fcram_mode { 755215976Sjmallett uint64_t u64; 756232812Sjmallett struct cvmx_asxx_rld_fcram_mode_s { 757232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 758215976Sjmallett uint64_t reserved_1_63 : 63; 759215976Sjmallett uint64_t mode : 1; /**< Memory Mode 760215976Sjmallett - 0: RLDRAM 761215976Sjmallett - 1: FCRAM */ 762215976Sjmallett#else 763215976Sjmallett uint64_t mode : 1; 764215976Sjmallett uint64_t reserved_1_63 : 63; 765215976Sjmallett#endif 766215976Sjmallett } s; 767215976Sjmallett struct cvmx_asxx_rld_fcram_mode_s cn38xx; 768215976Sjmallett struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 769215976Sjmallett}; 770215976Sjmalletttypedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t; 771215976Sjmallett 772215976Sjmallett/** 773215976Sjmallett * cvmx_asx#_rld_nctl_strong 774215976Sjmallett * 775215976Sjmallett * ASX_RLD_NCTL_STRONG 776215976Sjmallett * 777215976Sjmallett */ 778232812Sjmallettunion cvmx_asxx_rld_nctl_strong { 779215976Sjmallett uint64_t u64; 780232812Sjmallett struct cvmx_asxx_rld_nctl_strong_s { 781232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 782215976Sjmallett uint64_t reserved_5_63 : 59; 783215976Sjmallett uint64_t nctl : 5; /**< Duke's drive control */ 784215976Sjmallett#else 785215976Sjmallett uint64_t nctl : 5; 786215976Sjmallett uint64_t reserved_5_63 : 59; 787215976Sjmallett#endif 788215976Sjmallett } s; 789215976Sjmallett struct cvmx_asxx_rld_nctl_strong_s cn38xx; 790215976Sjmallett struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 791215976Sjmallett struct cvmx_asxx_rld_nctl_strong_s cn58xx; 792215976Sjmallett struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 793215976Sjmallett}; 794215976Sjmalletttypedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t; 795215976Sjmallett 796215976Sjmallett/** 797215976Sjmallett * cvmx_asx#_rld_nctl_weak 798215976Sjmallett * 799215976Sjmallett * ASX_RLD_NCTL_WEAK 800215976Sjmallett * 801215976Sjmallett */ 802232812Sjmallettunion cvmx_asxx_rld_nctl_weak { 803215976Sjmallett uint64_t u64; 804232812Sjmallett struct cvmx_asxx_rld_nctl_weak_s { 805232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 806215976Sjmallett uint64_t reserved_5_63 : 59; 807215976Sjmallett uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */ 808215976Sjmallett#else 809215976Sjmallett uint64_t nctl : 5; 810215976Sjmallett uint64_t reserved_5_63 : 59; 811215976Sjmallett#endif 812215976Sjmallett } s; 813215976Sjmallett struct cvmx_asxx_rld_nctl_weak_s cn38xx; 814215976Sjmallett struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 815215976Sjmallett struct cvmx_asxx_rld_nctl_weak_s cn58xx; 816215976Sjmallett struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 817215976Sjmallett}; 818215976Sjmalletttypedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t; 819215976Sjmallett 820215976Sjmallett/** 821215976Sjmallett * cvmx_asx#_rld_pctl_strong 822215976Sjmallett * 823215976Sjmallett * ASX_RLD_PCTL_STRONG 824215976Sjmallett * 825215976Sjmallett */ 826232812Sjmallettunion cvmx_asxx_rld_pctl_strong { 827215976Sjmallett uint64_t u64; 828232812Sjmallett struct cvmx_asxx_rld_pctl_strong_s { 829232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 830215976Sjmallett uint64_t reserved_5_63 : 59; 831215976Sjmallett uint64_t pctl : 5; /**< Duke's drive control */ 832215976Sjmallett#else 833215976Sjmallett uint64_t pctl : 5; 834215976Sjmallett uint64_t reserved_5_63 : 59; 835215976Sjmallett#endif 836215976Sjmallett } s; 837215976Sjmallett struct cvmx_asxx_rld_pctl_strong_s cn38xx; 838215976Sjmallett struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 839215976Sjmallett struct cvmx_asxx_rld_pctl_strong_s cn58xx; 840215976Sjmallett struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 841215976Sjmallett}; 842215976Sjmalletttypedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t; 843215976Sjmallett 844215976Sjmallett/** 845215976Sjmallett * cvmx_asx#_rld_pctl_weak 846215976Sjmallett * 847215976Sjmallett * ASX_RLD_PCTL_WEAK 848215976Sjmallett * 849215976Sjmallett */ 850232812Sjmallettunion cvmx_asxx_rld_pctl_weak { 851215976Sjmallett uint64_t u64; 852232812Sjmallett struct cvmx_asxx_rld_pctl_weak_s { 853232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 854215976Sjmallett uint64_t reserved_5_63 : 59; 855215976Sjmallett uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */ 856215976Sjmallett#else 857215976Sjmallett uint64_t pctl : 5; 858215976Sjmallett uint64_t reserved_5_63 : 59; 859215976Sjmallett#endif 860215976Sjmallett } s; 861215976Sjmallett struct cvmx_asxx_rld_pctl_weak_s cn38xx; 862215976Sjmallett struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 863215976Sjmallett struct cvmx_asxx_rld_pctl_weak_s cn58xx; 864215976Sjmallett struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 865215976Sjmallett}; 866215976Sjmalletttypedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t; 867215976Sjmallett 868215976Sjmallett/** 869215976Sjmallett * cvmx_asx#_rld_setting 870215976Sjmallett * 871215976Sjmallett * ASX_RLD_SETTING 872215976Sjmallett * 873215976Sjmallett */ 874232812Sjmallettunion cvmx_asxx_rld_setting { 875215976Sjmallett uint64_t u64; 876232812Sjmallett struct cvmx_asxx_rld_setting_s { 877232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 878215976Sjmallett uint64_t reserved_13_63 : 51; 879215976Sjmallett uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */ 880215976Sjmallett uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */ 881215976Sjmallett uint64_t dfalead : 1; /**< RLD ClkGen DLL Lead Error(debug) */ 882215976Sjmallett uint64_t dfalock : 1; /**< RLD ClkGen DLL Lock acquisition(debug) */ 883215976Sjmallett uint64_t setting : 5; /**< RLDCK90 DLL Setting(debug) */ 884215976Sjmallett#else 885215976Sjmallett uint64_t setting : 5; 886215976Sjmallett uint64_t dfalock : 1; 887215976Sjmallett uint64_t dfalead : 1; 888215976Sjmallett uint64_t dfalag : 1; 889215976Sjmallett uint64_t dfaset : 5; 890215976Sjmallett uint64_t reserved_13_63 : 51; 891215976Sjmallett#endif 892215976Sjmallett } s; 893232812Sjmallett struct cvmx_asxx_rld_setting_cn38xx { 894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 895215976Sjmallett uint64_t reserved_5_63 : 59; 896215976Sjmallett uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */ 897215976Sjmallett#else 898215976Sjmallett uint64_t setting : 5; 899215976Sjmallett uint64_t reserved_5_63 : 59; 900215976Sjmallett#endif 901215976Sjmallett } cn38xx; 902215976Sjmallett struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 903215976Sjmallett struct cvmx_asxx_rld_setting_s cn58xx; 904215976Sjmallett struct cvmx_asxx_rld_setting_s cn58xxp1; 905215976Sjmallett}; 906215976Sjmalletttypedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t; 907215976Sjmallett 908215976Sjmallett/** 909215976Sjmallett * cvmx_asx#_rx_clk_set# 910215976Sjmallett * 911215976Sjmallett * ASX_RX_CLK_SET = RGMII Clock delay setting 912215976Sjmallett * 913215976Sjmallett * 914215976Sjmallett * Notes: 915215976Sjmallett * Setting to place on the open-loop RXC (RGMII receive clk) 916215976Sjmallett * delay line, which can delay the recieved clock. This 917215976Sjmallett * can be used if the board and/or transmitting device 918215976Sjmallett * has not otherwise delayed the clock. 919215976Sjmallett * 920215976Sjmallett * A value of SETTING=0 disables the delay line. The delay 921215976Sjmallett * line should be disabled unless the transmitter or board 922215976Sjmallett * does not delay the clock. 923215976Sjmallett * 924215976Sjmallett * Note that this delay line provides only a coarse control 925215976Sjmallett * over the delay. Generally, it can only reliably provide 926215976Sjmallett * a delay in the range 1.25-2.5ns, which may not be adequate 927215976Sjmallett * for some system applications. 928215976Sjmallett * 929215976Sjmallett * The open loop delay line selects 930215976Sjmallett * from among a series of tap positions. Each incremental 931215976Sjmallett * tap position adds a delay of 50ps to 135ps per tap, depending 932215976Sjmallett * on the chip, its temperature, and the voltage. 933215976Sjmallett * To achieve from 1.25-2.5ns of delay on the recieved 934215976Sjmallett * clock, a fixed value of SETTING=24 may work. 935215976Sjmallett * For more precision, we recommend the following settings 936215976Sjmallett * based on the chip voltage: 937215976Sjmallett * 938215976Sjmallett * VDD SETTING 939215976Sjmallett * ----------------------------- 940215976Sjmallett * 1.0 18 941215976Sjmallett * 1.05 19 942215976Sjmallett * 1.1 21 943215976Sjmallett * 1.15 22 944215976Sjmallett * 1.2 23 945215976Sjmallett * 1.25 24 946215976Sjmallett * 1.3 25 947215976Sjmallett */ 948232812Sjmallettunion cvmx_asxx_rx_clk_setx { 949215976Sjmallett uint64_t u64; 950232812Sjmallett struct cvmx_asxx_rx_clk_setx_s { 951232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 952215976Sjmallett uint64_t reserved_5_63 : 59; 953215976Sjmallett uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */ 954215976Sjmallett#else 955215976Sjmallett uint64_t setting : 5; 956215976Sjmallett uint64_t reserved_5_63 : 59; 957215976Sjmallett#endif 958215976Sjmallett } s; 959215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn30xx; 960215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn31xx; 961215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn38xx; 962215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 963215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn50xx; 964215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn58xx; 965215976Sjmallett struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 966215976Sjmallett}; 967215976Sjmalletttypedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t; 968215976Sjmallett 969215976Sjmallett/** 970215976Sjmallett * cvmx_asx#_rx_prt_en 971215976Sjmallett * 972215976Sjmallett * ASX_RX_PRT_EN = RGMII Port Enable 973215976Sjmallett * 974215976Sjmallett */ 975232812Sjmallettunion cvmx_asxx_rx_prt_en { 976215976Sjmallett uint64_t u64; 977232812Sjmallett struct cvmx_asxx_rx_prt_en_s { 978232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 979215976Sjmallett uint64_t reserved_4_63 : 60; 980215976Sjmallett uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive 981215976Sjmallett RMGII traffic. When this bit clear on a given 982215976Sjmallett port, then the all RGMII cycles will appear as 983215976Sjmallett inter-frame cycles. */ 984215976Sjmallett#else 985215976Sjmallett uint64_t prt_en : 4; 986215976Sjmallett uint64_t reserved_4_63 : 60; 987215976Sjmallett#endif 988215976Sjmallett } s; 989232812Sjmallett struct cvmx_asxx_rx_prt_en_cn30xx { 990232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 991215976Sjmallett uint64_t reserved_3_63 : 61; 992215976Sjmallett uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive 993215976Sjmallett RMGII traffic. When this bit clear on a given 994215976Sjmallett port, then the all RGMII cycles will appear as 995215976Sjmallett inter-frame cycles. */ 996215976Sjmallett#else 997215976Sjmallett uint64_t prt_en : 3; 998215976Sjmallett uint64_t reserved_3_63 : 61; 999215976Sjmallett#endif 1000215976Sjmallett } cn30xx; 1001215976Sjmallett struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 1002215976Sjmallett struct cvmx_asxx_rx_prt_en_s cn38xx; 1003215976Sjmallett struct cvmx_asxx_rx_prt_en_s cn38xxp2; 1004215976Sjmallett struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 1005215976Sjmallett struct cvmx_asxx_rx_prt_en_s cn58xx; 1006215976Sjmallett struct cvmx_asxx_rx_prt_en_s cn58xxp1; 1007215976Sjmallett}; 1008215976Sjmalletttypedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t; 1009215976Sjmallett 1010215976Sjmallett/** 1011215976Sjmallett * cvmx_asx#_rx_wol 1012215976Sjmallett * 1013215976Sjmallett * ASX_RX_WOL = RGMII RX Wake on LAN status register 1014215976Sjmallett * 1015215976Sjmallett */ 1016232812Sjmallettunion cvmx_asxx_rx_wol { 1017215976Sjmallett uint64_t u64; 1018232812Sjmallett struct cvmx_asxx_rx_wol_s { 1019232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1020215976Sjmallett uint64_t reserved_2_63 : 62; 1021215976Sjmallett uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */ 1022215976Sjmallett uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */ 1023215976Sjmallett#else 1024215976Sjmallett uint64_t enable : 1; 1025215976Sjmallett uint64_t status : 1; 1026215976Sjmallett uint64_t reserved_2_63 : 62; 1027215976Sjmallett#endif 1028215976Sjmallett } s; 1029215976Sjmallett struct cvmx_asxx_rx_wol_s cn38xx; 1030215976Sjmallett struct cvmx_asxx_rx_wol_s cn38xxp2; 1031215976Sjmallett}; 1032215976Sjmalletttypedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t; 1033215976Sjmallett 1034215976Sjmallett/** 1035215976Sjmallett * cvmx_asx#_rx_wol_msk 1036215976Sjmallett * 1037215976Sjmallett * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask 1038215976Sjmallett * 1039215976Sjmallett */ 1040232812Sjmallettunion cvmx_asxx_rx_wol_msk { 1041215976Sjmallett uint64_t u64; 1042232812Sjmallett struct cvmx_asxx_rx_wol_msk_s { 1043232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1044215976Sjmallett uint64_t msk : 64; /**< Bytes to include in the CRC signature */ 1045215976Sjmallett#else 1046215976Sjmallett uint64_t msk : 64; 1047215976Sjmallett#endif 1048215976Sjmallett } s; 1049215976Sjmallett struct cvmx_asxx_rx_wol_msk_s cn38xx; 1050215976Sjmallett struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 1051215976Sjmallett}; 1052215976Sjmalletttypedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t; 1053215976Sjmallett 1054215976Sjmallett/** 1055215976Sjmallett * cvmx_asx#_rx_wol_powok 1056215976Sjmallett * 1057215976Sjmallett * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK 1058215976Sjmallett * 1059215976Sjmallett */ 1060232812Sjmallettunion cvmx_asxx_rx_wol_powok { 1061215976Sjmallett uint64_t u64; 1062232812Sjmallett struct cvmx_asxx_rx_wol_powok_s { 1063232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1064215976Sjmallett uint64_t reserved_1_63 : 63; 1065215976Sjmallett uint64_t powerok : 1; /**< Power OK */ 1066215976Sjmallett#else 1067215976Sjmallett uint64_t powerok : 1; 1068215976Sjmallett uint64_t reserved_1_63 : 63; 1069215976Sjmallett#endif 1070215976Sjmallett } s; 1071215976Sjmallett struct cvmx_asxx_rx_wol_powok_s cn38xx; 1072215976Sjmallett struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 1073215976Sjmallett}; 1074215976Sjmalletttypedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t; 1075215976Sjmallett 1076215976Sjmallett/** 1077215976Sjmallett * cvmx_asx#_rx_wol_sig 1078215976Sjmallett * 1079215976Sjmallett * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature 1080215976Sjmallett * 1081215976Sjmallett */ 1082232812Sjmallettunion cvmx_asxx_rx_wol_sig { 1083215976Sjmallett uint64_t u64; 1084232812Sjmallett struct cvmx_asxx_rx_wol_sig_s { 1085232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1086215976Sjmallett uint64_t reserved_32_63 : 32; 1087215976Sjmallett uint64_t sig : 32; /**< CRC signature */ 1088215976Sjmallett#else 1089215976Sjmallett uint64_t sig : 32; 1090215976Sjmallett uint64_t reserved_32_63 : 32; 1091215976Sjmallett#endif 1092215976Sjmallett } s; 1093215976Sjmallett struct cvmx_asxx_rx_wol_sig_s cn38xx; 1094215976Sjmallett struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 1095215976Sjmallett}; 1096215976Sjmalletttypedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t; 1097215976Sjmallett 1098215976Sjmallett/** 1099215976Sjmallett * cvmx_asx#_tx_clk_set# 1100215976Sjmallett * 1101215976Sjmallett * ASX_TX_CLK_SET = RGMII Clock delay setting 1102215976Sjmallett * 1103215976Sjmallett * 1104215976Sjmallett * Notes: 1105215976Sjmallett * Setting to place on the open-loop TXC (RGMII transmit clk) 1106215976Sjmallett * delay line, which can delay the transmited clock. This 1107215976Sjmallett * can be used if the board and/or transmitting device 1108215976Sjmallett * has not otherwise delayed the clock. 1109215976Sjmallett * 1110215976Sjmallett * A value of SETTING=0 disables the delay line. The delay 1111215976Sjmallett * line should be disabled unless the transmitter or board 1112215976Sjmallett * does not delay the clock. 1113215976Sjmallett * 1114215976Sjmallett * Note that this delay line provides only a coarse control 1115215976Sjmallett * over the delay. Generally, it can only reliably provide 1116215976Sjmallett * a delay in the range 1.25-2.5ns, which may not be adequate 1117215976Sjmallett * for some system applications. 1118215976Sjmallett * 1119215976Sjmallett * The open loop delay line selects 1120215976Sjmallett * from among a series of tap positions. Each incremental 1121215976Sjmallett * tap position adds a delay of 50ps to 135ps per tap, depending 1122215976Sjmallett * on the chip, its temperature, and the voltage. 1123215976Sjmallett * To achieve from 1.25-2.5ns of delay on the recieved 1124215976Sjmallett * clock, a fixed value of SETTING=24 may work. 1125215976Sjmallett * For more precision, we recommend the following settings 1126215976Sjmallett * based on the chip voltage: 1127215976Sjmallett * 1128215976Sjmallett * VDD SETTING 1129215976Sjmallett * ----------------------------- 1130215976Sjmallett * 1.0 18 1131215976Sjmallett * 1.05 19 1132215976Sjmallett * 1.1 21 1133215976Sjmallett * 1.15 22 1134215976Sjmallett * 1.2 23 1135215976Sjmallett * 1.25 24 1136215976Sjmallett * 1.3 25 1137215976Sjmallett */ 1138232812Sjmallettunion cvmx_asxx_tx_clk_setx { 1139215976Sjmallett uint64_t u64; 1140232812Sjmallett struct cvmx_asxx_tx_clk_setx_s { 1141232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1142215976Sjmallett uint64_t reserved_5_63 : 59; 1143215976Sjmallett uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */ 1144215976Sjmallett#else 1145215976Sjmallett uint64_t setting : 5; 1146215976Sjmallett uint64_t reserved_5_63 : 59; 1147215976Sjmallett#endif 1148215976Sjmallett } s; 1149215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn30xx; 1150215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn31xx; 1151215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn38xx; 1152215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 1153215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn50xx; 1154215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn58xx; 1155215976Sjmallett struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 1156215976Sjmallett}; 1157215976Sjmalletttypedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t; 1158215976Sjmallett 1159215976Sjmallett/** 1160215976Sjmallett * cvmx_asx#_tx_comp_byp 1161215976Sjmallett * 1162215976Sjmallett * ASX_TX_COMP_BYP = RGMII Clock delay setting 1163215976Sjmallett * 1164215976Sjmallett */ 1165232812Sjmallettunion cvmx_asxx_tx_comp_byp { 1166215976Sjmallett uint64_t u64; 1167232812Sjmallett struct cvmx_asxx_tx_comp_byp_s { 1168232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1169215976Sjmallett uint64_t reserved_0_63 : 64; 1170215976Sjmallett#else 1171215976Sjmallett uint64_t reserved_0_63 : 64; 1172215976Sjmallett#endif 1173215976Sjmallett } s; 1174232812Sjmallett struct cvmx_asxx_tx_comp_byp_cn30xx { 1175232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1176215976Sjmallett uint64_t reserved_9_63 : 55; 1177215976Sjmallett uint64_t bypass : 1; /**< Compensation bypass */ 1178215976Sjmallett uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1179215976Sjmallett uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1180215976Sjmallett#else 1181215976Sjmallett uint64_t nctl : 4; 1182215976Sjmallett uint64_t pctl : 4; 1183215976Sjmallett uint64_t bypass : 1; 1184215976Sjmallett uint64_t reserved_9_63 : 55; 1185215976Sjmallett#endif 1186215976Sjmallett } cn30xx; 1187215976Sjmallett struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 1188232812Sjmallett struct cvmx_asxx_tx_comp_byp_cn38xx { 1189232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1190215976Sjmallett uint64_t reserved_8_63 : 56; 1191215976Sjmallett uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1192215976Sjmallett uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1193215976Sjmallett#else 1194215976Sjmallett uint64_t nctl : 4; 1195215976Sjmallett uint64_t pctl : 4; 1196215976Sjmallett uint64_t reserved_8_63 : 56; 1197215976Sjmallett#endif 1198215976Sjmallett } cn38xx; 1199215976Sjmallett struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 1200232812Sjmallett struct cvmx_asxx_tx_comp_byp_cn50xx { 1201232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1202215976Sjmallett uint64_t reserved_17_63 : 47; 1203215976Sjmallett uint64_t bypass : 1; /**< Compensation bypass */ 1204215976Sjmallett uint64_t reserved_13_15 : 3; 1205215976Sjmallett uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1206215976Sjmallett uint64_t reserved_5_7 : 3; 1207215976Sjmallett uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1208215976Sjmallett#else 1209215976Sjmallett uint64_t nctl : 5; 1210215976Sjmallett uint64_t reserved_5_7 : 3; 1211215976Sjmallett uint64_t pctl : 5; 1212215976Sjmallett uint64_t reserved_13_15 : 3; 1213215976Sjmallett uint64_t bypass : 1; 1214215976Sjmallett uint64_t reserved_17_63 : 47; 1215215976Sjmallett#endif 1216215976Sjmallett } cn50xx; 1217232812Sjmallett struct cvmx_asxx_tx_comp_byp_cn58xx { 1218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1219215976Sjmallett uint64_t reserved_13_63 : 51; 1220215976Sjmallett uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1221215976Sjmallett uint64_t reserved_5_7 : 3; 1222215976Sjmallett uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1223215976Sjmallett#else 1224215976Sjmallett uint64_t nctl : 5; 1225215976Sjmallett uint64_t reserved_5_7 : 3; 1226215976Sjmallett uint64_t pctl : 5; 1227215976Sjmallett uint64_t reserved_13_63 : 51; 1228215976Sjmallett#endif 1229215976Sjmallett } cn58xx; 1230215976Sjmallett struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 1231215976Sjmallett}; 1232215976Sjmalletttypedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t; 1233215976Sjmallett 1234215976Sjmallett/** 1235215976Sjmallett * cvmx_asx#_tx_hi_water# 1236215976Sjmallett * 1237215976Sjmallett * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark 1238215976Sjmallett * 1239215976Sjmallett */ 1240232812Sjmallettunion cvmx_asxx_tx_hi_waterx { 1241215976Sjmallett uint64_t u64; 1242232812Sjmallett struct cvmx_asxx_tx_hi_waterx_s { 1243232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1244215976Sjmallett uint64_t reserved_4_63 : 60; 1245215976Sjmallett uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX 1246215976Sjmallett Value of 0 maps to 16 1247215976Sjmallett Reset value changed from 10 in pass1 1248215976Sjmallett Pass1 settings (assuming 125 tclk) 1249215976Sjmallett - 325-375: 12 1250215976Sjmallett - 375-437: 11 1251215976Sjmallett - 437-550: 10 1252215976Sjmallett - 550-687: 9 */ 1253215976Sjmallett#else 1254215976Sjmallett uint64_t mark : 4; 1255215976Sjmallett uint64_t reserved_4_63 : 60; 1256215976Sjmallett#endif 1257215976Sjmallett } s; 1258232812Sjmallett struct cvmx_asxx_tx_hi_waterx_cn30xx { 1259232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1260215976Sjmallett uint64_t reserved_3_63 : 61; 1261215976Sjmallett uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX 1262215976Sjmallett Value 0 maps to 8. */ 1263215976Sjmallett#else 1264215976Sjmallett uint64_t mark : 3; 1265215976Sjmallett uint64_t reserved_3_63 : 61; 1266215976Sjmallett#endif 1267215976Sjmallett } cn30xx; 1268215976Sjmallett struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 1269215976Sjmallett struct cvmx_asxx_tx_hi_waterx_s cn38xx; 1270215976Sjmallett struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 1271215976Sjmallett struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 1272215976Sjmallett struct cvmx_asxx_tx_hi_waterx_s cn58xx; 1273215976Sjmallett struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 1274215976Sjmallett}; 1275215976Sjmalletttypedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t; 1276215976Sjmallett 1277215976Sjmallett/** 1278215976Sjmallett * cvmx_asx#_tx_prt_en 1279215976Sjmallett * 1280215976Sjmallett * ASX_TX_PRT_EN = RGMII Port Enable 1281215976Sjmallett * 1282215976Sjmallett */ 1283232812Sjmallettunion cvmx_asxx_tx_prt_en { 1284215976Sjmallett uint64_t u64; 1285232812Sjmallett struct cvmx_asxx_tx_prt_en_s { 1286232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1287215976Sjmallett uint64_t reserved_4_63 : 60; 1288215976Sjmallett uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send 1289215976Sjmallett RMGII traffic. When this bit clear on a given 1290215976Sjmallett port, then all RGMII cycles will appear as 1291215976Sjmallett inter-frame cycles. */ 1292215976Sjmallett#else 1293215976Sjmallett uint64_t prt_en : 4; 1294215976Sjmallett uint64_t reserved_4_63 : 60; 1295215976Sjmallett#endif 1296215976Sjmallett } s; 1297232812Sjmallett struct cvmx_asxx_tx_prt_en_cn30xx { 1298232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1299215976Sjmallett uint64_t reserved_3_63 : 61; 1300215976Sjmallett uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send 1301215976Sjmallett RMGII traffic. When this bit clear on a given 1302215976Sjmallett port, then all RGMII cycles will appear as 1303215976Sjmallett inter-frame cycles. */ 1304215976Sjmallett#else 1305215976Sjmallett uint64_t prt_en : 3; 1306215976Sjmallett uint64_t reserved_3_63 : 61; 1307215976Sjmallett#endif 1308215976Sjmallett } cn30xx; 1309215976Sjmallett struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 1310215976Sjmallett struct cvmx_asxx_tx_prt_en_s cn38xx; 1311215976Sjmallett struct cvmx_asxx_tx_prt_en_s cn38xxp2; 1312215976Sjmallett struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 1313215976Sjmallett struct cvmx_asxx_tx_prt_en_s cn58xx; 1314215976Sjmallett struct cvmx_asxx_tx_prt_en_s cn58xxp1; 1315215976Sjmallett}; 1316215976Sjmalletttypedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t; 1317215976Sjmallett 1318215976Sjmallett#endif 1319