1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-dfa-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon dfa. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_DFA_DEFS_H__ 53#define __CVMX_DFA_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_DFA_BIST0 CVMX_DFA_BIST0_FUNC() 57static inline uint64_t CVMX_DFA_BIST0_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60 cvmx_warn("CVMX_DFA_BIST0 not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011800370007F0ull); 62} 63#else 64#define CVMX_DFA_BIST0 (CVMX_ADD_IO_SEG(0x00011800370007F0ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_DFA_BIST1 CVMX_DFA_BIST1_FUNC() 68static inline uint64_t CVMX_DFA_BIST1_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71 cvmx_warn("CVMX_DFA_BIST1 not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x00011800370007F8ull); 73} 74#else 75#define CVMX_DFA_BIST1 (CVMX_ADD_IO_SEG(0x00011800370007F8ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC() 79static inline uint64_t CVMX_DFA_BST0_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 82 cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x00011800300007F0ull); 84} 85#else 86#define CVMX_DFA_BST0 (CVMX_ADD_IO_SEG(0x00011800300007F0ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC() 90static inline uint64_t CVMX_DFA_BST1_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 93 cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x00011800300007F8ull); 95} 96#else 97#define CVMX_DFA_BST1 (CVMX_ADD_IO_SEG(0x00011800300007F8ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC() 101static inline uint64_t CVMX_DFA_CFG_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 104 cvmx_warn("CVMX_DFA_CFG not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001180030000000ull); 106} 107#else 108#define CVMX_DFA_CFG (CVMX_ADD_IO_SEG(0x0001180030000000ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_DFA_CONFIG CVMX_DFA_CONFIG_FUNC() 112static inline uint64_t CVMX_DFA_CONFIG_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 115 cvmx_warn("CVMX_DFA_CONFIG not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180037000000ull); 117} 118#else 119#define CVMX_DFA_CONFIG (CVMX_ADD_IO_SEG(0x0001180037000000ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_DFA_CONTROL CVMX_DFA_CONTROL_FUNC() 123static inline uint64_t CVMX_DFA_CONTROL_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 126 cvmx_warn("CVMX_DFA_CONTROL not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180037000020ull); 128} 129#else 130#define CVMX_DFA_CONTROL (CVMX_ADD_IO_SEG(0x0001180037000020ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC() 134static inline uint64_t CVMX_DFA_DBELL_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 137 cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001370000000000ull); 139} 140#else 141#define CVMX_DFA_DBELL (CVMX_ADD_IO_SEG(0x0001370000000000ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC() 145static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 148 cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x0001180030000210ull); 150} 151#else 152#define CVMX_DFA_DDR2_ADDR (CVMX_ADD_IO_SEG(0x0001180030000210ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC() 156static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 159 cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x0001180030000080ull); 161} 162#else 163#define CVMX_DFA_DDR2_BUS (CVMX_ADD_IO_SEG(0x0001180030000080ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC() 167static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 170 cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x0001180030000208ull); 172} 173#else 174#define CVMX_DFA_DDR2_CFG (CVMX_ADD_IO_SEG(0x0001180030000208ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC() 178static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 181 cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001180030000090ull); 183} 184#else 185#define CVMX_DFA_DDR2_COMP (CVMX_ADD_IO_SEG(0x0001180030000090ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC() 189static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 192 cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001180030000268ull); 194} 195#else 196#define CVMX_DFA_DDR2_EMRS (CVMX_ADD_IO_SEG(0x0001180030000268ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC() 200static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 203 cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x0001180030000078ull); 205} 206#else 207#define CVMX_DFA_DDR2_FCNT (CVMX_ADD_IO_SEG(0x0001180030000078ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC() 211static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 214 cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x0001180030000260ull); 216} 217#else 218#define CVMX_DFA_DDR2_MRS (CVMX_ADD_IO_SEG(0x0001180030000260ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC() 222static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 225 cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x0001180030000070ull); 227} 228#else 229#define CVMX_DFA_DDR2_OPT (CVMX_ADD_IO_SEG(0x0001180030000070ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC() 233static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 236 cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n"); 237 return CVMX_ADD_IO_SEG(0x0001180030000088ull); 238} 239#else 240#define CVMX_DFA_DDR2_PLL (CVMX_ADD_IO_SEG(0x0001180030000088ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC() 244static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void) 245{ 246 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 247 cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n"); 248 return CVMX_ADD_IO_SEG(0x0001180030000218ull); 249} 250#else 251#define CVMX_DFA_DDR2_TMG (CVMX_ADD_IO_SEG(0x0001180030000218ull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_DFA_DEBUG0 CVMX_DFA_DEBUG0_FUNC() 255static inline uint64_t CVMX_DFA_DEBUG0_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 258 cvmx_warn("CVMX_DFA_DEBUG0 not supported on this chip\n"); 259 return CVMX_ADD_IO_SEG(0x0001180037000040ull); 260} 261#else 262#define CVMX_DFA_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180037000040ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_DFA_DEBUG1 CVMX_DFA_DEBUG1_FUNC() 266static inline uint64_t CVMX_DFA_DEBUG1_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 269 cvmx_warn("CVMX_DFA_DEBUG1 not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x0001180037000048ull); 271} 272#else 273#define CVMX_DFA_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180037000048ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_DFA_DEBUG2 CVMX_DFA_DEBUG2_FUNC() 277static inline uint64_t CVMX_DFA_DEBUG2_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 280 cvmx_warn("CVMX_DFA_DEBUG2 not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x0001180037000050ull); 282} 283#else 284#define CVMX_DFA_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180037000050ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_DFA_DEBUG3 CVMX_DFA_DEBUG3_FUNC() 288static inline uint64_t CVMX_DFA_DEBUG3_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 291 cvmx_warn("CVMX_DFA_DEBUG3 not supported on this chip\n"); 292 return CVMX_ADD_IO_SEG(0x0001180037000058ull); 293} 294#else 295#define CVMX_DFA_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180037000058ull)) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC() 299static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void) 300{ 301 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 302 cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n"); 303 return CVMX_ADD_IO_SEG(0x0001370600000000ull); 304} 305#else 306#define CVMX_DFA_DIFCTL (CVMX_ADD_IO_SEG(0x0001370600000000ull)) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC() 310static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void) 311{ 312 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 313 cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n"); 314 return CVMX_ADD_IO_SEG(0x0001370200000000ull); 315} 316#else 317#define CVMX_DFA_DIFRDPTR (CVMX_ADD_IO_SEG(0x0001370200000000ull)) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320#define CVMX_DFA_DTCFADR CVMX_DFA_DTCFADR_FUNC() 321static inline uint64_t CVMX_DFA_DTCFADR_FUNC(void) 322{ 323 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 324 cvmx_warn("CVMX_DFA_DTCFADR not supported on this chip\n"); 325 return CVMX_ADD_IO_SEG(0x0001180037000060ull); 326} 327#else 328#define CVMX_DFA_DTCFADR (CVMX_ADD_IO_SEG(0x0001180037000060ull)) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC() 332static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void) 333{ 334 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX))) 335 cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n"); 336 return CVMX_ADD_IO_SEG(0x0001180030000200ull); 337} 338#else 339#define CVMX_DFA_ECLKCFG (CVMX_ADD_IO_SEG(0x0001180030000200ull)) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC() 343static inline uint64_t CVMX_DFA_ERR_FUNC(void) 344{ 345 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 346 cvmx_warn("CVMX_DFA_ERR not supported on this chip\n"); 347 return CVMX_ADD_IO_SEG(0x0001180030000028ull); 348} 349#else 350#define CVMX_DFA_ERR (CVMX_ADD_IO_SEG(0x0001180030000028ull)) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353#define CVMX_DFA_ERROR CVMX_DFA_ERROR_FUNC() 354static inline uint64_t CVMX_DFA_ERROR_FUNC(void) 355{ 356 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 357 cvmx_warn("CVMX_DFA_ERROR not supported on this chip\n"); 358 return CVMX_ADD_IO_SEG(0x0001180037000028ull); 359} 360#else 361#define CVMX_DFA_ERROR (CVMX_ADD_IO_SEG(0x0001180037000028ull)) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364#define CVMX_DFA_INTMSK CVMX_DFA_INTMSK_FUNC() 365static inline uint64_t CVMX_DFA_INTMSK_FUNC(void) 366{ 367 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 368 cvmx_warn("CVMX_DFA_INTMSK not supported on this chip\n"); 369 return CVMX_ADD_IO_SEG(0x0001180037000030ull); 370} 371#else 372#define CVMX_DFA_INTMSK (CVMX_ADD_IO_SEG(0x0001180037000030ull)) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC() 376static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void) 377{ 378 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 379 cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n"); 380 return CVMX_ADD_IO_SEG(0x0001180030000008ull); 381} 382#else 383#define CVMX_DFA_MEMCFG0 (CVMX_ADD_IO_SEG(0x0001180030000008ull)) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC() 387static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void) 388{ 389 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 390 cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n"); 391 return CVMX_ADD_IO_SEG(0x0001180030000010ull); 392} 393#else 394#define CVMX_DFA_MEMCFG1 (CVMX_ADD_IO_SEG(0x0001180030000010ull)) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC() 398static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void) 399{ 400 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 401 cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n"); 402 return CVMX_ADD_IO_SEG(0x0001180030000060ull); 403} 404#else 405#define CVMX_DFA_MEMCFG2 (CVMX_ADD_IO_SEG(0x0001180030000060ull)) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC() 409static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void) 410{ 411 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 412 cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n"); 413 return CVMX_ADD_IO_SEG(0x0001180030000030ull); 414} 415#else 416#define CVMX_DFA_MEMFADR (CVMX_ADD_IO_SEG(0x0001180030000030ull)) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC() 420static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void) 421{ 422 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 423 cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n"); 424 return CVMX_ADD_IO_SEG(0x0001180030000038ull); 425} 426#else 427#define CVMX_DFA_MEMFCR (CVMX_ADD_IO_SEG(0x0001180030000038ull)) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430#define CVMX_DFA_MEMHIDAT CVMX_DFA_MEMHIDAT_FUNC() 431static inline uint64_t CVMX_DFA_MEMHIDAT_FUNC(void) 432{ 433 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 434 cvmx_warn("CVMX_DFA_MEMHIDAT not supported on this chip\n"); 435 return CVMX_ADD_IO_SEG(0x0001370700000000ull); 436} 437#else 438#define CVMX_DFA_MEMHIDAT (CVMX_ADD_IO_SEG(0x0001370700000000ull)) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC() 442static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void) 443{ 444 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 445 cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n"); 446 return CVMX_ADD_IO_SEG(0x0001180030000018ull); 447} 448#else 449#define CVMX_DFA_MEMRLD (CVMX_ADD_IO_SEG(0x0001180030000018ull)) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC() 453static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void) 454{ 455 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 456 cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n"); 457 return CVMX_ADD_IO_SEG(0x0001180030000020ull); 458} 459#else 460#define CVMX_DFA_NCBCTL (CVMX_ADD_IO_SEG(0x0001180030000020ull)) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463#define CVMX_DFA_PFC0_CNT CVMX_DFA_PFC0_CNT_FUNC() 464static inline uint64_t CVMX_DFA_PFC0_CNT_FUNC(void) 465{ 466 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 467 cvmx_warn("CVMX_DFA_PFC0_CNT not supported on this chip\n"); 468 return CVMX_ADD_IO_SEG(0x0001180037000090ull); 469} 470#else 471#define CVMX_DFA_PFC0_CNT (CVMX_ADD_IO_SEG(0x0001180037000090ull)) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474#define CVMX_DFA_PFC0_CTL CVMX_DFA_PFC0_CTL_FUNC() 475static inline uint64_t CVMX_DFA_PFC0_CTL_FUNC(void) 476{ 477 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 478 cvmx_warn("CVMX_DFA_PFC0_CTL not supported on this chip\n"); 479 return CVMX_ADD_IO_SEG(0x0001180037000088ull); 480} 481#else 482#define CVMX_DFA_PFC0_CTL (CVMX_ADD_IO_SEG(0x0001180037000088ull)) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485#define CVMX_DFA_PFC1_CNT CVMX_DFA_PFC1_CNT_FUNC() 486static inline uint64_t CVMX_DFA_PFC1_CNT_FUNC(void) 487{ 488 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 489 cvmx_warn("CVMX_DFA_PFC1_CNT not supported on this chip\n"); 490 return CVMX_ADD_IO_SEG(0x00011800370000A0ull); 491} 492#else 493#define CVMX_DFA_PFC1_CNT (CVMX_ADD_IO_SEG(0x00011800370000A0ull)) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496#define CVMX_DFA_PFC1_CTL CVMX_DFA_PFC1_CTL_FUNC() 497static inline uint64_t CVMX_DFA_PFC1_CTL_FUNC(void) 498{ 499 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 500 cvmx_warn("CVMX_DFA_PFC1_CTL not supported on this chip\n"); 501 return CVMX_ADD_IO_SEG(0x0001180037000098ull); 502} 503#else 504#define CVMX_DFA_PFC1_CTL (CVMX_ADD_IO_SEG(0x0001180037000098ull)) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507#define CVMX_DFA_PFC2_CNT CVMX_DFA_PFC2_CNT_FUNC() 508static inline uint64_t CVMX_DFA_PFC2_CNT_FUNC(void) 509{ 510 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 511 cvmx_warn("CVMX_DFA_PFC2_CNT not supported on this chip\n"); 512 return CVMX_ADD_IO_SEG(0x00011800370000B0ull); 513} 514#else 515#define CVMX_DFA_PFC2_CNT (CVMX_ADD_IO_SEG(0x00011800370000B0ull)) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518#define CVMX_DFA_PFC2_CTL CVMX_DFA_PFC2_CTL_FUNC() 519static inline uint64_t CVMX_DFA_PFC2_CTL_FUNC(void) 520{ 521 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 522 cvmx_warn("CVMX_DFA_PFC2_CTL not supported on this chip\n"); 523 return CVMX_ADD_IO_SEG(0x00011800370000A8ull); 524} 525#else 526#define CVMX_DFA_PFC2_CTL (CVMX_ADD_IO_SEG(0x00011800370000A8ull)) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529#define CVMX_DFA_PFC3_CNT CVMX_DFA_PFC3_CNT_FUNC() 530static inline uint64_t CVMX_DFA_PFC3_CNT_FUNC(void) 531{ 532 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 533 cvmx_warn("CVMX_DFA_PFC3_CNT not supported on this chip\n"); 534 return CVMX_ADD_IO_SEG(0x00011800370000C0ull); 535} 536#else 537#define CVMX_DFA_PFC3_CNT (CVMX_ADD_IO_SEG(0x00011800370000C0ull)) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540#define CVMX_DFA_PFC3_CTL CVMX_DFA_PFC3_CTL_FUNC() 541static inline uint64_t CVMX_DFA_PFC3_CTL_FUNC(void) 542{ 543 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 544 cvmx_warn("CVMX_DFA_PFC3_CTL not supported on this chip\n"); 545 return CVMX_ADD_IO_SEG(0x00011800370000B8ull); 546} 547#else 548#define CVMX_DFA_PFC3_CTL (CVMX_ADD_IO_SEG(0x00011800370000B8ull)) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551#define CVMX_DFA_PFC_GCTL CVMX_DFA_PFC_GCTL_FUNC() 552static inline uint64_t CVMX_DFA_PFC_GCTL_FUNC(void) 553{ 554 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 555 cvmx_warn("CVMX_DFA_PFC_GCTL not supported on this chip\n"); 556 return CVMX_ADD_IO_SEG(0x0001180037000080ull); 557} 558#else 559#define CVMX_DFA_PFC_GCTL (CVMX_ADD_IO_SEG(0x0001180037000080ull)) 560#endif 561#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC() 563static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void) 564{ 565 if (!(OCTEON_IS_MODEL(OCTEON_CN58XX))) 566 cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n"); 567 return CVMX_ADD_IO_SEG(0x0001180030000068ull); 568} 569#else 570#define CVMX_DFA_RODT_COMP_CTL (CVMX_ADD_IO_SEG(0x0001180030000068ull)) 571#endif 572#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC() 574static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void) 575{ 576 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 577 cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n"); 578 return CVMX_ADD_IO_SEG(0x0001180030000040ull); 579} 580#else 581#define CVMX_DFA_SBD_DBG0 (CVMX_ADD_IO_SEG(0x0001180030000040ull)) 582#endif 583#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC() 585static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void) 586{ 587 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 588 cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n"); 589 return CVMX_ADD_IO_SEG(0x0001180030000048ull); 590} 591#else 592#define CVMX_DFA_SBD_DBG1 (CVMX_ADD_IO_SEG(0x0001180030000048ull)) 593#endif 594#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC() 596static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void) 597{ 598 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 599 cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n"); 600 return CVMX_ADD_IO_SEG(0x0001180030000050ull); 601} 602#else 603#define CVMX_DFA_SBD_DBG2 (CVMX_ADD_IO_SEG(0x0001180030000050ull)) 604#endif 605#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC() 607static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void) 608{ 609 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 610 cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n"); 611 return CVMX_ADD_IO_SEG(0x0001180030000058ull); 612} 613#else 614#define CVMX_DFA_SBD_DBG3 (CVMX_ADD_IO_SEG(0x0001180030000058ull)) 615#endif 616 617/** 618 * cvmx_dfa_bist0 619 * 620 * DFA_BIST0 = DFA Bist Status (per-DTC) 621 * 622 * Description: 623 */ 624union cvmx_dfa_bist0 { 625 uint64_t u64; 626 struct cvmx_dfa_bist0_s { 627#ifdef __BIG_ENDIAN_BITFIELD 628 uint64_t reserved_27_63 : 37; 629 uint64_t gfb : 3; /**< Bist Results for GFB RAM(s) (per-cluster) 630 - 0: GOOD (or bist in progress/never run) 631 - 1: BAD */ 632 uint64_t reserved_22_23 : 2; 633 uint64_t stx2 : 2; /**< Bist Results for STX2 RAM(s) 634 - 0: GOOD (or bist in progress/never run) 635 - 1: BAD */ 636 uint64_t stx1 : 2; /**< Bist Results for STX1 RAM(s) 637 - 0: GOOD (or bist in progress/never run) 638 - 1: BAD */ 639 uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 640 - 0: GOOD (or bist in progress/never run) 641 - 1: BAD */ 642 uint64_t reserved_14_15 : 2; 643 uint64_t dtx2 : 2; /**< Bist Results for DTX2 RAM(s) 644 - 0: GOOD (or bist in progress/never run) 645 - 1: BAD */ 646 uint64_t dtx1 : 2; /**< Bist Results for DTX1 RAM(s) 647 - 0: GOOD (or bist in progress/never run) 648 - 1: BAD */ 649 uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 650 - 0: GOOD (or bist in progress/never run) 651 - 1: BAD */ 652 uint64_t reserved_7_7 : 1; 653 uint64_t rdf : 3; /**< Bist Results for RWB RAM(s) (per-cluster) 654 - 0: GOOD (or bist in progress/never run) 655 - 1: BAD */ 656 uint64_t reserved_3_3 : 1; 657 uint64_t pdb : 3; /**< Bist Results for PDB RAM(s) (per-cluster) 658 - 0: GOOD (or bist in progress/never run) 659 - 1: BAD */ 660#else 661 uint64_t pdb : 3; 662 uint64_t reserved_3_3 : 1; 663 uint64_t rdf : 3; 664 uint64_t reserved_7_7 : 1; 665 uint64_t dtx : 2; 666 uint64_t dtx1 : 2; 667 uint64_t dtx2 : 2; 668 uint64_t reserved_14_15 : 2; 669 uint64_t stx : 2; 670 uint64_t stx1 : 2; 671 uint64_t stx2 : 2; 672 uint64_t reserved_22_23 : 2; 673 uint64_t gfb : 3; 674 uint64_t reserved_27_63 : 37; 675#endif 676 } s; 677 struct cvmx_dfa_bist0_cn61xx { 678#ifdef __BIG_ENDIAN_BITFIELD 679 uint64_t reserved_25_63 : 39; 680 uint64_t gfb : 1; /**< Bist Results for GFB RAM(s) (per-cluster) 681 - 0: GOOD (or bist in progress/never run) 682 - 1: BAD */ 683 uint64_t reserved_18_23 : 6; 684 uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 685 - 0: GOOD (or bist in progress/never run) 686 - 1: BAD */ 687 uint64_t reserved_10_15 : 6; 688 uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 689 - 0: GOOD (or bist in progress/never run) 690 - 1: BAD */ 691 uint64_t reserved_5_7 : 3; 692 uint64_t rdf : 1; /**< Bist Results for RWB RAM(s) (per-cluster) 693 - 0: GOOD (or bist in progress/never run) 694 - 1: BAD */ 695 uint64_t reserved_1_3 : 3; 696 uint64_t pdb : 1; /**< Bist Results for PDB RAM(s) (per-cluster) 697 - 0: GOOD (or bist in progress/never run) 698 - 1: BAD */ 699#else 700 uint64_t pdb : 1; 701 uint64_t reserved_1_3 : 3; 702 uint64_t rdf : 1; 703 uint64_t reserved_5_7 : 3; 704 uint64_t dtx : 2; 705 uint64_t reserved_10_15 : 6; 706 uint64_t stx : 2; 707 uint64_t reserved_18_23 : 6; 708 uint64_t gfb : 1; 709 uint64_t reserved_25_63 : 39; 710#endif 711 } cn61xx; 712 struct cvmx_dfa_bist0_cn63xx { 713#ifdef __BIG_ENDIAN_BITFIELD 714 uint64_t reserved_29_63 : 35; 715 uint64_t mwb : 1; /**< Bist Results for MWB RAM(s) 716 - 0: GOOD (or bist in progress/never run) 717 - 1: BAD */ 718 uint64_t reserved_25_27 : 3; 719 uint64_t gfb : 1; /**< Bist Results for GFB RAM(s) 720 - 0: GOOD (or bist in progress/never run) 721 - 1: BAD */ 722 uint64_t reserved_18_23 : 6; 723 uint64_t stx : 2; /**< Bist Results for STX RAM(s) 724 - 0: GOOD (or bist in progress/never run) 725 - 1: BAD */ 726 uint64_t reserved_10_15 : 6; 727 uint64_t dtx : 2; /**< Bist Results for DTX RAM(s) 728 - 0: GOOD (or bist in progress/never run) 729 - 1: BAD */ 730 uint64_t reserved_5_7 : 3; 731 uint64_t rdf : 1; /**< Bist Results for RWB[3:0] RAM(s) 732 - 0: GOOD (or bist in progress/never run) 733 - 1: BAD */ 734 uint64_t reserved_1_3 : 3; 735 uint64_t pdb : 1; /**< Bist Results for PDB RAM(s) 736 - 0: GOOD (or bist in progress/never run) 737 - 1: BAD */ 738#else 739 uint64_t pdb : 1; 740 uint64_t reserved_1_3 : 3; 741 uint64_t rdf : 1; 742 uint64_t reserved_5_7 : 3; 743 uint64_t dtx : 2; 744 uint64_t reserved_10_15 : 6; 745 uint64_t stx : 2; 746 uint64_t reserved_18_23 : 6; 747 uint64_t gfb : 1; 748 uint64_t reserved_25_27 : 3; 749 uint64_t mwb : 1; 750 uint64_t reserved_29_63 : 35; 751#endif 752 } cn63xx; 753 struct cvmx_dfa_bist0_cn63xx cn63xxp1; 754 struct cvmx_dfa_bist0_cn63xx cn66xx; 755 struct cvmx_dfa_bist0_cn68xx { 756#ifdef __BIG_ENDIAN_BITFIELD 757 uint64_t reserved_30_63 : 34; 758 uint64_t mrp : 2; /**< Bist Results for MRP RAM(s) (per-DLC) 759 - 0: GOOD (or bist in progress/never run) 760 - 1: BAD */ 761 uint64_t reserved_27_27 : 1; 762 uint64_t gfb : 3; /**< Bist Results for GFB RAM(s) (per-cluster) 763 - 0: GOOD (or bist in progress/never run) 764 - 1: BAD */ 765 uint64_t reserved_22_23 : 2; 766 uint64_t stx2 : 2; /**< Bist Results for STX2 RAM(s) 767 - 0: GOOD (or bist in progress/never run) 768 - 1: BAD */ 769 uint64_t stx1 : 2; /**< Bist Results for STX1 RAM(s) 770 - 0: GOOD (or bist in progress/never run) 771 - 1: BAD */ 772 uint64_t stx : 2; /**< Bist Results for STX0 RAM(s) 773 - 0: GOOD (or bist in progress/never run) 774 - 1: BAD */ 775 uint64_t reserved_14_15 : 2; 776 uint64_t dtx2 : 2; /**< Bist Results for DTX2 RAM(s) 777 - 0: GOOD (or bist in progress/never run) 778 - 1: BAD */ 779 uint64_t dtx1 : 2; /**< Bist Results for DTX1 RAM(s) 780 - 0: GOOD (or bist in progress/never run) 781 - 1: BAD */ 782 uint64_t dtx : 2; /**< Bist Results for DTX0 RAM(s) 783 - 0: GOOD (or bist in progress/never run) 784 - 1: BAD */ 785 uint64_t reserved_7_7 : 1; 786 uint64_t rdf : 3; /**< Bist Results for RWB RAM(s) (per-cluster) 787 - 0: GOOD (or bist in progress/never run) 788 - 1: BAD */ 789 uint64_t reserved_3_3 : 1; 790 uint64_t pdb : 3; /**< Bist Results for PDB RAM(s) (per-cluster) 791 - 0: GOOD (or bist in progress/never run) 792 - 1: BAD */ 793#else 794 uint64_t pdb : 3; 795 uint64_t reserved_3_3 : 1; 796 uint64_t rdf : 3; 797 uint64_t reserved_7_7 : 1; 798 uint64_t dtx : 2; 799 uint64_t dtx1 : 2; 800 uint64_t dtx2 : 2; 801 uint64_t reserved_14_15 : 2; 802 uint64_t stx : 2; 803 uint64_t stx1 : 2; 804 uint64_t stx2 : 2; 805 uint64_t reserved_22_23 : 2; 806 uint64_t gfb : 3; 807 uint64_t reserved_27_27 : 1; 808 uint64_t mrp : 2; 809 uint64_t reserved_30_63 : 34; 810#endif 811 } cn68xx; 812 struct cvmx_dfa_bist0_cn68xx cn68xxp1; 813}; 814typedef union cvmx_dfa_bist0 cvmx_dfa_bist0_t; 815 816/** 817 * cvmx_dfa_bist1 818 * 819 * DFA_BIST1 = DFA Bist Status (Globals) 820 * 821 * Description: 822 */ 823union cvmx_dfa_bist1 { 824 uint64_t u64; 825 struct cvmx_dfa_bist1_s { 826#ifdef __BIG_ENDIAN_BITFIELD 827 uint64_t reserved_21_63 : 43; 828 uint64_t dlc1ram : 1; /**< DLC1 Bist Results 829 - 0: GOOD (or bist in progress/never run) 830 - 1: BAD */ 831 uint64_t dlc0ram : 1; /**< DLC0 Bist Results 832 - 0: GOOD (or bist in progress/never run) 833 - 1: BAD */ 834 uint64_t dc2ram3 : 1; /**< Cluster#2 Bist Results for RAM3 RAM 835 - 0: GOOD (or bist in progress/never run) 836 - 1: BAD */ 837 uint64_t dc2ram2 : 1; /**< Cluster#2 Bist Results for RAM2 RAM 838 - 0: GOOD (or bist in progress/never run) 839 - 1: BAD */ 840 uint64_t dc2ram1 : 1; /**< Cluster#2 Bist Results for RAM1 RAM 841 - 0: GOOD (or bist in progress/never run) 842 - 1: BAD */ 843 uint64_t dc1ram3 : 1; /**< Cluster#1 Bist Results for RAM3 RAM 844 - 0: GOOD (or bist in progress/never run) 845 - 1: BAD */ 846 uint64_t dc1ram2 : 1; /**< Cluster#1 Bist Results for RAM2 RAM 847 - 0: GOOD (or bist in progress/never run) 848 - 1: BAD */ 849 uint64_t dc1ram1 : 1; /**< Cluster#1 Bist Results for RAM1 RAM 850 - 0: GOOD (or bist in progress/never run) 851 - 1: BAD */ 852 uint64_t ram3 : 1; /**< Cluster#0 Bist Results for RAM3 RAM 853 - 0: GOOD (or bist in progress/never run) 854 - 1: BAD */ 855 uint64_t ram2 : 1; /**< Cluster#0 Bist Results for RAM2 RAM 856 - 0: GOOD (or bist in progress/never run) 857 - 1: BAD */ 858 uint64_t ram1 : 1; /**< Cluster#0 Bist Results for RAM1 RAM 859 - 0: GOOD (or bist in progress/never run) 860 - 1: BAD */ 861 uint64_t crq : 1; /**< Bist Results for CRQ RAM 862 - 0: GOOD (or bist in progress/never run) 863 - 1: BAD */ 864 uint64_t gutv : 1; /**< Bist Results for GUTV RAM 865 - 0: GOOD (or bist in progress/never run) 866 - 1: BAD */ 867 uint64_t reserved_7_7 : 1; 868 uint64_t gutp : 3; /**< Bist Results for GUTP RAMs (per-cluster) 869 - 0: GOOD (or bist in progress/never run) 870 - 1: BAD */ 871 uint64_t ncd : 1; /**< Bist Results for NCD RAM 872 - 0: GOOD (or bist in progress/never run) 873 - 1: BAD */ 874 uint64_t gif : 1; /**< Bist Results for GIF RAM 875 - 0: GOOD (or bist in progress/never run) 876 - 1: BAD */ 877 uint64_t gib : 1; /**< Bist Results for GIB RAM 878 - 0: GOOD (or bist in progress/never run) 879 - 1: BAD */ 880 uint64_t gfu : 1; /**< Bist Results for GFU RAM 881 - 0: GOOD (or bist in progress/never run) 882 - 1: BAD */ 883#else 884 uint64_t gfu : 1; 885 uint64_t gib : 1; 886 uint64_t gif : 1; 887 uint64_t ncd : 1; 888 uint64_t gutp : 3; 889 uint64_t reserved_7_7 : 1; 890 uint64_t gutv : 1; 891 uint64_t crq : 1; 892 uint64_t ram1 : 1; 893 uint64_t ram2 : 1; 894 uint64_t ram3 : 1; 895 uint64_t dc1ram1 : 1; 896 uint64_t dc1ram2 : 1; 897 uint64_t dc1ram3 : 1; 898 uint64_t dc2ram1 : 1; 899 uint64_t dc2ram2 : 1; 900 uint64_t dc2ram3 : 1; 901 uint64_t dlc0ram : 1; 902 uint64_t dlc1ram : 1; 903 uint64_t reserved_21_63 : 43; 904#endif 905 } s; 906 struct cvmx_dfa_bist1_cn61xx { 907#ifdef __BIG_ENDIAN_BITFIELD 908 uint64_t reserved_20_63 : 44; 909 uint64_t dlc0ram : 1; /**< DLC0 Bist Results 910 - 0: GOOD (or bist in progress/never run) 911 - 1: BAD */ 912 uint64_t reserved_13_18 : 6; 913 uint64_t ram3 : 1; /**< Cluster#0 Bist Results for RAM3 RAM 914 - 0: GOOD (or bist in progress/never run) 915 - 1: BAD */ 916 uint64_t ram2 : 1; /**< Cluster#0 Bist Results for RAM2 RAM 917 - 0: GOOD (or bist in progress/never run) 918 - 1: BAD */ 919 uint64_t ram1 : 1; /**< Cluster#0 Bist Results for RAM1 RAM 920 - 0: GOOD (or bist in progress/never run) 921 - 1: BAD */ 922 uint64_t crq : 1; /**< Bist Results for CRQ RAM 923 - 0: GOOD (or bist in progress/never run) 924 - 1: BAD */ 925 uint64_t gutv : 1; /**< Bist Results for GUTV RAM 926 - 0: GOOD (or bist in progress/never run) 927 - 1: BAD */ 928 uint64_t reserved_5_7 : 3; 929 uint64_t gutp : 1; /**< Bist Results for GUTP RAMs 930 - 0: GOOD (or bist in progress/never run) 931 - 1: BAD */ 932 uint64_t ncd : 1; /**< Bist Results for NCD RAM 933 - 0: GOOD (or bist in progress/never run) 934 - 1: BAD */ 935 uint64_t gif : 1; /**< Bist Results for GIF RAM 936 - 0: GOOD (or bist in progress/never run) 937 - 1: BAD */ 938 uint64_t gib : 1; /**< Bist Results for GIB RAM 939 - 0: GOOD (or bist in progress/never run) 940 - 1: BAD */ 941 uint64_t gfu : 1; /**< Bist Results for GFU RAM 942 - 0: GOOD (or bist in progress/never run) 943 - 1: BAD */ 944#else 945 uint64_t gfu : 1; 946 uint64_t gib : 1; 947 uint64_t gif : 1; 948 uint64_t ncd : 1; 949 uint64_t gutp : 1; 950 uint64_t reserved_5_7 : 3; 951 uint64_t gutv : 1; 952 uint64_t crq : 1; 953 uint64_t ram1 : 1; 954 uint64_t ram2 : 1; 955 uint64_t ram3 : 1; 956 uint64_t reserved_13_18 : 6; 957 uint64_t dlc0ram : 1; 958 uint64_t reserved_20_63 : 44; 959#endif 960 } cn61xx; 961 struct cvmx_dfa_bist1_cn63xx { 962#ifdef __BIG_ENDIAN_BITFIELD 963 uint64_t reserved_13_63 : 51; 964 uint64_t ram3 : 1; /**< Bist Results for RAM3 RAM 965 - 0: GOOD (or bist in progress/never run) 966 - 1: BAD */ 967 uint64_t ram2 : 1; /**< Bist Results for RAM2 RAM 968 - 0: GOOD (or bist in progress/never run) 969 - 1: BAD */ 970 uint64_t ram1 : 1; /**< Bist Results for RAM1 RAM 971 - 0: GOOD (or bist in progress/never run) 972 - 1: BAD */ 973 uint64_t crq : 1; /**< Bist Results for CRQ RAM 974 - 0: GOOD (or bist in progress/never run) 975 - 1: BAD */ 976 uint64_t gutv : 1; /**< Bist Results for GUTV RAM 977 - 0: GOOD (or bist in progress/never run) 978 - 1: BAD */ 979 uint64_t reserved_5_7 : 3; 980 uint64_t gutp : 1; /**< Bist Results for NCD RAM 981 - 0: GOOD (or bist in progress/never run) 982 - 1: BAD */ 983 uint64_t ncd : 1; /**< Bist Results for NCD RAM 984 - 0: GOOD (or bist in progress/never run) 985 - 1: BAD */ 986 uint64_t gif : 1; /**< Bist Results for GIF RAM 987 - 0: GOOD (or bist in progress/never run) 988 - 1: BAD */ 989 uint64_t gib : 1; /**< Bist Results for GIB RAM 990 - 0: GOOD (or bist in progress/never run) 991 - 1: BAD */ 992 uint64_t gfu : 1; /**< Bist Results for GFU RAM 993 - 0: GOOD (or bist in progress/never run) 994 - 1: BAD */ 995#else 996 uint64_t gfu : 1; 997 uint64_t gib : 1; 998 uint64_t gif : 1; 999 uint64_t ncd : 1; 1000 uint64_t gutp : 1; 1001 uint64_t reserved_5_7 : 3; 1002 uint64_t gutv : 1; 1003 uint64_t crq : 1; 1004 uint64_t ram1 : 1; 1005 uint64_t ram2 : 1; 1006 uint64_t ram3 : 1; 1007 uint64_t reserved_13_63 : 51; 1008#endif 1009 } cn63xx; 1010 struct cvmx_dfa_bist1_cn63xx cn63xxp1; 1011 struct cvmx_dfa_bist1_cn63xx cn66xx; 1012 struct cvmx_dfa_bist1_s cn68xx; 1013 struct cvmx_dfa_bist1_s cn68xxp1; 1014}; 1015typedef union cvmx_dfa_bist1 cvmx_dfa_bist1_t; 1016 1017/** 1018 * cvmx_dfa_bst0 1019 * 1020 * DFA_BST0 = DFA Bist Status 1021 * 1022 * Description: 1023 */ 1024union cvmx_dfa_bst0 { 1025 uint64_t u64; 1026 struct cvmx_dfa_bst0_s { 1027#ifdef __BIG_ENDIAN_BITFIELD 1028 uint64_t reserved_32_63 : 32; 1029 uint64_t rdf : 16; /**< Bist Results for RDF[3:0] RAM(s) 1030 - 0: GOOD (or bist in progress/never run) 1031 - 1: BAD */ 1032 uint64_t pdf : 16; /**< Bist Results for PDF[3:0] RAM(s) 1033 - 0: GOOD (or bist in progress/never run) 1034 - 1: BAD */ 1035#else 1036 uint64_t pdf : 16; 1037 uint64_t rdf : 16; 1038 uint64_t reserved_32_63 : 32; 1039#endif 1040 } s; 1041 struct cvmx_dfa_bst0_s cn31xx; 1042 struct cvmx_dfa_bst0_s cn38xx; 1043 struct cvmx_dfa_bst0_s cn38xxp2; 1044 struct cvmx_dfa_bst0_cn58xx { 1045#ifdef __BIG_ENDIAN_BITFIELD 1046 uint64_t reserved_20_63 : 44; 1047 uint64_t rdf : 4; /**< Bist Results for RDF[3:0] RAM(s) 1048 - 0: GOOD (or bist in progress/never run) 1049 - 1: BAD */ 1050 uint64_t reserved_4_15 : 12; 1051 uint64_t pdf : 4; /**< Bist Results for PDF[3:0] RAM(s) 1052 - 0: GOOD (or bist in progress/never run) 1053 - 1: BAD */ 1054#else 1055 uint64_t pdf : 4; 1056 uint64_t reserved_4_15 : 12; 1057 uint64_t rdf : 4; 1058 uint64_t reserved_20_63 : 44; 1059#endif 1060 } cn58xx; 1061 struct cvmx_dfa_bst0_cn58xx cn58xxp1; 1062}; 1063typedef union cvmx_dfa_bst0 cvmx_dfa_bst0_t; 1064 1065/** 1066 * cvmx_dfa_bst1 1067 * 1068 * DFA_BST1 = DFA Bist Status 1069 * 1070 * Description: 1071 */ 1072union cvmx_dfa_bst1 { 1073 uint64_t u64; 1074 struct cvmx_dfa_bst1_s { 1075#ifdef __BIG_ENDIAN_BITFIELD 1076 uint64_t reserved_23_63 : 41; 1077 uint64_t crq : 1; /**< Bist Results for CRQ RAM 1078 - 0: GOOD (or bist in progress/never run) 1079 - 1: BAD */ 1080 uint64_t ifu : 1; /**< Bist Results for IFU RAM 1081 - 0: GOOD (or bist in progress/never run) 1082 - 1: BAD */ 1083 uint64_t gfu : 1; /**< Bist Results for GFU RAM 1084 - 0: GOOD (or bist in progress/never run) 1085 - 1: BAD */ 1086 uint64_t drf : 1; /**< Bist Results for DRF RAM 1087 - 0: GOOD (or bist in progress/never run) 1088 - 1: BAD */ 1089 uint64_t crf : 1; /**< Bist Results for CRF RAM 1090 - 0: GOOD (or bist in progress/never run) 1091 - 1: BAD */ 1092 uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 1093 - 0: GOOD (or bist in progress/never run) 1094 - 1: BAD */ 1095 uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 1096 - 0: GOOD (or bist in progress/never run) 1097 - 1: BAD */ 1098 uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 1099 - 0: GOOD (or bist in progress/never run) 1100 - 1: BAD */ 1101 uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 1102 - 0: GOOD (or bist in progress/never run) 1103 - 1: BAD */ 1104#else 1105 uint64_t p1_brf : 8; 1106 uint64_t p0_brf : 8; 1107 uint64_t p1_bwb : 1; 1108 uint64_t p0_bwb : 1; 1109 uint64_t crf : 1; 1110 uint64_t drf : 1; 1111 uint64_t gfu : 1; 1112 uint64_t ifu : 1; 1113 uint64_t crq : 1; 1114 uint64_t reserved_23_63 : 41; 1115#endif 1116 } s; 1117 struct cvmx_dfa_bst1_cn31xx { 1118#ifdef __BIG_ENDIAN_BITFIELD 1119 uint64_t reserved_23_63 : 41; 1120 uint64_t crq : 1; /**< Bist Results for CRQ RAM 1121 - 0: GOOD (or bist in progress/never run) 1122 - 1: BAD */ 1123 uint64_t ifu : 1; /**< Bist Results for IFU RAM 1124 - 0: GOOD (or bist in progress/never run) 1125 - 1: BAD */ 1126 uint64_t gfu : 1; /**< Bist Results for GFU RAM 1127 - 0: GOOD (or bist in progress/never run) 1128 - 1: BAD */ 1129 uint64_t drf : 1; /**< Bist Results for DRF RAM 1130 - 0: GOOD (or bist in progress/never run) 1131 - 1: BAD */ 1132 uint64_t crf : 1; /**< Bist Results for CRF RAM 1133 - 0: GOOD (or bist in progress/never run) 1134 - 1: BAD */ 1135 uint64_t reserved_0_17 : 18; 1136#else 1137 uint64_t reserved_0_17 : 18; 1138 uint64_t crf : 1; 1139 uint64_t drf : 1; 1140 uint64_t gfu : 1; 1141 uint64_t ifu : 1; 1142 uint64_t crq : 1; 1143 uint64_t reserved_23_63 : 41; 1144#endif 1145 } cn31xx; 1146 struct cvmx_dfa_bst1_s cn38xx; 1147 struct cvmx_dfa_bst1_s cn38xxp2; 1148 struct cvmx_dfa_bst1_cn58xx { 1149#ifdef __BIG_ENDIAN_BITFIELD 1150 uint64_t reserved_23_63 : 41; 1151 uint64_t crq : 1; /**< Bist Results for CRQ RAM 1152 - 0: GOOD (or bist in progress/never run) 1153 - 1: BAD */ 1154 uint64_t ifu : 1; /**< Bist Results for IFU RAM 1155 - 0: GOOD (or bist in progress/never run) 1156 - 1: BAD */ 1157 uint64_t gfu : 1; /**< Bist Results for GFU RAM 1158 - 0: GOOD (or bist in progress/never run) 1159 - 1: BAD */ 1160 uint64_t reserved_19_19 : 1; 1161 uint64_t crf : 1; /**< Bist Results for CRF RAM 1162 - 0: GOOD (or bist in progress/never run) 1163 - 1: BAD */ 1164 uint64_t p0_bwb : 1; /**< Bist Results for P0_BWB RAM 1165 - 0: GOOD (or bist in progress/never run) 1166 - 1: BAD */ 1167 uint64_t p1_bwb : 1; /**< Bist Results for P1_BWB RAM 1168 - 0: GOOD (or bist in progress/never run) 1169 - 1: BAD */ 1170 uint64_t p0_brf : 8; /**< Bist Results for P0_BRF RAM 1171 - 0: GOOD (or bist in progress/never run) 1172 - 1: BAD */ 1173 uint64_t p1_brf : 8; /**< Bist Results for P1_BRF RAM 1174 - 0: GOOD (or bist in progress/never run) 1175 - 1: BAD */ 1176#else 1177 uint64_t p1_brf : 8; 1178 uint64_t p0_brf : 8; 1179 uint64_t p1_bwb : 1; 1180 uint64_t p0_bwb : 1; 1181 uint64_t crf : 1; 1182 uint64_t reserved_19_19 : 1; 1183 uint64_t gfu : 1; 1184 uint64_t ifu : 1; 1185 uint64_t crq : 1; 1186 uint64_t reserved_23_63 : 41; 1187#endif 1188 } cn58xx; 1189 struct cvmx_dfa_bst1_cn58xx cn58xxp1; 1190}; 1191typedef union cvmx_dfa_bst1 cvmx_dfa_bst1_t; 1192 1193/** 1194 * cvmx_dfa_cfg 1195 * 1196 * Specify the RSL base addresses for the block 1197 * 1198 * DFA_CFG = DFA Configuration 1199 * 1200 * Description: 1201 */ 1202union cvmx_dfa_cfg { 1203 uint64_t u64; 1204 struct cvmx_dfa_cfg_s { 1205#ifdef __BIG_ENDIAN_BITFIELD 1206 uint64_t reserved_4_63 : 60; 1207 uint64_t nrpl_ena : 1; /**< When set, allows the per-node replication feature to be 1208 enabled. 1209 In 36-bit mode: The IWORD0[31:30]=SNREPL field AND 1210 bits [21:20] of the Next Node ptr are used in generating 1211 the next node address (see OCTEON HRM - DFA Chapter for 1212 psuedo-code of DTE next node address generation). 1213 NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode), 1214 (regardless of IWORD0[NRPLEN]), the Resultant Word1+ 1215 [[47:44],[23:20]] = Next Node's [27:20] bits. This allows 1216 SW to use the RESERVED bits of the final node for SW 1217 caching. Also, if required, SW will use [22:21]=Node 1218 Replication to re-start the same graph walk(if graph 1219 walk prematurely terminated (ie: DATA_GONE). 1220 In 18-bit mode: The IWORD0[31:30]=SNREPL field AND 1221 bit [16:14] of the Next Node ptr are used in generating 1222 the next node address (see OCTEON HRM - DFA Chapter for 1223 psuedo-code of DTE next node address generation). 1224 If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [ 1225 If next node ptr[16] is set [ 1226 next node ptr[15:14] indicates the next node repl 1227 next node ptr[13:0] indicates the position of the 1228 node relative to the first normal node (i.e. 1229 IWORD3[Msize] must be added to get the final node) 1230 ] 1231 else If next node ptr[16] is not set [ 1232 next node ptr[15:0] indicates the next node id 1233 next node repl = 0 1234 ] 1235 ] 1236 NOTE: For 18b node replication, MAX node space=64KB(2^16) 1237 is used in detecting terminal node space(see HRM for full 1238 description). 1239 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1240 aware of the "per-node" replication. */ 1241 uint64_t nxor_ena : 1; /**< When set, allows the DTE Instruction IWORD0[NXOREN] 1242 to be used to enable/disable the per-node address 'scramble' 1243 of the LLM address to lessen the effects of bank conflicts. 1244 If IWORD0[NXOREN] is also set, then: 1245 In 36-bit mode: The node_Id[7:0] 8-bit value is XORed 1246 against the LLM address addr[9:2]. 1247 In 18-bit mode: The node_id[6:0] 7-bit value is XORed 1248 against the LLM address addr[8:2]. (note: we don't address 1249 scramble outside the mode's node space). 1250 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1251 aware of the "per-node" address scramble. 1252 NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 1253 read/write operations. */ 1254 uint64_t gxor_ena : 1; /**< When set, the DTE Instruction IWORD0[GXOR] 1255 field is used to 'scramble' the LLM address 1256 to lessen the effects of bank conflicts. 1257 In 36-bit mode: The GXOR[7:0] 8-bit value is XORed 1258 against the LLM address addr[9:2]. 1259 In 18-bit mode: GXOR[6:0] 7-bit value is XORed against 1260 the LLM address addr[8:2]. (note: we don't address 1261 scramble outside the mode's node space) 1262 NOTE: The DFA graphs MUST BE built/written to DFA LLM memory 1263 aware of the "per-graph" address scramble. 1264 NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph 1265 read/write operations. */ 1266 uint64_t sarb : 1; /**< DFA Source Arbiter Mode 1267 Selects the arbitration mode used to select DFA 1268 requests issued from either CP2 or the DTE (NCB-CSR 1269 or DFA HW engine). 1270 - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1271 - 1: Round-Robin 1272 NOTE: This should only be written to a different value 1273 during power-on SW initialization. */ 1274#else 1275 uint64_t sarb : 1; 1276 uint64_t gxor_ena : 1; 1277 uint64_t nxor_ena : 1; 1278 uint64_t nrpl_ena : 1; 1279 uint64_t reserved_4_63 : 60; 1280#endif 1281 } s; 1282 struct cvmx_dfa_cfg_s cn38xx; 1283 struct cvmx_dfa_cfg_cn38xxp2 { 1284#ifdef __BIG_ENDIAN_BITFIELD 1285 uint64_t reserved_1_63 : 63; 1286 uint64_t sarb : 1; /**< DFA Source Arbiter Mode 1287 Selects the arbitration mode used to select DFA 1288 requests issued from either CP2 or the DTE (NCB-CSR 1289 or DFA HW engine). 1290 - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 1291 - 1: Round-Robin 1292 NOTE: This should only be written to a different value 1293 during power-on SW initialization. */ 1294#else 1295 uint64_t sarb : 1; 1296 uint64_t reserved_1_63 : 63; 1297#endif 1298 } cn38xxp2; 1299 struct cvmx_dfa_cfg_s cn58xx; 1300 struct cvmx_dfa_cfg_s cn58xxp1; 1301}; 1302typedef union cvmx_dfa_cfg cvmx_dfa_cfg_t; 1303 1304/** 1305 * cvmx_dfa_config 1306 * 1307 * Specify the RSL base addresses for the block 1308 * 1309 * DFA_CONFIG = DFA Configuration Register 1310 * 1311 * Description: 1312 */ 1313union cvmx_dfa_config { 1314 uint64_t u64; 1315 struct cvmx_dfa_config_s { 1316#ifdef __BIG_ENDIAN_BITFIELD 1317 uint64_t reserved_11_63 : 53; 1318 uint64_t dlcclear_bist : 1; /**< When DLCSTART_BIST is written 0->1, if DLCCLEAR_BIST=1, all 1319 previous DLC BiST state is cleared. 1320 NOTES: 1321 1) DLCCLEAR_BIST must be written to 1 before DLCSTART_BIST 1322 is written to 1 udsing a separate CSR write. 1323 2) DLCCLEAR_BIST must not be changed after writing DLCSTART_BIST 1324 0->1 until the BIST operation completes. */ 1325 uint64_t dlcstart_bist : 1; /**< When software writes DLCSTART_BIST=0->1, a BiST is executed 1326 for the DLC sub-block RAMs which contains DCLK domain 1327 asynchronous RAMs. 1328 NOTES: 1329 1) This bit should only be written after DCLK has been enabled 1330 by software and is stable. 1331 (see LMC initialization routine for details on how to enable 1332 the DDR3 memory (DCLK) - which requires LMC PLL init, clock 1333 divider and proper DLL initialization sequence). */ 1334 uint64_t repl_ena : 1; /**< Replication Mode Enable 1335 *** o63-P2 NEW *** 1336 When set, enables replication mode performance enhancement 1337 feature. This enables the DFA to communicate address 1338 replication information during memory references to the 1339 memory controller. 1340 For o63-P2: This is used by the memory controller 1341 to support graph data in multiple banks (or bank sets), so that 1342 the least full bank can be selected to minimize the effects of 1343 DDR3 bank conflicts (ie: tRC=row cycle time). 1344 For o68: This is used by the memory controller to support graph 1345 data in multiple ports (or port sets), so that the least full 1346 port can be selected to minimize latency effects. 1347 SWNOTE: Using this mode requires the DFA SW compiler and DFA 1348 driver to be aware of the address replication changes. 1349 This involves changes to the MLOAD/GWALK DFA instruction format 1350 (see: IWORD2.SREPL), as well as changes to node arc and metadata 1351 definitions which now support an additional REPL field. 1352 When clear, replication mode is disabled, and DFA will interpret 1353 DFA instructions and node-arc formats which DO NOT have 1354 address replication information. */ 1355 uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1356 A one in each bit of the mask represents which DTE cluster to 1357 cripple. 1358 NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1359 is the only bit used. 1360 o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1361 SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1362 be forced into this register at reset. Any fuse bits that 1363 contain '1' will be disallowed during a write and will always 1364 be read as '1'. */ 1365 uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1366 cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1367 within each cluster. However, when the DFA performance 1368 counters are used, SW may want to limit the \#of DTEs 1369 per cluster available, as there are only 4 parallel 1370 performance counters. 1371 DTE_CLCRIP | \#DTEs crippled(per cluster) 1372 ------------+----------------------------- 1373 0 | 0 DTE[15:0]:ON 1374 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1375 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1376 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1377 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1378 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1379 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1380 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1381 NOTE: Higher numbered DTEs are crippled first. For instance, 1382 on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1383 DTE#s [15:8] within the cluster are crippled and only 1384 DTE#s [7:0] are available. 1385 IMPNOTE: The encodings are done in such a way as to later 1386 be used with fuses (for future o2 revisions which will disable 1387 some \#of DTEs). Blowing a fuse has the effect that there will 1388 always be fewer DTEs available. [ie: we never want a customer 1389 to blow additional fuses to get more DTEs]. 1390 SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1391 be forced into this register at reset. Any fuse bits that 1392 contain '1' will be disallowed during a write and will always 1393 be read as '1'. */ 1394 uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1395 When SET, the DFA clocks for DTE(thread engine) 1396 operation are disabled (to conserve overall chip clocking 1397 power when the DFA function is not used). 1398 NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1399 operations to the DFA (will result in NCB Bus Timeout 1400 errors). 1401 NOTE: This should only be written to a different value 1402 during power-on SW initialization. 1403 SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1404 be forced into this register at reset. If the fuse bit 1405 contains '1', writes to DTECLKDIS are disallowed and 1406 will always be read as '1'. */ 1407#else 1408 uint64_t dteclkdis : 1; 1409 uint64_t cldtecrip : 3; 1410 uint64_t clmskcrip : 4; 1411 uint64_t repl_ena : 1; 1412 uint64_t dlcstart_bist : 1; 1413 uint64_t dlcclear_bist : 1; 1414 uint64_t reserved_11_63 : 53; 1415#endif 1416 } s; 1417 struct cvmx_dfa_config_s cn61xx; 1418 struct cvmx_dfa_config_cn63xx { 1419#ifdef __BIG_ENDIAN_BITFIELD 1420 uint64_t reserved_9_63 : 55; 1421 uint64_t repl_ena : 1; /**< Replication Mode Enable 1422 *** o63-P2 NEW *** 1423 When set, enables replication mode performance enhancement 1424 feature. This enables the DFA to communicate address 1425 replication information during memory references to the DFM 1426 (memory controller). This in turn is used by the DFM to support 1427 graph data in multiple banks (or bank sets), so that the least 1428 full bank can be selected to minimize the effects of DDR3 bank 1429 conflicts (ie: tRC=row cycle time). 1430 SWNOTE: Using this mode requires the DFA SW compiler and DFA 1431 driver to be aware of the o63-P2 address replication changes. 1432 This involves changes to the MLOAD/GWALK DFA instruction format 1433 (see: IWORD2.SREPL), as well as changes to node arc and metadata 1434 definitions which now support an additional REPL field. 1435 When clear, replication mode is disabled, and DFA will interpret 1436 o63-P1 DFA instructions and node-arc formats which DO NOT have 1437 address replication information. */ 1438 uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1439 A one in each bit of the mask represents which DTE cluster to 1440 cripple. 1441 NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1442 is the only bit used. 1443 o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1444 SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1445 be forced into this register at reset. Any fuse bits that 1446 contain '1' will be disallowed during a write and will always 1447 be read as '1'. */ 1448 uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1449 cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1450 within each cluster. However, when the DFA performance 1451 counters are used, SW may want to limit the \#of DTEs 1452 per cluster available, as there are only 4 parallel 1453 performance counters. 1454 DTE_CLCRIP | \#DTEs crippled(per cluster) 1455 ------------+----------------------------- 1456 0 | 0 DTE[15:0]:ON 1457 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1458 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1459 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1460 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1461 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1462 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1463 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1464 NOTE: Higher numbered DTEs are crippled first. For instance, 1465 on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1466 DTE#s [15:8] within the cluster are crippled and only 1467 DTE#s [7:0] are available. 1468 IMPNOTE: The encodings are done in such a way as to later 1469 be used with fuses (for future o2 revisions which will disable 1470 some \#of DTEs). Blowing a fuse has the effect that there will 1471 always be fewer DTEs available. [ie: we never want a customer 1472 to blow additional fuses to get more DTEs]. 1473 SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1474 be forced into this register at reset. Any fuse bits that 1475 contain '1' will be disallowed during a write and will always 1476 be read as '1'. */ 1477 uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1478 When SET, the DFA clocks for DTE(thread engine) 1479 operation are disabled (to conserve overall chip clocking 1480 power when the DFA function is not used). 1481 NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1482 operations to the DFA (will result in NCB Bus Timeout 1483 errors). 1484 NOTE: This should only be written to a different value 1485 during power-on SW initialization. 1486 SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1487 be forced into this register at reset. If the fuse bit 1488 contains '1', writes to DTECLKDIS are disallowed and 1489 will always be read as '1'. */ 1490#else 1491 uint64_t dteclkdis : 1; 1492 uint64_t cldtecrip : 3; 1493 uint64_t clmskcrip : 4; 1494 uint64_t repl_ena : 1; 1495 uint64_t reserved_9_63 : 55; 1496#endif 1497 } cn63xx; 1498 struct cvmx_dfa_config_cn63xxp1 { 1499#ifdef __BIG_ENDIAN_BITFIELD 1500 uint64_t reserved_8_63 : 56; 1501 uint64_t clmskcrip : 4; /**< Cluster Cripple Mask 1502 A one in each bit of the mask represents which DTE cluster to 1503 cripple. 1504 NOTE: o63 has only a single Cluster (therefore CLMSKCRIP[0] 1505 is the only bit used. 1506 o2 has 4 clusters, where all CLMSKCRIP mask bits are used. 1507 SWNOTE: The MIO_FUS___DFA_CLMASK_CRIPPLE[3:0] fuse bits will 1508 be forced into this register at reset. Any fuse bits that 1509 contain '1' will be disallowed during a write and will always 1510 be read as '1'. */ 1511 uint64_t cldtecrip : 3; /**< Encoding which represents \#of DTEs to cripple for each 1512 cluster. Typically DTE_CLCRIP=0 which enables all DTEs 1513 within each cluster. However, when the DFA performance 1514 counters are used, SW may want to limit the \#of DTEs 1515 per cluster available, as there are only 4 parallel 1516 performance counters. 1517 DTE_CLCRIP | \#DTEs crippled(per cluster) 1518 ------------+----------------------------- 1519 0 | 0 DTE[15:0]:ON 1520 1 | 1/2 DTE[15:8]:OFF /DTE[7:0]:ON 1521 2 | 1/4 DTE[15:12]:OFF /DTE[11:0]:ON 1522 3 | 3/4 DTE[15:4]:OFF /DTE[3:0]:ON 1523 4 | 1/8 DTE[15:14]:OFF /DTE[13:0]:ON 1524 5 | 5/8 DTE[15:6]:OFF /DTE[5:0]:ON 1525 6 | 3/8 DTE[15:10]:OFF /DTE[9:0]:ON 1526 7 | 7/8 DTE[15:2]:OFF /DTE[1:0]:ON 1527 NOTE: Higher numbered DTEs are crippled first. For instance, 1528 on o63 (with 16 DTEs/cluster), if DTE_CLCRIP=1(1/2), then 1529 DTE#s [15:8] within the cluster are crippled and only 1530 DTE#s [7:0] are available. 1531 IMPNOTE: The encodings are done in such a way as to later 1532 be used with fuses (for future o2 revisions which will disable 1533 some \#of DTEs). Blowing a fuse has the effect that there will 1534 always be fewer DTEs available. [ie: we never want a customer 1535 to blow additional fuses to get more DTEs]. 1536 SWNOTE: The MIO_FUS___DFA_NUMDTE_CRIPPLE[2:0] fuse bits will 1537 be forced into this register at reset. Any fuse bits that 1538 contain '1' will be disallowed during a write and will always 1539 be read as '1'. */ 1540 uint64_t dteclkdis : 1; /**< DFA Clock Disable Source 1541 When SET, the DFA clocks for DTE(thread engine) 1542 operation are disabled (to conserve overall chip clocking 1543 power when the DFA function is not used). 1544 NOTE: When SET, SW MUST NEVER issue NCB-Direct CSR 1545 operations to the DFA (will result in NCB Bus Timeout 1546 errors). 1547 NOTE: This should only be written to a different value 1548 during power-on SW initialization. 1549 SWNOTE: The MIO_FUS___DFA_DTE_DISABLE fuse bit will 1550 be forced into this register at reset. If the fuse bit 1551 contains '1', writes to DTECLKDIS are disallowed and 1552 will always be read as '1'. */ 1553#else 1554 uint64_t dteclkdis : 1; 1555 uint64_t cldtecrip : 3; 1556 uint64_t clmskcrip : 4; 1557 uint64_t reserved_8_63 : 56; 1558#endif 1559 } cn63xxp1; 1560 struct cvmx_dfa_config_cn63xx cn66xx; 1561 struct cvmx_dfa_config_s cn68xx; 1562 struct cvmx_dfa_config_s cn68xxp1; 1563}; 1564typedef union cvmx_dfa_config cvmx_dfa_config_t; 1565 1566/** 1567 * cvmx_dfa_control 1568 * 1569 * DFA_CONTROL = DFA Control Register 1570 * 1571 * Description: 1572 */ 1573union cvmx_dfa_control { 1574 uint64_t u64; 1575 struct cvmx_dfa_control_s { 1576#ifdef __BIG_ENDIAN_BITFIELD 1577 uint64_t reserved_12_63 : 52; 1578 uint64_t sbdnum : 6; /**< SBD Debug Entry# 1579 *FOR INTERNAL USE ONLY* 1580 DFA Scoreboard debug control 1581 Selects which one of 48 DFA Scoreboard entries is 1582 latched into the DFA_SBD_DBG[0-3] registers. */ 1583 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 1584 *FOR INTERNAL USE ONLY* 1585 DFA Scoreboard debug control 1586 When written with a '1', the DFA Scoreboard Debug 1587 registers (DFA_SBD_DBG[0-3]) are all locked down. 1588 This allows SW to lock down the contents of the entire 1589 SBD for a single instant in time. All subsequent reads 1590 of the DFA scoreboard registers will return the data 1591 from that instant in time. */ 1592 uint64_t reserved_3_4 : 2; 1593 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 1594 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 1595 NOTE: This should only be written to a different value 1596 during power-on SW initialization. */ 1597 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 1598 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 1599 NOTE: This should only be written to a different value 1600 during power-on SW initialization. */ 1601 uint64_t imode : 1; /**< NCB-Inbound Arbiter 1602 (0=FP [LP=NRQ,HP=NRP], 1=RR) 1603 NOTE: This should only be written to a different value 1604 during power-on SW initialization. */ 1605#else 1606 uint64_t imode : 1; 1607 uint64_t qmode : 1; 1608 uint64_t pmode : 1; 1609 uint64_t reserved_3_4 : 2; 1610 uint64_t sbdlck : 1; 1611 uint64_t sbdnum : 6; 1612 uint64_t reserved_12_63 : 52; 1613#endif 1614 } s; 1615 struct cvmx_dfa_control_cn61xx { 1616#ifdef __BIG_ENDIAN_BITFIELD 1617 uint64_t reserved_10_63 : 54; 1618 uint64_t sbdnum : 4; /**< SBD Debug Entry# 1619 *FOR INTERNAL USE ONLY* 1620 DFA Scoreboard debug control 1621 Selects which one of 16 DFA Scoreboard entries is 1622 latched into the DFA_SBD_DBG[0-3] registers. */ 1623 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 1624 *FOR INTERNAL USE ONLY* 1625 DFA Scoreboard debug control 1626 When written with a '1', the DFA Scoreboard Debug 1627 registers (DFA_SBD_DBG[0-3]) are all locked down. 1628 This allows SW to lock down the contents of the entire 1629 SBD for a single instant in time. All subsequent reads 1630 of the DFA scoreboard registers will return the data 1631 from that instant in time. */ 1632 uint64_t reserved_3_4 : 2; 1633 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 1634 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 1635 NOTE: This should only be written to a different value 1636 during power-on SW initialization. */ 1637 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 1638 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 1639 NOTE: This should only be written to a different value 1640 during power-on SW initialization. */ 1641 uint64_t imode : 1; /**< NCB-Inbound Arbiter 1642 (0=FP [LP=NRQ,HP=NRP], 1=RR) 1643 NOTE: This should only be written to a different value 1644 during power-on SW initialization. */ 1645#else 1646 uint64_t imode : 1; 1647 uint64_t qmode : 1; 1648 uint64_t pmode : 1; 1649 uint64_t reserved_3_4 : 2; 1650 uint64_t sbdlck : 1; 1651 uint64_t sbdnum : 4; 1652 uint64_t reserved_10_63 : 54; 1653#endif 1654 } cn61xx; 1655 struct cvmx_dfa_control_cn61xx cn63xx; 1656 struct cvmx_dfa_control_cn61xx cn63xxp1; 1657 struct cvmx_dfa_control_cn61xx cn66xx; 1658 struct cvmx_dfa_control_s cn68xx; 1659 struct cvmx_dfa_control_s cn68xxp1; 1660}; 1661typedef union cvmx_dfa_control cvmx_dfa_control_t; 1662 1663/** 1664 * cvmx_dfa_dbell 1665 * 1666 * DFA_DBELL = DFA Doorbell Register 1667 * 1668 * Description: 1669 * NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00. 1670 * To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00. 1671 * 1672 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect. 1673 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect. 1674 */ 1675union cvmx_dfa_dbell { 1676 uint64_t u64; 1677 struct cvmx_dfa_dbell_s { 1678#ifdef __BIG_ENDIAN_BITFIELD 1679 uint64_t reserved_20_63 : 44; 1680 uint64_t dbell : 20; /**< Represents the cumulative total of pending 1681 DFA instructions which SW has previously written 1682 into the DFA Instruction FIFO (DIF) in main memory. 1683 Each DFA instruction contains a fixed size 32B 1684 instruction word which is executed by the DFA HW. 1685 The DBL register can hold up to 1M-1 (2^20-1) 1686 pending DFA instruction requests. 1687 During a read (by SW), the 'most recent' contents 1688 of the DFA_DBELL register are returned at the time 1689 the NCB-INB bus is driven. 1690 NOTE: Since DFA HW updates this register, its 1691 contents are unpredictable in SW. */ 1692#else 1693 uint64_t dbell : 20; 1694 uint64_t reserved_20_63 : 44; 1695#endif 1696 } s; 1697 struct cvmx_dfa_dbell_s cn31xx; 1698 struct cvmx_dfa_dbell_s cn38xx; 1699 struct cvmx_dfa_dbell_s cn38xxp2; 1700 struct cvmx_dfa_dbell_s cn58xx; 1701 struct cvmx_dfa_dbell_s cn58xxp1; 1702 struct cvmx_dfa_dbell_s cn61xx; 1703 struct cvmx_dfa_dbell_s cn63xx; 1704 struct cvmx_dfa_dbell_s cn63xxp1; 1705 struct cvmx_dfa_dbell_s cn66xx; 1706 struct cvmx_dfa_dbell_s cn68xx; 1707 struct cvmx_dfa_dbell_s cn68xxp1; 1708}; 1709typedef union cvmx_dfa_dbell cvmx_dfa_dbell_t; 1710 1711/** 1712 * cvmx_dfa_ddr2_addr 1713 * 1714 * DFA_DDR2_ADDR = DFA DDR2 fclk-domain Memory Address Config Register 1715 * 1716 * 1717 * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK 1718 * etc. 1719 */ 1720union cvmx_dfa_ddr2_addr { 1721 uint64_t u64; 1722 struct cvmx_dfa_ddr2_addr_s { 1723#ifdef __BIG_ENDIAN_BITFIELD 1724 uint64_t reserved_9_63 : 55; 1725 uint64_t rdimm_ena : 1; /**< If there is a need to insert a register chip on the 1726 system (the equivalent of a registered DIMM) to 1727 provide better setup for the command and control bits 1728 turn this mode on. 1729 RDIMM_ENA 1730 0 Registered Mode OFF 1731 1 Registered Mode ON */ 1732 uint64_t num_rnks : 2; /**< NUM_RNKS is programmed based on how many ranks there 1733 are in the system. This needs to be programmed correctly 1734 regardless of whether we are in RNK_LO mode or not. 1735 NUM_RNKS \# of Ranks 1736 0 1 1737 1 2 1738 2 4 1739 3 RESERVED */ 1740 uint64_t rnk_lo : 1; /**< When this mode is turned on, consecutive addresses 1741 outside the bank boundary 1742 are programmed to go to different ranks in order to 1743 minimize bank conflicts. It is useful in 4-bank DDR2 1744 parts based memory to extend out the \#physical banks 1745 available and minimize bank conflicts. 1746 On 8 bank ddr2 parts, this mode is not very useful 1747 because this mode does come with 1748 a penalty which is that every successive reads that 1749 cross rank boundary will need a 1 cycle bubble 1750 inserted to prevent bus turnaround conflicts. 1751 RNK_LO 1752 0 - OFF 1753 1 - ON */ 1754 uint64_t num_colrows : 3; /**< NUM_COLROWS is used to set the MSB of the ROW_ADDR 1755 and the LSB of RANK address when not in RNK_LO mode. 1756 Calculate the sum of \#COL and \#ROW and program the 1757 controller appropriately 1758 RANK_LSB \#COLs + \#ROWs 1759 ------------------------------ 1760 - 000: 22 1761 - 001: 23 1762 - 010: 24 1763 - 011: 25 1764 - 100-111: RESERVED */ 1765 uint64_t num_cols : 2; /**< The Long word address that the controller receives 1766 needs to be converted to Row, Col, Rank and Bank 1767 addresses depending on the memory part's micro arch. 1768 NUM_COL tells the controller how many colum bits 1769 there are and the controller uses this info to map 1770 the LSB of the row address 1771 - 00: num_cols = 9 1772 - 01: num_cols = 10 1773 - 10: num_cols = 11 1774 - 11: RESERVED */ 1775#else 1776 uint64_t num_cols : 2; 1777 uint64_t num_colrows : 3; 1778 uint64_t rnk_lo : 1; 1779 uint64_t num_rnks : 2; 1780 uint64_t rdimm_ena : 1; 1781 uint64_t reserved_9_63 : 55; 1782#endif 1783 } s; 1784 struct cvmx_dfa_ddr2_addr_s cn31xx; 1785}; 1786typedef union cvmx_dfa_ddr2_addr cvmx_dfa_ddr2_addr_t; 1787 1788/** 1789 * cvmx_dfa_ddr2_bus 1790 * 1791 * DFA_DDR2_BUS = DFA DDR Bus Activity Counter 1792 * 1793 * 1794 * Description: This counter counts \# cycles that the memory bus is doing a read/write/command 1795 * Useful to benchmark the bus utilization as a ratio of 1796 * \#Cycles of Data Transfer/\#Cycles since init or 1797 * \#Cycles of Data Transfer/\#Cycles that memory controller is active 1798 */ 1799union cvmx_dfa_ddr2_bus { 1800 uint64_t u64; 1801 struct cvmx_dfa_ddr2_bus_s { 1802#ifdef __BIG_ENDIAN_BITFIELD 1803 uint64_t reserved_47_63 : 17; 1804 uint64_t bus_cnt : 47; /**< Counter counts the \# cycles of Data transfer */ 1805#else 1806 uint64_t bus_cnt : 47; 1807 uint64_t reserved_47_63 : 17; 1808#endif 1809 } s; 1810 struct cvmx_dfa_ddr2_bus_s cn31xx; 1811}; 1812typedef union cvmx_dfa_ddr2_bus cvmx_dfa_ddr2_bus_t; 1813 1814/** 1815 * cvmx_dfa_ddr2_cfg 1816 * 1817 * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register 1818 * 1819 * Description: 1820 */ 1821union cvmx_dfa_ddr2_cfg { 1822 uint64_t u64; 1823 struct cvmx_dfa_ddr2_cfg_s { 1824#ifdef __BIG_ENDIAN_BITFIELD 1825 uint64_t reserved_41_63 : 23; 1826 uint64_t trfc : 5; /**< Establishes tRFC(from DDR2 data sheets) in \# of 1827 4 fclk intervals. 1828 General Equation: 1829 TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))] 1830 Example: 1831 tRFC(data-sheet-ns) = 127.5ns 1832 Operational Frequency: 533MHz DDR rate 1833 [fclk=266MHz(3.75ns)] 1834 Then: 1835 TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)] 1836 = 9 */ 1837 uint64_t mrs_pgm : 1; /**< When clear, the HW initialization sequence fixes 1838 some of the *MRS register bit definitions. 1839 EMRS: 1840 A[14:13] = 0 RESERVED 1841 A[12] = 0 Output Buffers Enabled (FIXED) 1842 A[11] = 0 RDQS Disabled (FIXED) 1843 A[10] = 0 DQSn Enabled (FIXED) 1844 A[9:7] = 0 OCD Not supported (FIXED) 1845 A[6] = 0 RTT Disabled (FIXED) 1846 A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1) 1847 Additive LATENCY (Programmable) 1848 A[2]=0 RTT Disabled (FIXED) 1849 A[1]=DFA_DDR2_TMG[DIC] (Programmable) 1850 A[0] = 0 DLL Enabled (FIXED) 1851 MRS: 1852 A[14:13] = 0 RESERVED 1853 A[12] = 0 Fast Active Power Down Mode (FIXED) 1854 A[11:9] = DFA_DDR2_TMG[TWR](Programmable) 1855 A[8] = 1 DLL Reset (FIXED) 1856 A[7] = 0 Test Mode (FIXED) 1857 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable) 1858 A[3] = 0 Burst Type(must be 0:Sequential) (FIXED) 1859 A[2:0] = 2 Burst Length=4 (must be 0:Sequential) (FIXED) 1860 When set, the HW initialization sequence sources 1861 the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are 1862 driven onto the DFA_A[] pins. (this allows the MRS/EMRS 1863 fields to be completely programmable - however care 1864 must be taken by software). 1865 This mode is useful for customers who wish to: 1866 1) override the FIXED definitions(above), or 1867 2) Use a "clamshell mode" of operation where the 1868 address bits(per rank) are swizzled on the 1869 board to reduce stub lengths for optimal 1870 frequency operation. 1871 Use this in combination with DFA_DDR2_CFG[RNK_MSK] 1872 to specify the INIT sequence for each of the 4 1873 supported ranks. */ 1874 uint64_t fpip : 3; /**< Early Fill Programmable Pipe [\#fclks] 1875 This field dictates the \#fclks prior to the arrival 1876 of fill data(in fclk domain), to start the 'early' fill 1877 command pipe (in the eclk domain) so as to minimize the 1878 overall fill latency. 1879 The programmable early fill command signal is synchronized 1880 into the eclk domain, where it is used to pull data out of 1881 asynchronous RAM as fast as possible. 1882 NOTE: A value of FPIP=0 is the 'safest' setting and will 1883 result in the early fill command pipe starting in the 1884 same cycle as the fill data. 1885 General Equation: (for FPIP) 1886 FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)] 1887 where: 1888 EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)] 1889 Example: FCLK=200MHz/ECLK=600MHz 1890 FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)] 1891 FPIP <= 3 */ 1892 uint64_t reserved_29_31 : 3; 1893 uint64_t ref_int : 13; /**< Refresh Interval (represented in \#of fclk 1894 increments). 1895 Each refresh interval will generate a single 1896 auto-refresh command sequence which implicitly targets 1897 all banks within the device: 1898 Example: For fclk=200MHz(5ns)/400MHz(DDR): 1899 trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet] 1900 REF_INT = ROUND_DOWN[(trefint/fclk)] 1901 = ROUND_DOWN[(3900ns/5ns)] 1902 = 780 fclks (0x30c) 1903 NOTE: This should only be written to a different value 1904 during power-on SW initialization. */ 1905 uint64_t reserved_14_15 : 2; 1906 uint64_t tskw : 2; /**< Board Skew (represented in \#fclks) 1907 Represents additional board skew of DQ/DQS. 1908 - 00: board-skew = 0 fclk 1909 - 01: board-skew = 1 fclk 1910 - 10: board-skew = 2 fclk 1911 - 11: board-skew = 3 fclk 1912 NOTE: This should only be written to a different value 1913 during power-on SW initialization. */ 1914 uint64_t rnk_msk : 4; /**< Controls the CS_N[3:0] during a) a HW Initialization 1915 sequence (triggered by DFA_DDR2_CFG[INIT]) or 1916 b) during a normal refresh sequence. If 1917 the RNK_MSK[x]=1, the corresponding CS_N[x] is driven. 1918 NOTE: This is required for DRAM used in a 1919 clamshell configuration, since the address lines 1920 carry Mode Register write data that is unique 1921 per rank(or clam). In a clamshell configuration, 1922 the N3K DFA_A[x] pin may be tied into Clam#0's A[x] 1923 and also into Clam#1's 'mirrored' address bit A[y] 1924 (eg: Clam0 sees A[5] and Clam1 sees A[15]). 1925 To support clamshell designs, SW must initiate 1926 separate HW init sequences each unique rank address 1927 mapping. Before each HW init sequence is triggered, 1928 SW must preload the DFA_DDR2_MRS/EMRS registers with 1929 the data that will be driven onto the A[14:0] wires 1930 during the EMRS/MRS mode register write(s). 1931 NOTE: After the final HW initialization sequence has 1932 been triggered, SW must wait 64K eclks before writing 1933 the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0] 1934 is driven during refresh sequences in normal operation. 1935 NOTE: This should only be written to a different value 1936 during power-on SW initialization. */ 1937 uint64_t silo_qc : 1; /**< Enables Quarter Cycle move of the Rd sampling window */ 1938 uint64_t silo_hc : 1; /**< A combination of SILO_HC, SILO_QC and TSKW 1939 specifies the positioning of the sampling strobe 1940 when receiving read data back from DDR2. This is 1941 done to offset any board trace induced delay on 1942 the DQ and DQS which inherently makes these 1943 asynchronous with respect to the internal clk of 1944 controller. TSKW moves this sampling window by 1945 integer cycles. SILO_QC and HC move this quarter 1946 and half a cycle respectively. */ 1947 uint64_t sil_lat : 2; /**< Silo Latency (\#fclks): On reads, determines how many 1948 additional fclks to wait (on top of CASLAT+1) before 1949 pulling data out of the padring silos used for time 1950 domain boundary crossing. 1951 NOTE: This should only be written to a different value 1952 during power-on SW initialization. */ 1953 uint64_t bprch : 1; /**< Tristate Enable (back porch) (\#fclks) 1954 On reads, allows user to control the shape of the 1955 tristate disable back porch for the DQ data bus. 1956 This parameter is also very dependent on the 1957 RW_DLY and WR_DLY parameters and care must be 1958 taken when programming these parameters to avoid 1959 data bus contention. Valid range [0..2] 1960 NOTE: This should only be written to a different value 1961 during power-on SW initialization. */ 1962 uint64_t fprch : 1; /**< Tristate Enable (front porch) (\#fclks) 1963 On reads, allows user to control the shape of the 1964 tristate disable front porch for the DQ data bus. 1965 This parameter is also very dependent on the 1966 RW_DLY and WR_DLY parameters and care must be 1967 taken when programming these parameters to avoid 1968 data bus contention. Valid range [0..2] 1969 NOTE: This should only be written to a different value 1970 during power-on SW initialization. */ 1971 uint64_t init : 1; /**< When a '1' is written (and the previous value was '0'), 1972 the HW init sequence(s) for the LLM Memory Port is 1973 initiated. 1974 NOTE: To initialize memory, SW must: 1975 1) Enable memory port 1976 a) PRTENA=1 1977 2) Wait 200us (to ensure a stable clock 1978 to the DDR2) - as per DDR2 spec. 1979 3) Write a '1' to the INIT which 1980 will initiate a hardware initialization 1981 sequence. 1982 NOTE: After writing a '1', SW must wait 64K eclk 1983 cycles to ensure the HW init sequence has completed 1984 before writing to ANY of the DFA_DDR2* registers. 1985 NOTE: This should only be written to a different value 1986 during power-on SW initialization. */ 1987 uint64_t prtena : 1; /**< Enable DFA Memory 1988 When enabled, this bit lets N3K be the default 1989 driver for DFA-LLM memory port. */ 1990#else 1991 uint64_t prtena : 1; 1992 uint64_t init : 1; 1993 uint64_t fprch : 1; 1994 uint64_t bprch : 1; 1995 uint64_t sil_lat : 2; 1996 uint64_t silo_hc : 1; 1997 uint64_t silo_qc : 1; 1998 uint64_t rnk_msk : 4; 1999 uint64_t tskw : 2; 2000 uint64_t reserved_14_15 : 2; 2001 uint64_t ref_int : 13; 2002 uint64_t reserved_29_31 : 3; 2003 uint64_t fpip : 3; 2004 uint64_t mrs_pgm : 1; 2005 uint64_t trfc : 5; 2006 uint64_t reserved_41_63 : 23; 2007#endif 2008 } s; 2009 struct cvmx_dfa_ddr2_cfg_s cn31xx; 2010}; 2011typedef union cvmx_dfa_ddr2_cfg cvmx_dfa_ddr2_cfg_t; 2012 2013/** 2014 * cvmx_dfa_ddr2_comp 2015 * 2016 * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration 2017 * 2018 * 2019 * Description: The following are registers to program the DDR2 PLL and DLL 2020 */ 2021union cvmx_dfa_ddr2_comp { 2022 uint64_t u64; 2023 struct cvmx_dfa_ddr2_comp_s { 2024#ifdef __BIG_ENDIAN_BITFIELD 2025 uint64_t dfa__pctl : 4; /**< DFA DDR pctl from compensation circuit 2026 Internal DBG only */ 2027 uint64_t dfa__nctl : 4; /**< DFA DDR nctl from compensation circuit 2028 Internal DBG only */ 2029 uint64_t reserved_9_55 : 47; 2030 uint64_t pctl_csr : 4; /**< Compensation control bits */ 2031 uint64_t nctl_csr : 4; /**< Compensation control bits */ 2032 uint64_t comp_bypass : 1; /**< Compensation Bypass */ 2033#else 2034 uint64_t comp_bypass : 1; 2035 uint64_t nctl_csr : 4; 2036 uint64_t pctl_csr : 4; 2037 uint64_t reserved_9_55 : 47; 2038 uint64_t dfa__nctl : 4; 2039 uint64_t dfa__pctl : 4; 2040#endif 2041 } s; 2042 struct cvmx_dfa_ddr2_comp_s cn31xx; 2043}; 2044typedef union cvmx_dfa_ddr2_comp cvmx_dfa_ddr2_comp_t; 2045 2046/** 2047 * cvmx_dfa_ddr2_emrs 2048 * 2049 * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0] 2050 * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 2051 * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 2052 * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 2053 * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 2054 * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 2055 * 2056 * Notes: 2057 * For DDR-II please consult your device's data sheet for further details: 2058 * 2059 */ 2060union cvmx_dfa_ddr2_emrs { 2061 uint64_t u64; 2062 struct cvmx_dfa_ddr2_emrs_s { 2063#ifdef __BIG_ENDIAN_BITFIELD 2064 uint64_t reserved_31_63 : 33; 2065 uint64_t emrs1_ocd : 15; /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)" 2066 step \#12a "EMRS OCD Default Command" A[9:7]=111 2067 of DDR2 HW initialization sequence. 2068 (See JEDEC DDR2 specification (JESD79-2): 2069 Power Up and initialization sequence). 2070 A[14:13] = 0, RESERVED 2071 A[12] = 0, Output Buffers Enabled 2072 A[11] = 0, RDQS Disabled (we do not support RDQS) 2073 A[10] = 0, DQSn Enabled 2074 A[9:7] = 7, OCD Calibration Mode Default 2075 A[6] = 0, ODT Disabled 2076 A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 2077 A[2]=0 Termination Res RTT (ODT off Default) 2078 [A6,A2] = 0 -> ODT Disabled 2079 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 2080 A[1]=0 Normal Output Driver Imp mode 2081 (1 - weak ie., 60% of normal drive strength) 2082 A[0] = 0 DLL Enabled */ 2083 uint64_t reserved_15_15 : 1; 2084 uint64_t emrs1 : 15; /**< Memory Address[14:0] during: 2085 a) Step \#7 "EMRS1 to enable DLL (A[0]=0)" 2086 b) Step \#12b "EMRS OCD Calibration Mode Exit" 2087 steps of DDR2 HW initialization sequence. 2088 (See JEDEC DDR2 specification (JESD79-2): Power Up and 2089 initialization sequence). 2090 A[14:13] = 0, RESERVED 2091 A[12] = 0, Output Buffers Enabled 2092 A[11] = 0, RDQS Disabled (we do not support RDQS) 2093 A[10] = 0, DQSn Enabled 2094 A[9:7] = 0, OCD Calibration Mode exit/maintain 2095 A[6] = 0, ODT Disabled 2096 A[5:3]=DFA_DDR2_TMG[ADDLAT] Additive LATENCY (Default 0) 2097 A[2]=0 Termination Res RTT (ODT off Default) 2098 [A6,A2] = 0 -> ODT Disabled 2099 1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved 2100 A[1]=0 Normal Output Driver Imp mode 2101 (1 - weak ie., 60% of normal drive strength) 2102 A[0] = 0 DLL Enabled */ 2103#else 2104 uint64_t emrs1 : 15; 2105 uint64_t reserved_15_15 : 1; 2106 uint64_t emrs1_ocd : 15; 2107 uint64_t reserved_31_63 : 33; 2108#endif 2109 } s; 2110 struct cvmx_dfa_ddr2_emrs_s cn31xx; 2111}; 2112typedef union cvmx_dfa_ddr2_emrs cvmx_dfa_ddr2_emrs_t; 2113 2114/** 2115 * cvmx_dfa_ddr2_fcnt 2116 * 2117 * DFA_DDR2_FCNT = DFA FCLK Counter 2118 * 2119 * 2120 * Description: This FCLK cycle counter gets going after memory has been initialized 2121 */ 2122union cvmx_dfa_ddr2_fcnt { 2123 uint64_t u64; 2124 struct cvmx_dfa_ddr2_fcnt_s { 2125#ifdef __BIG_ENDIAN_BITFIELD 2126 uint64_t reserved_47_63 : 17; 2127 uint64_t fcyc_cnt : 47; /**< Counter counts FCLK cycles or \# cycles that the memory 2128 controller has requests queued up depending on FCNT_MODE 2129 If FCNT_MODE = 0, this counter counts the \# FCLK cycles 2130 If FCNT_MODE = 1, this counter counts the \# cycles the 2131 controller is active with memory requests. */ 2132#else 2133 uint64_t fcyc_cnt : 47; 2134 uint64_t reserved_47_63 : 17; 2135#endif 2136 } s; 2137 struct cvmx_dfa_ddr2_fcnt_s cn31xx; 2138}; 2139typedef union cvmx_dfa_ddr2_fcnt cvmx_dfa_ddr2_fcnt_t; 2140 2141/** 2142 * cvmx_dfa_ddr2_mrs 2143 * 2144 * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0] 2145 * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT 2146 * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init 2147 * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these 2148 * registers during the HW initialization sequence (see N3K specific restrictions in notes below). 2149 * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature. 2150 * 2151 * Notes: 2152 * For DDR-II please consult your device's data sheet for further details: 2153 * 2154 */ 2155union cvmx_dfa_ddr2_mrs { 2156 uint64_t u64; 2157 struct cvmx_dfa_ddr2_mrs_s { 2158#ifdef __BIG_ENDIAN_BITFIELD 2159 uint64_t reserved_31_63 : 33; 2160 uint64_t mrs : 15; /**< Memory Address[14:0] during "MRS without resetting 2161 DLL A[8]=0" step of HW initialization sequence. 2162 (See JEDEC DDR2 specification (JESD79-2): Power Up 2163 and initialization sequence - Step \#11). 2164 A[14:13] = 0, RESERVED 2165 A[12] = 0, Fast Active Power Down Mode 2166 A[11:9] = DFA_DDR2_TMG[TWR] 2167 A[8] = 0, for DLL Reset 2168 A[7] =0 Test Mode (must be 0 for normal operation) 2169 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 2170 A[3]=0 Burst Type(must be 0:Sequential) 2171 A[2:0]=2 Burst Length=4(default) */ 2172 uint64_t reserved_15_15 : 1; 2173 uint64_t mrs_dll : 15; /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1" 2174 step of HW initialization sequence. 2175 (See JEDEC DDR2 specification (JESD79-2): Power Up 2176 and initialization sequence - Step \#8). 2177 A[14:13] = 0, RESERVED 2178 A[12] = 0, Fast Active Power Down Mode 2179 A[11:9] = DFA_DDR2_TMG[TWR] 2180 A[8] = 1, for DLL Reset 2181 A[7] = 0 Test Mode (must be 0 for normal operation) 2182 A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4) 2183 A[3] = 0 Burst Type(must be 0:Sequential) 2184 A[2:0] = 2 Burst Length=4(default) */ 2185#else 2186 uint64_t mrs_dll : 15; 2187 uint64_t reserved_15_15 : 1; 2188 uint64_t mrs : 15; 2189 uint64_t reserved_31_63 : 33; 2190#endif 2191 } s; 2192 struct cvmx_dfa_ddr2_mrs_s cn31xx; 2193}; 2194typedef union cvmx_dfa_ddr2_mrs cvmx_dfa_ddr2_mrs_t; 2195 2196/** 2197 * cvmx_dfa_ddr2_opt 2198 * 2199 * DFA_DDR2_OPT = DFA DDR2 Optimization Registers 2200 * 2201 * 2202 * Description: The following are registers to tweak certain parameters to boost performance 2203 */ 2204union cvmx_dfa_ddr2_opt { 2205 uint64_t u64; 2206 struct cvmx_dfa_ddr2_opt_s { 2207#ifdef __BIG_ENDIAN_BITFIELD 2208 uint64_t reserved_10_63 : 54; 2209 uint64_t max_read_batch : 5; /**< Maximum number of consecutive read to service before 2210 allowing write to interrupt. */ 2211 uint64_t max_write_batch : 5; /**< Maximum number of consecutive writes to service before 2212 allowing reads to interrupt. */ 2213#else 2214 uint64_t max_write_batch : 5; 2215 uint64_t max_read_batch : 5; 2216 uint64_t reserved_10_63 : 54; 2217#endif 2218 } s; 2219 struct cvmx_dfa_ddr2_opt_s cn31xx; 2220}; 2221typedef union cvmx_dfa_ddr2_opt cvmx_dfa_ddr2_opt_t; 2222 2223/** 2224 * cvmx_dfa_ddr2_pll 2225 * 2226 * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration 2227 * 2228 * 2229 * Description: The following are registers to program the DDR2 PLL and DLL 2230 */ 2231union cvmx_dfa_ddr2_pll { 2232 uint64_t u64; 2233 struct cvmx_dfa_ddr2_pll_s { 2234#ifdef __BIG_ENDIAN_BITFIELD 2235 uint64_t pll_setting : 17; /**< Internal Debug Use Only */ 2236 uint64_t reserved_32_46 : 15; 2237 uint64_t setting90 : 5; /**< Contains the setting of DDR DLL; Internal DBG only */ 2238 uint64_t reserved_21_26 : 6; 2239 uint64_t dll_setting : 5; /**< Contains the open loop setting value for the DDR90 delay 2240 line. */ 2241 uint64_t dll_byp : 1; /**< DLL Bypass. When set, the DDR90 DLL is bypassed and 2242 the DLL behaves in Open Loop giving a fixed delay 2243 set by DLL_SETTING */ 2244 uint64_t qdll_ena : 1; /**< DDR Quad DLL Enable: A 0->1 transition on this bit after 2245 erst deassertion will reset the DDR 90 DLL. Allow 2246 200 micro seconds for Lock before DDR Init. */ 2247 uint64_t bw_ctl : 4; /**< Internal Use Only - for Debug */ 2248 uint64_t bw_upd : 1; /**< Internal Use Only - for Debug */ 2249 uint64_t pll_div2 : 1; /**< PLL Output is further divided by 2. Useful for slow 2250 fclk frequencies where the PLL may be out of range. */ 2251 uint64_t reserved_7_7 : 1; 2252 uint64_t pll_ratio : 5; /**< Bits <6:2> sets the clk multiplication ratio 2253 If the fclk frequency desired is less than 260MHz 2254 (lower end saturation point of the pll), write 2x 2255 the ratio desired in this register and set PLL_DIV2 */ 2256 uint64_t pll_bypass : 1; /**< PLL Bypass. Uses the ref_clk without multiplication. */ 2257 uint64_t pll_init : 1; /**< Need a 0 to 1 pulse on this CSR to get the DFA 2258 Clk Generator Started. Write this register before 2259 starting anything. Allow 200 uS for PLL Lock before 2260 doing anything. */ 2261#else 2262 uint64_t pll_init : 1; 2263 uint64_t pll_bypass : 1; 2264 uint64_t pll_ratio : 5; 2265 uint64_t reserved_7_7 : 1; 2266 uint64_t pll_div2 : 1; 2267 uint64_t bw_upd : 1; 2268 uint64_t bw_ctl : 4; 2269 uint64_t qdll_ena : 1; 2270 uint64_t dll_byp : 1; 2271 uint64_t dll_setting : 5; 2272 uint64_t reserved_21_26 : 6; 2273 uint64_t setting90 : 5; 2274 uint64_t reserved_32_46 : 15; 2275 uint64_t pll_setting : 17; 2276#endif 2277 } s; 2278 struct cvmx_dfa_ddr2_pll_s cn31xx; 2279}; 2280typedef union cvmx_dfa_ddr2_pll cvmx_dfa_ddr2_pll_t; 2281 2282/** 2283 * cvmx_dfa_ddr2_tmg 2284 * 2285 * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register 2286 * 2287 * 2288 * Description: The following are registers to program the DDR2 memory timing parameters. 2289 */ 2290union cvmx_dfa_ddr2_tmg { 2291 uint64_t u64; 2292 struct cvmx_dfa_ddr2_tmg_s { 2293#ifdef __BIG_ENDIAN_BITFIELD 2294 uint64_t reserved_47_63 : 17; 2295 uint64_t fcnt_mode : 1; /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles 2296 If FCNT_MODE = 1, this counter counts the \# cycles the 2297 controller is active with memory requests. */ 2298 uint64_t cnt_clr : 1; /**< Clears the FCLK Cyc & Bus Util counter */ 2299 uint64_t cavmipo : 1; /**< RESERVED */ 2300 uint64_t ctr_rst : 1; /**< Reset oneshot pulse for refresh counter & Perf counters 2301 SW should first write this field to a one to clear 2302 & then write to a zero for normal operation */ 2303 uint64_t odt_rtt : 2; /**< DDR2 Termination Resistor Setting 2304 These two bits are loaded into the RTT 2305 portion of the EMRS register bits A6 & A2. If DDR2's 2306 termination (for the memory's DQ/DQS/DM pads) is not 2307 desired, set it to 00. If it is, chose between 2308 01 for 75 ohm and 10 for 150 ohm termination. 2309 00 = ODT Disabled 2310 01 = 75 ohm Termination 2311 10 = 150 ohm Termination 2312 11 = 50 ohm Termination */ 2313 uint64_t dqsn_ena : 1; /**< For DDR-II Mode, DIC[1] is used to load into EMRS 2314 bit 10 - DQSN Enable/Disable field. By default, we 2315 program the DDR's to drive the DQSN also. Set it to 2316 1 if DQSN should be Hi-Z. 2317 0 - DQSN Enable 2318 1 - DQSN Disable */ 2319 uint64_t dic : 1; /**< Drive Strength Control: 2320 For DDR-I/II Mode, DIC[0] is 2321 loaded into the Extended Mode Register (EMRS) A1 bit 2322 during initialization. (see DDR-I data sheet EMRS 2323 description) 2324 0 = Normal 2325 1 = Reduced */ 2326 uint64_t r2r_slot : 1; /**< A 1 on this register will force the controller to 2327 slot a bubble between every reads */ 2328 uint64_t tfaw : 5; /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1 2329 Four Access Window time. Relevant only in 2330 8-bank parts. 2331 TFAW = 5'b0 for DDR2-4bank 2332 TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */ 2333 uint64_t twtr : 4; /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)] 2334 Last Wr Data to Rd Command time. 2335 (Represented in fclk cycles) 2336 TYP=15ns 2337 - 0000: RESERVED 2338 - 0001: 1 2339 - ... 2340 - 0111: 7 2341 - 1000-1111: RESERVED */ 2342 uint64_t twr : 3; /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech 2343 This is not a direct encoding of the value. Its 2344 programmed as below per DDR2 spec. The decimal number 2345 on the right is RNDUP(tWR(ns) / clkFreq) 2346 TYP=15ns 2347 - 000: RESERVED 2348 - 001: 2 2349 - 010: 3 2350 - 011: 4 2351 - 100: 5 2352 - 101: 6 2353 - 110-111: RESERVED */ 2354 uint64_t trp : 4; /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)] 2355 (Represented in fclk cycles) 2356 TYP=15ns 2357 - 0000: RESERVED 2358 - 0001: 1 2359 - ... 2360 - 0111: 7 2361 - 1000-1111: RESERVED 2362 When using parts with 8 banks (DFA_CFG->MAX_BNK 2363 is 1), load tRP cycles + 1 into this register. */ 2364 uint64_t tras : 5; /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)] 2365 (Represented in fclk cycles) 2366 TYP=45ns 2367 - 00000-0001: RESERVED 2368 - 00010: 2 2369 - ... 2370 - 10100: 20 2371 - 10101-11111: RESERVED */ 2372 uint64_t trrd : 3; /**< tRRD cycles: ACT-ACT timing parameter for different 2373 banks. (Represented in fclk cycles) 2374 For DDR2, TYP=7.5ns 2375 - 000: RESERVED 2376 - 001: 1 tCYC 2377 - 010: 2 tCYC 2378 - 011: 3 tCYC 2379 - 100: 4 tCYC 2380 - 101: 5 tCYC 2381 - 110-111: RESERVED */ 2382 uint64_t trcd : 4; /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)] 2383 (Represented in fclk cycles) 2384 TYP=15ns 2385 - 0000: RESERVED 2386 - 0001: 2 (2 is the smallest value allowed) 2387 - 0002: 2 2388 - ... 2389 - 0111: 7 2390 - 1110-1111: RESERVED */ 2391 uint64_t addlat : 3; /**< When in Posted CAS mode ADDLAT needs to be programmed 2392 to tRCD-1 2393 ADDLAT \#additional latency cycles 2394 000 0 2395 001 1 (tRCD = 2 fclk's) 2396 010 2 (tRCD = 3 fclk's) 2397 011 3 (tRCD = 4 fclk's) 2398 100 4 (tRCD = 5 fclk's) 2399 101 5 (tRCD = 6 fclk's) 2400 110 6 (tRCD = 7 fclk's) 2401 111 7 (tRCD = 8 fclk's) */ 2402 uint64_t pocas : 1; /**< Posted CAS mode. When 1, we use DDR2's Posted CAS 2403 feature. When using this mode, ADDLAT needs to be 2404 programmed as well */ 2405 uint64_t caslat : 3; /**< CAS Latency in \# fclk Cycles 2406 CASLAT \# CAS latency cycles 2407 000 - 010 RESERVED 2408 011 3 2409 100 4 2410 101 5 2411 110 6 2412 111 7 */ 2413 uint64_t tmrd : 2; /**< tMRD Cycles 2414 (Represented in fclk tCYC) 2415 For DDR2, its TYP 2*tCYC) 2416 - 000: RESERVED 2417 - 001: 1 2418 - 010: 2 2419 - 011: 3 */ 2420 uint64_t ddr2t : 1; /**< When 2T mode is turned on, command signals are 2421 setup a cycle ahead of when the CS is enabled 2422 and kept for a total of 2 cycles. This mode is 2423 enabled in higher speeds when there is difficulty 2424 meeting setup. Performance could 2425 be negatively affected in 2T mode */ 2426#else 2427 uint64_t ddr2t : 1; 2428 uint64_t tmrd : 2; 2429 uint64_t caslat : 3; 2430 uint64_t pocas : 1; 2431 uint64_t addlat : 3; 2432 uint64_t trcd : 4; 2433 uint64_t trrd : 3; 2434 uint64_t tras : 5; 2435 uint64_t trp : 4; 2436 uint64_t twr : 3; 2437 uint64_t twtr : 4; 2438 uint64_t tfaw : 5; 2439 uint64_t r2r_slot : 1; 2440 uint64_t dic : 1; 2441 uint64_t dqsn_ena : 1; 2442 uint64_t odt_rtt : 2; 2443 uint64_t ctr_rst : 1; 2444 uint64_t cavmipo : 1; 2445 uint64_t cnt_clr : 1; 2446 uint64_t fcnt_mode : 1; 2447 uint64_t reserved_47_63 : 17; 2448#endif 2449 } s; 2450 struct cvmx_dfa_ddr2_tmg_s cn31xx; 2451}; 2452typedef union cvmx_dfa_ddr2_tmg cvmx_dfa_ddr2_tmg_t; 2453 2454/** 2455 * cvmx_dfa_debug0 2456 * 2457 * DFA_DEBUG0 = DFA Scoreboard Debug \#0 Register 2458 * *FOR INTERNAL USE ONLY* 2459 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2460 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2461 * CSR read. 2462 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2463 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2464 * instruction. 2465 */ 2466union cvmx_dfa_debug0 { 2467 uint64_t u64; 2468 struct cvmx_dfa_debug0_s { 2469#ifdef __BIG_ENDIAN_BITFIELD 2470 uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 2471 (DFA Scoreboard Debug) 2472 [63:38] (26) rptr[28:3]: Result Base Pointer (QW-aligned) 2473 [37:22] (16) Cumulative Result Write Counter (for HDR write) 2474 [21] (1) Waiting for GRdRsp EOT 2475 [20] (1) Waiting for GRdReq Issue (to NRQ) 2476 [19] (1) GLPTR/GLCNT Valid 2477 [18] (1) Completion Mark Detected 2478 [17:15] (3) Completion Code [0=PDGONE/1=PERR/2=RFULL/3=TERM] 2479 [14] (1) Completion Detected 2480 [13] (1) Waiting for HDR RWrCmtRsp 2481 [12] (1) Waiting for LAST RESULT RWrCmtRsp 2482 [11] (1) Waiting for HDR RWrReq 2483 [10] (1) Waiting for RWrReq 2484 [9] (1) Waiting for WQWrReq issue 2485 [8] (1) Waiting for PRdRsp EOT 2486 [7] (1) Waiting for PRdReq Issue (to NRQ) 2487 [6] (1) Packet Data Valid 2488 [5] (1) WQVLD 2489 [4] (1) WQ Done Point (either WQWrReq issued (for WQPTR<>0) OR HDR RWrCmtRsp) 2490 [3] (1) Resultant write STF/P Mode 2491 [2] (1) Packet Data LDT mode 2492 [1] (1) Gather Mode 2493 [0] (1) Valid */ 2494#else 2495 uint64_t sbd0 : 64; 2496#endif 2497 } s; 2498 struct cvmx_dfa_debug0_s cn61xx; 2499 struct cvmx_dfa_debug0_s cn63xx; 2500 struct cvmx_dfa_debug0_s cn63xxp1; 2501 struct cvmx_dfa_debug0_s cn66xx; 2502 struct cvmx_dfa_debug0_s cn68xx; 2503 struct cvmx_dfa_debug0_s cn68xxp1; 2504}; 2505typedef union cvmx_dfa_debug0 cvmx_dfa_debug0_t; 2506 2507/** 2508 * cvmx_dfa_debug1 2509 * 2510 * DFA_DEBUG1 = DFA Scoreboard Debug \#1 Register 2511 * *FOR INTERNAL USE ONLY* 2512 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2513 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2514 * CSR read. 2515 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2516 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2517 * instruction. 2518 */ 2519union cvmx_dfa_debug1 { 2520 uint64_t u64; 2521 struct cvmx_dfa_debug1_s { 2522#ifdef __BIG_ENDIAN_BITFIELD 2523 uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 2524 DFA Scoreboard Debug Data 2525 [63:56] (8) UNUSED 2526 [55:16] (40) Packet Data Pointer 2527 [15:0] (16) Packet Data Counter */ 2528#else 2529 uint64_t sbd1 : 64; 2530#endif 2531 } s; 2532 struct cvmx_dfa_debug1_s cn61xx; 2533 struct cvmx_dfa_debug1_s cn63xx; 2534 struct cvmx_dfa_debug1_s cn63xxp1; 2535 struct cvmx_dfa_debug1_s cn66xx; 2536 struct cvmx_dfa_debug1_s cn68xx; 2537 struct cvmx_dfa_debug1_s cn68xxp1; 2538}; 2539typedef union cvmx_dfa_debug1 cvmx_dfa_debug1_t; 2540 2541/** 2542 * cvmx_dfa_debug2 2543 * 2544 * DFA_DEBUG2 = DFA Scoreboard Debug \#2 Register 2545 * 2546 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2547 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2548 * CSR read. 2549 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2550 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2551 * instruction. 2552 */ 2553union cvmx_dfa_debug2 { 2554 uint64_t u64; 2555 struct cvmx_dfa_debug2_s { 2556#ifdef __BIG_ENDIAN_BITFIELD 2557 uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 2558 [63:45] (19) UNUSED 2559 [44:42] (3) Instruction Type 2560 [41:5] (37) rwptr[39:3]: Result Write Pointer 2561 [4:0] (5) prwcnt[4:0]: Pending Result Write Counter */ 2562#else 2563 uint64_t sbd2 : 64; 2564#endif 2565 } s; 2566 struct cvmx_dfa_debug2_s cn61xx; 2567 struct cvmx_dfa_debug2_s cn63xx; 2568 struct cvmx_dfa_debug2_s cn63xxp1; 2569 struct cvmx_dfa_debug2_s cn66xx; 2570 struct cvmx_dfa_debug2_s cn68xx; 2571 struct cvmx_dfa_debug2_s cn68xxp1; 2572}; 2573typedef union cvmx_dfa_debug2 cvmx_dfa_debug2_t; 2574 2575/** 2576 * cvmx_dfa_debug3 2577 * 2578 * DFA_DEBUG3 = DFA Scoreboard Debug \#3 Register 2579 * 2580 * Description: When the DFA_CONTROL[SBDLCK] bit is written '1', the contents of this register are locked down. 2581 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 2582 * CSR read. 2583 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 2584 * on the reads unless the DTE Engine specified by DFA_CONTROL[SBDNUM] has previously been assigned an 2585 * instruction. 2586 */ 2587union cvmx_dfa_debug3 { 2588 uint64_t u64; 2589 struct cvmx_dfa_debug3_s { 2590#ifdef __BIG_ENDIAN_BITFIELD 2591 uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 2592 [63:52] (11) rptr[39:29]: Result Base Pointer (QW-aligned) 2593 [52:16] (37) glptr[39:3]: Gather List Pointer 2594 [15:0] (16) glcnt Gather List Counter */ 2595#else 2596 uint64_t sbd3 : 64; 2597#endif 2598 } s; 2599 struct cvmx_dfa_debug3_s cn61xx; 2600 struct cvmx_dfa_debug3_s cn63xx; 2601 struct cvmx_dfa_debug3_s cn63xxp1; 2602 struct cvmx_dfa_debug3_s cn66xx; 2603 struct cvmx_dfa_debug3_s cn68xx; 2604 struct cvmx_dfa_debug3_s cn68xxp1; 2605}; 2606typedef union cvmx_dfa_debug3 cvmx_dfa_debug3_t; 2607 2608/** 2609 * cvmx_dfa_difctl 2610 * 2611 * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register 2612 * 2613 * Description: 2614 * NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b110. 2615 * To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b110. 2616 * 2617 * NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could 2618 * cause the DFA and FPA HW to become unpredictable. 2619 * 2620 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect. 2621 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect. 2622 */ 2623union cvmx_dfa_difctl { 2624 uint64_t u64; 2625 struct cvmx_dfa_difctl_s { 2626#ifdef __BIG_ENDIAN_BITFIELD 2627 uint64_t reserved_26_63 : 38; 2628 uint64_t msegbase : 6; /**< Memory Segmentation Base Address 2629 For debug purposes, backdoor accesses to the DFA 2630 memory are supported via NCB-Direct CSR accesses to 2631 the DFA Memory REGION(if addr[34:32]=5. However due 2632 to the existing NCB address decoding scheme, the 2633 address only offers a 4GB extent into the DFA memory 2634 REGION. Therefore, the MSEGBASE CSR field provides 2635 the additional upper memory address bits to allow access 2636 to the full extent of memory (128GB MAX). 2637 For DFA Memory REGION read NCB-Direct CSR accesses, the 2638 38bit L2/DRAM memory byte address is generated as follows: 2639 memaddr[37:0] = [DFA_DIFCTL[MSEGBASE],ncb_addr[31:3],3'b0] 2640 NOTE: See the upper 6bits of the memory address are sourced 2641 from DFA_DIFCTL[MSEGBASE] CSR field. The lower 4GB address 2642 offset is directly referenced using the NCB address bits during 2643 the reference itself. 2644 NOTE: The DFA_DIFCTL[MSEGBASE] is shared amongst all references. 2645 As such, if multiple PPs are accessing different segments in memory, 2646 their must be a SW mutual exclusive lock during each DFA Memory 2647 REGION access to avoid collisions between PPs using the same MSEGBASE 2648 CSR field. 2649 NOTE: See also DFA_ERROR[DFANXM] programmable interrupt which is 2650 flagged if SW tries to access non-existent memory space (address hole 2651 or upper unused region of 38bit address space). */ 2652 uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction 2653 buffer that may be dirty and should not be 2654 written-back to memory when the instruction 2655 chunk is returned to the Free Page list. 2656 NOTE: Typically SW will want to mark all DFA 2657 Instruction memory returned to the Free Page list 2658 as DWB (Don't WriteBack), therefore SW should 2659 seed this register as: 2660 DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */ 2661 uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW 2662 when the DFA instruction chunk is recycled back 2663 to the Free Page List maintained by the FPA HW 2664 (once the DFA instruction has been issued). */ 2665 uint64_t size : 9; /**< Represents the \# of 32B instructions contained 2666 within each DFA instruction chunk. At Power-on, 2667 SW will seed the SIZE register with a fixed 2668 chunk-size. (Must be at least 3) 2669 DFA HW uses this field to determine the size 2670 of each DFA instruction chunk, in order to: 2671 a) determine when to read the next DFA 2672 instruction chunk pointer which is 2673 written by SW at the end of the current 2674 DFA instruction chunk (see DFA description 2675 of next chunk buffer Ptr for format). 2676 b) determine when a DFA instruction chunk 2677 can be returned to the Free Page List 2678 maintained by the FPA HW. */ 2679#else 2680 uint64_t size : 9; 2681 uint64_t pool : 3; 2682 uint64_t dwbcnt : 8; 2683 uint64_t msegbase : 6; 2684 uint64_t reserved_26_63 : 38; 2685#endif 2686 } s; 2687 struct cvmx_dfa_difctl_cn31xx { 2688#ifdef __BIG_ENDIAN_BITFIELD 2689 uint64_t reserved_20_63 : 44; 2690 uint64_t dwbcnt : 8; /**< Represents the \# of cache lines in the instruction 2691 buffer that may be dirty and should not be 2692 written-back to memory when the instruction 2693 chunk is returned to the Free Page list. 2694 NOTE: Typically SW will want to mark all DFA 2695 Instruction memory returned to the Free Page list 2696 as DWB (Don't WriteBack), therefore SW should 2697 seed this register as: 2698 DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */ 2699 uint64_t pool : 3; /**< Represents the 3bit buffer pool-id used by DFA HW 2700 when the DFA instruction chunk is recycled back 2701 to the Free Page List maintained by the FPA HW 2702 (once the DFA instruction has been issued). */ 2703 uint64_t size : 9; /**< Represents the \# of 32B instructions contained 2704 within each DFA instruction chunk. At Power-on, 2705 SW will seed the SIZE register with a fixed 2706 chunk-size. (Must be at least 3) 2707 DFA HW uses this field to determine the size 2708 of each DFA instruction chunk, in order to: 2709 a) determine when to read the next DFA 2710 instruction chunk pointer which is 2711 written by SW at the end of the current 2712 DFA instruction chunk (see DFA description 2713 of next chunk buffer Ptr for format). 2714 b) determine when a DFA instruction chunk 2715 can be returned to the Free Page List 2716 maintained by the FPA HW. */ 2717#else 2718 uint64_t size : 9; 2719 uint64_t pool : 3; 2720 uint64_t dwbcnt : 8; 2721 uint64_t reserved_20_63 : 44; 2722#endif 2723 } cn31xx; 2724 struct cvmx_dfa_difctl_cn31xx cn38xx; 2725 struct cvmx_dfa_difctl_cn31xx cn38xxp2; 2726 struct cvmx_dfa_difctl_cn31xx cn58xx; 2727 struct cvmx_dfa_difctl_cn31xx cn58xxp1; 2728 struct cvmx_dfa_difctl_s cn61xx; 2729 struct cvmx_dfa_difctl_cn31xx cn63xx; 2730 struct cvmx_dfa_difctl_cn31xx cn63xxp1; 2731 struct cvmx_dfa_difctl_cn31xx cn66xx; 2732 struct cvmx_dfa_difctl_s cn68xx; 2733 struct cvmx_dfa_difctl_s cn68xxp1; 2734}; 2735typedef union cvmx_dfa_difctl cvmx_dfa_difctl_t; 2736 2737/** 2738 * cvmx_dfa_difrdptr 2739 * 2740 * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register 2741 * 2742 * Description: 2743 * NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01. 2744 * To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01. 2745 * 2746 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect. 2747 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect. 2748 */ 2749union cvmx_dfa_difrdptr { 2750 uint64_t u64; 2751 struct cvmx_dfa_difrdptr_s { 2752#ifdef __BIG_ENDIAN_BITFIELD 2753 uint64_t reserved_40_63 : 24; 2754 uint64_t rdptr : 35; /**< Represents the 32B-aligned address of the current 2755 instruction in the DFA Instruction FIFO in main 2756 memory. The RDPTR must be seeded by software at 2757 boot time, and is then maintained thereafter 2758 by DFA HW. 2759 During the seed write (by SW), RDPTR[6:5]=0, 2760 since DFA instruction chunks must be 128B aligned. 2761 During a read (by SW), the 'most recent' contents 2762 of the RDPTR register are returned at the time 2763 the NCB-INB bus is driven. 2764 NOTE: Since DFA HW updates this register, its 2765 contents are unpredictable in SW (unless 2766 its guaranteed that no new DoorBell register 2767 writes have occurred and the DoorBell register is 2768 read as zero). */ 2769 uint64_t reserved_0_4 : 5; 2770#else 2771 uint64_t reserved_0_4 : 5; 2772 uint64_t rdptr : 35; 2773 uint64_t reserved_40_63 : 24; 2774#endif 2775 } s; 2776 struct cvmx_dfa_difrdptr_cn31xx { 2777#ifdef __BIG_ENDIAN_BITFIELD 2778 uint64_t reserved_36_63 : 28; 2779 uint64_t rdptr : 31; /**< Represents the 32B-aligned address of the current 2780 instruction in the DFA Instruction FIFO in main 2781 memory. The RDPTR must be seeded by software at 2782 boot time, and is then maintained thereafter 2783 by DFA HW. 2784 During the seed write (by SW), RDPTR[6:5]=0, 2785 since DFA instruction chunks must be 128B aligned. 2786 During a read (by SW), the 'most recent' contents 2787 of the RDPTR register are returned at the time 2788 the NCB-INB bus is driven. 2789 NOTE: Since DFA HW updates this register, its 2790 contents are unpredictable in SW (unless 2791 its guaranteed that no new DoorBell register 2792 writes have occurred and the DoorBell register is 2793 read as zero). */ 2794 uint64_t reserved_0_4 : 5; 2795#else 2796 uint64_t reserved_0_4 : 5; 2797 uint64_t rdptr : 31; 2798 uint64_t reserved_36_63 : 28; 2799#endif 2800 } cn31xx; 2801 struct cvmx_dfa_difrdptr_cn31xx cn38xx; 2802 struct cvmx_dfa_difrdptr_cn31xx cn38xxp2; 2803 struct cvmx_dfa_difrdptr_cn31xx cn58xx; 2804 struct cvmx_dfa_difrdptr_cn31xx cn58xxp1; 2805 struct cvmx_dfa_difrdptr_s cn61xx; 2806 struct cvmx_dfa_difrdptr_s cn63xx; 2807 struct cvmx_dfa_difrdptr_s cn63xxp1; 2808 struct cvmx_dfa_difrdptr_s cn66xx; 2809 struct cvmx_dfa_difrdptr_s cn68xx; 2810 struct cvmx_dfa_difrdptr_s cn68xxp1; 2811}; 2812typedef union cvmx_dfa_difrdptr cvmx_dfa_difrdptr_t; 2813 2814/** 2815 * cvmx_dfa_dtcfadr 2816 * 2817 * DFA_DTCFADR = DFA DTC Failing Address Register 2818 * 2819 * Description: DFA Node Cache Failing Address/Control Error Capture information 2820 * This register contains useful information to help in isolating a Node Cache RAM failure. 2821 * NOTE: The first detected PERR failure is captured in DFA_DTCFADR (locked down), until the 2822 * corresponding PERR Interrupt is cleared by writing one (W1C). (see: DFA_ERR[DC0PERR[2:0]]). 2823 * NOTE: In the rare event that multiple parity errors are detected in the same cycle from multiple 2824 * clusters, the FADR register will be locked down for the least signicant cluster \# (0->3). 2825 */ 2826union cvmx_dfa_dtcfadr { 2827 uint64_t u64; 2828 struct cvmx_dfa_dtcfadr_s { 2829#ifdef __BIG_ENDIAN_BITFIELD 2830 uint64_t reserved_44_63 : 20; 2831 uint64_t ram3fadr : 12; /**< DFA RAM3 Failing Address 2832 If DFA_ERR[DC0PERR<2>]=1, this field indicates the 2833 failing RAM3 Address. The failing address is locked 2834 down until the DC0PERR<2> W1C occurs. 2835 NOTE: If multiple DC0PERR<0>=1 errors are detected, 2836 then the lsb cluster error information is captured. */ 2837 uint64_t reserved_25_31 : 7; 2838 uint64_t ram2fadr : 9; /**< DFA RAM2 Failing Address 2839 If DFA_ERR[DC0PERR<1>]=1, this field indicates the 2840 failing RAM2 Address. The failing address is locked 2841 down until the DC0PERR<1> W1C occurs. 2842 NOTE: If multiple DC0PERR<0>=1 errors are detected, 2843 then the lsb cluster error information is captured. */ 2844 uint64_t reserved_14_15 : 2; 2845 uint64_t ram1fadr : 14; /**< DFA RAM1 Failing Address 2846 If DFA_ERR[DC0PERR<0>]=1, this field indicates the 2847 failing RAM1 Address. The failing address is locked 2848 down until the DC0PERR<0> W1C occurs. 2849 NOTE: If multiple DC0PERR<0>=1 errors are detected, 2850 then the lsb cluster error information is captured. */ 2851#else 2852 uint64_t ram1fadr : 14; 2853 uint64_t reserved_14_15 : 2; 2854 uint64_t ram2fadr : 9; 2855 uint64_t reserved_25_31 : 7; 2856 uint64_t ram3fadr : 12; 2857 uint64_t reserved_44_63 : 20; 2858#endif 2859 } s; 2860 struct cvmx_dfa_dtcfadr_s cn61xx; 2861 struct cvmx_dfa_dtcfadr_s cn63xx; 2862 struct cvmx_dfa_dtcfadr_s cn63xxp1; 2863 struct cvmx_dfa_dtcfadr_s cn66xx; 2864 struct cvmx_dfa_dtcfadr_s cn68xx; 2865 struct cvmx_dfa_dtcfadr_s cn68xxp1; 2866}; 2867typedef union cvmx_dfa_dtcfadr cvmx_dfa_dtcfadr_t; 2868 2869/** 2870 * cvmx_dfa_eclkcfg 2871 * 2872 * Specify the RSL base addresses for the block 2873 * 2874 * DFA_ECLKCFG = DFA eclk-domain Configuration Registers 2875 * 2876 * Description: 2877 */ 2878union cvmx_dfa_eclkcfg { 2879 uint64_t u64; 2880 struct cvmx_dfa_eclkcfg_s { 2881#ifdef __BIG_ENDIAN_BITFIELD 2882 uint64_t reserved_19_63 : 45; 2883 uint64_t sbdnum : 3; /**< SBD Debug Entry# 2884 For internal use only. (DFA Scoreboard debug) 2885 Selects which one of 8 DFA Scoreboard entries is 2886 latched into the DFA_SBD_DBG[0-3] registers. */ 2887 uint64_t reserved_15_15 : 1; 2888 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 2889 For internal use only. (DFA Scoreboard debug) 2890 When written with a '1', the DFA Scoreboard Debug 2891 registers (DFA_SBD_DBG[0-3]) are all locked down. 2892 This allows SW to lock down the contents of the entire 2893 SBD for a single instant in time. All subsequent reads 2894 of the DFA scoreboard registers will return the data 2895 from that instant in time. */ 2896 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 2897 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 2898 NOTE: This should only be written to a different value 2899 during power-on SW initialization. */ 2900 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 2901 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 2902 NOTE: This should only be written to a different value 2903 during power-on SW initialization. */ 2904 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 2905 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 2906 NOTE: This should only be written to a different value 2907 during power-on SW initialization. */ 2908 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 2909 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 2910 NOTE: This should only be written to a different value 2911 during power-on SW initialization. */ 2912 uint64_t imode : 1; /**< NCB-Inbound Arbiter 2913 (0=FP [LP=NRQ,HP=NRP], 1=RR) 2914 NOTE: This should only be written to a different value 2915 during power-on SW initialization. */ 2916 uint64_t sarb : 1; /**< DFA Source Arbiter Mode 2917 Selects the arbitration mode used to select DFA requests 2918 issued from either CP2 or the DTE (NCB-CSR or DFA HW engine). 2919 - 0: Fixed Priority [Highest=CP2, Lowest=DTE] 2920 - 1: Round-Robin 2921 NOTE: This should only be written to a different value 2922 during power-on SW initialization. */ 2923 uint64_t reserved_3_7 : 5; 2924 uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 2925 When SET, the DFA clocks for DTE(thread engine) 2926 operation are disabled. 2927 NOTE: When SET, SW MUST NEVER issue ANY operations to 2928 the DFA via the NCB Bus. All DFA Operations must be 2929 issued solely through the CP2 interface. */ 2930 uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 2931 when extracting address bits for the memory bank#. 2932 - 0: 4 banks/device 2933 - 1: 8 banks/device */ 2934 uint64_t dfa_frstn : 1; /**< Hold this 0 until the DFA DDR PLL and DLL lock 2935 and then write a 1. A 1 on this register deasserts 2936 the internal frst_n. Refer to DFA_DDR2_PLL registers for more 2937 startup information. 2938 Startup sequence if DFA interface needs to be ON: 2939 After valid power up, 2940 Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS 2941 to the appropriate values 2942 Wait a few cycles 2943 Write a 1 DFA_DDR2_PLL -> PLL_INIT 2944 Wait 100 microseconds 2945 Write a 1 to DFA_DDR2_PLL -> QDLL_ENA 2946 Wait 10 microseconds 2947 Write a 1 to this register DFA_FRSTN to pull DFA out of 2948 reset 2949 Now the DFA block is ready to be initialized (follow the 2950 DDR init sequence). */ 2951#else 2952 uint64_t dfa_frstn : 1; 2953 uint64_t maxbnk : 1; 2954 uint64_t dteclkdis : 1; 2955 uint64_t reserved_3_7 : 5; 2956 uint64_t sarb : 1; 2957 uint64_t imode : 1; 2958 uint64_t qmode : 1; 2959 uint64_t pmode : 1; 2960 uint64_t dtmode : 1; 2961 uint64_t dcmode : 1; 2962 uint64_t sbdlck : 1; 2963 uint64_t reserved_15_15 : 1; 2964 uint64_t sbdnum : 3; 2965 uint64_t reserved_19_63 : 45; 2966#endif 2967 } s; 2968 struct cvmx_dfa_eclkcfg_s cn31xx; 2969}; 2970typedef union cvmx_dfa_eclkcfg cvmx_dfa_eclkcfg_t; 2971 2972/** 2973 * cvmx_dfa_err 2974 * 2975 * DFA_ERR = DFA ERROR Register 2976 * 2977 * Description: 2978 */ 2979union cvmx_dfa_err { 2980 uint64_t u64; 2981 struct cvmx_dfa_err_s { 2982#ifdef __BIG_ENDIAN_BITFIELD 2983 uint64_t reserved_33_63 : 31; 2984 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 2985 When set, doorbell overflow conditions are reported. */ 2986 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 2987 When set, the 20b accumulated doorbell register 2988 had overflowed (SW wrote too many doorbell requests). 2989 If the DBLINA had previously been enabled(set), 2990 an interrupt will be posted. Software can clear 2991 the interrupt by writing a 1 to this register bit. 2992 NOTE: Detection of a Doorbell Register overflow 2993 is a catastrophic error which may leave the DFA 2994 HW in an unrecoverable state. */ 2995 uint64_t cp2pina : 1; /**< CP2 LW Mode Parity Error Interrupt Enable bit. 2996 When set, all PP-generated LW Mode read 2997 transactions which encounter a parity error (across 2998 the 36b of data) are reported. */ 2999 uint64_t cp2perr : 1; /**< PP-CP2 Parity Error Detected - Status bit 3000 When set, a parity error had been detected for a 3001 PP-generated LW Mode read transaction. 3002 If the CP2PINA had previously been enabled(set), 3003 an interrupt will be posted. Software can clear 3004 the interrupt by writing a 1 to this register bit. 3005 See also: DFA_MEMFADR CSR which contains more data 3006 about the memory address/control to help isolate 3007 the failure. */ 3008 uint64_t cp2parena : 1; /**< CP2 LW Mode Parity Error Enable 3009 When set, all PP-generated LW Mode read 3010 transactions which encounter a parity error (across 3011 the 36b of data) are reported. 3012 NOTE: This signal must only be written to a different 3013 value when there are no PP-CP2 transactions 3014 (preferrably during power-on software initialization). */ 3015 uint64_t dtepina : 1; /**< DTE Parity Error Interrupt Enable bit 3016 (for 18b SIMPLE mode ONLY). 3017 When set, all DTE-generated 18b SIMPLE Mode read 3018 transactions which encounter a parity error (across 3019 the 17b of data) are reported. */ 3020 uint64_t dteperr : 1; /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY) 3021 When set, all DTE-generated 18b SIMPLE Mode read 3022 transactions which encounter a parity error (across 3023 the 17b of data) are reported. */ 3024 uint64_t dteparena : 1; /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY) 3025 When set, all DTE-generated 18b SIMPLE Mode read 3026 transactions which encounter a parity error (across 3027 the 17b of data) are reported. 3028 NOTE: This signal must only be written to a different 3029 value when there are no DFA thread engines active 3030 (preferrably during power-on). */ 3031 uint64_t dtesyn : 7; /**< DTE 29b ECC Failing 6bit Syndrome 3032 When DTESBE or DTEDBE are set, this field contains 3033 the failing 7b ECC syndrome. */ 3034 uint64_t dtedbina : 1; /**< DTE 29b Double Bit Error Interrupt Enable bit 3035 When set, an interrupt is posted for any DTE-generated 3036 36b SIMPLE Mode read which encounters a double bit 3037 error. */ 3038 uint64_t dtesbina : 1; /**< DTE 29b Single Bit Error Interrupt Enable bit 3039 When set, an interrupt is posted for any DTE-generated 3040 36b SIMPLE Mode read which encounters a single bit 3041 error (which is also corrected). */ 3042 uint64_t dtedbe : 1; /**< DTE 29b Double Bit Error Detected - Status bit 3043 When set, a double bit error had been detected 3044 for a DTE-generated 36b SIMPLE Mode read transaction. 3045 The DTESYN contains the failing syndrome. 3046 If the DTEDBINA had previously been enabled(set), 3047 an interrupt will be posted. Software can clear 3048 the interrupt by writing a 1 to this register bit. 3049 See also: DFA_MEMFADR CSR which contains more data 3050 about the memory address/control to help isolate 3051 the failure. 3052 NOTE: DTE-generated 18b SIMPLE Mode Read transactions 3053 do not participate in ECC check/correct). */ 3054 uint64_t dtesbe : 1; /**< DTE 29b Single Bit Error Corrected - Status bit 3055 When set, a single bit error had been detected and 3056 corrected for a DTE-generated 36b SIMPLE Mode read 3057 transaction. 3058 If the DTEDBE=0, then the DTESYN contains the 3059 failing syndrome (used during correction). 3060 NOTE: DTE-generated 18b SIMPLE Mode Read 3061 transactions do not participate in ECC check/correct). 3062 If the DTESBINA had previously been enabled(set), 3063 an interrupt will be posted. Software can clear 3064 the interrupt by writing a 1 to this register bit. 3065 See also: DFA_MEMFADR CSR which contains more data 3066 about the memory address/control to help isolate 3067 the failure. */ 3068 uint64_t dteeccena : 1; /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY) 3069 When set, 29b ECC is enabled on all DTE-generated 3070 36b SIMPLE Mode read transactions. 3071 NOTE: This signal must only be written to a different 3072 value when there are no DFA thread engines active 3073 (preferrably during power-on software initialization). */ 3074 uint64_t cp2syn : 8; /**< PP-CP2 QW ECC Failing 8bit Syndrome 3075 When CP2SBE or CP2DBE are set, this field contains 3076 the failing ECC 8b syndrome. 3077 Refer to CP2ECCENA. */ 3078 uint64_t cp2dbina : 1; /**< PP-CP2 Double Bit Error Interrupt Enable bit 3079 When set, an interrupt is posted for any PP-generated 3080 QW Mode read which encounters a double bit error. 3081 Refer to CP2DBE. */ 3082 uint64_t cp2sbina : 1; /**< PP-CP2 Single Bit Error Interrupt Enable bit 3083 When set, an interrupt is posted for any PP-generated 3084 QW Mode read which encounters a single bit error 3085 (which is also corrected). 3086 Refer to CP2SBE. */ 3087 uint64_t cp2dbe : 1; /**< PP-CP2 Double Bit Error Detected - Status bit 3088 When set, a double bit error had been detected 3089 for a PP-generated QW Mode read transaction. 3090 The CP2SYN contains the failing syndrome. 3091 NOTE: PP-generated LW Mode Read transactions 3092 do not participate in ECC check/correct). 3093 Refer to CP2ECCENA. 3094 If the CP2DBINA had previously been enabled(set), 3095 an interrupt will be posted. Software can clear 3096 the interrupt by writing a 1 to this register bit. 3097 See also: DFA_MEMFADR CSR which contains more data 3098 about the memory address/control to help isolate 3099 the failure. */ 3100 uint64_t cp2sbe : 1; /**< PP-CP2 Single Bit Error Corrected - Status bit 3101 When set, a single bit error had been detected and 3102 corrected for a PP-generated QW Mode read 3103 transaction. 3104 If the CP2DBE=0, then the CP2SYN contains the 3105 failing syndrome (used during correction). 3106 Refer to CP2ECCENA. 3107 If the CP2SBINA had previously been enabled(set), 3108 an interrupt will be posted. Software can clear 3109 the interrupt by writing a 1 to this register bit. 3110 See also: DFA_MEMFADR CSR which contains more data 3111 about the memory address/control to help isolate 3112 the failure. 3113 NOTE: PP-generated LW Mode Read transactions 3114 do not participate in ECC check/correct). */ 3115 uint64_t cp2eccena : 1; /**< PP-CP2 QW ECC Enable (for QW Mode transactions) 3116 When set, 8bit QW ECC is enabled on all PP-generated 3117 QW Mode read transactions, CP2SBE and 3118 CP2DBE may be set, and CP2SYN may be filled. 3119 NOTE: This signal must only be written to a different 3120 value when there are no PP-CP2 transactions 3121 (preferrably during power-on software initialization). 3122 NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3123 by a processor core). LW refers to a 36-bit load/store. */ 3124#else 3125 uint64_t cp2eccena : 1; 3126 uint64_t cp2sbe : 1; 3127 uint64_t cp2dbe : 1; 3128 uint64_t cp2sbina : 1; 3129 uint64_t cp2dbina : 1; 3130 uint64_t cp2syn : 8; 3131 uint64_t dteeccena : 1; 3132 uint64_t dtesbe : 1; 3133 uint64_t dtedbe : 1; 3134 uint64_t dtesbina : 1; 3135 uint64_t dtedbina : 1; 3136 uint64_t dtesyn : 7; 3137 uint64_t dteparena : 1; 3138 uint64_t dteperr : 1; 3139 uint64_t dtepina : 1; 3140 uint64_t cp2parena : 1; 3141 uint64_t cp2perr : 1; 3142 uint64_t cp2pina : 1; 3143 uint64_t dblovf : 1; 3144 uint64_t dblina : 1; 3145 uint64_t reserved_33_63 : 31; 3146#endif 3147 } s; 3148 struct cvmx_dfa_err_s cn31xx; 3149 struct cvmx_dfa_err_s cn38xx; 3150 struct cvmx_dfa_err_s cn38xxp2; 3151 struct cvmx_dfa_err_s cn58xx; 3152 struct cvmx_dfa_err_s cn58xxp1; 3153}; 3154typedef union cvmx_dfa_err cvmx_dfa_err_t; 3155 3156/** 3157 * cvmx_dfa_error 3158 * 3159 * DFA_ERROR = DFA ERROR Register 3160 * 3161 * Description: 3162 */ 3163union cvmx_dfa_error { 3164 uint64_t u64; 3165 struct cvmx_dfa_error_s { 3166#ifdef __BIG_ENDIAN_BITFIELD 3167 uint64_t reserved_19_63 : 45; 3168 uint64_t replerr : 1; /**< DFA Illegal Replication Factor Error 3169 For o68: DFA only supports 1x, 2x, and 4x port replication. 3170 Legal configurations for memory are to support 2 port or 3171 4 port configurations. 3172 The REPLERR interrupt will be set in the following illegal 3173 configuration cases: 3174 1) An 8x replication factor is detected for any memory reference. 3175 2) A 4x replication factor is detected for any memory reference 3176 when only 2 memory ports are enabled. 3177 NOTE: If REPLERR is set during a DFA Graph Walk operation, 3178 then the walk will prematurely terminate with RWORD0[REA]=ERR. 3179 If REPLERR is set during a NCB-Direct CSR read access to DFA 3180 Memory REGION, then the CSR read response data is UNPREDICTABLE. */ 3181 uint64_t dfanxm : 1; /**< DFA Non-existent Memory Access 3182 For o68: DTEs (and backdoor CSR DFA Memory REGION reads) 3183 have access to the following 38bit L2/DRAM address space 3184 which maps to a 37bit physical DDR3 SDRAM address space. 3185 see: 3186 DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF 3187 maps to lower 256MB of physical DDR3 SDRAM 3188 DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF 3189 maps to upper 127.75GB of DDR3 SDRAM 3190 L2/DRAM address space Physical DDR3 SDRAM Address space 3191 (38bit address) (37bit address) 3192 +-----------+ 0x0020.0FFF.FFFF 3193 3194 === DR1 === +-----------+ 0x001F.FFFF.FFFF 3195 (128GB-256MB)| | 3196 | | => | | (128GB-256MB) 3197 +-----------+ 0x0000.1FFF.FFFF | DR1 3198 256MB | HOLE | (DO NOT USE) 3199 +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF 3200 256MB | DR0 | | DR0 | (256MB) 3201 +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000 3202 In the event the DFA generates a reference to the L2/DRAM 3203 address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to 3204 an address above 0x0020.0FFF.FFFF, the DFANXM programmable 3205 interrupt bit will be set. 3206 SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR 3207 accesses to DFA Memory REGION MUST avoid making references 3208 to these non-existent memory regions. 3209 NOTE: If DFANXM is set during a DFA Graph Walk operation, 3210 then the walk will prematurely terminate with RWORD0[REA]=ERR. 3211 If DFANXM is set during a NCB-Direct CSR read access to DFA 3212 Memory REGION, then the CSR read response data is forced to 3213 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW 3214 being accessed, either the upper or lower QW will be returned). */ 3215 uint64_t cndrd : 1; /**< If Any of the cluster's detected a Parity error on RAM1 3216 this additional bit further specifies that the 3217 RAM1 parity error was detected during a CND-RD 3218 (Cache Node Metadata Read). 3219 3220 For CNDRD Parity Error, the previous CNA arc fetch 3221 information is written to RWORD1+ as follows: 3222 RWORD1+[NTYPE]=MNODE 3223 RWORD1+[NDNID]=cna.ndnid 3224 RWORD1+[NHMSK]=cna.hmsk 3225 RWORD1+[NNPTR]=cna.nnptr[13:0] 3226 NOTE: This bit is set if ANY node cluster's RAM1 accesses 3227 detect a CNDRD error. */ 3228 uint64_t reserved_15_15 : 1; 3229 uint64_t dlc1_ovferr : 1; /**< DLC1 Fifo Overflow Error Detected 3230 This condition should NEVER architecturally occur, and 3231 is here in case HW credit/debit scheme is not working. */ 3232 uint64_t dlc0_ovferr : 1; /**< DLC0 Fifo Overflow Error Detected 3233 This condition should NEVER architecturally occur, and 3234 is here in case HW credit/debit scheme is not working. */ 3235 uint64_t reserved_10_12 : 3; 3236 uint64_t dc2perr : 3; /**< Cluster#2 RAM[3:1] Parity Error Detected 3237 See also DFA_DTCFADR register which contains the 3238 failing addresses for the internal node cache RAMs. */ 3239 uint64_t dc1perr : 3; /**< Cluster#1 RAM[3:1] Parity Error Detected 3240 See also DFA_DTCFADR register which contains the 3241 failing addresses for the internal node cache RAMs. */ 3242 uint64_t dc0perr : 3; /**< Cluster#0 RAM[3:1] Parity Error Detected 3243 See also DFA_DTCFADR register which contains the 3244 failing addresses for the internal node cache RAMs. */ 3245 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3246 When set, the 20b accumulated doorbell register 3247 had overflowed (SW wrote too many doorbell requests). 3248 If the DBLINA had previously been enabled(set), 3249 an interrupt will be posted. Software can clear 3250 the interrupt by writing a 1 to this register bit. 3251 NOTE: Detection of a Doorbell Register overflow 3252 is a catastrophic error which may leave the DFA 3253 HW in an unrecoverable state. */ 3254#else 3255 uint64_t dblovf : 1; 3256 uint64_t dc0perr : 3; 3257 uint64_t dc1perr : 3; 3258 uint64_t dc2perr : 3; 3259 uint64_t reserved_10_12 : 3; 3260 uint64_t dlc0_ovferr : 1; 3261 uint64_t dlc1_ovferr : 1; 3262 uint64_t reserved_15_15 : 1; 3263 uint64_t cndrd : 1; 3264 uint64_t dfanxm : 1; 3265 uint64_t replerr : 1; 3266 uint64_t reserved_19_63 : 45; 3267#endif 3268 } s; 3269 struct cvmx_dfa_error_cn61xx { 3270#ifdef __BIG_ENDIAN_BITFIELD 3271 uint64_t reserved_19_63 : 45; 3272 uint64_t replerr : 1; /**< DFA Illegal Replication Factor Error 3273 For o68: DFA only supports 1x, 2x, and 4x port replication. 3274 Legal configurations for memory are to support 2 port or 3275 4 port configurations. 3276 The REPLERR interrupt will be set in the following illegal 3277 configuration cases: 3278 1) An 8x replication factor is detected for any memory reference. 3279 2) A 4x replication factor is detected for any memory reference 3280 when only 2 memory ports are enabled. 3281 NOTE: If REPLERR is set during a DFA Graph Walk operation, 3282 then the walk will prematurely terminate with RWORD0[REA]=ERR. 3283 If REPLERR is set during a NCB-Direct CSR read access to DFA 3284 Memory REGION, then the CSR read response data is UNPREDICTABLE. */ 3285 uint64_t dfanxm : 1; /**< DFA Non-existent Memory Access 3286 For o68/o61: DTEs (and backdoor CSR DFA Memory REGION reads) 3287 have access to the following 38bit L2/DRAM address space 3288 which maps to a 37bit physical DDR3 SDRAM address space. 3289 see: 3290 DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF 3291 maps to lower 256MB of physical DDR3 SDRAM 3292 DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF 3293 maps to upper 127.75GB of DDR3 SDRAM 3294 L2/DRAM address space Physical DDR3 SDRAM Address space 3295 (38bit address) (37bit address) 3296 +-----------+ 0x0020.0FFF.FFFF 3297 | 3298 === DR1 === +-----------+ 0x001F.FFFF.FFFF 3299 (128GB-256MB)| | | 3300 | | => | | (128GB-256MB) 3301 +-----------+ 0x0000.1FFF.FFFF | DR1 3302 256MB | HOLE | (DO NOT USE) | 3303 +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF 3304 256MB | DR0 | | DR0 | (256MB) 3305 +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000 3306 In the event the DFA generates a reference to the L2/DRAM 3307 address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to 3308 an address above 0x0020.0FFF.FFFF, the DFANXM programmable 3309 interrupt bit will be set. 3310 SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR 3311 accesses to DFA Memory REGION MUST avoid making references 3312 to these non-existent memory regions. 3313 NOTE: If DFANXM is set during a DFA Graph Walk operation, 3314 then the walk will prematurely terminate with RWORD0[REA]=ERR. 3315 If DFANXM is set during a NCB-Direct CSR read access to DFA 3316 Memory REGION, then the CSR read response data is forced to 3317 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW 3318 being accessed, either the upper or lower QW will be returned). */ 3319 uint64_t cndrd : 1; /**< If any of the cluster's detected a Parity error on RAM1 3320 this additional bit further specifies that the 3321 RAM1 parity error was detected during a CND-RD 3322 (Cache Node Metadata Read). 3323 3324 For CNDRD Parity Error, the previous CNA arc fetch 3325 information is written to RWORD1+ as follows: 3326 RWORD1+[NTYPE]=MNODE 3327 RWORD1+[NDNID]=cna.ndnid 3328 RWORD1+[NHMSK]=cna.hmsk 3329 RWORD1+[NNPTR]=cna.nnptr[13:0] 3330 NOTE: This bit is set if ANY node cluster's RAM1 accesses 3331 detect a CNDRD error. */ 3332 uint64_t reserved_14_15 : 2; 3333 uint64_t dlc0_ovferr : 1; /**< DLC0 Fifo Overflow Error Detected 3334 This condition should NEVER architecturally occur, and 3335 is here in case HW credit/debit scheme is not working. */ 3336 uint64_t reserved_4_12 : 9; 3337 uint64_t dc0perr : 3; /**< Cluster#0 RAM[3:1] Parity Error Detected 3338 See also DFA_DTCFADR register which contains the 3339 failing addresses for the internal node cache RAMs. */ 3340 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3341 When set, the 20b accumulated doorbell register 3342 had overflowed (SW wrote too many doorbell requests). 3343 If the DBLINA had previously been enabled(set), 3344 an interrupt will be posted. Software can clear 3345 the interrupt by writing a 1 to this register bit. 3346 NOTE: Detection of a Doorbell Register overflow 3347 is a catastrophic error which may leave the DFA 3348 HW in an unrecoverable state. */ 3349#else 3350 uint64_t dblovf : 1; 3351 uint64_t dc0perr : 3; 3352 uint64_t reserved_4_12 : 9; 3353 uint64_t dlc0_ovferr : 1; 3354 uint64_t reserved_14_15 : 2; 3355 uint64_t cndrd : 1; 3356 uint64_t dfanxm : 1; 3357 uint64_t replerr : 1; 3358 uint64_t reserved_19_63 : 45; 3359#endif 3360 } cn61xx; 3361 struct cvmx_dfa_error_cn63xx { 3362#ifdef __BIG_ENDIAN_BITFIELD 3363 uint64_t reserved_17_63 : 47; 3364 uint64_t cndrd : 1; /**< If DC0PERR[0]=1 indicating a RAM1 Parity error, 3365 this additional bit further specifies that the 3366 RAM1 parity error was detected during a CND-RD 3367 (Cache Node Metadata Read). 3368 3369 For CNDRD Parity Error, the previous CNA arc fetch 3370 information is written to RWORD1+ as follows: 3371 RWORD1+[NTYPE]=MNODE 3372 RWORD1+[NDNID]=cna.ndnid 3373 RWORD1+[NHMSK]=cna.hmsk 3374 RWORD1+[NNPTR]=cna.nnptr[13:0] */ 3375 uint64_t reserved_4_15 : 12; 3376 uint64_t dc0perr : 3; /**< RAM[3:1] Parity Error Detected from Node Cluster \#0 3377 See also DFA_DTCFADR register which contains the 3378 failing addresses for the internal node cache RAMs. */ 3379 uint64_t dblovf : 1; /**< Doorbell Overflow detected - Status bit 3380 When set, the 20b accumulated doorbell register 3381 had overflowed (SW wrote too many doorbell requests). 3382 If the DBLINA had previously been enabled(set), 3383 an interrupt will be posted. Software can clear 3384 the interrupt by writing a 1 to this register bit. 3385 NOTE: Detection of a Doorbell Register overflow 3386 is a catastrophic error which may leave the DFA 3387 HW in an unrecoverable state. */ 3388#else 3389 uint64_t dblovf : 1; 3390 uint64_t dc0perr : 3; 3391 uint64_t reserved_4_15 : 12; 3392 uint64_t cndrd : 1; 3393 uint64_t reserved_17_63 : 47; 3394#endif 3395 } cn63xx; 3396 struct cvmx_dfa_error_cn63xx cn63xxp1; 3397 struct cvmx_dfa_error_cn63xx cn66xx; 3398 struct cvmx_dfa_error_s cn68xx; 3399 struct cvmx_dfa_error_s cn68xxp1; 3400}; 3401typedef union cvmx_dfa_error cvmx_dfa_error_t; 3402 3403/** 3404 * cvmx_dfa_intmsk 3405 * 3406 * DFA_INTMSK = DFA ERROR Interrupt Mask Register 3407 * 3408 * Description: 3409 */ 3410union cvmx_dfa_intmsk { 3411 uint64_t u64; 3412 struct cvmx_dfa_intmsk_s { 3413#ifdef __BIG_ENDIAN_BITFIELD 3414 uint64_t reserved_19_63 : 45; 3415 uint64_t replerrena : 1; /**< DFA Illegal Replication Factor Interrupt Enable */ 3416 uint64_t dfanxmena : 1; /**< DFA Non-existent Memory Access Interrupt Enable */ 3417 uint64_t reserved_15_16 : 2; 3418 uint64_t dlc1_ovfena : 1; /**< DLC1 Fifo Overflow Error Interrupt Enable */ 3419 uint64_t dlc0_ovfena : 1; /**< DLC0 Fifo Overflow Error Interrupt Enable */ 3420 uint64_t reserved_10_12 : 3; 3421 uint64_t dc2pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#2 */ 3422 uint64_t dc1pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#1 */ 3423 uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3424 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3425 When set, doorbell overflow conditions are reported. */ 3426#else 3427 uint64_t dblina : 1; 3428 uint64_t dc0pena : 3; 3429 uint64_t dc1pena : 3; 3430 uint64_t dc2pena : 3; 3431 uint64_t reserved_10_12 : 3; 3432 uint64_t dlc0_ovfena : 1; 3433 uint64_t dlc1_ovfena : 1; 3434 uint64_t reserved_15_16 : 2; 3435 uint64_t dfanxmena : 1; 3436 uint64_t replerrena : 1; 3437 uint64_t reserved_19_63 : 45; 3438#endif 3439 } s; 3440 struct cvmx_dfa_intmsk_cn61xx { 3441#ifdef __BIG_ENDIAN_BITFIELD 3442 uint64_t reserved_19_63 : 45; 3443 uint64_t replerrena : 1; /**< DFA Illegal Replication Factor Interrupt Enable */ 3444 uint64_t dfanxmena : 1; /**< DFA Non-existent Memory Access Interrupt Enable */ 3445 uint64_t reserved_14_16 : 3; 3446 uint64_t dlc0_ovfena : 1; /**< DLC0 Fifo Overflow Error Interrupt Enable */ 3447 uint64_t reserved_4_12 : 9; 3448 uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3449 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3450 When set, doorbell overflow conditions are reported. */ 3451#else 3452 uint64_t dblina : 1; 3453 uint64_t dc0pena : 3; 3454 uint64_t reserved_4_12 : 9; 3455 uint64_t dlc0_ovfena : 1; 3456 uint64_t reserved_14_16 : 3; 3457 uint64_t dfanxmena : 1; 3458 uint64_t replerrena : 1; 3459 uint64_t reserved_19_63 : 45; 3460#endif 3461 } cn61xx; 3462 struct cvmx_dfa_intmsk_cn63xx { 3463#ifdef __BIG_ENDIAN_BITFIELD 3464 uint64_t reserved_4_63 : 60; 3465 uint64_t dc0pena : 3; /**< RAM[3:1] Parity Error Enabled Node Cluster \#0 */ 3466 uint64_t dblina : 1; /**< Doorbell Overflow Interrupt Enable bit. 3467 When set, doorbell overflow conditions are reported. */ 3468#else 3469 uint64_t dblina : 1; 3470 uint64_t dc0pena : 3; 3471 uint64_t reserved_4_63 : 60; 3472#endif 3473 } cn63xx; 3474 struct cvmx_dfa_intmsk_cn63xx cn63xxp1; 3475 struct cvmx_dfa_intmsk_cn63xx cn66xx; 3476 struct cvmx_dfa_intmsk_s cn68xx; 3477 struct cvmx_dfa_intmsk_s cn68xxp1; 3478}; 3479typedef union cvmx_dfa_intmsk cvmx_dfa_intmsk_t; 3480 3481/** 3482 * cvmx_dfa_memcfg0 3483 * 3484 * DFA_MEMCFG0 = DFA Memory Configuration 3485 * 3486 * Description: 3487 */ 3488union cvmx_dfa_memcfg0 { 3489 uint64_t u64; 3490 struct cvmx_dfa_memcfg0_s { 3491#ifdef __BIG_ENDIAN_BITFIELD 3492 uint64_t reserved_32_63 : 32; 3493 uint64_t rldqck90_rst : 1; /**< RLDCK90 and RLDQK90 DLL SW Reset 3494 When written with a '1' the RLDCK90 and RLDQK90 DLL are 3495 in soft-reset. */ 3496 uint64_t rldck_rst : 1; /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset 3497 When written with a '1' the RLDCK zero delay DLL is in 3498 soft-reset. */ 3499 uint64_t clkdiv : 2; /**< RLDCLK Divisor Select 3500 - 0: RLDx_CK_H/L = Core Clock /2 3501 - 1: RESERVED (must not be used) 3502 - 2: RLDx_CK_H/L = Core Clock /3 3503 - 3: RLDx_CK_H/L = Core Clock /4 3504 The DFA LLM interface(s) are tied to the core clock 3505 frequency through this programmable clock divisor. 3506 Examples: 3507 Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV 3508 -----------------+--------------------+-------- 3509 800 | 400/(800-DDR) | /2 3510 1000 | 333/(666-DDR) | /3 3511 800 | 200/(400-DDR) | /4 3512 NOTE: This value MUST BE programmed BEFORE doing a 3513 Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits). */ 3514 uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 3515 When enabled, PP-core LLM accesses to the lower-512MB 3516 LLM address space are sent to the single DFA port 3517 which is enabled. NOTE: If LPP_ENA=1, only 3518 one DFA RLDRAM port may be enabled for RLDRAM accesses 3519 (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 3520 PP-core LLM accesses to the upper-512MB LLM address 3521 space are sent to the other 'disabled' DFA port. 3522 SW RESTRICTION: If LPP_ENA=1, then only one DFA port 3523 may be enabled for RLDRAM accesses (ie: ENA_P0 and 3524 ENA_P1 CAN NEVER BOTH be set). 3525 NOTE: This bit is used to allow PP-Core LLM accesses to a 3526 disabled port, such that each port can be sequentially 3527 addressed (ie: disable LW address interleaving). 3528 Enabling this bit allows BOTH PORTs to be active and 3529 sequentially addressable. The single port that is 3530 enabled(ENA_Px) will respond to the low-512MB LLM address 3531 space, and the other 'disabled' port will respond to the 3532 high-512MB LLM address space. 3533 Example usage: 3534 - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 3535 - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 3536 USAGE NOTE: 3537 If LPP_ENA=1 and SW DOES NOT initialize the disabled port 3538 (ie: INIT_Px=0->1), then refreshes and the HW init 3539 sequence WILL NOT occur for the disabled port. 3540 If LPP_ENA=1 and SW does initialize the disabled port 3541 (INIT_Px=0->1 with ENA_Px=0), then refreshes and 3542 the HW init sequence WILL occur to the disabled port. */ 3543 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3544 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3545 b) during a normal refresh sequence. If 3546 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3547 NOTE: This is required for DRAM used in a 3548 clamshell configuration, since the address lines 3549 carry Mode Register write data that is unique 3550 per bunk(or clam). In a clamshell configuration, 3551 The N3K A[x] pin may be tied into Clam#0's A[x] 3552 and also into Clam#1's 'mirrored' address bit A[y] 3553 (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3554 To support clamshell designs, SW must initiate 3555 two separate HW init sequences for the two bunks 3556 (or clams) . Before each HW init sequence is triggered, 3557 SW must preload the DFA_MEMRLD[22:0] with the data 3558 that will be driven onto the A[22:0] wires during 3559 an MRS mode register write. 3560 NOTE: After the final HW initialization sequence has 3561 been triggered, SW must wait 64K eclks before writing 3562 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3563 driven during refresh sequences in normal operation. 3564 NOTE: This should only be written to a different value 3565 during power-on SW initialization. */ 3566 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3567 the HW init sequence(s) for Memory Port \#0 is 3568 initiated. 3569 NOTE: To initialize memory, SW must: 3570 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 3571 RLDRAM operation. 3572 [legal values 0: DIV2 2: DIV3 3: DIV4] 3573 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 3574 and DFA_MEM_CFG0[RLDQCK90_RST] field at 3575 the SAME TIME. This step puts all three DLLs in 3576 SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 3577 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 3578 This step takes the RLDCK DLL out of soft-reset so 3579 that the DLL can generate the RLDx_CK_H/L clock pins. 3580 4) Wait 1ms (for RLDCK DLL to achieve lock) 3581 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 3582 This step takes the RLDCK90 DLL AND RLDQK90 DLL out 3583 of soft-reset. 3584 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 3585 7) Enable memory port(s): ENA_P0=1/ENA_P1=1 3586 8) Wait 100us (to ensure a stable clock 3587 to the RLDRAMs) - as per RLDRAM spec. 3588 - - - - - Hardware Initialization Sequence - - - - - 3589 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 3590 intended to be initialized. 3591 10) Write a '1' to the corresponding INIT_Px which 3592 will initiate a hardware initialization 3593 sequence to that'specific' port. 3594 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 3595 [to ensure the HW init sequence has completed 3596 before writing to ANY of the DFA_MEM* registers] 3597 - - - - - Hardware Initialization Sequence - - - - - 3598 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 3599 refreshes to BOTH bunks. 3600 NOTE: In some cases (where the address wires are routed 3601 differently between the front and back 'bunks'), 3602 SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 3603 control the Hardware initialization sequence for a 3604 'specific bunk'. In these cases, SW would setup the 3605 BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 3606 NOTE: This should only be written to a different value 3607 during power-on SW initialization. 3608 NOTE: DFA Memory Port#0 corresponds to the Octeon 3609 RLD0_* pins. */ 3610 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3611 the HW init sequence(s) for Memory Port \#1 is 3612 initiated. 3613 NOTE: To initialize memory, SW must: 3614 1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended 3615 RLDRAM operation. 3616 [legal values 0: DIV2 2: DIV3 3: DIV4] 3617 2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST] 3618 and DFA_MEM_CFG0[RLDQCK90_RST] field at 3619 the SAME TIME. This step puts all three DLLs in 3620 SW reset (RLDCK, RLDCK90, RLDQK90 DLLs). 3621 3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field. 3622 This step takes the RLDCK DLL out of soft-reset so 3623 that the DLL can generate the RLDx_CK_H/L clock pins. 3624 4) Wait 1ms (for RLDCK DLL to achieve lock) 3625 5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field. 3626 This step takes the RLDCK90 DLL AND RLDQK90 DLL out 3627 of soft-reset. 3628 6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock) 3629 7) Enable memory port(s) ENA_P0=1/ENA_P1=1 3630 8) Wait 100us (to ensure a stable clock 3631 to the RLDRAMs) - as per RLDRAM spec. 3632 - - - - - Hardware Initialization Sequence - - - - - 3633 9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s) 3634 intended to be initialized. 3635 10) Write a '1' to the corresponding INIT_Px which 3636 will initiate a hardware initialization 3637 sequence to that'specific' port. 3638 11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles. 3639 [to ensure the HW init sequence has completed 3640 before writing to ANY of the DFA_MEM* registers] 3641 - - - - - Hardware Initialization Sequence - - - - - 3642 12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable 3643 refreshes to BOTH bunks. 3644 NOTE: In some cases (where the address wires are routed 3645 differently between the front and back 'bunks'), 3646 SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to 3647 control the Hardware initialization sequence for a 3648 'specific bunk'. In these cases, SW would setup the 3649 BUNK_INIT and repeat Steps \#9-11 for each bunk/port. 3650 NOTE: This should only be written to a different value 3651 during power-on SW initialization. 3652 NOTE: DFA Memory Port#1 corresponds to the Octeon 3653 RLD1_* pins. */ 3654 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3655 if back to back reads are issued to different physical 3656 bunks. This is to avoid DQ data bus collisions when 3657 references cross between physical bunks. 3658 [NOTE: the physical bunk address boundary is determined 3659 by the PBUNK bit]. 3660 NOTE: This should only be written to a different value 3661 during power-on SW initialization. */ 3662 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3663 Specifies which address bit within the Longword 3664 Memory address MA[23:0] is used to determine the 3665 chip selects. 3666 [RLD_CS0_N corresponds to physical bunk \#0, and 3667 RLD_CS1_N corresponds to physical bunk \#1]. 3668 - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3669 - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3670 - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3671 - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3672 - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3673 - 101-111: CS0_N = 0 /CS1_N = 1 3674 Example(s): 3675 To build out a 128MB DFA memory, 4x 32Mx9 3676 parts could be used to fill out TWO physical 3677 bunks (clamshell configuration). Each (of the 3678 two) physical bunks contains 2x 32Mx9 = 16Mx36. 3679 Each RLDRAM device also contains 8 internal banks, 3680 therefore the memory Address is 16M/8banks = 2M 3681 addresses/bunk (2^21). In this case, MA[21] would 3682 select the physical bunk. 3683 NOTE: This should only be written to a different value 3684 during power-on SW initialization. 3685 be used to determine the Chip Select(s). */ 3686 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3687 NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */ 3688 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3689 On reads, allows user to control the shape of the 3690 tristate disable back porch for the DQ data bus. 3691 This parameter is also very dependent on the 3692 RW_DLY and WR_DLY parameters and care must be 3693 taken when programming these parameters to avoid 3694 data bus contention. Valid range [0..2] 3695 NOTE: This should only be written to a different value 3696 during power-on SW initialization. */ 3697 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3698 On reads, allows user to control the shape of the 3699 tristate disable front porch for the DQ data bus. 3700 This parameter is also very dependent on the 3701 RW_DLY and WR_DLY parameters and care must be 3702 taken when programming these parameters to avoid 3703 data bus contention. Valid range [0..2] 3704 NOTE: This should only be written to a different value 3705 during power-on SW initialization. */ 3706 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3707 Determines \#mclk cycles to insert when controller 3708 switches from write to read. This allows programmer 3709 to control the data bus contention. 3710 For RLDRAM-II(BL2): (TBL=1) 3711 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3712 NOTE: This should only be written to a different value 3713 during power-on SW initialization. 3714 NOTE: For aggressive(performance optimal) designs, 3715 the WR_DLY 'may' be tuned down(-1) if bus fight 3716 on W->R transitions is not pronounced. */ 3717 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3718 Determines \#mclk cycles to insert when controller 3719 switches from read to write. This allows programmer 3720 to control the data bus contention. 3721 For RLDRAM-II(BL2): (TBL=1) 3722 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3723 NOTE: This should only be written to a different value 3724 during power-on SW initialization. 3725 NOTE: For aggressive(performance optimal) designs, 3726 the RW_DLY 'may' be tuned down(-1) if bus fight 3727 on R->W transitions is not pronounced. */ 3728 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3729 additional dclks to wait (on top of tRL+1) before 3730 pulling data out of the padring silos used for time 3731 domain boundary crossing. 3732 NOTE: This should only be written to a different value 3733 during power-on SW initialization. */ 3734 uint64_t mtype : 1; /**< FCRAM-II Memory Type 3735 *** CN58XX UNSUPPORTED *** */ 3736 uint64_t reserved_2_2 : 1; 3737 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 3738 When enabled, this bit lets N3K be the default 3739 driver for memory port \#0. 3740 NOTE: a customer is at 3741 liberty to enable either Port#0 or Port#1 or both. 3742 NOTE: Once a port has been disabled, it MUST NEVER 3743 be re-enabled. [the only way to enable a port is 3744 through a chip reset]. 3745 NOTE: DFA Memory Port#0 corresponds to the Octeon 3746 RLD0_* pins. */ 3747 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 3748 When enabled, this bit lets N3K be the default 3749 driver for memory port \#1. 3750 NOTE: a customer is at 3751 liberty to enable either Port#0 or Port#1 or both. 3752 NOTE: Once a port has been disabled, it MUST NEVER 3753 be re-enabled. [the only way to enable a port is 3754 through a chip reset]. 3755 NOTE: DFA Memory Port#1 corresponds to the Octeon 3756 RLD1_* pins. */ 3757#else 3758 uint64_t ena_p1 : 1; 3759 uint64_t ena_p0 : 1; 3760 uint64_t reserved_2_2 : 1; 3761 uint64_t mtype : 1; 3762 uint64_t sil_lat : 2; 3763 uint64_t rw_dly : 4; 3764 uint64_t wr_dly : 4; 3765 uint64_t fprch : 2; 3766 uint64_t bprch : 2; 3767 uint64_t blen : 1; 3768 uint64_t pbunk : 3; 3769 uint64_t r2r_pbunk : 1; 3770 uint64_t init_p1 : 1; 3771 uint64_t init_p0 : 1; 3772 uint64_t bunk_init : 2; 3773 uint64_t lpp_ena : 1; 3774 uint64_t clkdiv : 2; 3775 uint64_t rldck_rst : 1; 3776 uint64_t rldqck90_rst : 1; 3777 uint64_t reserved_32_63 : 32; 3778#endif 3779 } s; 3780 struct cvmx_dfa_memcfg0_cn38xx { 3781#ifdef __BIG_ENDIAN_BITFIELD 3782 uint64_t reserved_28_63 : 36; 3783 uint64_t lpp_ena : 1; /**< PP Linear Port Addressing Mode Enable 3784 When enabled, PP-core LLM accesses to the lower-512MB 3785 LLM address space are sent to the single DFA port 3786 which is enabled. NOTE: If LPP_ENA=1, only 3787 one DFA RLDRAM port may be enabled for RLDRAM accesses 3788 (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set). 3789 PP-core LLM accesses to the upper-512MB LLM address 3790 space are sent to the other 'disabled' DFA port. 3791 SW RESTRICTION: If LPP_ENA=1, then only one DFA port 3792 may be enabled for RLDRAM accesses (ie: ENA_P0 and 3793 ENA_P1 CAN NEVER BOTH be set). 3794 NOTE: This bit is used to allow PP-Core LLM accesses to a 3795 disabled port, such that each port can be sequentially 3796 addressed (ie: disable LW address interleaving). 3797 Enabling this bit allows BOTH PORTs to be active and 3798 sequentially addressable. The single port that is 3799 enabled(ENA_Px) will respond to the low-512MB LLM address 3800 space, and the other 'disabled' port will respond to the 3801 high-512MB LLM address space. 3802 Example usage: 3803 - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses) 3804 - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses). 3805 USAGE NOTE: 3806 If LPP_ENA=1 and SW DOES NOT initialize the disabled port 3807 (ie: INIT_Px=0->1), then refreshes and the HW init 3808 sequence WILL NOT occur for the disabled port. 3809 If LPP_ENA=1 and SW does initialize the disabled port 3810 (INIT_Px=0->1 with ENA_Px=0), then refreshes and 3811 the HW init sequence WILL occur to the disabled port. */ 3812 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 3813 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 3814 b) during a normal refresh sequence. If 3815 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 3816 NOTE: This is required for DRAM used in a 3817 clamshell configuration, since the address lines 3818 carry Mode Register write data that is unique 3819 per bunk(or clam). In a clamshell configuration, 3820 The N3K A[x] pin may be tied into Clam#0's A[x] 3821 and also into Clam#1's 'mirrored' address bit A[y] 3822 (eg: Clam0 sees A[5] and Clam1 sees A[15]). 3823 To support clamshell designs, SW must initiate 3824 two separate HW init sequences for the two bunks 3825 (or clams) . Before each HW init sequence is triggered, 3826 SW must preload the DFA_MEMRLD[22:0] with the data 3827 that will be driven onto the A[22:0] wires during 3828 an MRS mode register write. 3829 NOTE: After the final HW initialization sequence has 3830 been triggered, SW must wait 64K eclks before writing 3831 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 3832 driven during refresh sequences in normal operation. 3833 NOTE: This should only be written to a different value 3834 during power-on SW initialization. 3835 NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 3836 initialized independently. In other words, a HW init 3837 must be done for Bunk#0, and then another HW init 3838 must be done for Bunk#1 at power-on. */ 3839 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 3840 the HW init sequence(s) for Memory Port \#0 is 3841 initiated. 3842 NOTE: To initialize memory, SW must: 3843 1) Enable memory port(s): 3844 a) ENA_P1=1 (single port in pass 1) OR 3845 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3846 2) Wait 100us (to ensure a stable clock 3847 to the RLDRAMs) - as per RLDRAM spec. 3848 3) Write a '1' to the corresponding INIT_Px which 3849 will initiate a hardware initialization 3850 sequence. 3851 NOTE: After writing a '1', SW must wait 64K eclk 3852 cycles to ensure the HW init sequence has completed 3853 before writing to ANY of the DFA_MEM* registers. 3854 NOTE: This should only be written to a different value 3855 during power-on SW initialization. 3856 NOTE: DFA Memory Port#0 corresponds to the Octeon 3857 RLD0_* pins. */ 3858 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 3859 the HW init sequence(s) for Memory Port \#1 is 3860 initiated. 3861 NOTE: To initialize memory, SW must: 3862 1) Enable memory port(s): 3863 a) ENA_P1=1 (single port in pass 1) OR 3864 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 3865 2) Wait 100us (to ensure a stable clock 3866 to the RLDRAMs) - as per RLDRAM spec. 3867 3) Write a '1' to the corresponding INIT_Px which 3868 will initiate a hardware initialization 3869 sequence. 3870 NOTE: After writing a '1', SW must wait 64K eclk 3871 cycles to ensure the HW init sequence has completed 3872 before writing to ANY of the DFA_MEM* registers. 3873 NOTE: This should only be written to a different value 3874 during power-on SW initialization. 3875 NOTE: DFA Memory Port#1 corresponds to the Octeon 3876 RLD1_* pins. */ 3877 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 3878 if back to back reads are issued to different physical 3879 bunks. This is to avoid DQ data bus collisions when 3880 references cross between physical bunks. 3881 [NOTE: the physical bunk address boundary is determined 3882 by the PBUNK bit]. 3883 NOTE: This should only be written to a different value 3884 during power-on SW initialization. 3885 When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 3886 ZERO(for optimal performance). However, if electrically, 3887 DQ-sharing becomes a power/heat issue, then R2R_PBUNK 3888 should be set (but at a cost to performance (1/2 BW). */ 3889 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 3890 Specifies which address bit within the Longword 3891 Memory address MA[23:0] is used to determine the 3892 chip selects. 3893 [RLD_CS0_N corresponds to physical bunk \#0, and 3894 RLD_CS1_N corresponds to physical bunk \#1]. 3895 - 000: CS0_N = MA[19]/CS1_N = !MA[19] 3896 - 001: CS0_N = MA[20]/CS1_N = !MA[20] 3897 - 010: CS0_N = MA[21]/CS1_N = !MA[21] 3898 - 011: CS0_N = MA[22]/CS1_N = !MA[22] 3899 - 100: CS0_N = MA[23]/CS1_N = !MA[23] 3900 - 101-111: CS0_N = 0 /CS1_N = 1 3901 Example(s): 3902 To build out a 128MB DFA memory, 4x 32Mx9 3903 parts could be used to fill out TWO physical 3904 bunks (clamshell configuration). Each (of the 3905 two) physical bunks contains 2x 32Mx9 = 16Mx36. 3906 Each RLDRAM device also contains 8 internal banks, 3907 therefore the memory Address is 16M/8banks = 2M 3908 addresses/bunk (2^21). In this case, MA[21] would 3909 select the physical bunk. 3910 NOTE: This should only be written to a different value 3911 during power-on SW initialization. 3912 be used to determine the Chip Select(s). 3913 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 3914 "Redundant Bunk" scheme is employed to provide the 3915 highest overall performance (1 Req/ MCLK cycle). 3916 In this mode, it's imperative that SW set the PBUNK 3917 field +1 'above' the highest address bit. (such that 3918 the PBUNK extracted from the address will always be 3919 zero). In this mode, the CS_N[1:0] pins are driven 3920 to each redundant bunk based on a TDM scheme: 3921 [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 3922 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 3923 When BLEN=0(BL2), all QW reads/writes from CP2 are 3924 decomposed into 2 separate BL2(LW) requests to the 3925 Low-Latency memory. 3926 When BLEN=1(BL4), a LW request (from CP2 or NCB) is 3927 treated as 1 BL4(QW) request to the low latency memory. 3928 NOTE: QW refers to a 64-bit LLM Load/Store (intiated 3929 by a processor core). LW refers to a 36-bit load/store. 3930 NOTE: This should only be written to a different value 3931 during power-on SW initialization before the DFA LLM 3932 (low latency memory) is used. 3933 NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 3934 NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 3935 multi-bunk(clam) board design. 3936 NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 3937 SW SHOULD use CP2 QW read/write requests (for 3938 optimal low-latency bus performance). 3939 [LW length read/write requests(in BL4 mode) use 50% 3940 of the available bus bandwidth] 3941 NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 3942 be used with FCRAM-II devices which support BL2 mode 3943 (see: Toshiba FCRAM-II, where DQ tristate after 2 data 3944 transfers). 3945 NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 3946 write requests (FCRAM-II+ device specification has removed 3947 the variable write mask function from the devices). 3948 As such, if this mode is used, SW must be careful to 3949 issue only PP-CP2 QW write requests. */ 3950 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 3951 On reads, allows user to control the shape of the 3952 tristate disable back porch for the DQ data bus. 3953 This parameter is also very dependent on the 3954 RW_DLY and WR_DLY parameters and care must be 3955 taken when programming these parameters to avoid 3956 data bus contention. Valid range [0..2] 3957 NOTE: This should only be written to a different value 3958 during power-on SW initialization. */ 3959 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 3960 On reads, allows user to control the shape of the 3961 tristate disable front porch for the DQ data bus. 3962 This parameter is also very dependent on the 3963 RW_DLY and WR_DLY parameters and care must be 3964 taken when programming these parameters to avoid 3965 data bus contention. Valid range [0..2] 3966 NOTE: This should only be written to a different value 3967 during power-on SW initialization. */ 3968 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 3969 Determines \#mclk cycles to insert when controller 3970 switches from write to read. This allows programmer 3971 to control the data bus contention. 3972 For RLDRAM-II(BL2): (TBL=1) 3973 For FCRAM-II (BL4): (TBL=2) 3974 For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 3975 For FCRAM-II (BL2 grepl>=2x): (TBL=3) 3976 NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 3977 grepl>=2x, writes require redundant bunk writes 3978 which require an additional 2 cycles before slotting 3979 the next read. 3980 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 3981 NOTE: This should only be written to a different value 3982 during power-on SW initialization. 3983 NOTE: For aggressive(performance optimal) designs, 3984 the WR_DLY 'may' be tuned down(-1) if bus fight 3985 on W->R transitions is not pronounced. */ 3986 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 3987 Determines \#mclk cycles to insert when controller 3988 switches from read to write. This allows programmer 3989 to control the data bus contention. 3990 For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 3991 For FCRAM-II (BL4): (TBL=2) 3992 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 3993 NOTE: This should only be written to a different value 3994 during power-on SW initialization. 3995 NOTE: For aggressive(performance optimal) designs, 3996 the RW_DLY 'may' be tuned down(-1) if bus fight 3997 on R->W transitions is not pronounced. */ 3998 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 3999 additional dclks to wait (on top of tRL+1) before 4000 pulling data out of the padring silos used for time 4001 domain boundary crossing. 4002 NOTE: This should only be written to a different value 4003 during power-on SW initialization. */ 4004 uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 4005 NOTE: N3K-P1 only supports RLDRAM-II 4006 NOTE: This should only be written to a different value 4007 during power-on SW initialization. 4008 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 4009 "unidirectional DS/QS" mode is supported. (see FCRAM 4010 data sheet EMRS[A6:A5]=SS(Strobe Select) register 4011 definition. [in FCRAM 2-burst mode, we use FCRAM 4012 in a clamshell configuration such that clam0 is 4013 addressed independently of clam1, and DQ is shared 4014 for optimal performance. As such it's imperative that 4015 the QS are conditionally received (and are NOT 4016 free-running), as the N3K receive data capture silos 4017 OR the clam0/1 QS strobes. 4018 NOTE: If this bit is SET, the ASX0/1 4019 ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 4020 in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 4021 uint64_t reserved_2_2 : 1; 4022 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 4023 When enabled, this bit lets N3K be the default 4024 driver for memory port \#0. 4025 NOTE: For N3K-P1, to enable Port#0(2nd port), 4026 Port#1 MUST ALSO be enabled. 4027 NOTE: For N3K-P2, single port mode, a customer is at 4028 liberty to enable either Port#0 or Port#1. 4029 NOTE: Once a port has been disabled, it MUST NEVER 4030 be re-enabled. [the only way to enable a port is 4031 through a chip reset]. 4032 NOTE: DFA Memory Port#0 corresponds to the Octeon 4033 RLD0_* pins. */ 4034 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 4035 When enabled, this bit lets N3K be the default 4036 driver for memory port \#1. 4037 NOTE: For N3K-P1, If the customer wishes to use a 4038 single port, s/he must enable Port#1 (and not Port#0). 4039 NOTE: For N3K-P2, single port mode, a customer is at 4040 liberty to enable either Port#0 or Port#1. 4041 NOTE: Once a port has been disabled, it MUST NEVER 4042 be re-enabled. [the only way to enable a port is 4043 through a chip reset]. 4044 NOTE: DFA Memory Port#1 corresponds to the Octeon 4045 RLD1_* pins. */ 4046#else 4047 uint64_t ena_p1 : 1; 4048 uint64_t ena_p0 : 1; 4049 uint64_t reserved_2_2 : 1; 4050 uint64_t mtype : 1; 4051 uint64_t sil_lat : 2; 4052 uint64_t rw_dly : 4; 4053 uint64_t wr_dly : 4; 4054 uint64_t fprch : 2; 4055 uint64_t bprch : 2; 4056 uint64_t blen : 1; 4057 uint64_t pbunk : 3; 4058 uint64_t r2r_pbunk : 1; 4059 uint64_t init_p1 : 1; 4060 uint64_t init_p0 : 1; 4061 uint64_t bunk_init : 2; 4062 uint64_t lpp_ena : 1; 4063 uint64_t reserved_28_63 : 36; 4064#endif 4065 } cn38xx; 4066 struct cvmx_dfa_memcfg0_cn38xxp2 { 4067#ifdef __BIG_ENDIAN_BITFIELD 4068 uint64_t reserved_27_63 : 37; 4069 uint64_t bunk_init : 2; /**< Controls the CS_N[1:0] during a) a HW Initialization 4070 sequence (triggered by DFA_MEMCFG0[INIT_Px]) or 4071 b) during a normal refresh sequence. If 4072 the BNK_INIT[x]=1, the corresponding CS_N[x] is driven. 4073 NOTE: This is required for DRAM used in a 4074 clamshell configuration, since the address lines 4075 carry Mode Register write data that is unique 4076 per bunk(or clam). In a clamshell configuration, 4077 The N3K A[x] pin may be tied into Clam#0's A[x] 4078 and also into Clam#1's 'mirrored' address bit A[y] 4079 (eg: Clam0 sees A[5] and Clam1 sees A[15]). 4080 To support clamshell designs, SW must initiate 4081 two separate HW init sequences for the two bunks 4082 (or clams) . Before each HW init sequence is triggered, 4083 SW must preload the DFA_MEMRLD[22:0] with the data 4084 that will be driven onto the A[22:0] wires during 4085 an MRS mode register write. 4086 NOTE: After the final HW initialization sequence has 4087 been triggered, SW must wait 64K eclks before writing 4088 the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is 4089 driven during refresh sequences in normal operation. 4090 NOTE: This should only be written to a different value 4091 during power-on SW initialization. 4092 NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE 4093 initialized independently. In other words, a HW init 4094 must be done for Bunk#0, and then another HW init 4095 must be done for Bunk#1 at power-on. */ 4096 uint64_t init_p0 : 1; /**< When a '1' is written (and the previous value was '0'), 4097 the HW init sequence(s) for Memory Port \#0 is 4098 initiated. 4099 NOTE: To initialize memory, SW must: 4100 1) Enable memory port(s): 4101 a) ENA_P1=1 (single port in pass 1) OR 4102 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 4103 2) Wait 100us (to ensure a stable clock 4104 to the RLDRAMs) - as per RLDRAM spec. 4105 3) Write a '1' to the corresponding INIT_Px which 4106 will initiate a hardware initialization 4107 sequence. 4108 NOTE: After writing a '1', SW must wait 64K eclk 4109 cycles to ensure the HW init sequence has completed 4110 before writing to ANY of the DFA_MEM* registers. 4111 NOTE: This should only be written to a different value 4112 during power-on SW initialization. 4113 NOTE: DFA Memory Port#0 corresponds to the Octeon 4114 RLD0_* pins. */ 4115 uint64_t init_p1 : 1; /**< When a '1' is written (and the previous value was '0'), 4116 the HW init sequence(s) for Memory Port \#1 is 4117 initiated. 4118 NOTE: To initialize memory, SW must: 4119 1) Enable memory port(s): 4120 a) ENA_P1=1 (single port in pass 1) OR 4121 b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1) 4122 2) Wait 100us (to ensure a stable clock 4123 to the RLDRAMs) - as per RLDRAM spec. 4124 3) Write a '1' to the corresponding INIT_Px which 4125 will initiate a hardware initialization 4126 sequence. 4127 NOTE: After writing a '1', SW must wait 64K eclk 4128 cycles to ensure the HW init sequence has completed 4129 before writing to ANY of the DFA_MEM* registers. 4130 NOTE: This should only be written to a different value 4131 during power-on SW initialization. 4132 NOTE: DFA Memory Port#1 corresponds to the Octeon 4133 RLD1_* pins. */ 4134 uint64_t r2r_pbunk : 1; /**< When enabled, an additional command bubble is inserted 4135 if back to back reads are issued to different physical 4136 bunks. This is to avoid DQ data bus collisions when 4137 references cross between physical bunks. 4138 [NOTE: the physical bunk address boundary is determined 4139 by the PBUNK bit]. 4140 NOTE: This should only be written to a different value 4141 during power-on SW initialization. 4142 When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE 4143 ZERO(for optimal performance). However, if electrically, 4144 DQ-sharing becomes a power/heat issue, then R2R_PBUNK 4145 should be set (but at a cost to performance (1/2 BW). */ 4146 uint64_t pbunk : 3; /**< Physical Bunk address bit pointer. 4147 Specifies which address bit within the Longword 4148 Memory address MA[23:0] is used to determine the 4149 chip selects. 4150 [RLD_CS0_N corresponds to physical bunk \#0, and 4151 RLD_CS1_N corresponds to physical bunk \#1]. 4152 - 000: CS0_N = MA[19]/CS1_N = !MA[19] 4153 - 001: CS0_N = MA[20]/CS1_N = !MA[20] 4154 - 010: CS0_N = MA[21]/CS1_N = !MA[21] 4155 - 011: CS0_N = MA[22]/CS1_N = !MA[22] 4156 - 100: CS0_N = MA[23]/CS1_N = !MA[23] 4157 - 101-111: CS0_N = 0 /CS1_N = 1 4158 Example(s): 4159 To build out a 128MB DFA memory, 4x 32Mx9 4160 parts could be used to fill out TWO physical 4161 bunks (clamshell configuration). Each (of the 4162 two) physical bunks contains 2x 32Mx9 = 16Mx36. 4163 Each RLDRAM device also contains 8 internal banks, 4164 therefore the memory Address is 16M/8banks = 2M 4165 addresses/bunk (2^21). In this case, MA[21] would 4166 select the physical bunk. 4167 NOTE: This should only be written to a different value 4168 during power-on SW initialization. 4169 be used to determine the Chip Select(s). 4170 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a 4171 "Redundant Bunk" scheme is employed to provide the 4172 highest overall performance (1 Req/ MCLK cycle). 4173 In this mode, it's imperative that SW set the PBUNK 4174 field +1 'above' the highest address bit. (such that 4175 the PBUNK extracted from the address will always be 4176 zero). In this mode, the CS_N[1:0] pins are driven 4177 to each redundant bunk based on a TDM scheme: 4178 [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */ 4179 uint64_t blen : 1; /**< Device Burst Length (0=2-burst/1=4-burst) 4180 When BLEN=0(BL2), all QW reads/writes from CP2 are 4181 decomposed into 2 separate BL2(LW) requests to the 4182 Low-Latency memory. 4183 When BLEN=1(BL4), a LW request (from CP2 or NCB) is 4184 treated as 1 BL4(QW) request to the low latency memory. 4185 NOTE: QW refers to a 64-bit LLM Load/Store (intiated 4186 by a processor core). LW refers to a 36-bit load/store. 4187 NOTE: This should only be written to a different value 4188 during power-on SW initialization before the DFA LLM 4189 (low latency memory) is used. 4190 NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst) 4191 NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a 4192 multi-bunk(clam) board design. 4193 NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4), 4194 SW SHOULD use CP2 QW read/write requests (for 4195 optimal low-latency bus performance). 4196 [LW length read/write requests(in BL4 mode) use 50% 4197 of the available bus bandwidth] 4198 NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only 4199 be used with FCRAM-II devices which support BL2 mode 4200 (see: Toshiba FCRAM-II, where DQ tristate after 2 data 4201 transfers). 4202 NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW 4203 write requests (FCRAM-II+ device specification has removed 4204 the variable write mask function from the devices). 4205 As such, if this mode is used, SW must be careful to 4206 issue only PP-CP2 QW write requests. */ 4207 uint64_t bprch : 2; /**< Tristate Enable (back porch) (\#dclks) 4208 On reads, allows user to control the shape of the 4209 tristate disable back porch for the DQ data bus. 4210 This parameter is also very dependent on the 4211 RW_DLY and WR_DLY parameters and care must be 4212 taken when programming these parameters to avoid 4213 data bus contention. Valid range [0..2] 4214 NOTE: This should only be written to a different value 4215 during power-on SW initialization. */ 4216 uint64_t fprch : 2; /**< Tristate Enable (front porch) (\#dclks) 4217 On reads, allows user to control the shape of the 4218 tristate disable front porch for the DQ data bus. 4219 This parameter is also very dependent on the 4220 RW_DLY and WR_DLY parameters and care must be 4221 taken when programming these parameters to avoid 4222 data bus contention. Valid range [0..2] 4223 NOTE: This should only be written to a different value 4224 during power-on SW initialization. */ 4225 uint64_t wr_dly : 4; /**< Write->Read CMD Delay (\#mclks): 4226 Determines \#mclk cycles to insert when controller 4227 switches from write to read. This allows programmer 4228 to control the data bus contention. 4229 For RLDRAM-II(BL2): (TBL=1) 4230 For FCRAM-II (BL4): (TBL=2) 4231 For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1) 4232 For FCRAM-II (BL2 grepl>=2x): (TBL=3) 4233 NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode), 4234 grepl>=2x, writes require redundant bunk writes 4235 which require an additional 2 cycles before slotting 4236 the next read. 4237 WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1 4238 NOTE: This should only be written to a different value 4239 during power-on SW initialization. 4240 NOTE: For aggressive(performance optimal) designs, 4241 the WR_DLY 'may' be tuned down(-1) if bus fight 4242 on W->R transitions is not pronounced. */ 4243 uint64_t rw_dly : 4; /**< Read->Write CMD Delay (\#mclks): 4244 Determines \#mclk cycles to insert when controller 4245 switches from read to write. This allows programmer 4246 to control the data bus contention. 4247 For RLDRAM-II/FCRAM-II (BL2): (TBL=1) 4248 For FCRAM-II (BL4): (TBL=2) 4249 RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1 4250 NOTE: This should only be written to a different value 4251 during power-on SW initialization. 4252 NOTE: For aggressive(performance optimal) designs, 4253 the RW_DLY 'may' be tuned down(-1) if bus fight 4254 on R->W transitions is not pronounced. */ 4255 uint64_t sil_lat : 2; /**< Silo Latency (\#dclks): On reads, determines how many 4256 additional dclks to wait (on top of tRL+1) before 4257 pulling data out of the padring silos used for time 4258 domain boundary crossing. 4259 NOTE: This should only be written to a different value 4260 during power-on SW initialization. */ 4261 uint64_t mtype : 1; /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM) 4262 NOTE: N3K-P1 only supports RLDRAM-II 4263 NOTE: This should only be written to a different value 4264 during power-on SW initialization. 4265 NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the 4266 "unidirectional DS/QS" mode is supported. (see FCRAM 4267 data sheet EMRS[A6:A5]=SS(Strobe Select) register 4268 definition. [in FCRAM 2-burst mode, we use FCRAM 4269 in a clamshell configuration such that clam0 is 4270 addressed independently of clam1, and DQ is shared 4271 for optimal performance. As such it's imperative that 4272 the QS are conditionally received (and are NOT 4273 free-running), as the N3K receive data capture silos 4274 OR the clam0/1 QS strobes. 4275 NOTE: If this bit is SET, the ASX0/1 4276 ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET 4277 in order for the RLD0/1-PHY(s) to support FCRAM devices. */ 4278 uint64_t reserved_2_2 : 1; 4279 uint64_t ena_p0 : 1; /**< Enable DFA RLDRAM Port#0 4280 When enabled, this bit lets N3K be the default 4281 driver for memory port \#0. 4282 NOTE: For N3K-P1, to enable Port#0(2nd port), 4283 Port#1 MUST ALSO be enabled. 4284 NOTE: For N3K-P2, single port mode, a customer is at 4285 liberty to enable either Port#0 or Port#1. 4286 NOTE: Once a port has been disabled, it MUST NEVER 4287 be re-enabled. [the only way to enable a port is 4288 through a chip reset]. 4289 NOTE: DFA Memory Port#0 corresponds to the Octeon 4290 RLD0_* pins. */ 4291 uint64_t ena_p1 : 1; /**< Enable DFA RLDRAM Port#1 4292 When enabled, this bit lets N3K be the default 4293 driver for memory port \#1. 4294 NOTE: For N3K-P1, If the customer wishes to use a 4295 single port, s/he must enable Port#1 (and not Port#0). 4296 NOTE: For N3K-P2, single port mode, a customer is at 4297 liberty to enable either Port#0 or Port#1. 4298 NOTE: Once a port has been disabled, it MUST NEVER 4299 be re-enabled. [the only way to enable a port is 4300 through a chip reset]. 4301 NOTE: DFA Memory Port#1 corresponds to the Octeon 4302 RLD1_* pins. */ 4303#else 4304 uint64_t ena_p1 : 1; 4305 uint64_t ena_p0 : 1; 4306 uint64_t reserved_2_2 : 1; 4307 uint64_t mtype : 1; 4308 uint64_t sil_lat : 2; 4309 uint64_t rw_dly : 4; 4310 uint64_t wr_dly : 4; 4311 uint64_t fprch : 2; 4312 uint64_t bprch : 2; 4313 uint64_t blen : 1; 4314 uint64_t pbunk : 3; 4315 uint64_t r2r_pbunk : 1; 4316 uint64_t init_p1 : 1; 4317 uint64_t init_p0 : 1; 4318 uint64_t bunk_init : 2; 4319 uint64_t reserved_27_63 : 37; 4320#endif 4321 } cn38xxp2; 4322 struct cvmx_dfa_memcfg0_s cn58xx; 4323 struct cvmx_dfa_memcfg0_s cn58xxp1; 4324}; 4325typedef union cvmx_dfa_memcfg0 cvmx_dfa_memcfg0_t; 4326 4327/** 4328 * cvmx_dfa_memcfg1 4329 * 4330 * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration 4331 * 4332 * Description: 4333 */ 4334union cvmx_dfa_memcfg1 { 4335 uint64_t u64; 4336 struct cvmx_dfa_memcfg1_s { 4337#ifdef __BIG_ENDIAN_BITFIELD 4338 uint64_t reserved_34_63 : 30; 4339 uint64_t ref_intlo : 9; /**< Burst Refresh Interval[8:0] (\#dclks) 4340 For finer refresh interval granularity control. 4341 This field provides an additional level of granularity 4342 for the refresh interval. It specifies the additional 4343 \#dclks [0...511] to be added to the REF_INT[3:0] field. 4344 For RLDRAM-II: For dclk(400MHz=2.5ns): 4345 Example: 64K AREF cycles required within tREF=32ms 4346 trefint = tREF(ms)/(64K cycles/8banks) 4347 = 32ms/8K = 3.9us = 3900ns 4348 REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512] 4349 = ROUND_DOWN[(3900/2.5)/512] 4350 = 3 4351 REF_INTLO[8:0] = MOD[(trefint/dclk)/512] 4352 = MOD[(3900/2.5)/512] 4353 = 24 4354 NOTE: This should only be written to a different value 4355 during power-on SW initialization. */ 4356 uint64_t aref_ena : 1; /**< Auto Refresh Cycle Enable 4357 INTERNAL USE ONLY: 4358 NOTE: This mode bit is ONLY intended to be used by 4359 low-level power-on initialization routines in the 4360 event that the hardware initialization routine 4361 does not work. It allows SW to create AREF 4362 commands on the RLDRAM bus directly. 4363 When this bit is set, ALL RLDRAM writes (issued by 4364 a PP through the NCB or CP2) are converted to AREF 4365 commands on the RLDRAM bus. The write-address is 4366 presented on the A[20:0]/BA[2:0] pins (for which 4367 the RLDRAM only interprets BA[2:0]). 4368 When this bit is set, only writes are allowed 4369 and MUST use grepl=0 (1x). 4370 NOTE: This should only be written to a different value 4371 during power-on SW initialization. 4372 NOTE: MRS_ENA and AREF_ENA are mutually exclusive 4373 (SW can set one or the other, but never both!) 4374 NOTE: AREF commands generated using this method target 4375 the 'addressed' bunk. */ 4376 uint64_t mrs_ena : 1; /**< Mode Register Set Cycle Enable 4377 INTERNAL USE ONLY: 4378 NOTE: This mode bit is ONLY intended to be used by 4379 low-level power-on initialization routines in the 4380 event that the hardware initialization routine 4381 does not work. It allows SW to create MRS 4382 commands on the RLDRAM bus directly. 4383 When this bit is set, ALL RLDRAM writes (issued by 4384 a PP through the NCB or CP2) are converted to MRS 4385 commands on the RLDRAM bus. The write-address is 4386 presented on the A[20:0]/BA[2:0] pins (for which 4387 the RLDRAM only interprets A[17:0]). 4388 When this bit is set, only writes are allowed 4389 and MUST use grepl=0 (1x). 4390 NOTE: This should only be written to a different value 4391 during power-on SW initialization. 4392 NOTE: MRS_ENA and AREF_ENA are mutually exclusive 4393 (SW can set one or the other, but never both!) 4394 NOTE: MRS commands generated using this method target 4395 the 'addressed' bunk. */ 4396 uint64_t tmrsc : 3; /**< Mode Register Set Cycle Time (represented in \#mclks) 4397 - 000-001: RESERVED 4398 - 010: tMRSC = 2 mclks 4399 - 011: tMRSC = 3 mclks 4400 - ... 4401 - 111: tMRSC = 7 mclks 4402 NOTE: The device tMRSC parameter is a function of CL 4403 (which during HW initialization is not known. Its 4404 recommended to load tMRSC(MAX) value to avoid timing 4405 violations. 4406 NOTE: This should only be written to a different value 4407 during power-on SW initialization. */ 4408 uint64_t trc : 4; /**< Row Cycle Time (represented in \#mclks) 4409 see also: DFA_MEMRLD[RLCFG] field which must 4410 correspond with tRL/tWL parameter(s). 4411 - 0000-0010: RESERVED 4412 - 0011: tRC = 3 mclks 4413 - 0100: tRC = 4 mclks 4414 - 0101: tRC = 5 mclks 4415 - 0110: tRC = 6 mclks 4416 - 0111: tRC = 7 mclks 4417 - 1000: tRC = 8 mclks 4418 - 1001: tRC = 9 mclks 4419 - 1010-1111: RESERVED 4420 NOTE: This should only be written to a different value 4421 during power-on SW initialization. */ 4422 uint64_t twl : 4; /**< Write Latency (represented in \#mclks) 4423 see also: DFA_MEMRLD[RLCFG] field which must 4424 correspond with tRL/tWL parameter(s). 4425 - 0000-0001: RESERVED 4426 - 0010: Write Latency (WL=2.0 mclk) 4427 - 0011: Write Latency (WL=3.0 mclks) 4428 - 0100: Write Latency (WL=4.0 mclks) 4429 - 0101: Write Latency (WL=5.0 mclks) 4430 - 0110: Write Latency (WL=6.0 mclks) 4431 - 0111: Write Latency (WL=7.0 mclks) 4432 - 1000: Write Latency (WL=8.0 mclks) 4433 - 1001: Write Latency (WL=9.0 mclks) 4434 - 1010: Write Latency (WL=10.0 mclks) 4435 - 1011-1111: RESERVED 4436 NOTE: This should only be written to a different value 4437 during power-on SW initialization. */ 4438 uint64_t trl : 4; /**< Read Latency (represented in \#mclks) 4439 see also: DFA_MEMRLD[RLCFG] field which must 4440 correspond with tRL/tWL parameter(s). 4441 - 0000-0010: RESERVED 4442 - 0011: Read Latency = 3 mclks 4443 - 0100: Read Latency = 4 mclks 4444 - 0101: Read Latency = 5 mclks 4445 - 0110: Read Latency = 6 mclks 4446 - 0111: Read Latency = 7 mclks 4447 - 1000: Read Latency = 8 mclks 4448 - 1001: Read Latency = 9 mclks 4449 - 1010: Read Latency = 10 mclks 4450 - 1011-1111: RESERVED 4451 NOTE: This should only be written to a different value 4452 during power-on SW initialization. */ 4453 uint64_t reserved_6_7 : 2; 4454 uint64_t tskw : 2; /**< Board Skew (represented in \#dclks) 4455 Represents additional board skew of DQ/DQS. 4456 - 00: board-skew = 0 dclk 4457 - 01: board-skew = 1 dclk 4458 - 10: board-skew = 2 dclk 4459 - 11: board-skew = 3 dclk 4460 NOTE: This should only be written to a different value 4461 during power-on SW initialization. */ 4462 uint64_t ref_int : 4; /**< Refresh Interval (represented in \#of 512 dclk 4463 increments). 4464 - 0000: RESERVED 4465 - 0001: 1 * 512 = 512 dclks 4466 - ... 4467 - 1111: 15 * 512 = 7680 dclks 4468 NOTE: For finer level of granularity, refer to 4469 REF_INTLO[8:0] field. 4470 For RLDRAM-II, each refresh interval will 4471 generate a burst of 8 AREF commands, one to each of 4472 8 explicit banks (referenced using the RLD_BA[2:0] 4473 pins. 4474 Example: For mclk=200MHz/dclk(400MHz=2.5ns): 4475 64K AREF cycles required within tREF=32ms 4476 trefint = tREF(ms)/(64K cycles/8banks) 4477 = 32ms/8K = 3.9us = 3900ns 4478 REF_INT = ROUND_DOWN[(trefint/dclk)/512] 4479 = ROUND_DOWN[(3900/2.5)/512] 4480 = 3 4481 NOTE: This should only be written to a different value 4482 during power-on SW initialization. */ 4483#else 4484 uint64_t ref_int : 4; 4485 uint64_t tskw : 2; 4486 uint64_t reserved_6_7 : 2; 4487 uint64_t trl : 4; 4488 uint64_t twl : 4; 4489 uint64_t trc : 4; 4490 uint64_t tmrsc : 3; 4491 uint64_t mrs_ena : 1; 4492 uint64_t aref_ena : 1; 4493 uint64_t ref_intlo : 9; 4494 uint64_t reserved_34_63 : 30; 4495#endif 4496 } s; 4497 struct cvmx_dfa_memcfg1_s cn38xx; 4498 struct cvmx_dfa_memcfg1_s cn38xxp2; 4499 struct cvmx_dfa_memcfg1_s cn58xx; 4500 struct cvmx_dfa_memcfg1_s cn58xxp1; 4501}; 4502typedef union cvmx_dfa_memcfg1 cvmx_dfa_memcfg1_t; 4503 4504/** 4505 * cvmx_dfa_memcfg2 4506 * 4507 * DFA_MEMCFG2 = DFA Memory Config Register \#2 4508 * *** NOTE: Pass2 Addition 4509 * 4510 * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II 4511 */ 4512union cvmx_dfa_memcfg2 { 4513 uint64_t u64; 4514 struct cvmx_dfa_memcfg2_s { 4515#ifdef __BIG_ENDIAN_BITFIELD 4516 uint64_t reserved_12_63 : 52; 4517 uint64_t dteclkdis : 1; /**< DFA DTE Clock Disable 4518 When SET, the DFA clocks for DTE(thread engine) 4519 operation are disabled. 4520 NOTE: When SET, SW MUST NEVER issue ANY operations to 4521 the DFA via the NCB Bus. All DFA Operations must be 4522 issued solely through the CP2 interface. 4523 4524 NOTE: When DTECLKDIS=1, if CP2 Errors are encountered 4525 (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR 4526 does not reflect the failing address/ctl information. */ 4527 uint64_t silrst : 1; /**< LLM-PHY Silo Reset 4528 When a '1' is written (when the previous 4529 value was a '0') causes the the LLM-PHY Silo read/write 4530 pointers to be reset. 4531 NOTE: SW MUST WAIT 400 dclks after the LAST HW Init 4532 sequence was launched (ie: INIT_START 0->1 CSR write), 4533 before the SILRST can be triggered (0->1). */ 4534 uint64_t trfc : 5; /**< FCRAM-II Refresh Interval 4535 *** CN58XX UNSUPPORTED *** */ 4536 uint64_t refshort : 1; /**< FCRAM Short Refresh Mode 4537 *** CN58XX UNSUPPORTED *** */ 4538 uint64_t ua_start : 2; /**< FCRAM-II Upper Addres Start 4539 *** CN58XX UNSUPPORTED *** */ 4540 uint64_t maxbnk : 1; /**< Maximum Banks per-device (used by the address mapper 4541 when extracting address bits for the memory bank#. 4542 - 0: 4 banks/device 4543 - 1: 8 banks/device */ 4544 uint64_t fcram2p : 1; /**< FCRAM-II+ Mode Enable 4545 *** CN58XX UNSUPPORTED *** */ 4546#else 4547 uint64_t fcram2p : 1; 4548 uint64_t maxbnk : 1; 4549 uint64_t ua_start : 2; 4550 uint64_t refshort : 1; 4551 uint64_t trfc : 5; 4552 uint64_t silrst : 1; 4553 uint64_t dteclkdis : 1; 4554 uint64_t reserved_12_63 : 52; 4555#endif 4556 } s; 4557 struct cvmx_dfa_memcfg2_s cn38xx; 4558 struct cvmx_dfa_memcfg2_s cn38xxp2; 4559 struct cvmx_dfa_memcfg2_s cn58xx; 4560 struct cvmx_dfa_memcfg2_s cn58xxp1; 4561}; 4562typedef union cvmx_dfa_memcfg2 cvmx_dfa_memcfg2_t; 4563 4564/** 4565 * cvmx_dfa_memfadr 4566 * 4567 * DFA_MEMFADR = RLDRAM Failing Address/Control Register 4568 * 4569 * Description: DFA Memory Failing Address/Control Error Capture information 4570 * This register contains useful information to help in isolating an RLDRAM memory failure. 4571 * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is 4572 * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt 4573 * via the FSRC field. 4574 * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED. 4575 */ 4576union cvmx_dfa_memfadr { 4577 uint64_t u64; 4578 struct cvmx_dfa_memfadr_s { 4579#ifdef __BIG_ENDIAN_BITFIELD 4580 uint64_t reserved_24_63 : 40; 4581 uint64_t maddr : 24; /**< Memory Address */ 4582#else 4583 uint64_t maddr : 24; 4584 uint64_t reserved_24_63 : 40; 4585#endif 4586 } s; 4587 struct cvmx_dfa_memfadr_cn31xx { 4588#ifdef __BIG_ENDIAN_BITFIELD 4589 uint64_t reserved_40_63 : 24; 4590 uint64_t fdst : 9; /**< Fill-Destination 4591 FSRC[1:0] | FDST[8:0] 4592 -------------+------------------------------------- 4593 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 4594 1(NCB-CSR) | [ncbSRC[8:0]] 4595 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 4596 where: 4597 DTE: DFA Thread Engine ID# 4598 PP: Packet Processor ID# 4599 FID: Fill-ID# (unique per PP) 4600 WIDX: 16b SIMPLE Mode (index) 4601 DMODE: (0=16b SIMPLE/1=32b SIMPLE) 4602 SIZE: (0=LW Mode access/1=QW Mode Access) 4603 INDEX: (0=Low LW/1=High LW) 4604 NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated 4605 by a processor core). LW refers to a 32-bit load/store. */ 4606 uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 4607 uint64_t pnum : 1; /**< Memory Port 4608 NOTE: For O2P, this bit will always return zero. */ 4609 uint64_t bnum : 3; /**< Memory Bank 4610 When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0]. 4611 (RANK[1] can be inferred from MADDR[24:0]) */ 4612 uint64_t maddr : 25; /**< Memory Address */ 4613#else 4614 uint64_t maddr : 25; 4615 uint64_t bnum : 3; 4616 uint64_t pnum : 1; 4617 uint64_t fsrc : 2; 4618 uint64_t fdst : 9; 4619 uint64_t reserved_40_63 : 24; 4620#endif 4621 } cn31xx; 4622 struct cvmx_dfa_memfadr_cn38xx { 4623#ifdef __BIG_ENDIAN_BITFIELD 4624 uint64_t reserved_39_63 : 25; 4625 uint64_t fdst : 9; /**< Fill-Destination 4626 FSRC[1:0] | FDST[8:0] 4627 -------------+------------------------------------- 4628 0(NCB-DTE) | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)] 4629 1(NCB-CSR) | [ncbSRC[8:0]] 4630 3(CP2-PP) | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)] 4631 where: 4632 DTE: DFA Thread Engine ID# 4633 PP: Packet Processor ID# 4634 FID: Fill-ID# (unique per PP) 4635 WIDX: 18b SIMPLE Mode (index) 4636 DMODE: (0=18b SIMPLE/1=36b SIMPLE) 4637 SIZE: (0=LW Mode access/1=QW Mode Access) 4638 INDEX: (0=Low LW/1=High LW) 4639 NOTE: QW refers to a 64-bit LLM Load/Store (intiated 4640 by a processor core). LW refers to a 36-bit load/store. */ 4641 uint64_t fsrc : 2; /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */ 4642 uint64_t pnum : 1; /**< Memory Port 4643 NOTE: the port id's are reversed 4644 PNUM==0 => port#1 4645 PNUM==1 => port#0 */ 4646 uint64_t bnum : 3; /**< Memory Bank */ 4647 uint64_t maddr : 24; /**< Memory Address */ 4648#else 4649 uint64_t maddr : 24; 4650 uint64_t bnum : 3; 4651 uint64_t pnum : 1; 4652 uint64_t fsrc : 2; 4653 uint64_t fdst : 9; 4654 uint64_t reserved_39_63 : 25; 4655#endif 4656 } cn38xx; 4657 struct cvmx_dfa_memfadr_cn38xx cn38xxp2; 4658 struct cvmx_dfa_memfadr_cn38xx cn58xx; 4659 struct cvmx_dfa_memfadr_cn38xx cn58xxp1; 4660}; 4661typedef union cvmx_dfa_memfadr cvmx_dfa_memfadr_t; 4662 4663/** 4664 * cvmx_dfa_memfcr 4665 * 4666 * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0] 4667 * *** CN58XX UNSUPPORTED *** 4668 * 4669 * Notes: 4670 * For FCRAM-II please consult your device's data sheet for further details: 4671 * MRS Definition: 4672 * A[13:8]=0 RESERVED 4673 * A[7]=0 TEST MODE (N3K requires test mode 0:"disabled") 4674 * A[6:4] CAS LATENCY (fully programmable - SW must ensure that the value programmed 4675 * into DFA_MEM_CFG0[TRL] corresponds with this value). 4676 * A[3]=0 BURST TYPE (N3K requires 0:"Sequential" Burst Type) 4677 * A[2:0] BURST LENGTH Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4) 4678 * 4679 * In BL2 mode(for highest performance), only 1/2 the phsyical 4680 * memory is unique (ie: each bunk stores the same information). 4681 * In BL4 mode(highest capacity), all of the physical memory 4682 * is unique (ie: each bunk is uniquely addressable). 4683 * EMRS Definition: 4684 * A[13:12] REFRESH MODE (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes) 4685 * 4686 * (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT] 4687 * is also reflected in the Refresh Mode encoding). 4688 * A[11:7]=0 RESERVED 4689 * A[6:5]=2 STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture 4690 * silos rely on a conditional QS strobe) 4691 * A[4:3] DIC(QS) QS Drive Strength: fully programmable (consult your FCRAM-II data sheet) 4692 * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 4693 * A[2:1] DIC(DQ) DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet) 4694 * [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive] 4695 * A[0] DLL DLL Enable: Programmable [0:DLL Enable/1: DLL Disable] 4696 * 4697 * EMRS2 Definition: (for FCRAM-II+) 4698 * A[13:11]=0 RESERVED 4699 * A[10:8] ODTDS On Die Termination (DS+/-) 4700 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4701 * A[7:6]=0 MBW Multi-Bank Write: (N3K requires use of 0:"single bank" mode only) 4702 * A[5:3] ODTin On Die Termination (input pin) 4703 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4704 * A[2:0] ODTDQ On Die Termination (DQ) 4705 * [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED] 4706 */ 4707union cvmx_dfa_memfcr { 4708 uint64_t u64; 4709 struct cvmx_dfa_memfcr_s { 4710#ifdef __BIG_ENDIAN_BITFIELD 4711 uint64_t reserved_47_63 : 17; 4712 uint64_t emrs2 : 15; /**< Memory Address[14:0] during EMRS2(for FCRAM-II+) 4713 *** CN58XX UNSUPPORTED *** */ 4714 uint64_t reserved_31_31 : 1; 4715 uint64_t emrs : 15; /**< Memory Address[14:0] during EMRS 4716 *** CN58XX UNSUPPORTED *** 4717 A[0]=1: DLL Enabled) */ 4718 uint64_t reserved_15_15 : 1; 4719 uint64_t mrs : 15; /**< FCRAM Memory Address[14:0] during MRS 4720 *** CN58XX UNSUPPORTED *** 4721 A[6:4]=4 CAS LATENCY=4(default) 4722 A[3]=0 Burst Type(must be 0:Sequential) 4723 A[2:0]=2 Burst Length=4(default) */ 4724#else 4725 uint64_t mrs : 15; 4726 uint64_t reserved_15_15 : 1; 4727 uint64_t emrs : 15; 4728 uint64_t reserved_31_31 : 1; 4729 uint64_t emrs2 : 15; 4730 uint64_t reserved_47_63 : 17; 4731#endif 4732 } s; 4733 struct cvmx_dfa_memfcr_s cn38xx; 4734 struct cvmx_dfa_memfcr_s cn38xxp2; 4735 struct cvmx_dfa_memfcr_s cn58xx; 4736 struct cvmx_dfa_memfcr_s cn58xxp1; 4737}; 4738typedef union cvmx_dfa_memfcr cvmx_dfa_memfcr_t; 4739 4740/** 4741 * cvmx_dfa_memhidat 4742 * 4743 * DFA_MEMHIDAT = DFA NCB-Direct CSR access to DFM Memory Space (High QW) 4744 * 4745 * Description: 4746 * DFA supports NCB-Direct CSR acccesses to DFM Memory space for debug purposes. Unfortunately, NCB-Direct accesses 4747 * are limited to QW-size(64bits), whereas the minimum access granularity for DFM Memory space is OW(128bits). To 4748 * support writes to DFM Memory space, the Hi-QW of data is sourced from the DFA_MEMHIDAT register. Recall, the 4749 * OW(128b) in DDR3 memory space is fixed format: 4750 * OWDATA[127:118]: OWECC[9:0] 10bits of in-band OWECC SEC/DED codeword 4751 * This can be precomputed/written by SW OR 4752 * if DFM_FNTCTL[ECC_WENA]=1, DFM hardware will auto-compute the 10b OWECC and place in the 4753 * OWDATA[127:118] before being written to memory. 4754 * OWDATA[117:0]: Memory Data (contains fixed MNODE/MONODE arc formats for use by DTEs(thread engines). 4755 * Or, a user may choose to treat DFM Memory Space as 'scratch pad' in which case the 4756 * OWDATA[117:0] may contain user-specified information accessible via NCB-Direct CSR mode 4757 * accesses to DFA Memory Space. 4758 * NOTE: To write to the DFA_MEMHIDAT register, a device would issue an IOBST directed at the DFA with addr[34:32]=3'b111. 4759 * To read the DFA_MEMHIDAT register, a device would issue an IOBLD64 directed at the DFA with addr[34:32]=3'b111. 4760 * 4761 * NOTE: If DFA_CONFIG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_MEMHIDAT register do not take effect. 4762 * NOTE: If FUSE[TBD]="DFA DTE disable" is blown, reads/writes to the DFA_MEMHIDAT register do not take effect. 4763 * 4764 * NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM 4765 */ 4766union cvmx_dfa_memhidat { 4767 uint64_t u64; 4768 struct cvmx_dfa_memhidat_s { 4769#ifdef __BIG_ENDIAN_BITFIELD 4770 uint64_t hidat : 64; /**< DFA Hi-QW of Write data during NCB-Direct DFM DDR3 4771 Memory accesses. 4772 All DFM DDR3 memory accesses are OW(128b) references, 4773 and since NCB-Direct Mode writes only support QW(64b), 4774 the Hi QW of data must be sourced from a CSR register. 4775 NOTE: This single register is 'shared' for ALL DFM 4776 DDR3 Memory writes. 4777 For o68: This register is UNUSED. Treat as spare bits. 4778 NOTE: PLEASE REMOVE DEFINITION FROM o68 HRM */ 4779#else 4780 uint64_t hidat : 64; 4781#endif 4782 } s; 4783 struct cvmx_dfa_memhidat_s cn61xx; 4784 struct cvmx_dfa_memhidat_s cn63xx; 4785 struct cvmx_dfa_memhidat_s cn63xxp1; 4786 struct cvmx_dfa_memhidat_s cn66xx; 4787 struct cvmx_dfa_memhidat_s cn68xx; 4788 struct cvmx_dfa_memhidat_s cn68xxp1; 4789}; 4790typedef union cvmx_dfa_memhidat cvmx_dfa_memhidat_t; 4791 4792/** 4793 * cvmx_dfa_memrld 4794 * 4795 * DFA_MEMRLD = DFA RLDRAM MRS Register Values 4796 * 4797 * Description: 4798 */ 4799union cvmx_dfa_memrld { 4800 uint64_t u64; 4801 struct cvmx_dfa_memrld_s { 4802#ifdef __BIG_ENDIAN_BITFIELD 4803 uint64_t reserved_23_63 : 41; 4804 uint64_t mrsdat : 23; /**< This field represents the data driven onto the 4805 A[22:0] address lines during MRS(Mode Register Set) 4806 commands (during a HW init sequence). This field 4807 corresponds with the Mode Register Bit Map from 4808 your RLDRAM-II device specific data sheet. 4809 A[17:10]: RESERVED 4810 A[9]: ODT (on die termination) 4811 A[8]: Impedance Matching 4812 A[7]: DLL Reset 4813 A[6]: UNUSED 4814 A[5]: Address Mux (for N3K: MUST BE ZERO) 4815 A[4:3]: Burst Length (for N3K: MUST BE ZERO) 4816 A[2:0]: Configuration (see data sheet for 4817 specific RLDRAM-II device). 4818 - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5] 4819 - 010: CFG=2 [tRC=6/tRL=6/tWL=7] 4820 - 011: CFG=3 [tRC=8/tRL=8/tWL=9] 4821 - 100-111: RESERVED 4822 NOTE: For additional density, the RLDRAM-II parts 4823 can be 'clamshelled' (ie: two devices mounted on 4824 different sides of the PCB board), since the BGA 4825 pinout supports 'mirroring'. 4826 To support a clamshell design, SW must preload 4827 the MRSDAT[22:0] with the proper A[22:0] pin mapping 4828 which is dependent on the 'selected' bunk/clam 4829 (see also: DFA_MEMCFG0[BUNK_INIT] field). 4830 NOTE: Care MUST BE TAKEN NOT to write to this register 4831 within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1). 4832 NOTE: This should only be written to a different value 4833 during power-on SW initialization. */ 4834#else 4835 uint64_t mrsdat : 23; 4836 uint64_t reserved_23_63 : 41; 4837#endif 4838 } s; 4839 struct cvmx_dfa_memrld_s cn38xx; 4840 struct cvmx_dfa_memrld_s cn38xxp2; 4841 struct cvmx_dfa_memrld_s cn58xx; 4842 struct cvmx_dfa_memrld_s cn58xxp1; 4843}; 4844typedef union cvmx_dfa_memrld cvmx_dfa_memrld_t; 4845 4846/** 4847 * cvmx_dfa_ncbctl 4848 * 4849 * DFA_NCBCTL = DFA NCB CTL Register 4850 * 4851 * Description: 4852 */ 4853union cvmx_dfa_ncbctl { 4854 uint64_t u64; 4855 struct cvmx_dfa_ncbctl_s { 4856#ifdef __BIG_ENDIAN_BITFIELD 4857 uint64_t reserved_11_63 : 53; 4858 uint64_t sbdnum : 5; /**< SBD Debug Entry# 4859 For internal use only. (DFA Scoreboard debug) 4860 Selects which one of 32 DFA Scoreboard entries is 4861 latched into the DFA_SBD_DBG[0-3] registers. */ 4862 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4863 For internal use only. (DFA Scoreboard debug) 4864 When written with a '1', the DFA Scoreboard Debug 4865 registers (DFA_SBD_DBG[0-3]) are all locked down. 4866 This allows SW to lock down the contents of the entire 4867 SBD for a single instant in time. All subsequent reads 4868 of the DFA scoreboard registers will return the data 4869 from that instant in time. */ 4870 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4871 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4872 NOTE: This should only be written to a different value 4873 during power-on SW initialization. */ 4874 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4875 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4876 NOTE: This should only be written to a different value 4877 during power-on SW initialization. */ 4878 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4879 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4880 NOTE: This should only be written to a different value 4881 during power-on SW initialization. */ 4882 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4883 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4884 NOTE: This should only be written to a different value 4885 during power-on SW initialization. */ 4886 uint64_t imode : 1; /**< NCB-Inbound Arbiter 4887 (0=FP [LP=NRQ,HP=NRP], 1=RR) 4888 NOTE: This should only be written to a different value 4889 during power-on SW initialization. */ 4890#else 4891 uint64_t imode : 1; 4892 uint64_t qmode : 1; 4893 uint64_t pmode : 1; 4894 uint64_t dtmode : 1; 4895 uint64_t dcmode : 1; 4896 uint64_t sbdlck : 1; 4897 uint64_t sbdnum : 5; 4898 uint64_t reserved_11_63 : 53; 4899#endif 4900 } s; 4901 struct cvmx_dfa_ncbctl_cn38xx { 4902#ifdef __BIG_ENDIAN_BITFIELD 4903 uint64_t reserved_10_63 : 54; 4904 uint64_t sbdnum : 4; /**< SBD Debug Entry# 4905 For internal use only. (DFA Scoreboard debug) 4906 Selects which one of 16 DFA Scoreboard entries is 4907 latched into the DFA_SBD_DBG[0-3] registers. */ 4908 uint64_t sbdlck : 1; /**< DFA Scoreboard LOCK Strobe 4909 For internal use only. (DFA Scoreboard debug) 4910 When written with a '1', the DFA Scoreboard Debug 4911 registers (DFA_SBD_DBG[0-3]) are all locked down. 4912 This allows SW to lock down the contents of the entire 4913 SBD for a single instant in time. All subsequent reads 4914 of the DFA scoreboard registers will return the data 4915 from that instant in time. */ 4916 uint64_t dcmode : 1; /**< DRF-CRQ/DTE Arbiter Mode 4917 DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR) 4918 NOTE: This should only be written to a different value 4919 during power-on SW initialization. */ 4920 uint64_t dtmode : 1; /**< DRF-DTE Arbiter Mode 4921 DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR) 4922 NOTE: This should only be written to a different value 4923 during power-on SW initialization. */ 4924 uint64_t pmode : 1; /**< NCB-NRP Arbiter Mode 4925 (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR 4926 NOTE: This should only be written to a different value 4927 during power-on SW initialization. */ 4928 uint64_t qmode : 1; /**< NCB-NRQ Arbiter Mode 4929 (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR 4930 NOTE: This should only be written to a different value 4931 during power-on SW initialization. */ 4932 uint64_t imode : 1; /**< NCB-Inbound Arbiter 4933 (0=FP [LP=NRQ,HP=NRP], 1=RR) 4934 NOTE: This should only be written to a different value 4935 during power-on SW initialization. */ 4936#else 4937 uint64_t imode : 1; 4938 uint64_t qmode : 1; 4939 uint64_t pmode : 1; 4940 uint64_t dtmode : 1; 4941 uint64_t dcmode : 1; 4942 uint64_t sbdlck : 1; 4943 uint64_t sbdnum : 4; 4944 uint64_t reserved_10_63 : 54; 4945#endif 4946 } cn38xx; 4947 struct cvmx_dfa_ncbctl_cn38xx cn38xxp2; 4948 struct cvmx_dfa_ncbctl_s cn58xx; 4949 struct cvmx_dfa_ncbctl_s cn58xxp1; 4950}; 4951typedef union cvmx_dfa_ncbctl cvmx_dfa_ncbctl_t; 4952 4953/** 4954 * cvmx_dfa_pfc0_cnt 4955 * 4956 * DFA_PFC0_CNT = DFA Performance Counter \#0 4957 * *FOR INTERNAL USE ONLY* 4958 * Description: 4959 */ 4960union cvmx_dfa_pfc0_cnt { 4961 uint64_t u64; 4962 struct cvmx_dfa_pfc0_cnt_s { 4963#ifdef __BIG_ENDIAN_BITFIELD 4964 uint64_t pfcnt0 : 64; /**< Performance Counter \#0 4965 When DFA_PFC_GCTL[CNT0ENA]=1, the event selected 4966 by DFA_PFC0_CTL[EVSEL] is counted. 4967 See also DFA_PFC_GCTL[CNT0WCLR] and DFA_PFC_GCTL 4968 [CNT0RCLR] for special clear count cases available 4969 for SW data collection. */ 4970#else 4971 uint64_t pfcnt0 : 64; 4972#endif 4973 } s; 4974 struct cvmx_dfa_pfc0_cnt_s cn61xx; 4975 struct cvmx_dfa_pfc0_cnt_s cn63xx; 4976 struct cvmx_dfa_pfc0_cnt_s cn63xxp1; 4977 struct cvmx_dfa_pfc0_cnt_s cn66xx; 4978 struct cvmx_dfa_pfc0_cnt_s cn68xx; 4979 struct cvmx_dfa_pfc0_cnt_s cn68xxp1; 4980}; 4981typedef union cvmx_dfa_pfc0_cnt cvmx_dfa_pfc0_cnt_t; 4982 4983/** 4984 * cvmx_dfa_pfc0_ctl 4985 * 4986 * DFA_PFC0_CTL = DFA Performance Counter#0 Control 4987 * *FOR INTERNAL USE ONLY* 4988 * Description: 4989 */ 4990union cvmx_dfa_pfc0_ctl { 4991 uint64_t u64; 4992 struct cvmx_dfa_pfc0_ctl_s { 4993#ifdef __BIG_ENDIAN_BITFIELD 4994 uint64_t reserved_14_63 : 50; 4995 uint64_t evsel : 6; /**< Performance Counter#0 Event Selector 4996 // Events [0-31] are based on PMODE(0:per cluster-DTE 1:per graph) 4997 - 0: \#Total Cycles 4998 - 1: \#LDNODE visits 4999 - 2: \#SDNODE visits 5000 - 3: \#DNODE visits (LD/SD) 5001 - 4: \#LCNODE visits 5002 - 5: \#SCNODE visits 5003 - 6: \#CNODE visits (LC/SC) 5004 - 7: \#LMNODE visits 5005 - 8: \#SMNODE visits 5006 - 9: \#MNODE visits (LM/SM) 5007 - 10: \#MONODE visits 5008 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5009 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5010 - 13: \#MEMORY visits (MNODE+MONODE) 5011 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5012 - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5013 - 16: \#RESCANs detected (occur when HASH collision is detected) 5014 - 17: \#GWALK iterations STALLED - Packet data/Result Buffer 5015 - 18: \#GWALK iterations NON-STALLED 5016 - 19: \#CLOAD iterations 5017 - 20: \#MLOAD iterations 5018 [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 5019 - 21: \#RWORD1+ writes 5020 - 22: \#cycles Cluster is busy 5021 - 23: \#GWALK Instructions 5022 - 24: \#CLOAD Instructions 5023 - 25: \#MLOAD Instructions 5024 [NOTE: If PMODE=1(per-graph) the MLOAD IWORD0.VGID will be used to discern graph#]. 5025 - 26: \#GFREE Instructions 5026 - 27-30: RESERVED 5027 - 31: \# Node Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE,EDNODE] registers 5028 //============================================================= 5029 // Events [32-63] are used ONLY FOR PMODE=0(per-cluster DTE mode): 5030 - 32: \#cycles a specific cluster-DTE remains active(valid state) 5031 - 33: \#cycles a specific cluster-DTE waits for Memory Response Data 5032 - 34: \#cycles a specific cluster-DTE waits in resource stall state 5033 (waiting for packet data or result buffer space) 5034 - 35: \#cycles a specific cluster-DTE waits in resource pending state 5035 - 36-63: RESERVED 5036 //============================================================= */ 5037 uint64_t reserved_6_7 : 2; 5038 uint64_t cldte : 4; /**< Performance Counter#0 Cluster DTE Selector 5039 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5040 is used to select/monitor the cluster's DTE# for all events 5041 associated with Performance Counter#0. */ 5042 uint64_t clnum : 2; /**< Performance Counter#0 Cluster Selector 5043 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5044 is used to select/monitor the cluster# for all events 5045 associated with Performance Counter#0. */ 5046#else 5047 uint64_t clnum : 2; 5048 uint64_t cldte : 4; 5049 uint64_t reserved_6_7 : 2; 5050 uint64_t evsel : 6; 5051 uint64_t reserved_14_63 : 50; 5052#endif 5053 } s; 5054 struct cvmx_dfa_pfc0_ctl_s cn61xx; 5055 struct cvmx_dfa_pfc0_ctl_s cn63xx; 5056 struct cvmx_dfa_pfc0_ctl_s cn63xxp1; 5057 struct cvmx_dfa_pfc0_ctl_s cn66xx; 5058 struct cvmx_dfa_pfc0_ctl_s cn68xx; 5059 struct cvmx_dfa_pfc0_ctl_s cn68xxp1; 5060}; 5061typedef union cvmx_dfa_pfc0_ctl cvmx_dfa_pfc0_ctl_t; 5062 5063/** 5064 * cvmx_dfa_pfc1_cnt 5065 * 5066 * DFA_PFC1_CNT = DFA Performance Counter \#1 5067 * *FOR INTERNAL USE ONLY* 5068 * Description: 5069 */ 5070union cvmx_dfa_pfc1_cnt { 5071 uint64_t u64; 5072 struct cvmx_dfa_pfc1_cnt_s { 5073#ifdef __BIG_ENDIAN_BITFIELD 5074 uint64_t pfcnt1 : 64; /**< Performance Counter \#1 5075 When DFA_PFC_GCTL[CNT1ENA]=1, the event selected 5076 by DFA_PFC1_CTL[EVSEL] is counted. 5077 See also DFA_PFC_GCTL[CNT1WCLR] and DFA_PFC_GCTL 5078 [CNT1RCLR] for special clear count cases available 5079 for SW data collection. */ 5080#else 5081 uint64_t pfcnt1 : 64; 5082#endif 5083 } s; 5084 struct cvmx_dfa_pfc1_cnt_s cn61xx; 5085 struct cvmx_dfa_pfc1_cnt_s cn63xx; 5086 struct cvmx_dfa_pfc1_cnt_s cn63xxp1; 5087 struct cvmx_dfa_pfc1_cnt_s cn66xx; 5088 struct cvmx_dfa_pfc1_cnt_s cn68xx; 5089 struct cvmx_dfa_pfc1_cnt_s cn68xxp1; 5090}; 5091typedef union cvmx_dfa_pfc1_cnt cvmx_dfa_pfc1_cnt_t; 5092 5093/** 5094 * cvmx_dfa_pfc1_ctl 5095 * 5096 * DFA_PFC1_CTL = DFA Performance Counter#1 Control 5097 * *FOR INTERNAL USE ONLY* 5098 * Description: 5099 */ 5100union cvmx_dfa_pfc1_ctl { 5101 uint64_t u64; 5102 struct cvmx_dfa_pfc1_ctl_s { 5103#ifdef __BIG_ENDIAN_BITFIELD 5104 uint64_t reserved_14_63 : 50; 5105 uint64_t evsel : 6; /**< Performance Counter#1 Event Selector 5106 - 0: \#Cycles 5107 - 1: \#LDNODE visits 5108 - 2: \#SDNODE visits 5109 - 3: \#DNODE visits (LD/SD) 5110 - 4: \#LCNODE visits 5111 - 5: \#SCNODE visits 5112 - 6: \#CNODE visits (LC/SC) 5113 - 7: \#LMNODE visits 5114 - 8: \#SMNODE visits 5115 - 9: \#MNODE visits (LM/SM) 5116 - 10: \#MONODE visits 5117 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5118 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5119 - 13: \#MEMORY visits (MNODE+MONODE) 5120 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5121 - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5122 - 16: \#RESCANs detected (occur when HASH collision is detected) 5123 - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5124 - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5125 - 19: \#CLOAD DTE cycles 5126 - 20: \#MLOAD DTE cycles 5127 - 21: \#cycles waiting for Memory Response Data 5128 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5129 - 23: \#cycles waiting in resource pending state 5130 - 24: \#RWORD1+ writes 5131 - 25: \#DTE-VLD cycles 5132 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5133 - 27: \#GWALK Instructions 5134 - 28: \#CLOAD Instructions 5135 - 29: \#MLOAD Instructions 5136 - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5137 - 31: RESERVED 5138 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5139 uint64_t reserved_6_7 : 2; 5140 uint64_t cldte : 4; /**< Performance Counter#1 Cluster DTE Selector 5141 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5142 is used to select/monitor the cluster's DTE# for all events 5143 associated with Performance Counter#1. */ 5144 uint64_t clnum : 2; /**< Performance Counter#1 Cluster Selector 5145 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5146 is used to select/monitor the cluster# for all events 5147 associated with Performance Counter#1. */ 5148#else 5149 uint64_t clnum : 2; 5150 uint64_t cldte : 4; 5151 uint64_t reserved_6_7 : 2; 5152 uint64_t evsel : 6; 5153 uint64_t reserved_14_63 : 50; 5154#endif 5155 } s; 5156 struct cvmx_dfa_pfc1_ctl_s cn61xx; 5157 struct cvmx_dfa_pfc1_ctl_s cn63xx; 5158 struct cvmx_dfa_pfc1_ctl_s cn63xxp1; 5159 struct cvmx_dfa_pfc1_ctl_s cn66xx; 5160 struct cvmx_dfa_pfc1_ctl_s cn68xx; 5161 struct cvmx_dfa_pfc1_ctl_s cn68xxp1; 5162}; 5163typedef union cvmx_dfa_pfc1_ctl cvmx_dfa_pfc1_ctl_t; 5164 5165/** 5166 * cvmx_dfa_pfc2_cnt 5167 * 5168 * DFA_PFC2_CNT = DFA Performance Counter \#2 5169 * *FOR INTERNAL USE ONLY* 5170 * Description: 5171 */ 5172union cvmx_dfa_pfc2_cnt { 5173 uint64_t u64; 5174 struct cvmx_dfa_pfc2_cnt_s { 5175#ifdef __BIG_ENDIAN_BITFIELD 5176 uint64_t pfcnt2 : 64; /**< Performance Counter \#2 5177 When DFA_PFC_GCTL[CNT2ENA]=1, the event selected 5178 by DFA_PFC2_CTL[EVSEL] is counted. 5179 See also DFA_PFC_GCTL[CNT2WCLR] and DFA_PFC_GCTL 5180 [CNT2RCLR] for special clear count cases available 5181 for SW data collection. */ 5182#else 5183 uint64_t pfcnt2 : 64; 5184#endif 5185 } s; 5186 struct cvmx_dfa_pfc2_cnt_s cn61xx; 5187 struct cvmx_dfa_pfc2_cnt_s cn63xx; 5188 struct cvmx_dfa_pfc2_cnt_s cn63xxp1; 5189 struct cvmx_dfa_pfc2_cnt_s cn66xx; 5190 struct cvmx_dfa_pfc2_cnt_s cn68xx; 5191 struct cvmx_dfa_pfc2_cnt_s cn68xxp1; 5192}; 5193typedef union cvmx_dfa_pfc2_cnt cvmx_dfa_pfc2_cnt_t; 5194 5195/** 5196 * cvmx_dfa_pfc2_ctl 5197 * 5198 * DFA_PFC2_CTL = DFA Performance Counter#2 Control 5199 * *FOR INTERNAL USE ONLY* 5200 * Description: 5201 */ 5202union cvmx_dfa_pfc2_ctl { 5203 uint64_t u64; 5204 struct cvmx_dfa_pfc2_ctl_s { 5205#ifdef __BIG_ENDIAN_BITFIELD 5206 uint64_t reserved_14_63 : 50; 5207 uint64_t evsel : 6; /**< Performance Counter#2 Event Selector 5208 - 0: \#Cycles 5209 - 1: \#LDNODE visits 5210 - 2: \#SDNODE visits 5211 - 3: \#DNODE visits (LD/SD) 5212 - 4: \#LCNODE visits 5213 - 5: \#SCNODE visits 5214 - 6: \#CNODE visits (LC/SC) 5215 - 7: \#LMNODE visits 5216 - 8: \#SMNODE visits 5217 - 9: \#MNODE visits (LM/SM) 5218 - 10: \#MONODE visits 5219 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5220 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5221 - 13: \#MEMORY visits (MNODE+MONODE) 5222 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5223 - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5224 - 16: \#RESCANs detected (occur when HASH collision is detected) 5225 - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5226 - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5227 - 19: \#CLOAD DTE cycles 5228 - 20: \#MLOAD DTE cycles 5229 - 21: \#cycles waiting for Memory Response Data 5230 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5231 - 23: \#cycles waiting in resource pending state 5232 - 24: \#RWORD1+ writes 5233 - 25: \#DTE-VLD cycles 5234 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5235 - 27: \#GWALK Instructions 5236 - 28: \#CLOAD Instructions 5237 - 29: \#MLOAD Instructions 5238 - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5239 - 31: RESERVED 5240 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5241 uint64_t reserved_6_7 : 2; 5242 uint64_t cldte : 4; /**< Performance Counter#2 Cluster DTE Selector 5243 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5244 is used to select/monitor the cluster's DTE# for all events 5245 associated with Performance Counter#2. */ 5246 uint64_t clnum : 2; /**< Performance Counter#2 Cluster Selector 5247 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5248 is used to select/monitor the cluster# for all events 5249 associated with Performance Counter#2. */ 5250#else 5251 uint64_t clnum : 2; 5252 uint64_t cldte : 4; 5253 uint64_t reserved_6_7 : 2; 5254 uint64_t evsel : 6; 5255 uint64_t reserved_14_63 : 50; 5256#endif 5257 } s; 5258 struct cvmx_dfa_pfc2_ctl_s cn61xx; 5259 struct cvmx_dfa_pfc2_ctl_s cn63xx; 5260 struct cvmx_dfa_pfc2_ctl_s cn63xxp1; 5261 struct cvmx_dfa_pfc2_ctl_s cn66xx; 5262 struct cvmx_dfa_pfc2_ctl_s cn68xx; 5263 struct cvmx_dfa_pfc2_ctl_s cn68xxp1; 5264}; 5265typedef union cvmx_dfa_pfc2_ctl cvmx_dfa_pfc2_ctl_t; 5266 5267/** 5268 * cvmx_dfa_pfc3_cnt 5269 * 5270 * DFA_PFC3_CNT = DFA Performance Counter \#3 5271 * *FOR INTERNAL USE ONLY* 5272 * Description: 5273 */ 5274union cvmx_dfa_pfc3_cnt { 5275 uint64_t u64; 5276 struct cvmx_dfa_pfc3_cnt_s { 5277#ifdef __BIG_ENDIAN_BITFIELD 5278 uint64_t pfcnt3 : 64; /**< Performance Counter \#3 5279 When DFA_PFC_GCTL[CNT3ENA]=1, the event selected 5280 by DFA_PFC3_CTL[EVSEL] is counted. 5281 See also DFA_PFC_GCTL[CNT3WCLR] and DFA_PFC_GCTL 5282 [CNT3RCLR] for special clear count cases available 5283 for SW data collection. */ 5284#else 5285 uint64_t pfcnt3 : 64; 5286#endif 5287 } s; 5288 struct cvmx_dfa_pfc3_cnt_s cn61xx; 5289 struct cvmx_dfa_pfc3_cnt_s cn63xx; 5290 struct cvmx_dfa_pfc3_cnt_s cn63xxp1; 5291 struct cvmx_dfa_pfc3_cnt_s cn66xx; 5292 struct cvmx_dfa_pfc3_cnt_s cn68xx; 5293 struct cvmx_dfa_pfc3_cnt_s cn68xxp1; 5294}; 5295typedef union cvmx_dfa_pfc3_cnt cvmx_dfa_pfc3_cnt_t; 5296 5297/** 5298 * cvmx_dfa_pfc3_ctl 5299 * 5300 * DFA_PFC3_CTL = DFA Performance Counter#3 Control 5301 * *FOR INTERNAL USE ONLY* 5302 * Description: 5303 */ 5304union cvmx_dfa_pfc3_ctl { 5305 uint64_t u64; 5306 struct cvmx_dfa_pfc3_ctl_s { 5307#ifdef __BIG_ENDIAN_BITFIELD 5308 uint64_t reserved_14_63 : 50; 5309 uint64_t evsel : 6; /**< Performance Counter#3 Event Selector 5310 - 0: \#Cycles 5311 - 1: \#LDNODE visits 5312 - 2: \#SDNODE visits 5313 - 3: \#DNODE visits (LD/SD) 5314 - 4: \#LCNODE visits 5315 - 5: \#SCNODE visits 5316 - 6: \#CNODE visits (LC/SC) 5317 - 7: \#LMNODE visits 5318 - 8: \#SMNODE visits 5319 - 9: \#MNODE visits (LM/SM) 5320 - 10: \#MONODE visits 5321 - 11: \#CACHE visits (DNODE,CNODE) exc: CNDRD,MPHIDX 5322 - 12: \#CACHE visits (DNODE,CNODE)+(CNDRD,MPHIDX) 5323 - 13: \#MEMORY visits (MNODE+MONODE) 5324 - 14: \#CNDRDs detected (occur for SCNODE->*MNODE transitions) 5325 - 15: \#MPHIDX detected (occur for ->LMNODE transitions) 5326 - 16: \#RESCANs detected (occur when HASH collision is detected) 5327 - 17: \#GWALK STALLs detected - Packet data/Result Buffer 5328 - 18: \#GWALK DTE cycles (all DTE-GNT[3a]) 5329 - 19: \#CLOAD DTE cycles 5330 - 20: \#MLOAD DTE cycles 5331 - 21: \#cycles waiting for Memory Response Data 5332 - 22: \#cycles waiting in resource stall state (waiting for packet data or result buffer space) 5333 - 23: \#cycles waiting in resource pending state 5334 - 24: \#RWORD1+ writes 5335 - 25: \#DTE-VLD cycles 5336 - 26: \#DTE Transitions detected (see DFA_PFC_GCTL[SNODE,ENODE] registers 5337 - 27: \#GWALK Instructions 5338 - 28: \#CLOAD Instructions 5339 - 29: \#MLOAD Instructions 5340 - 30: \#GFREE Instructions (== \#GFREE DTE cycles) 5341 - 31: RESERVED 5342 - 32: \#DTE-Busy cycles (ALL DTE-GNT strobes) */ 5343 uint64_t reserved_6_7 : 2; 5344 uint64_t cldte : 4; /**< Performance Counter#3 Cluster DTE Selector 5345 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5346 is used to select/monitor the cluster's DTE# for all events 5347 associated with Performance Counter#3. */ 5348 uint64_t clnum : 2; /**< Performance Counter#3 Cluster Selector 5349 When DFA_PFC_GCTL[PMODE]=0 (per-cluster DTE), this field 5350 is used to select/monitor the cluster# for all events 5351 associated with Performance Counter#3. */ 5352#else 5353 uint64_t clnum : 2; 5354 uint64_t cldte : 4; 5355 uint64_t reserved_6_7 : 2; 5356 uint64_t evsel : 6; 5357 uint64_t reserved_14_63 : 50; 5358#endif 5359 } s; 5360 struct cvmx_dfa_pfc3_ctl_s cn61xx; 5361 struct cvmx_dfa_pfc3_ctl_s cn63xx; 5362 struct cvmx_dfa_pfc3_ctl_s cn63xxp1; 5363 struct cvmx_dfa_pfc3_ctl_s cn66xx; 5364 struct cvmx_dfa_pfc3_ctl_s cn68xx; 5365 struct cvmx_dfa_pfc3_ctl_s cn68xxp1; 5366}; 5367typedef union cvmx_dfa_pfc3_ctl cvmx_dfa_pfc3_ctl_t; 5368 5369/** 5370 * cvmx_dfa_pfc_gctl 5371 * 5372 * DFA_PFC_GCTL = DFA Performance Counter Global Control 5373 * *FOR INTERNAL USE ONLY* 5374 * Description: 5375 */ 5376union cvmx_dfa_pfc_gctl { 5377 uint64_t u64; 5378 struct cvmx_dfa_pfc_gctl_s { 5379#ifdef __BIG_ENDIAN_BITFIELD 5380 uint64_t reserved_29_63 : 35; 5381 uint64_t vgid : 8; /**< Virtual Graph Id# 5382 When PMODE=1(per-graph selector), this field is used 5383 to select/monitor only those events which are 5384 associated with this selected VGID(virtual graph ID). 5385 This field is used globally across all four performance 5386 counters. 5387 IMPNOTE: I implemented a global VGID across all 4 performance 5388 counters to save wires/area. */ 5389 uint64_t pmode : 1; /**< Select Mode 5390 - 0: Events are selected on a per-cluster DTE# (CLNUM/CLDTE) 5391 DFA_PFCx_CTL[CLNUM,CLDTE] specifies the cluster-DTE for 5392 each 1(of 4) performance counters. 5393 - 1: Events are selected on a per-graph basis (VGID=virtual Graph ID). 5394 NOTE: Only EVSEL=[0...31] can be used in conjunction with PMODE=1. 5395 DFA_PFC_GCTL[VGID] specifies the Virtual graph ID used across 5396 all four performance counters. */ 5397 uint64_t ednode : 2; /**< Ending DNODE Selector 5398 When ENODE=0/1(*DNODE), this field is used to further 5399 specify the Ending DNODE transition sub-type: 5400 - 0: ALL DNODE sub-types 5401 - 1: ->D2e (explicit DNODE transition node-arc alone transitions to DNODE) 5402 - 2: ->D2i (implicit DNODE transition:arc-present triggers transition) 5403 - 3: ->D1r (rescan DNODE transition) */ 5404 uint64_t enode : 3; /**< Ending Node Selector 5405 When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the ENODE 5406 field is used to select Ending Node, and the SNODE 5407 field is used to select the Starting Node. 5408 - 0: LDNODE 5409 - 1: SDNODE 5410 - 2: LCNODE 5411 - 3: SCNODE 5412 - 4: LMNODE 5413 - 5: SMNODE 5414 - 6: MONODE 5415 - 7: RESERVED */ 5416 uint64_t snode : 3; /**< Starting Node Selector 5417 When DFA_PFCx_CTL[EVSEL]=Node Transition(31), the SNODE 5418 field is used to select Starting Node, and the ENODE 5419 field is used to select the Ending Node. 5420 - 0: LDNODE 5421 - 1: SDNODE 5422 - 2: LCNODE 5423 - 3: SCNODE 5424 - 4: LMNODE 5425 - 5: SMNODE 5426 - 6: MONODE 5427 - 7: RESERVED */ 5428 uint64_t cnt3rclr : 1; /**< Performance Counter \#3 Read Clear 5429 If this bit is set, CSR reads to the DFA_PFC3_CNT 5430 will clear the count value. This allows SW to maintain 5431 'cumulative' counters to avoid HW wraparound. */ 5432 uint64_t cnt2rclr : 1; /**< Performance Counter \#2 Read Clear 5433 If this bit is set, CSR reads to the DFA_PFC2_CNT 5434 will clear the count value. This allows SW to maintain 5435 'cumulative' counters to avoid HW wraparound. */ 5436 uint64_t cnt1rclr : 1; /**< Performance Counter \#1 Read Clear 5437 If this bit is set, CSR reads to the DFA_PFC1_CNT 5438 will clear the count value. This allows SW to maintain 5439 'cumulative' counters to avoid HW wraparound. */ 5440 uint64_t cnt0rclr : 1; /**< Performance Counter \#0 Read Clear 5441 If this bit is set, CSR reads to the DFA_PFC0_CNT 5442 will clear the count value. This allows SW to maintain 5443 'cumulative' counters to avoid HW wraparound. */ 5444 uint64_t cnt3wclr : 1; /**< Performance Counter \#3 Write Clear 5445 If this bit is set, CSR writes to the DFA_PFC3_CNT 5446 will clear the count value. 5447 If this bit is clear, CSR writes to the DFA_PFC3_CNT 5448 will continue the count from the written value. */ 5449 uint64_t cnt2wclr : 1; /**< Performance Counter \#2 Write Clear 5450 If this bit is set, CSR writes to the DFA_PFC2_CNT 5451 will clear the count value. 5452 If this bit is clear, CSR writes to the DFA_PFC2_CNT 5453 will continue the count from the written value. */ 5454 uint64_t cnt1wclr : 1; /**< Performance Counter \#1 Write Clear 5455 If this bit is set, CSR writes to the DFA_PFC1_CNT 5456 will clear the count value. 5457 If this bit is clear, CSR writes to the DFA_PFC1_CNT 5458 will continue the count from the written value. */ 5459 uint64_t cnt0wclr : 1; /**< Performance Counter \#0 Write Clear 5460 If this bit is set, CSR writes to the DFA_PFC0_CNT 5461 will clear the count value. 5462 If this bit is clear, CSR writes to the DFA_PFC0_CNT 5463 will continue the count from the written value. */ 5464 uint64_t cnt3ena : 1; /**< Performance Counter 3 Enable 5465 When this bit is set, the performance counter \#3 5466 is enabled. */ 5467 uint64_t cnt2ena : 1; /**< Performance Counter 2 Enable 5468 When this bit is set, the performance counter \#2 5469 is enabled. */ 5470 uint64_t cnt1ena : 1; /**< Performance Counter 1 Enable 5471 When this bit is set, the performance counter \#1 5472 is enabled. */ 5473 uint64_t cnt0ena : 1; /**< Performance Counter 0 Enable 5474 When this bit is set, the performance counter \#0 5475 is enabled. */ 5476#else 5477 uint64_t cnt0ena : 1; 5478 uint64_t cnt1ena : 1; 5479 uint64_t cnt2ena : 1; 5480 uint64_t cnt3ena : 1; 5481 uint64_t cnt0wclr : 1; 5482 uint64_t cnt1wclr : 1; 5483 uint64_t cnt2wclr : 1; 5484 uint64_t cnt3wclr : 1; 5485 uint64_t cnt0rclr : 1; 5486 uint64_t cnt1rclr : 1; 5487 uint64_t cnt2rclr : 1; 5488 uint64_t cnt3rclr : 1; 5489 uint64_t snode : 3; 5490 uint64_t enode : 3; 5491 uint64_t ednode : 2; 5492 uint64_t pmode : 1; 5493 uint64_t vgid : 8; 5494 uint64_t reserved_29_63 : 35; 5495#endif 5496 } s; 5497 struct cvmx_dfa_pfc_gctl_s cn61xx; 5498 struct cvmx_dfa_pfc_gctl_s cn63xx; 5499 struct cvmx_dfa_pfc_gctl_s cn63xxp1; 5500 struct cvmx_dfa_pfc_gctl_s cn66xx; 5501 struct cvmx_dfa_pfc_gctl_s cn68xx; 5502 struct cvmx_dfa_pfc_gctl_s cn68xxp1; 5503}; 5504typedef union cvmx_dfa_pfc_gctl cvmx_dfa_pfc_gctl_t; 5505 5506/** 5507 * cvmx_dfa_rodt_comp_ctl 5508 * 5509 * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination") 5510 * 5511 */ 5512union cvmx_dfa_rodt_comp_ctl { 5513 uint64_t u64; 5514 struct cvmx_dfa_rodt_comp_ctl_s { 5515#ifdef __BIG_ENDIAN_BITFIELD 5516 uint64_t reserved_17_63 : 47; 5517 uint64_t enable : 1; /**< Read On Die Termination Enable 5518 (0=disable, 1=enable) */ 5519 uint64_t reserved_12_15 : 4; 5520 uint64_t nctl : 4; /**< Compensation control bits */ 5521 uint64_t reserved_5_7 : 3; 5522 uint64_t pctl : 5; /**< Compensation control bits */ 5523#else 5524 uint64_t pctl : 5; 5525 uint64_t reserved_5_7 : 3; 5526 uint64_t nctl : 4; 5527 uint64_t reserved_12_15 : 4; 5528 uint64_t enable : 1; 5529 uint64_t reserved_17_63 : 47; 5530#endif 5531 } s; 5532 struct cvmx_dfa_rodt_comp_ctl_s cn58xx; 5533 struct cvmx_dfa_rodt_comp_ctl_s cn58xxp1; 5534}; 5535typedef union cvmx_dfa_rodt_comp_ctl cvmx_dfa_rodt_comp_ctl_t; 5536 5537/** 5538 * cvmx_dfa_sbd_dbg0 5539 * 5540 * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register 5541 * 5542 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5543 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5544 * CSR read. 5545 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5546 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5547 * instruction. 5548 */ 5549union cvmx_dfa_sbd_dbg0 { 5550 uint64_t u64; 5551 struct cvmx_dfa_sbd_dbg0_s { 5552#ifdef __BIG_ENDIAN_BITFIELD 5553 uint64_t sbd0 : 64; /**< DFA ScoreBoard \#0 Data 5554 For internal use only! (DFA Scoreboard Debug) 5555 [63:40] rptr[26:3]: Result Base Pointer 5556 [39:24] rwcnt[15:0] Cumulative Result Write Counter 5557 [23] lastgrdrsp: Last Gather-Rd Response 5558 [22] wtgrdrsp: Waiting Gather-Rd Response 5559 [21] wtgrdreq: Waiting for Gather-Rd Issue 5560 [20] glvld: GLPTR/GLCNT Valid 5561 [19] cmpmark: Completion Marked Node Detected 5562 [18:17] cmpcode[1:0]: Completion Code 5563 [0=PDGONE/1=PERR/2=RFULL/3=TERM] 5564 [16] cmpdet: Completion Detected 5565 [15] wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp 5566 [14] wtlastwrcmtrsp: Waiting for LAST RESULT 5567 RWrCmtRsp 5568 [13] hdrwrreq: Waiting for HDR RWrReq 5569 [12] wtrwrreq: Waiting for RWrReq 5570 [11] wtwqwrreq: Waiting for WQWrReq issue 5571 [10] lastprdrspeot: Last Packet-Rd Response 5572 [9] lastprdrsp: Last Packet-Rd Response 5573 [8] wtprdrsp: Waiting for PRdRsp EOT 5574 [7] wtprdreq: Waiting for PRdReq Issue 5575 [6] lastpdvld: PDPTR/PDLEN Valid 5576 [5] pdvld: Packet Data Valid 5577 [4] wqvld: WQVLD 5578 [3] wqdone: WorkQueue Done condition 5579 a) WQWrReq issued(for WQPTR<>0) OR 5580 b) HDR RWrCmtRsp completed) 5581 [2] rwstf: Resultant write STF/P Mode 5582 [1] pdldt: Packet-Data LDT mode 5583 [0] gmode: Gather-Mode */ 5584#else 5585 uint64_t sbd0 : 64; 5586#endif 5587 } s; 5588 struct cvmx_dfa_sbd_dbg0_s cn31xx; 5589 struct cvmx_dfa_sbd_dbg0_s cn38xx; 5590 struct cvmx_dfa_sbd_dbg0_s cn38xxp2; 5591 struct cvmx_dfa_sbd_dbg0_s cn58xx; 5592 struct cvmx_dfa_sbd_dbg0_s cn58xxp1; 5593}; 5594typedef union cvmx_dfa_sbd_dbg0 cvmx_dfa_sbd_dbg0_t; 5595 5596/** 5597 * cvmx_dfa_sbd_dbg1 5598 * 5599 * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register 5600 * 5601 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5602 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5603 * CSR read. 5604 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5605 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5606 * instruction. 5607 */ 5608union cvmx_dfa_sbd_dbg1 { 5609 uint64_t u64; 5610 struct cvmx_dfa_sbd_dbg1_s { 5611#ifdef __BIG_ENDIAN_BITFIELD 5612 uint64_t sbd1 : 64; /**< DFA ScoreBoard \#1 Data 5613 For internal use only! (DFA Scoreboard Debug) 5614 [63:61] wqptr[35:33]: Work Queue Pointer 5615 [60:52] rptr[35:27]: Result Base Pointer 5616 [51:16] pdptr[35:0]: Packet Data Pointer 5617 [15:0] pdcnt[15:0]: Packet Data Counter */ 5618#else 5619 uint64_t sbd1 : 64; 5620#endif 5621 } s; 5622 struct cvmx_dfa_sbd_dbg1_s cn31xx; 5623 struct cvmx_dfa_sbd_dbg1_s cn38xx; 5624 struct cvmx_dfa_sbd_dbg1_s cn38xxp2; 5625 struct cvmx_dfa_sbd_dbg1_s cn58xx; 5626 struct cvmx_dfa_sbd_dbg1_s cn58xxp1; 5627}; 5628typedef union cvmx_dfa_sbd_dbg1 cvmx_dfa_sbd_dbg1_t; 5629 5630/** 5631 * cvmx_dfa_sbd_dbg2 5632 * 5633 * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register 5634 * 5635 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5636 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5637 * CSR read. 5638 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5639 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5640 * instruction. 5641 */ 5642union cvmx_dfa_sbd_dbg2 { 5643 uint64_t u64; 5644 struct cvmx_dfa_sbd_dbg2_s { 5645#ifdef __BIG_ENDIAN_BITFIELD 5646 uint64_t sbd2 : 64; /**< DFA ScoreBoard \#2 Data 5647 [63:49] wqptr[17:3]: Work Queue Pointer 5648 [48:16] rwptr[35:3]: Result Write Pointer 5649 [15:0] prwcnt[15:0]: Pending Result Write Counter */ 5650#else 5651 uint64_t sbd2 : 64; 5652#endif 5653 } s; 5654 struct cvmx_dfa_sbd_dbg2_s cn31xx; 5655 struct cvmx_dfa_sbd_dbg2_s cn38xx; 5656 struct cvmx_dfa_sbd_dbg2_s cn38xxp2; 5657 struct cvmx_dfa_sbd_dbg2_s cn58xx; 5658 struct cvmx_dfa_sbd_dbg2_s cn58xxp1; 5659}; 5660typedef union cvmx_dfa_sbd_dbg2 cvmx_dfa_sbd_dbg2_t; 5661 5662/** 5663 * cvmx_dfa_sbd_dbg3 5664 * 5665 * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register 5666 * 5667 * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down. 5668 * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the 5669 * CSR read. 5670 * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model) 5671 * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an 5672 * instruction. 5673 */ 5674union cvmx_dfa_sbd_dbg3 { 5675 uint64_t u64; 5676 struct cvmx_dfa_sbd_dbg3_s { 5677#ifdef __BIG_ENDIAN_BITFIELD 5678 uint64_t sbd3 : 64; /**< DFA ScoreBoard \#3 Data 5679 [63:49] wqptr[32:18]: Work Queue Pointer 5680 [48:16] glptr[35:3]: Gather List Pointer 5681 [15:0] glcnt[15:0]: Gather List Counter */ 5682#else 5683 uint64_t sbd3 : 64; 5684#endif 5685 } s; 5686 struct cvmx_dfa_sbd_dbg3_s cn31xx; 5687 struct cvmx_dfa_sbd_dbg3_s cn38xx; 5688 struct cvmx_dfa_sbd_dbg3_s cn38xxp2; 5689 struct cvmx_dfa_sbd_dbg3_s cn58xx; 5690 struct cvmx_dfa_sbd_dbg3_s cn58xxp1; 5691}; 5692typedef union cvmx_dfa_sbd_dbg3 cvmx_dfa_sbd_dbg3_t; 5693 5694#endif 5695