1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-mio-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon mio. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_MIO_DEFS_H__ 53232812Sjmallett#define __CVMX_MIO_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull)) 56215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 57215976Sjmallett#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC() 58215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void) 59215976Sjmallett{ 60232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 61215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n"); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800000000B8ull); 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull)) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 73232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 75232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 78215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset); 79215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8; 80215976Sjmallett} 81215976Sjmallett#else 82215976Sjmallett#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8) 83215976Sjmallett#endif 84215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 85215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset) 86215976Sjmallett{ 87215976Sjmallett if (!( 88215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 90232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 94232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 95215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset); 96215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8; 97215976Sjmallett} 98215976Sjmallett#else 99215976Sjmallett#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8) 100215976Sjmallett#endif 101215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 102215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset) 103215976Sjmallett{ 104215976Sjmallett if (!( 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 109232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 110232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 112215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset); 113215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8; 114215976Sjmallett} 115215976Sjmallett#else 116215976Sjmallett#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8) 117215976Sjmallett#endif 118215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 119215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset) 120215976Sjmallett{ 121215976Sjmallett if (!( 122215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 124232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 125232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 126232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 127232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 128232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 129215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset); 130215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8; 131215976Sjmallett} 132215976Sjmallett#else 133215976Sjmallett#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8) 134215976Sjmallett#endif 135215976Sjmallett#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull)) 136215976Sjmallett#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull)) 137215976Sjmallett#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull)) 138215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset) 140215976Sjmallett{ 141215976Sjmallett if (!( 142215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 145215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 146215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 154215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8; 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8) 159215976Sjmallett#endif 160215976Sjmallett#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull)) 161215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 162215976Sjmallett#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC() 163215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void) 164215976Sjmallett{ 165232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 166215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n"); 167215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800000000C0ull); 168215976Sjmallett} 169215976Sjmallett#else 170215976Sjmallett#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull)) 171215976Sjmallett#endif 172215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset) 174215976Sjmallett{ 175215976Sjmallett if (!( 176215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 177215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 188215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset); 189215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8; 190215976Sjmallett} 191215976Sjmallett#else 192215976Sjmallett#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 193215976Sjmallett#endif 194215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 195215976Sjmallettstatic inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset) 196215976Sjmallett{ 197215976Sjmallett if (!( 198215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 199215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 200215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 201215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 205232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 206232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 207232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 208232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 209232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 210215976Sjmallett cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset); 211215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8; 212215976Sjmallett} 213215976Sjmallett#else 214215976Sjmallett#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 215215976Sjmallett#endif 216215976Sjmallett#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 217215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 218232812Sjmallett#define CVMX_MIO_EMM_BUF_DAT CVMX_MIO_EMM_BUF_DAT_FUNC() 219232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_BUF_DAT_FUNC(void) 220232812Sjmallett{ 221232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 222232812Sjmallett cvmx_warn("CVMX_MIO_EMM_BUF_DAT not supported on this chip\n"); 223232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800000020E8ull); 224232812Sjmallett} 225232812Sjmallett#else 226232812Sjmallett#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull)) 227232812Sjmallett#endif 228232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 229232812Sjmallett#define CVMX_MIO_EMM_BUF_IDX CVMX_MIO_EMM_BUF_IDX_FUNC() 230232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_BUF_IDX_FUNC(void) 231232812Sjmallett{ 232232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 233232812Sjmallett cvmx_warn("CVMX_MIO_EMM_BUF_IDX not supported on this chip\n"); 234232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800000020E0ull); 235232812Sjmallett} 236232812Sjmallett#else 237232812Sjmallett#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull)) 238232812Sjmallett#endif 239232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 240232812Sjmallett#define CVMX_MIO_EMM_CFG CVMX_MIO_EMM_CFG_FUNC() 241232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_CFG_FUNC(void) 242232812Sjmallett{ 243232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 244232812Sjmallett cvmx_warn("CVMX_MIO_EMM_CFG not supported on this chip\n"); 245232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002000ull); 246232812Sjmallett} 247232812Sjmallett#else 248232812Sjmallett#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull)) 249232812Sjmallett#endif 250232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251232812Sjmallett#define CVMX_MIO_EMM_CMD CVMX_MIO_EMM_CMD_FUNC() 252232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_CMD_FUNC(void) 253232812Sjmallett{ 254232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 255232812Sjmallett cvmx_warn("CVMX_MIO_EMM_CMD not supported on this chip\n"); 256232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002058ull); 257232812Sjmallett} 258232812Sjmallett#else 259232812Sjmallett#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull)) 260232812Sjmallett#endif 261232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 262232812Sjmallett#define CVMX_MIO_EMM_DMA CVMX_MIO_EMM_DMA_FUNC() 263232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_DMA_FUNC(void) 264232812Sjmallett{ 265232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 266232812Sjmallett cvmx_warn("CVMX_MIO_EMM_DMA not supported on this chip\n"); 267232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002050ull); 268232812Sjmallett} 269232812Sjmallett#else 270232812Sjmallett#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull)) 271232812Sjmallett#endif 272232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 273232812Sjmallett#define CVMX_MIO_EMM_INT CVMX_MIO_EMM_INT_FUNC() 274232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_INT_FUNC(void) 275232812Sjmallett{ 276232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 277232812Sjmallett cvmx_warn("CVMX_MIO_EMM_INT not supported on this chip\n"); 278232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002078ull); 279232812Sjmallett} 280232812Sjmallett#else 281232812Sjmallett#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull)) 282232812Sjmallett#endif 283232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 284232812Sjmallett#define CVMX_MIO_EMM_INT_EN CVMX_MIO_EMM_INT_EN_FUNC() 285232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_INT_EN_FUNC(void) 286232812Sjmallett{ 287232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 288232812Sjmallett cvmx_warn("CVMX_MIO_EMM_INT_EN not supported on this chip\n"); 289232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002080ull); 290232812Sjmallett} 291232812Sjmallett#else 292232812Sjmallett#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull)) 293232812Sjmallett#endif 294232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 295232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_MODEX(unsigned long offset) 296232812Sjmallett{ 297232812Sjmallett if (!( 298232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 300232812Sjmallett cvmx_warn("CVMX_MIO_EMM_MODEX(%lu) is invalid on this chip\n", offset); 301232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8; 302232812Sjmallett} 303232812Sjmallett#else 304232812Sjmallett#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8) 305232812Sjmallett#endif 306232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 307232812Sjmallett#define CVMX_MIO_EMM_RCA CVMX_MIO_EMM_RCA_FUNC() 308232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_RCA_FUNC(void) 309232812Sjmallett{ 310232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 311232812Sjmallett cvmx_warn("CVMX_MIO_EMM_RCA not supported on this chip\n"); 312232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800000020A0ull); 313232812Sjmallett} 314232812Sjmallett#else 315232812Sjmallett#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull)) 316232812Sjmallett#endif 317232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 318232812Sjmallett#define CVMX_MIO_EMM_RSP_HI CVMX_MIO_EMM_RSP_HI_FUNC() 319232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_RSP_HI_FUNC(void) 320232812Sjmallett{ 321232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 322232812Sjmallett cvmx_warn("CVMX_MIO_EMM_RSP_HI not supported on this chip\n"); 323232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002070ull); 324232812Sjmallett} 325232812Sjmallett#else 326232812Sjmallett#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull)) 327232812Sjmallett#endif 328232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329232812Sjmallett#define CVMX_MIO_EMM_RSP_LO CVMX_MIO_EMM_RSP_LO_FUNC() 330232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_RSP_LO_FUNC(void) 331232812Sjmallett{ 332232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 333232812Sjmallett cvmx_warn("CVMX_MIO_EMM_RSP_LO not supported on this chip\n"); 334232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002068ull); 335232812Sjmallett} 336232812Sjmallett#else 337232812Sjmallett#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull)) 338232812Sjmallett#endif 339232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 340232812Sjmallett#define CVMX_MIO_EMM_RSP_STS CVMX_MIO_EMM_RSP_STS_FUNC() 341232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_RSP_STS_FUNC(void) 342232812Sjmallett{ 343232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 344232812Sjmallett cvmx_warn("CVMX_MIO_EMM_RSP_STS not supported on this chip\n"); 345232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002060ull); 346232812Sjmallett} 347232812Sjmallett#else 348232812Sjmallett#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull)) 349232812Sjmallett#endif 350232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 351232812Sjmallett#define CVMX_MIO_EMM_SAMPLE CVMX_MIO_EMM_SAMPLE_FUNC() 352232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_SAMPLE_FUNC(void) 353232812Sjmallett{ 354232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 355232812Sjmallett cvmx_warn("CVMX_MIO_EMM_SAMPLE not supported on this chip\n"); 356232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002090ull); 357232812Sjmallett} 358232812Sjmallett#else 359232812Sjmallett#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull)) 360232812Sjmallett#endif 361232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362232812Sjmallett#define CVMX_MIO_EMM_STS_MASK CVMX_MIO_EMM_STS_MASK_FUNC() 363232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_STS_MASK_FUNC(void) 364232812Sjmallett{ 365232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 366232812Sjmallett cvmx_warn("CVMX_MIO_EMM_STS_MASK not supported on this chip\n"); 367232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002098ull); 368232812Sjmallett} 369232812Sjmallett#else 370232812Sjmallett#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull)) 371232812Sjmallett#endif 372232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 373232812Sjmallett#define CVMX_MIO_EMM_SWITCH CVMX_MIO_EMM_SWITCH_FUNC() 374232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_SWITCH_FUNC(void) 375232812Sjmallett{ 376232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 377232812Sjmallett cvmx_warn("CVMX_MIO_EMM_SWITCH not supported on this chip\n"); 378232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002048ull); 379232812Sjmallett} 380232812Sjmallett#else 381232812Sjmallett#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull)) 382232812Sjmallett#endif 383232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 384232812Sjmallett#define CVMX_MIO_EMM_WDOG CVMX_MIO_EMM_WDOG_FUNC() 385232812Sjmallettstatic inline uint64_t CVMX_MIO_EMM_WDOG_FUNC(void) 386232812Sjmallett{ 387232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 388232812Sjmallett cvmx_warn("CVMX_MIO_EMM_WDOG not supported on this chip\n"); 389232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000002088ull); 390232812Sjmallett} 391232812Sjmallett#else 392232812Sjmallett#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull)) 393232812Sjmallett#endif 394232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 395215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset) 396215976Sjmallett{ 397215976Sjmallett if (!( 398215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 399215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 401215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 402232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 403232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 405232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 406232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 407215976Sjmallett cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset); 408215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8; 409215976Sjmallett} 410215976Sjmallett#else 411215976Sjmallett#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 412215976Sjmallett#endif 413215976Sjmallett#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 414215976Sjmallett#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 415215976Sjmallett#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull)) 416215976Sjmallett#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull)) 417215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418215976Sjmallett#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC() 419215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void) 420215976Sjmallett{ 421232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 422215976Sjmallett cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n"); 423215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001550ull); 424215976Sjmallett} 425215976Sjmallett#else 426215976Sjmallett#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull)) 427215976Sjmallett#endif 428215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 429215976Sjmallett#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC() 430215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void) 431215976Sjmallett{ 432232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 433215976Sjmallett cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n"); 434215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001420ull); 435215976Sjmallett} 436215976Sjmallett#else 437215976Sjmallett#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull)) 438215976Sjmallett#endif 439215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 440215976Sjmallett#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC() 441215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void) 442215976Sjmallett{ 443232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 444215976Sjmallett cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n"); 445215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001580ull); 446215976Sjmallett} 447215976Sjmallett#else 448215976Sjmallett#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull)) 449215976Sjmallett#endif 450215976Sjmallett#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull)) 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallett#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC() 453215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void) 454215976Sjmallett{ 455232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 456215976Sjmallett cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n"); 457215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001518ull); 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull)) 461215976Sjmallett#endif 462215976Sjmallett#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull)) 463215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464215976Sjmallett#define CVMX_MIO_FUS_READ_TIMES CVMX_MIO_FUS_READ_TIMES_FUNC() 465215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void) 466215976Sjmallett{ 467232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 468215976Sjmallett cvmx_warn("CVMX_MIO_FUS_READ_TIMES not supported on this chip\n"); 469215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001570ull); 470215976Sjmallett} 471215976Sjmallett#else 472215976Sjmallett#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull)) 473215976Sjmallett#endif 474215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 475215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES0 CVMX_MIO_FUS_REPAIR_RES0_FUNC() 476215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void) 477215976Sjmallett{ 478232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 479215976Sjmallett cvmx_warn("CVMX_MIO_FUS_REPAIR_RES0 not supported on this chip\n"); 480215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001558ull); 481215976Sjmallett} 482215976Sjmallett#else 483215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull)) 484215976Sjmallett#endif 485215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 486215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES1 CVMX_MIO_FUS_REPAIR_RES1_FUNC() 487215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void) 488215976Sjmallett{ 489232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 490215976Sjmallett cvmx_warn("CVMX_MIO_FUS_REPAIR_RES1 not supported on this chip\n"); 491215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001560ull); 492215976Sjmallett} 493215976Sjmallett#else 494215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull)) 495215976Sjmallett#endif 496215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 497215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES2 CVMX_MIO_FUS_REPAIR_RES2_FUNC() 498215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void) 499215976Sjmallett{ 500232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 501215976Sjmallett cvmx_warn("CVMX_MIO_FUS_REPAIR_RES2 not supported on this chip\n"); 502215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001568ull); 503215976Sjmallett} 504215976Sjmallett#else 505215976Sjmallett#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 506215976Sjmallett#endif 507215976Sjmallett#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 508215976Sjmallett#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 509215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 510232812Sjmallett#define CVMX_MIO_FUS_TGG CVMX_MIO_FUS_TGG_FUNC() 511232812Sjmallettstatic inline uint64_t CVMX_MIO_FUS_TGG_FUNC(void) 512232812Sjmallett{ 513232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 514232812Sjmallett cvmx_warn("CVMX_MIO_FUS_TGG not supported on this chip\n"); 515232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001428ull); 516232812Sjmallett} 517232812Sjmallett#else 518232812Sjmallett#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull)) 519232812Sjmallett#endif 520232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521215976Sjmallett#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC() 522215976Sjmallettstatic inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void) 523215976Sjmallett{ 524215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 525215976Sjmallett cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n"); 526215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001578ull); 527215976Sjmallett} 528215976Sjmallett#else 529215976Sjmallett#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 530215976Sjmallett#endif 531215976Sjmallett#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 532215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 533215976Sjmallett#define CVMX_MIO_GPIO_COMP CVMX_MIO_GPIO_COMP_FUNC() 534215976Sjmallettstatic inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void) 535215976Sjmallett{ 536232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 537215976Sjmallett cvmx_warn("CVMX_MIO_GPIO_COMP not supported on this chip\n"); 538215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800000000C8ull); 539215976Sjmallett} 540215976Sjmallett#else 541215976Sjmallett#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 542215976Sjmallett#endif 543215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 544215976Sjmallett#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC() 545215976Sjmallettstatic inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void) 546215976Sjmallett{ 547232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 548215976Sjmallett cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n"); 549215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000168ull); 550215976Sjmallett} 551215976Sjmallett#else 552215976Sjmallett#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull)) 553215976Sjmallett#endif 554215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 555215976Sjmallett#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC() 556215976Sjmallettstatic inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void) 557215976Sjmallett{ 558232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 559215976Sjmallett cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n"); 560215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000170ull); 561215976Sjmallett} 562215976Sjmallett#else 563215976Sjmallett#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull)) 564215976Sjmallett#endif 565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566215976Sjmallett#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC() 567215976Sjmallettstatic inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void) 568215976Sjmallett{ 569232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 570215976Sjmallett cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n"); 571215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000178ull); 572215976Sjmallett} 573215976Sjmallett#else 574215976Sjmallett#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 575215976Sjmallett#endif 576215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 577215976Sjmallett#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC() 578215976Sjmallettstatic inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void) 579215976Sjmallett{ 580215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 581215976Sjmallett cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n"); 582215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001448ull); 583215976Sjmallett} 584215976Sjmallett#else 585215976Sjmallett#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 586215976Sjmallett#endif 587215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 588215976Sjmallett#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC() 589215976Sjmallettstatic inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void) 590215976Sjmallett{ 591215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 592215976Sjmallett cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n"); 593215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001440ull); 594215976Sjmallett} 595215976Sjmallett#else 596215976Sjmallett#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 597215976Sjmallett#endif 598215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 599232812Sjmallett#define CVMX_MIO_PTP_CKOUT_HI_INCR CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC() 600232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC(void) 601232812Sjmallett{ 602232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 603232812Sjmallett cvmx_warn("CVMX_MIO_PTP_CKOUT_HI_INCR not supported on this chip\n"); 604232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F40ull); 605232812Sjmallett} 606232812Sjmallett#else 607232812Sjmallett#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull)) 608232812Sjmallett#endif 609232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 610232812Sjmallett#define CVMX_MIO_PTP_CKOUT_LO_INCR CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC() 611232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC(void) 612232812Sjmallett{ 613232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 614232812Sjmallett cvmx_warn("CVMX_MIO_PTP_CKOUT_LO_INCR not supported on this chip\n"); 615232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F48ull); 616232812Sjmallett} 617232812Sjmallett#else 618232812Sjmallett#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull)) 619232812Sjmallett#endif 620232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 621232812Sjmallett#define CVMX_MIO_PTP_CKOUT_THRESH_HI CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC() 622232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC(void) 623232812Sjmallett{ 624232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 625232812Sjmallett cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_HI not supported on this chip\n"); 626232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F38ull); 627232812Sjmallett} 628232812Sjmallett#else 629232812Sjmallett#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull)) 630232812Sjmallett#endif 631232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 632232812Sjmallett#define CVMX_MIO_PTP_CKOUT_THRESH_LO CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC() 633232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC(void) 634232812Sjmallett{ 635232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 636232812Sjmallett cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_LO not supported on this chip\n"); 637232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F30ull); 638232812Sjmallett} 639232812Sjmallett#else 640232812Sjmallett#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull)) 641232812Sjmallett#endif 642232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 643215976Sjmallett#define CVMX_MIO_PTP_CLOCK_CFG CVMX_MIO_PTP_CLOCK_CFG_FUNC() 644215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void) 645215976Sjmallett{ 646232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 647215976Sjmallett cvmx_warn("CVMX_MIO_PTP_CLOCK_CFG not supported on this chip\n"); 648215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F00ull); 649215976Sjmallett} 650215976Sjmallett#else 651215976Sjmallett#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 652215976Sjmallett#endif 653215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 654215976Sjmallett#define CVMX_MIO_PTP_CLOCK_COMP CVMX_MIO_PTP_CLOCK_COMP_FUNC() 655215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void) 656215976Sjmallett{ 657232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 658215976Sjmallett cvmx_warn("CVMX_MIO_PTP_CLOCK_COMP not supported on this chip\n"); 659215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F18ull); 660215976Sjmallett} 661215976Sjmallett#else 662215976Sjmallett#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 663215976Sjmallett#endif 664215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 665215976Sjmallett#define CVMX_MIO_PTP_CLOCK_HI CVMX_MIO_PTP_CLOCK_HI_FUNC() 666215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void) 667215976Sjmallett{ 668232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 669215976Sjmallett cvmx_warn("CVMX_MIO_PTP_CLOCK_HI not supported on this chip\n"); 670215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F10ull); 671215976Sjmallett} 672215976Sjmallett#else 673215976Sjmallett#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 674215976Sjmallett#endif 675215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 676215976Sjmallett#define CVMX_MIO_PTP_CLOCK_LO CVMX_MIO_PTP_CLOCK_LO_FUNC() 677215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void) 678215976Sjmallett{ 679232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 680215976Sjmallett cvmx_warn("CVMX_MIO_PTP_CLOCK_LO not supported on this chip\n"); 681215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F08ull); 682215976Sjmallett} 683215976Sjmallett#else 684215976Sjmallett#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 685215976Sjmallett#endif 686215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 687215976Sjmallett#define CVMX_MIO_PTP_EVT_CNT CVMX_MIO_PTP_EVT_CNT_FUNC() 688215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void) 689215976Sjmallett{ 690232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 691215976Sjmallett cvmx_warn("CVMX_MIO_PTP_EVT_CNT not supported on this chip\n"); 692215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F28ull); 693215976Sjmallett} 694215976Sjmallett#else 695215976Sjmallett#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 696215976Sjmallett#endif 697215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 698232812Sjmallett#define CVMX_MIO_PTP_PHY_1PPS_IN CVMX_MIO_PTP_PHY_1PPS_IN_FUNC() 699232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_PHY_1PPS_IN_FUNC(void) 700232812Sjmallett{ 701232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 702232812Sjmallett cvmx_warn("CVMX_MIO_PTP_PHY_1PPS_IN not supported on this chip\n"); 703232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F70ull); 704232812Sjmallett} 705232812Sjmallett#else 706232812Sjmallett#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) 707232812Sjmallett#endif 708232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 709232812Sjmallett#define CVMX_MIO_PTP_PPS_HI_INCR CVMX_MIO_PTP_PPS_HI_INCR_FUNC() 710232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_PPS_HI_INCR_FUNC(void) 711232812Sjmallett{ 712232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 713232812Sjmallett cvmx_warn("CVMX_MIO_PTP_PPS_HI_INCR not supported on this chip\n"); 714232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F60ull); 715232812Sjmallett} 716232812Sjmallett#else 717232812Sjmallett#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) 718232812Sjmallett#endif 719232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 720232812Sjmallett#define CVMX_MIO_PTP_PPS_LO_INCR CVMX_MIO_PTP_PPS_LO_INCR_FUNC() 721232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_PPS_LO_INCR_FUNC(void) 722232812Sjmallett{ 723232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 724232812Sjmallett cvmx_warn("CVMX_MIO_PTP_PPS_LO_INCR not supported on this chip\n"); 725232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F68ull); 726232812Sjmallett} 727232812Sjmallett#else 728232812Sjmallett#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) 729232812Sjmallett#endif 730232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731232812Sjmallett#define CVMX_MIO_PTP_PPS_THRESH_HI CVMX_MIO_PTP_PPS_THRESH_HI_FUNC() 732232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_PPS_THRESH_HI_FUNC(void) 733232812Sjmallett{ 734232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 735232812Sjmallett cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_HI not supported on this chip\n"); 736232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F58ull); 737232812Sjmallett} 738232812Sjmallett#else 739232812Sjmallett#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) 740232812Sjmallett#endif 741232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 742232812Sjmallett#define CVMX_MIO_PTP_PPS_THRESH_LO CVMX_MIO_PTP_PPS_THRESH_LO_FUNC() 743232812Sjmallettstatic inline uint64_t CVMX_MIO_PTP_PPS_THRESH_LO_FUNC(void) 744232812Sjmallett{ 745232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 746232812Sjmallett cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_LO not supported on this chip\n"); 747232812Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F50ull); 748232812Sjmallett} 749232812Sjmallett#else 750232812Sjmallett#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull)) 751232812Sjmallett#endif 752232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753215976Sjmallett#define CVMX_MIO_PTP_TIMESTAMP CVMX_MIO_PTP_TIMESTAMP_FUNC() 754215976Sjmallettstatic inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void) 755215976Sjmallett{ 756232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 757215976Sjmallett cvmx_warn("CVMX_MIO_PTP_TIMESTAMP not supported on this chip\n"); 758215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000F20ull); 759215976Sjmallett} 760215976Sjmallett#else 761215976Sjmallett#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 762215976Sjmallett#endif 763215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 764232812Sjmallettstatic inline uint64_t CVMX_MIO_QLMX_CFG(unsigned long offset) 765232812Sjmallett{ 766232812Sjmallett if (!( 767232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 2))) || 768232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2))) || 769232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 4))) || 770232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 771232812Sjmallett cvmx_warn("CVMX_MIO_QLMX_CFG(%lu) is invalid on this chip\n", offset); 772232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8; 773232812Sjmallett} 774232812Sjmallett#else 775232812Sjmallett#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) 776232812Sjmallett#endif 777232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 778215976Sjmallett#define CVMX_MIO_RST_BOOT CVMX_MIO_RST_BOOT_FUNC() 779215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void) 780215976Sjmallett{ 781232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 782215976Sjmallett cvmx_warn("CVMX_MIO_RST_BOOT not supported on this chip\n"); 783215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001600ull); 784215976Sjmallett} 785215976Sjmallett#else 786215976Sjmallett#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 787215976Sjmallett#endif 788215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 789215976Sjmallett#define CVMX_MIO_RST_CFG CVMX_MIO_RST_CFG_FUNC() 790215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_CFG_FUNC(void) 791215976Sjmallett{ 792232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 793215976Sjmallett cvmx_warn("CVMX_MIO_RST_CFG not supported on this chip\n"); 794215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001610ull); 795215976Sjmallett} 796215976Sjmallett#else 797215976Sjmallett#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 798215976Sjmallett#endif 799215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 800232812Sjmallett#define CVMX_MIO_RST_CKILL CVMX_MIO_RST_CKILL_FUNC() 801232812Sjmallettstatic inline uint64_t CVMX_MIO_RST_CKILL_FUNC(void) 802232812Sjmallett{ 803232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 804232812Sjmallett cvmx_warn("CVMX_MIO_RST_CKILL not supported on this chip\n"); 805232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001638ull); 806232812Sjmallett} 807232812Sjmallett#else 808232812Sjmallett#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull)) 809232812Sjmallett#endif 810232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 811232812Sjmallettstatic inline uint64_t CVMX_MIO_RST_CNTLX(unsigned long offset) 812232812Sjmallett{ 813232812Sjmallett if (!( 814232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 815232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 816232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 817232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 818232812Sjmallett cvmx_warn("CVMX_MIO_RST_CNTLX(%lu) is invalid on this chip\n", offset); 819232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8; 820232812Sjmallett} 821232812Sjmallett#else 822232812Sjmallett#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8) 823232812Sjmallett#endif 824232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 825215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset) 826215976Sjmallett{ 827215976Sjmallett if (!( 828232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 829232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 830232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 831232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 832232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 833215976Sjmallett cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset); 834215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8; 835215976Sjmallett} 836215976Sjmallett#else 837215976Sjmallett#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 838215976Sjmallett#endif 839215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 840215976Sjmallett#define CVMX_MIO_RST_DELAY CVMX_MIO_RST_DELAY_FUNC() 841215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void) 842215976Sjmallett{ 843232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 844215976Sjmallett cvmx_warn("CVMX_MIO_RST_DELAY not supported on this chip\n"); 845215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001608ull); 846215976Sjmallett} 847215976Sjmallett#else 848215976Sjmallett#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 849215976Sjmallett#endif 850215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 851215976Sjmallett#define CVMX_MIO_RST_INT CVMX_MIO_RST_INT_FUNC() 852215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_INT_FUNC(void) 853215976Sjmallett{ 854232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 855215976Sjmallett cvmx_warn("CVMX_MIO_RST_INT not supported on this chip\n"); 856215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001628ull); 857215976Sjmallett} 858215976Sjmallett#else 859215976Sjmallett#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 860215976Sjmallett#endif 861215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 862215976Sjmallett#define CVMX_MIO_RST_INT_EN CVMX_MIO_RST_INT_EN_FUNC() 863215976Sjmallettstatic inline uint64_t CVMX_MIO_RST_INT_EN_FUNC(void) 864215976Sjmallett{ 865232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 866215976Sjmallett cvmx_warn("CVMX_MIO_RST_INT_EN not supported on this chip\n"); 867215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001630ull); 868215976Sjmallett} 869215976Sjmallett#else 870215976Sjmallett#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull)) 871215976Sjmallett#endif 872215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 873215976Sjmallettstatic inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset) 874215976Sjmallett{ 875215976Sjmallett if (!( 876215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 877215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 878215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 879215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 880215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 881215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 882215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 883232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 884232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 885232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 886232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 887232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 888215976Sjmallett cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset); 889215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512; 890215976Sjmallett} 891215976Sjmallett#else 892215976Sjmallett#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512) 893215976Sjmallett#endif 894215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 895215976Sjmallettstatic inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset) 896215976Sjmallett{ 897215976Sjmallett if (!( 898215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 899215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 900215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 901215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 902215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 903215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 904215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 905232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 906232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 907232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 908232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 909232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 910215976Sjmallett cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset); 911215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512; 912215976Sjmallett} 913215976Sjmallett#else 914215976Sjmallett#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512) 915215976Sjmallett#endif 916215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 917215976Sjmallettstatic inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset) 918215976Sjmallett{ 919215976Sjmallett if (!( 920215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 921215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 922215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 923215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 924215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 925215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 926215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 927232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 928232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 929232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 930232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 931232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 932215976Sjmallett cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset); 933215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512; 934215976Sjmallett} 935215976Sjmallett#else 936215976Sjmallett#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512) 937215976Sjmallett#endif 938215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 939215976Sjmallettstatic inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset) 940215976Sjmallett{ 941215976Sjmallett if (!( 942215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 943215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 944215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 945215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 946215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 947215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 948215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 949232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 950232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 951232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 952232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 953232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 954215976Sjmallett cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset); 955215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512; 956215976Sjmallett} 957215976Sjmallett#else 958215976Sjmallett#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512) 959215976Sjmallett#endif 960215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 961215976Sjmallett#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC() 962215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void) 963215976Sjmallett{ 964215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 965215976Sjmallett cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n"); 966215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000488ull); 967215976Sjmallett} 968215976Sjmallett#else 969215976Sjmallett#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull)) 970215976Sjmallett#endif 971215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 972215976Sjmallett#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC() 973215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void) 974215976Sjmallett{ 975215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 976215976Sjmallett cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n"); 977215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000480ull); 978215976Sjmallett} 979215976Sjmallett#else 980215976Sjmallett#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull)) 981215976Sjmallett#endif 982215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 983215976Sjmallett#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC() 984215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void) 985215976Sjmallett{ 986215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 987215976Sjmallett cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n"); 988215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000520ull); 989215976Sjmallett} 990215976Sjmallett#else 991215976Sjmallett#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull)) 992215976Sjmallett#endif 993215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 994215976Sjmallett#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC() 995215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void) 996215976Sjmallett{ 997215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 998215976Sjmallett cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n"); 999215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000450ull); 1000215976Sjmallett} 1001215976Sjmallett#else 1002215976Sjmallett#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull)) 1003215976Sjmallett#endif 1004215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1005215976Sjmallett#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC() 1006215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void) 1007215976Sjmallett{ 1008215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1009215976Sjmallett cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n"); 1010215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000708ull); 1011215976Sjmallett} 1012215976Sjmallett#else 1013215976Sjmallett#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull)) 1014215976Sjmallett#endif 1015215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1016215976Sjmallett#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC() 1017215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_IER_FUNC(void) 1018215976Sjmallett{ 1019215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1020215976Sjmallett cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n"); 1021215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000408ull); 1022215976Sjmallett} 1023215976Sjmallett#else 1024215976Sjmallett#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull)) 1025215976Sjmallett#endif 1026215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1027215976Sjmallett#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC() 1028215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void) 1029215976Sjmallett{ 1030215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1031215976Sjmallett cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n"); 1032215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000410ull); 1033215976Sjmallett} 1034215976Sjmallett#else 1035215976Sjmallett#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull)) 1036215976Sjmallett#endif 1037215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1038215976Sjmallett#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC() 1039215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void) 1040215976Sjmallett{ 1041215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1042215976Sjmallett cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n"); 1043215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000418ull); 1044215976Sjmallett} 1045215976Sjmallett#else 1046215976Sjmallett#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull)) 1047215976Sjmallett#endif 1048215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1049215976Sjmallett#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC() 1050215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void) 1051215976Sjmallett{ 1052215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1053215976Sjmallett cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n"); 1054215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000428ull); 1055215976Sjmallett} 1056215976Sjmallett#else 1057215976Sjmallett#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull)) 1058215976Sjmallett#endif 1059215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1060215976Sjmallett#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC() 1061215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void) 1062215976Sjmallett{ 1063215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1064215976Sjmallett cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n"); 1065215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000420ull); 1066215976Sjmallett} 1067215976Sjmallett#else 1068215976Sjmallett#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull)) 1069215976Sjmallett#endif 1070215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1071215976Sjmallett#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC() 1072215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void) 1073215976Sjmallett{ 1074215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1075215976Sjmallett cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n"); 1076215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000430ull); 1077215976Sjmallett} 1078215976Sjmallett#else 1079215976Sjmallett#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull)) 1080215976Sjmallett#endif 1081215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1082215976Sjmallett#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC() 1083215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void) 1084215976Sjmallett{ 1085215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1086215976Sjmallett cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n"); 1087215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000400ull); 1088215976Sjmallett} 1089215976Sjmallett#else 1090215976Sjmallett#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull)) 1091215976Sjmallett#endif 1092215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1093215976Sjmallett#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC() 1094215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void) 1095215976Sjmallett{ 1096215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1097215976Sjmallett cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n"); 1098215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000608ull); 1099215976Sjmallett} 1100215976Sjmallett#else 1101215976Sjmallett#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull)) 1102215976Sjmallett#endif 1103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1104215976Sjmallett#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC() 1105215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void) 1106215976Sjmallett{ 1107215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1108215976Sjmallett cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n"); 1109215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000530ull); 1110215976Sjmallett} 1111215976Sjmallett#else 1112215976Sjmallett#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull)) 1113215976Sjmallett#endif 1114215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1115215976Sjmallett#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC() 1116215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void) 1117215976Sjmallett{ 1118215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1119215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n"); 1120215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000620ull); 1121215976Sjmallett} 1122215976Sjmallett#else 1123215976Sjmallett#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull)) 1124215976Sjmallett#endif 1125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1126215976Sjmallett#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC() 1127215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void) 1128215976Sjmallett{ 1129215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1130215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n"); 1131215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000438ull); 1132215976Sjmallett} 1133215976Sjmallett#else 1134215976Sjmallett#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull)) 1135215976Sjmallett#endif 1136215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1137215976Sjmallett#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC() 1138215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void) 1139215976Sjmallett{ 1140215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1141215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n"); 1142215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000630ull); 1143215976Sjmallett} 1144215976Sjmallett#else 1145215976Sjmallett#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull)) 1146215976Sjmallett#endif 1147215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1148215976Sjmallett#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC() 1149215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void) 1150215976Sjmallett{ 1151215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1152215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n"); 1153215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000610ull); 1154215976Sjmallett} 1155215976Sjmallett#else 1156215976Sjmallett#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull)) 1157215976Sjmallett#endif 1158215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1159215976Sjmallett#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC() 1160215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void) 1161215976Sjmallett{ 1162215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1163215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n"); 1164215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000638ull); 1165215976Sjmallett} 1166215976Sjmallett#else 1167215976Sjmallett#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull)) 1168215976Sjmallett#endif 1169215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1170215976Sjmallett#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC() 1171215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void) 1172215976Sjmallett{ 1173215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1174215976Sjmallett cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n"); 1175215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000618ull); 1176215976Sjmallett} 1177215976Sjmallett#else 1178215976Sjmallett#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull)) 1179215976Sjmallett#endif 1180215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1181215976Sjmallett#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC() 1182215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_STT_FUNC(void) 1183215976Sjmallett{ 1184215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1185215976Sjmallett cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n"); 1186215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000700ull); 1187215976Sjmallett} 1188215976Sjmallett#else 1189215976Sjmallett#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull)) 1190215976Sjmallett#endif 1191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1192215976Sjmallett#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC() 1193215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void) 1194215976Sjmallett{ 1195215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1196215976Sjmallett cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n"); 1197215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000600ull); 1198215976Sjmallett} 1199215976Sjmallett#else 1200215976Sjmallett#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull)) 1201215976Sjmallett#endif 1202215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1203215976Sjmallett#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC() 1204215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void) 1205215976Sjmallett{ 1206215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1207215976Sjmallett cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n"); 1208215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000528ull); 1209215976Sjmallett} 1210215976Sjmallett#else 1211215976Sjmallett#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull)) 1212215976Sjmallett#endif 1213215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1214215976Sjmallett#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC() 1215215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_THR_FUNC(void) 1216215976Sjmallett{ 1217215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1218215976Sjmallett cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n"); 1219215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000440ull); 1220215976Sjmallett} 1221215976Sjmallett#else 1222215976Sjmallett#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull)) 1223215976Sjmallett#endif 1224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1225215976Sjmallett#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC() 1226215976Sjmallettstatic inline uint64_t CVMX_MIO_UART2_USR_FUNC(void) 1227215976Sjmallett{ 1228215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1229215976Sjmallett cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n"); 1230215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000538ull); 1231215976Sjmallett} 1232215976Sjmallett#else 1233215976Sjmallett#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull)) 1234215976Sjmallett#endif 1235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1236215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset) 1237215976Sjmallett{ 1238215976Sjmallett if (!( 1239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1244215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1245215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1246232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1247232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1248232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1251215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset); 1252215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024; 1253215976Sjmallett} 1254215976Sjmallett#else 1255215976Sjmallett#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024) 1256215976Sjmallett#endif 1257215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1258215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset) 1259215976Sjmallett{ 1260215976Sjmallett if (!( 1261215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1262215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1265215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1266215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1267215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1273215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset); 1274215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024; 1275215976Sjmallett} 1276215976Sjmallett#else 1277215976Sjmallett#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024) 1278215976Sjmallett#endif 1279215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1280215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset) 1281215976Sjmallett{ 1282215976Sjmallett if (!( 1283215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1288215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1289215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1290232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1291232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1292232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1293232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1294232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1295215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset); 1296215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024; 1297215976Sjmallett} 1298215976Sjmallett#else 1299215976Sjmallett#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024) 1300215976Sjmallett#endif 1301215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1302215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset) 1303215976Sjmallett{ 1304215976Sjmallett if (!( 1305215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1306215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1307215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1308215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1309215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1310215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1311215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1312232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1317215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset); 1318215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024; 1319215976Sjmallett} 1320215976Sjmallett#else 1321215976Sjmallett#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024) 1322215976Sjmallett#endif 1323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1324215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset) 1325215976Sjmallett{ 1326215976Sjmallett if (!( 1327215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1328215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1338232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1339215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset); 1340215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024; 1341215976Sjmallett} 1342215976Sjmallett#else 1343215976Sjmallett#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024) 1344215976Sjmallett#endif 1345215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1346215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset) 1347215976Sjmallett{ 1348215976Sjmallett if (!( 1349215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1351215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1352215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1353215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1354215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1355215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1356232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1357232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1358232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1360232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1361215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset); 1362215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024; 1363215976Sjmallett} 1364215976Sjmallett#else 1365215976Sjmallett#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024) 1366215976Sjmallett#endif 1367215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1368215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset) 1369215976Sjmallett{ 1370215976Sjmallett if (!( 1371215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1372215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1373215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1378232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1379232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1380232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1381232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1382232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1383215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset); 1384215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024; 1385215976Sjmallett} 1386215976Sjmallett#else 1387215976Sjmallett#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024) 1388215976Sjmallett#endif 1389215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1390215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset) 1391215976Sjmallett{ 1392215976Sjmallett if (!( 1393215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1394215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1395215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1396215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1397215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1398215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1399215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1400232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1401232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1402232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1403232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1405215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset); 1406215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024; 1407215976Sjmallett} 1408215976Sjmallett#else 1409215976Sjmallett#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024) 1410215976Sjmallett#endif 1411215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1412215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset) 1413215976Sjmallett{ 1414215976Sjmallett if (!( 1415215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1416215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1417215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1418215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1419215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1420215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1421215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1422232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1423232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1424232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1425232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1426232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1427215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset); 1428215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024; 1429215976Sjmallett} 1430215976Sjmallett#else 1431215976Sjmallett#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024) 1432215976Sjmallett#endif 1433215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1434215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset) 1435215976Sjmallett{ 1436215976Sjmallett if (!( 1437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1439215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1440215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1441215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1442215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1443215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1444232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1445232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1446232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1447232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1448232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1449215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset); 1450215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024; 1451215976Sjmallett} 1452215976Sjmallett#else 1453215976Sjmallett#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024) 1454215976Sjmallett#endif 1455215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1456215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset) 1457215976Sjmallett{ 1458215976Sjmallett if (!( 1459215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1460215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1461215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1462215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1463215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1464215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1465215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1466232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1467232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1468232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1469232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1470232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1471215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset); 1472215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024; 1473215976Sjmallett} 1474215976Sjmallett#else 1475215976Sjmallett#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024) 1476215976Sjmallett#endif 1477215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1478215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset) 1479215976Sjmallett{ 1480215976Sjmallett if (!( 1481215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1482215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1483215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1484215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1485215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1486215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1487215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1488232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1489232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1490232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1491232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1492232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1493215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset); 1494215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024; 1495215976Sjmallett} 1496215976Sjmallett#else 1497215976Sjmallett#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024) 1498215976Sjmallett#endif 1499215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1500215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset) 1501215976Sjmallett{ 1502215976Sjmallett if (!( 1503215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1504215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1505215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1506215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1507215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1508215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1509215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1510232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1511232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1512232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1513232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1514232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1515215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset); 1516215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024; 1517215976Sjmallett} 1518215976Sjmallett#else 1519215976Sjmallett#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024) 1520215976Sjmallett#endif 1521215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1522215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset) 1523215976Sjmallett{ 1524215976Sjmallett if (!( 1525215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1526215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1527215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1528215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1529215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1530215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1531215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1532232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1533232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1534232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1535232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1536232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1537215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset); 1538215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024; 1539215976Sjmallett} 1540215976Sjmallett#else 1541215976Sjmallett#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024) 1542215976Sjmallett#endif 1543215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1544215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset) 1545215976Sjmallett{ 1546215976Sjmallett if (!( 1547215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1548215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1549215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1550215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1551215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1552215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1553215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1555232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1558232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1559215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset); 1560215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024; 1561215976Sjmallett} 1562215976Sjmallett#else 1563215976Sjmallett#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024) 1564215976Sjmallett#endif 1565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1566215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset) 1567215976Sjmallett{ 1568215976Sjmallett if (!( 1569215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1570215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1571215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1572215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1573215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1574215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1575215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1576232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1577232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1578232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1579232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1580232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1581215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset); 1582215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024; 1583215976Sjmallett} 1584215976Sjmallett#else 1585215976Sjmallett#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024) 1586215976Sjmallett#endif 1587215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1588215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset) 1589215976Sjmallett{ 1590215976Sjmallett if (!( 1591215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1592215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1593215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1594215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1595215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1596215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1597215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1598232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1599232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1600232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1601232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1602232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1603215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset); 1604215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024; 1605215976Sjmallett} 1606215976Sjmallett#else 1607215976Sjmallett#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024) 1608215976Sjmallett#endif 1609215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1610215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset) 1611215976Sjmallett{ 1612215976Sjmallett if (!( 1613215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1614215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1615215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1616215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1617215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1618215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1619215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1620232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1621232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1622232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1623232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1624232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1625215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset); 1626215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024; 1627215976Sjmallett} 1628215976Sjmallett#else 1629215976Sjmallett#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024) 1630215976Sjmallett#endif 1631215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1632215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset) 1633215976Sjmallett{ 1634215976Sjmallett if (!( 1635215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1636215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1637215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1638215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1639215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1640215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1641215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1642232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1643232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1644232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1645232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1646232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1647215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset); 1648215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024; 1649215976Sjmallett} 1650215976Sjmallett#else 1651215976Sjmallett#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024) 1652215976Sjmallett#endif 1653215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1654215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset) 1655215976Sjmallett{ 1656215976Sjmallett if (!( 1657215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1658215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1659215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1660215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1661215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1662215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1663215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1664232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1665232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1666232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1667232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1668232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1669215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset); 1670215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024; 1671215976Sjmallett} 1672215976Sjmallett#else 1673215976Sjmallett#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024) 1674215976Sjmallett#endif 1675215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1676215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset) 1677215976Sjmallett{ 1678215976Sjmallett if (!( 1679215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1680215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1681215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1682215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1683215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1684215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1685215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1686232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1687232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1688232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1689232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1690232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1691215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset); 1692215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024; 1693215976Sjmallett} 1694215976Sjmallett#else 1695215976Sjmallett#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024) 1696215976Sjmallett#endif 1697215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1698215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset) 1699215976Sjmallett{ 1700215976Sjmallett if (!( 1701215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1702215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1703215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1704215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1705215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1706215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1707215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1708232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1709232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1710232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1711232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1712232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1713215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset); 1714215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024; 1715215976Sjmallett} 1716215976Sjmallett#else 1717215976Sjmallett#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024) 1718215976Sjmallett#endif 1719215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1720215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset) 1721215976Sjmallett{ 1722215976Sjmallett if (!( 1723215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1724215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1725215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1726215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1727215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1728215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1729215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1730232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1731232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1732232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1733232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1734232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1735215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset); 1736215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024; 1737215976Sjmallett} 1738215976Sjmallett#else 1739215976Sjmallett#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024) 1740215976Sjmallett#endif 1741215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1742215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset) 1743215976Sjmallett{ 1744215976Sjmallett if (!( 1745215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1746215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1747215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1748215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1749215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1750215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1751215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1752232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1753232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1754232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1755232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1756232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1757215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset); 1758215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024; 1759215976Sjmallett} 1760215976Sjmallett#else 1761215976Sjmallett#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024) 1762215976Sjmallett#endif 1763215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1764215976Sjmallettstatic inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset) 1765215976Sjmallett{ 1766215976Sjmallett if (!( 1767215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1768215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1769215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1770215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1771215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1772215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1773215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1774232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1775232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1776232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1777232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1778232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1779215976Sjmallett cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset); 1780215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024; 1781215976Sjmallett} 1782215976Sjmallett#else 1783215976Sjmallett#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024) 1784215976Sjmallett#endif 1785215976Sjmallett 1786215976Sjmallett/** 1787215976Sjmallett * cvmx_mio_boot_bist_stat 1788215976Sjmallett * 1789215976Sjmallett * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register 1790215976Sjmallett * 1791215976Sjmallett * Contains the BIST status for the MIO boot memories. '0' = pass, '1' = fail. 1792215976Sjmallett */ 1793232812Sjmallettunion cvmx_mio_boot_bist_stat { 1794215976Sjmallett uint64_t u64; 1795232812Sjmallett struct cvmx_mio_boot_bist_stat_s { 1796232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1797215976Sjmallett uint64_t reserved_0_63 : 64; 1798215976Sjmallett#else 1799215976Sjmallett uint64_t reserved_0_63 : 64; 1800215976Sjmallett#endif 1801215976Sjmallett } s; 1802232812Sjmallett struct cvmx_mio_boot_bist_stat_cn30xx { 1803232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1804215976Sjmallett uint64_t reserved_4_63 : 60; 1805215976Sjmallett uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */ 1806215976Sjmallett uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */ 1807215976Sjmallett uint64_t loc : 1; /**< Local memory BIST status */ 1808215976Sjmallett uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1809215976Sjmallett#else 1810215976Sjmallett uint64_t ncbi : 1; 1811215976Sjmallett uint64_t loc : 1; 1812215976Sjmallett uint64_t ncbo_0 : 1; 1813215976Sjmallett uint64_t ncbo_1 : 1; 1814215976Sjmallett uint64_t reserved_4_63 : 60; 1815215976Sjmallett#endif 1816215976Sjmallett } cn30xx; 1817215976Sjmallett struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; 1818232812Sjmallett struct cvmx_mio_boot_bist_stat_cn38xx { 1819232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1820215976Sjmallett uint64_t reserved_3_63 : 61; 1821215976Sjmallett uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1822215976Sjmallett uint64_t loc : 1; /**< Local memory BIST status */ 1823215976Sjmallett uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1824215976Sjmallett#else 1825215976Sjmallett uint64_t ncbi : 1; 1826215976Sjmallett uint64_t loc : 1; 1827215976Sjmallett uint64_t ncbo_0 : 1; 1828215976Sjmallett uint64_t reserved_3_63 : 61; 1829215976Sjmallett#endif 1830215976Sjmallett } cn38xx; 1831215976Sjmallett struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; 1832232812Sjmallett struct cvmx_mio_boot_bist_stat_cn50xx { 1833232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1834215976Sjmallett uint64_t reserved_6_63 : 58; 1835215976Sjmallett uint64_t pcm_1 : 1; /**< PCM memory 1 BIST status */ 1836215976Sjmallett uint64_t pcm_0 : 1; /**< PCM memory 0 BIST status */ 1837215976Sjmallett uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */ 1838215976Sjmallett uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */ 1839232812Sjmallett uint64_t loc : 1; /**< Local memory region BIST status */ 1840215976Sjmallett uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1841215976Sjmallett#else 1842215976Sjmallett uint64_t ncbi : 1; 1843215976Sjmallett uint64_t loc : 1; 1844215976Sjmallett uint64_t ncbo_0 : 1; 1845215976Sjmallett uint64_t ncbo_1 : 1; 1846215976Sjmallett uint64_t pcm_0 : 1; 1847215976Sjmallett uint64_t pcm_1 : 1; 1848215976Sjmallett uint64_t reserved_6_63 : 58; 1849215976Sjmallett#endif 1850215976Sjmallett } cn50xx; 1851232812Sjmallett struct cvmx_mio_boot_bist_stat_cn52xx { 1852232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1853215976Sjmallett uint64_t reserved_6_63 : 58; 1854215976Sjmallett uint64_t ndf : 2; /**< NAND flash BIST status */ 1855215976Sjmallett uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1856215976Sjmallett uint64_t dma : 1; /**< DMA memory BIST status */ 1857215976Sjmallett uint64_t loc : 1; /**< Local memory BIST status */ 1858215976Sjmallett uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1859215976Sjmallett#else 1860215976Sjmallett uint64_t ncbi : 1; 1861215976Sjmallett uint64_t loc : 1; 1862215976Sjmallett uint64_t dma : 1; 1863215976Sjmallett uint64_t ncbo_0 : 1; 1864215976Sjmallett uint64_t ndf : 2; 1865215976Sjmallett uint64_t reserved_6_63 : 58; 1866215976Sjmallett#endif 1867215976Sjmallett } cn52xx; 1868232812Sjmallett struct cvmx_mio_boot_bist_stat_cn52xxp1 { 1869232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1870215976Sjmallett uint64_t reserved_4_63 : 60; 1871215976Sjmallett uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1872215976Sjmallett uint64_t dma : 1; /**< DMA memory BIST status */ 1873232812Sjmallett uint64_t loc : 1; /**< Local memory region BIST status */ 1874215976Sjmallett uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1875215976Sjmallett#else 1876215976Sjmallett uint64_t ncbi : 1; 1877215976Sjmallett uint64_t loc : 1; 1878215976Sjmallett uint64_t dma : 1; 1879215976Sjmallett uint64_t ncbo_0 : 1; 1880215976Sjmallett uint64_t reserved_4_63 : 60; 1881215976Sjmallett#endif 1882215976Sjmallett } cn52xxp1; 1883215976Sjmallett struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; 1884215976Sjmallett struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 1885215976Sjmallett struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 1886215976Sjmallett struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 1887232812Sjmallett struct cvmx_mio_boot_bist_stat_cn61xx { 1888232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1889232812Sjmallett uint64_t reserved_12_63 : 52; 1890232812Sjmallett uint64_t stat : 12; /**< BIST status */ 1891232812Sjmallett#else 1892232812Sjmallett uint64_t stat : 12; 1893232812Sjmallett uint64_t reserved_12_63 : 52; 1894232812Sjmallett#endif 1895232812Sjmallett } cn61xx; 1896232812Sjmallett struct cvmx_mio_boot_bist_stat_cn63xx { 1897232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1898215976Sjmallett uint64_t reserved_9_63 : 55; 1899215976Sjmallett uint64_t stat : 9; /**< BIST status */ 1900215976Sjmallett#else 1901215976Sjmallett uint64_t stat : 9; 1902215976Sjmallett uint64_t reserved_9_63 : 55; 1903215976Sjmallett#endif 1904215976Sjmallett } cn63xx; 1905215976Sjmallett struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 1906232812Sjmallett struct cvmx_mio_boot_bist_stat_cn66xx { 1907232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1908232812Sjmallett uint64_t reserved_10_63 : 54; 1909232812Sjmallett uint64_t stat : 10; /**< BIST status */ 1910232812Sjmallett#else 1911232812Sjmallett uint64_t stat : 10; 1912232812Sjmallett uint64_t reserved_10_63 : 54; 1913232812Sjmallett#endif 1914232812Sjmallett } cn66xx; 1915232812Sjmallett struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; 1916232812Sjmallett struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; 1917232812Sjmallett struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; 1918215976Sjmallett}; 1919215976Sjmalletttypedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t; 1920215976Sjmallett 1921215976Sjmallett/** 1922215976Sjmallett * cvmx_mio_boot_comp 1923215976Sjmallett * 1924215976Sjmallett * MIO_BOOT_COMP = MIO Boot Compensation Register 1925215976Sjmallett * 1926215976Sjmallett * Reset value is as follows: 1927215976Sjmallett * 1928215976Sjmallett * no pullups, PCTL=38, NCTL=30 (25 ohm termination) 1929215976Sjmallett * pullup on boot_ad[9], PCTL=19, NCTL=15 (50 ohm termination) 1930215976Sjmallett * pullup on boot_ad[10], PCTL=15, NCTL=12 (65 ohm termination) 1931215976Sjmallett * pullups on boot_ad[10:9], PCTL=15, NCTL=12 (65 ohm termination) 1932215976Sjmallett */ 1933232812Sjmallettunion cvmx_mio_boot_comp { 1934215976Sjmallett uint64_t u64; 1935232812Sjmallett struct cvmx_mio_boot_comp_s { 1936232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1937215976Sjmallett uint64_t reserved_0_63 : 64; 1938215976Sjmallett#else 1939215976Sjmallett uint64_t reserved_0_63 : 64; 1940215976Sjmallett#endif 1941215976Sjmallett } s; 1942232812Sjmallett struct cvmx_mio_boot_comp_cn50xx { 1943232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1944215976Sjmallett uint64_t reserved_10_63 : 54; 1945215976Sjmallett uint64_t pctl : 5; /**< Boot bus PCTL */ 1946215976Sjmallett uint64_t nctl : 5; /**< Boot bus NCTL */ 1947215976Sjmallett#else 1948215976Sjmallett uint64_t nctl : 5; 1949215976Sjmallett uint64_t pctl : 5; 1950215976Sjmallett uint64_t reserved_10_63 : 54; 1951215976Sjmallett#endif 1952215976Sjmallett } cn50xx; 1953215976Sjmallett struct cvmx_mio_boot_comp_cn50xx cn52xx; 1954215976Sjmallett struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 1955215976Sjmallett struct cvmx_mio_boot_comp_cn50xx cn56xx; 1956215976Sjmallett struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 1957232812Sjmallett struct cvmx_mio_boot_comp_cn61xx { 1958232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1959215976Sjmallett uint64_t reserved_12_63 : 52; 1960215976Sjmallett uint64_t pctl : 6; /**< Boot bus PCTL */ 1961215976Sjmallett uint64_t nctl : 6; /**< Boot bus NCTL */ 1962215976Sjmallett#else 1963215976Sjmallett uint64_t nctl : 6; 1964215976Sjmallett uint64_t pctl : 6; 1965215976Sjmallett uint64_t reserved_12_63 : 52; 1966215976Sjmallett#endif 1967232812Sjmallett } cn61xx; 1968232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cn63xx; 1969232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cn63xxp1; 1970232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cn66xx; 1971232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cn68xx; 1972232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cn68xxp1; 1973232812Sjmallett struct cvmx_mio_boot_comp_cn61xx cnf71xx; 1974215976Sjmallett}; 1975215976Sjmalletttypedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t; 1976215976Sjmallett 1977215976Sjmallett/** 1978215976Sjmallett * cvmx_mio_boot_dma_cfg# 1979215976Sjmallett * 1980215976Sjmallett * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines) 1981215976Sjmallett * 1982215976Sjmallett * SIZE is specified in number of bus transfers, where one transfer is equal to the following number 1983215976Sjmallett * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]: 1984215976Sjmallett * 1985215976Sjmallett * WIDTH DDR Transfer Size (bytes) 1986215976Sjmallett * ---------------------------------------- 1987215976Sjmallett * 0 0 2 1988215976Sjmallett * 0 1 4 1989215976Sjmallett * 1 0 4 1990215976Sjmallett * 1 1 8 1991215976Sjmallett * 1992215976Sjmallett * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1). 1993215976Sjmallett */ 1994232812Sjmallettunion cvmx_mio_boot_dma_cfgx { 1995215976Sjmallett uint64_t u64; 1996232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s { 1997232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1998215976Sjmallett uint64_t en : 1; /**< DMA Engine X enable */ 1999215976Sjmallett uint64_t rw : 1; /**< DMA Engine X R/W bit (0 = read, 1 = write) */ 2000215976Sjmallett uint64_t clr : 1; /**< DMA Engine X clear EN on device terminated burst */ 2001215976Sjmallett uint64_t reserved_60_60 : 1; 2002215976Sjmallett uint64_t swap32 : 1; /**< DMA Engine X 32 bit swap */ 2003215976Sjmallett uint64_t swap16 : 1; /**< DMA Engine X 16 bit swap */ 2004215976Sjmallett uint64_t swap8 : 1; /**< DMA Engine X 8 bit swap */ 2005215976Sjmallett uint64_t endian : 1; /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */ 2006215976Sjmallett uint64_t size : 20; /**< DMA Engine X size */ 2007215976Sjmallett uint64_t adr : 36; /**< DMA Engine X address */ 2008215976Sjmallett#else 2009215976Sjmallett uint64_t adr : 36; 2010215976Sjmallett uint64_t size : 20; 2011215976Sjmallett uint64_t endian : 1; 2012215976Sjmallett uint64_t swap8 : 1; 2013215976Sjmallett uint64_t swap16 : 1; 2014215976Sjmallett uint64_t swap32 : 1; 2015215976Sjmallett uint64_t reserved_60_60 : 1; 2016215976Sjmallett uint64_t clr : 1; 2017215976Sjmallett uint64_t rw : 1; 2018215976Sjmallett uint64_t en : 1; 2019215976Sjmallett#endif 2020215976Sjmallett } s; 2021215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn52xx; 2022215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 2023215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn56xx; 2024215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 2025232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn61xx; 2026215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn63xx; 2027215976Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 2028232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn66xx; 2029232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn68xx; 2030232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; 2031232812Sjmallett struct cvmx_mio_boot_dma_cfgx_s cnf71xx; 2032215976Sjmallett}; 2033215976Sjmalletttypedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t; 2034215976Sjmallett 2035215976Sjmallett/** 2036215976Sjmallett * cvmx_mio_boot_dma_int# 2037215976Sjmallett * 2038215976Sjmallett * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines) 2039215976Sjmallett * 2040215976Sjmallett */ 2041232812Sjmallettunion cvmx_mio_boot_dma_intx { 2042215976Sjmallett uint64_t u64; 2043232812Sjmallett struct cvmx_mio_boot_dma_intx_s { 2044232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2045215976Sjmallett uint64_t reserved_2_63 : 62; 2046215976Sjmallett uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt */ 2047215976Sjmallett uint64_t done : 1; /**< DMA Engine X request completion interrupt */ 2048215976Sjmallett#else 2049215976Sjmallett uint64_t done : 1; 2050215976Sjmallett uint64_t dmarq : 1; 2051215976Sjmallett uint64_t reserved_2_63 : 62; 2052215976Sjmallett#endif 2053215976Sjmallett } s; 2054215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn52xx; 2055215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn52xxp1; 2056215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn56xx; 2057215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn56xxp1; 2058232812Sjmallett struct cvmx_mio_boot_dma_intx_s cn61xx; 2059215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn63xx; 2060215976Sjmallett struct cvmx_mio_boot_dma_intx_s cn63xxp1; 2061232812Sjmallett struct cvmx_mio_boot_dma_intx_s cn66xx; 2062232812Sjmallett struct cvmx_mio_boot_dma_intx_s cn68xx; 2063232812Sjmallett struct cvmx_mio_boot_dma_intx_s cn68xxp1; 2064232812Sjmallett struct cvmx_mio_boot_dma_intx_s cnf71xx; 2065215976Sjmallett}; 2066215976Sjmalletttypedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t; 2067215976Sjmallett 2068215976Sjmallett/** 2069215976Sjmallett * cvmx_mio_boot_dma_int_en# 2070215976Sjmallett * 2071215976Sjmallett * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines) 2072215976Sjmallett * 2073215976Sjmallett */ 2074232812Sjmallettunion cvmx_mio_boot_dma_int_enx { 2075215976Sjmallett uint64_t u64; 2076232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s { 2077232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2078215976Sjmallett uint64_t reserved_2_63 : 62; 2079215976Sjmallett uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt enable */ 2080215976Sjmallett uint64_t done : 1; /**< DMA Engine X request completion interrupt enable */ 2081215976Sjmallett#else 2082215976Sjmallett uint64_t done : 1; 2083215976Sjmallett uint64_t dmarq : 1; 2084215976Sjmallett uint64_t reserved_2_63 : 62; 2085215976Sjmallett#endif 2086215976Sjmallett } s; 2087215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn52xx; 2088215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 2089215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn56xx; 2090215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 2091232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn61xx; 2092215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn63xx; 2093215976Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 2094232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn66xx; 2095232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn68xx; 2096232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; 2097232812Sjmallett struct cvmx_mio_boot_dma_int_enx_s cnf71xx; 2098215976Sjmallett}; 2099215976Sjmalletttypedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t; 2100215976Sjmallett 2101215976Sjmallett/** 2102215976Sjmallett * cvmx_mio_boot_dma_tim# 2103215976Sjmallett * 2104215976Sjmallett * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines) 2105215976Sjmallett * 2106215976Sjmallett * DMACK_PI inverts the assertion level of boot_dmack[n]. The default polarity of boot_dmack[1:0] is 2107215976Sjmallett * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high 2108215976Sjmallett * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity). 2109215976Sjmallett * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default 2110215976Sjmallett * polarity on engine n. To interface with CF cards in True IDE Mode, either a pullup should be placed 2111215976Sjmallett * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set. 2112215976Sjmallett * 2113215976Sjmallett * DMARQ_PI inverts the assertion level of boot_dmarq[n]. The default polarity of boot_dmarq[1:0] is 2114215976Sjmallett * active high, thus setting the polarity inversion bits changes the polarity to active low. To 2115215976Sjmallett * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear. 2116215976Sjmallett * 2117215976Sjmallett * TIM_MULT specifies the timing multiplier for an engine. The timing multiplier applies to all timing 2118215976Sjmallett * parameters, except for DMARQ and RD_DLY, which simply count eclks. TIM_MULT is encoded as follows: 2119215976Sjmallett * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x. 2120215976Sjmallett * 2121215976Sjmallett * RD_DLY specifies the read sample delay in eclk cycles for an engine. For reads, the data bus is 2122215976Sjmallett * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode). 2123215976Sjmallett * This parameter can delay that sampling edge by up to 7 eclks. Note: the number of eclk cycles 2124215976Sjmallett * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY. 2125215976Sjmallett * 2126215976Sjmallett * If DDR is set, then WE_N must be less than WE_A. 2127215976Sjmallett */ 2128232812Sjmallettunion cvmx_mio_boot_dma_timx { 2129215976Sjmallett uint64_t u64; 2130232812Sjmallett struct cvmx_mio_boot_dma_timx_s { 2131232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2132215976Sjmallett uint64_t dmack_pi : 1; /**< DMA Engine X DMA ack polarity inversion */ 2133215976Sjmallett uint64_t dmarq_pi : 1; /**< DMA Engine X DMA request polarity inversion */ 2134215976Sjmallett uint64_t tim_mult : 2; /**< DMA Engine X timing multiplier */ 2135215976Sjmallett uint64_t rd_dly : 3; /**< DMA Engine X read sample delay */ 2136215976Sjmallett uint64_t ddr : 1; /**< DMA Engine X DDR mode */ 2137215976Sjmallett uint64_t width : 1; /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */ 2138215976Sjmallett uint64_t reserved_48_54 : 7; 2139215976Sjmallett uint64_t pause : 6; /**< DMA Engine X pause count */ 2140215976Sjmallett uint64_t dmack_h : 6; /**< DMA Engine X DMA ack hold count */ 2141215976Sjmallett uint64_t we_n : 6; /**< DMA Engine X write enable negated count */ 2142215976Sjmallett uint64_t we_a : 6; /**< DMA Engine X write enable asserted count */ 2143215976Sjmallett uint64_t oe_n : 6; /**< DMA Engine X output enable negated count */ 2144215976Sjmallett uint64_t oe_a : 6; /**< DMA Engine X output enable asserted count */ 2145215976Sjmallett uint64_t dmack_s : 6; /**< DMA Engine X DMA ack setup count */ 2146215976Sjmallett uint64_t dmarq : 6; /**< DMA Engine X DMA request count (must be non-zero) */ 2147215976Sjmallett#else 2148215976Sjmallett uint64_t dmarq : 6; 2149215976Sjmallett uint64_t dmack_s : 6; 2150215976Sjmallett uint64_t oe_a : 6; 2151215976Sjmallett uint64_t oe_n : 6; 2152215976Sjmallett uint64_t we_a : 6; 2153215976Sjmallett uint64_t we_n : 6; 2154215976Sjmallett uint64_t dmack_h : 6; 2155215976Sjmallett uint64_t pause : 6; 2156215976Sjmallett uint64_t reserved_48_54 : 7; 2157215976Sjmallett uint64_t width : 1; 2158215976Sjmallett uint64_t ddr : 1; 2159215976Sjmallett uint64_t rd_dly : 3; 2160215976Sjmallett uint64_t tim_mult : 2; 2161215976Sjmallett uint64_t dmarq_pi : 1; 2162215976Sjmallett uint64_t dmack_pi : 1; 2163215976Sjmallett#endif 2164215976Sjmallett } s; 2165215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn52xx; 2166215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn52xxp1; 2167215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn56xx; 2168215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn56xxp1; 2169232812Sjmallett struct cvmx_mio_boot_dma_timx_s cn61xx; 2170215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn63xx; 2171215976Sjmallett struct cvmx_mio_boot_dma_timx_s cn63xxp1; 2172232812Sjmallett struct cvmx_mio_boot_dma_timx_s cn66xx; 2173232812Sjmallett struct cvmx_mio_boot_dma_timx_s cn68xx; 2174232812Sjmallett struct cvmx_mio_boot_dma_timx_s cn68xxp1; 2175232812Sjmallett struct cvmx_mio_boot_dma_timx_s cnf71xx; 2176215976Sjmallett}; 2177215976Sjmalletttypedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t; 2178215976Sjmallett 2179215976Sjmallett/** 2180215976Sjmallett * cvmx_mio_boot_err 2181215976Sjmallett * 2182215976Sjmallett * MIO_BOOT_ERR = MIO Boot Error Register 2183215976Sjmallett * 2184215976Sjmallett * Contains the address decode error and wait mode error bits. Address decode error is set when a 2185232812Sjmallett * boot bus access does not hit in any of the 8 remote regions or 2 local memory regions. Wait mode error is 2186215976Sjmallett * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles. 2187215976Sjmallett */ 2188232812Sjmallettunion cvmx_mio_boot_err { 2189215976Sjmallett uint64_t u64; 2190232812Sjmallett struct cvmx_mio_boot_err_s { 2191232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2192215976Sjmallett uint64_t reserved_2_63 : 62; 2193215976Sjmallett uint64_t wait_err : 1; /**< Wait mode error */ 2194215976Sjmallett uint64_t adr_err : 1; /**< Address decode error */ 2195215976Sjmallett#else 2196215976Sjmallett uint64_t adr_err : 1; 2197215976Sjmallett uint64_t wait_err : 1; 2198215976Sjmallett uint64_t reserved_2_63 : 62; 2199215976Sjmallett#endif 2200215976Sjmallett } s; 2201215976Sjmallett struct cvmx_mio_boot_err_s cn30xx; 2202215976Sjmallett struct cvmx_mio_boot_err_s cn31xx; 2203215976Sjmallett struct cvmx_mio_boot_err_s cn38xx; 2204215976Sjmallett struct cvmx_mio_boot_err_s cn38xxp2; 2205215976Sjmallett struct cvmx_mio_boot_err_s cn50xx; 2206215976Sjmallett struct cvmx_mio_boot_err_s cn52xx; 2207215976Sjmallett struct cvmx_mio_boot_err_s cn52xxp1; 2208215976Sjmallett struct cvmx_mio_boot_err_s cn56xx; 2209215976Sjmallett struct cvmx_mio_boot_err_s cn56xxp1; 2210215976Sjmallett struct cvmx_mio_boot_err_s cn58xx; 2211215976Sjmallett struct cvmx_mio_boot_err_s cn58xxp1; 2212232812Sjmallett struct cvmx_mio_boot_err_s cn61xx; 2213215976Sjmallett struct cvmx_mio_boot_err_s cn63xx; 2214215976Sjmallett struct cvmx_mio_boot_err_s cn63xxp1; 2215232812Sjmallett struct cvmx_mio_boot_err_s cn66xx; 2216232812Sjmallett struct cvmx_mio_boot_err_s cn68xx; 2217232812Sjmallett struct cvmx_mio_boot_err_s cn68xxp1; 2218232812Sjmallett struct cvmx_mio_boot_err_s cnf71xx; 2219215976Sjmallett}; 2220215976Sjmalletttypedef union cvmx_mio_boot_err cvmx_mio_boot_err_t; 2221215976Sjmallett 2222215976Sjmallett/** 2223215976Sjmallett * cvmx_mio_boot_int 2224215976Sjmallett * 2225215976Sjmallett * MIO_BOOT_INT = MIO Boot Interrupt Register 2226215976Sjmallett * 2227215976Sjmallett * Contains the interrupt enable bits for address decode error and wait mode error. 2228215976Sjmallett */ 2229232812Sjmallettunion cvmx_mio_boot_int { 2230215976Sjmallett uint64_t u64; 2231232812Sjmallett struct cvmx_mio_boot_int_s { 2232232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2233215976Sjmallett uint64_t reserved_2_63 : 62; 2234215976Sjmallett uint64_t wait_int : 1; /**< Wait mode error interrupt enable */ 2235215976Sjmallett uint64_t adr_int : 1; /**< Address decode error interrupt enable */ 2236215976Sjmallett#else 2237215976Sjmallett uint64_t adr_int : 1; 2238215976Sjmallett uint64_t wait_int : 1; 2239215976Sjmallett uint64_t reserved_2_63 : 62; 2240215976Sjmallett#endif 2241215976Sjmallett } s; 2242215976Sjmallett struct cvmx_mio_boot_int_s cn30xx; 2243215976Sjmallett struct cvmx_mio_boot_int_s cn31xx; 2244215976Sjmallett struct cvmx_mio_boot_int_s cn38xx; 2245215976Sjmallett struct cvmx_mio_boot_int_s cn38xxp2; 2246215976Sjmallett struct cvmx_mio_boot_int_s cn50xx; 2247215976Sjmallett struct cvmx_mio_boot_int_s cn52xx; 2248215976Sjmallett struct cvmx_mio_boot_int_s cn52xxp1; 2249215976Sjmallett struct cvmx_mio_boot_int_s cn56xx; 2250215976Sjmallett struct cvmx_mio_boot_int_s cn56xxp1; 2251215976Sjmallett struct cvmx_mio_boot_int_s cn58xx; 2252215976Sjmallett struct cvmx_mio_boot_int_s cn58xxp1; 2253232812Sjmallett struct cvmx_mio_boot_int_s cn61xx; 2254215976Sjmallett struct cvmx_mio_boot_int_s cn63xx; 2255215976Sjmallett struct cvmx_mio_boot_int_s cn63xxp1; 2256232812Sjmallett struct cvmx_mio_boot_int_s cn66xx; 2257232812Sjmallett struct cvmx_mio_boot_int_s cn68xx; 2258232812Sjmallett struct cvmx_mio_boot_int_s cn68xxp1; 2259232812Sjmallett struct cvmx_mio_boot_int_s cnf71xx; 2260215976Sjmallett}; 2261215976Sjmalletttypedef union cvmx_mio_boot_int cvmx_mio_boot_int_t; 2262215976Sjmallett 2263215976Sjmallett/** 2264215976Sjmallett * cvmx_mio_boot_loc_adr 2265215976Sjmallett * 2266232812Sjmallett * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Region Address Register 2267215976Sjmallett * 2268232812Sjmallett * Specifies the address for reading or writing the local memory region. This address will post-increment 2269232812Sjmallett * following an access to the MIO Boot Local Memory Region Data Register (MIO_BOOT_LOC_DAT). 2270215976Sjmallett * 2271215976Sjmallett * Local memory region 0 exists from addresses 0x00 - 0x78. 2272215976Sjmallett * Local memory region 1 exists from addresses 0x80 - 0xf8. 2273215976Sjmallett */ 2274232812Sjmallettunion cvmx_mio_boot_loc_adr { 2275215976Sjmallett uint64_t u64; 2276232812Sjmallett struct cvmx_mio_boot_loc_adr_s { 2277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2278215976Sjmallett uint64_t reserved_8_63 : 56; 2279232812Sjmallett uint64_t adr : 5; /**< Local memory region address */ 2280215976Sjmallett uint64_t reserved_0_2 : 3; 2281215976Sjmallett#else 2282215976Sjmallett uint64_t reserved_0_2 : 3; 2283215976Sjmallett uint64_t adr : 5; 2284215976Sjmallett uint64_t reserved_8_63 : 56; 2285215976Sjmallett#endif 2286215976Sjmallett } s; 2287215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn30xx; 2288215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn31xx; 2289215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn38xx; 2290215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn38xxp2; 2291215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn50xx; 2292215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn52xx; 2293215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn52xxp1; 2294215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn56xx; 2295215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn56xxp1; 2296215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn58xx; 2297215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn58xxp1; 2298232812Sjmallett struct cvmx_mio_boot_loc_adr_s cn61xx; 2299215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn63xx; 2300215976Sjmallett struct cvmx_mio_boot_loc_adr_s cn63xxp1; 2301232812Sjmallett struct cvmx_mio_boot_loc_adr_s cn66xx; 2302232812Sjmallett struct cvmx_mio_boot_loc_adr_s cn68xx; 2303232812Sjmallett struct cvmx_mio_boot_loc_adr_s cn68xxp1; 2304232812Sjmallett struct cvmx_mio_boot_loc_adr_s cnf71xx; 2305215976Sjmallett}; 2306215976Sjmalletttypedef union cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_adr_t; 2307215976Sjmallett 2308215976Sjmallett/** 2309215976Sjmallett * cvmx_mio_boot_loc_cfg# 2310215976Sjmallett * 2311232812Sjmallett * MIO_BOOT_LOC_CFG = MIO Boot Local Memory Region Config Register (1 per region * 2 regions) 2312215976Sjmallett * 2313232812Sjmallett * Contains local memory region enable and local memory region base address parameters. Each local memory region is 128 2314215976Sjmallett * bytes organized as 16 entries x 8 bytes. 2315215976Sjmallett * 2316215976Sjmallett * Base address specifies address bits [31:7] of the region. 2317215976Sjmallett */ 2318232812Sjmallettunion cvmx_mio_boot_loc_cfgx { 2319215976Sjmallett uint64_t u64; 2320232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s { 2321232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2322215976Sjmallett uint64_t reserved_32_63 : 32; 2323232812Sjmallett uint64_t en : 1; /**< Local memory region X enable */ 2324215976Sjmallett uint64_t reserved_28_30 : 3; 2325232812Sjmallett uint64_t base : 25; /**< Local memory region X base address */ 2326215976Sjmallett uint64_t reserved_0_2 : 3; 2327215976Sjmallett#else 2328215976Sjmallett uint64_t reserved_0_2 : 3; 2329215976Sjmallett uint64_t base : 25; 2330215976Sjmallett uint64_t reserved_28_30 : 3; 2331215976Sjmallett uint64_t en : 1; 2332215976Sjmallett uint64_t reserved_32_63 : 32; 2333215976Sjmallett#endif 2334215976Sjmallett } s; 2335215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn30xx; 2336215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn31xx; 2337215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn38xx; 2338215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; 2339215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn50xx; 2340215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn52xx; 2341215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; 2342215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn56xx; 2343215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 2344215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn58xx; 2345215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 2346232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn61xx; 2347215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn63xx; 2348215976Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 2349232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn66xx; 2350232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn68xx; 2351232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; 2352232812Sjmallett struct cvmx_mio_boot_loc_cfgx_s cnf71xx; 2353215976Sjmallett}; 2354215976Sjmalletttypedef union cvmx_mio_boot_loc_cfgx cvmx_mio_boot_loc_cfgx_t; 2355215976Sjmallett 2356215976Sjmallett/** 2357215976Sjmallett * cvmx_mio_boot_loc_dat 2358215976Sjmallett * 2359232812Sjmallett * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Region Data Register 2360215976Sjmallett * 2361232812Sjmallett * This is a pseudo-register that will read/write the local memory region at the address specified by the MIO 2362232812Sjmallett * Boot Local Memory Region Address Register (MIO_BOOT_LOC_ADR) when accessed. 2363215976Sjmallett */ 2364232812Sjmallettunion cvmx_mio_boot_loc_dat { 2365215976Sjmallett uint64_t u64; 2366232812Sjmallett struct cvmx_mio_boot_loc_dat_s { 2367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2368232812Sjmallett uint64_t data : 64; /**< Local memory region data */ 2369215976Sjmallett#else 2370215976Sjmallett uint64_t data : 64; 2371215976Sjmallett#endif 2372215976Sjmallett } s; 2373215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn30xx; 2374215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn31xx; 2375215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn38xx; 2376215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn38xxp2; 2377215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn50xx; 2378215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn52xx; 2379215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn52xxp1; 2380215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn56xx; 2381215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn56xxp1; 2382215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn58xx; 2383215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn58xxp1; 2384232812Sjmallett struct cvmx_mio_boot_loc_dat_s cn61xx; 2385215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn63xx; 2386215976Sjmallett struct cvmx_mio_boot_loc_dat_s cn63xxp1; 2387232812Sjmallett struct cvmx_mio_boot_loc_dat_s cn66xx; 2388232812Sjmallett struct cvmx_mio_boot_loc_dat_s cn68xx; 2389232812Sjmallett struct cvmx_mio_boot_loc_dat_s cn68xxp1; 2390232812Sjmallett struct cvmx_mio_boot_loc_dat_s cnf71xx; 2391215976Sjmallett}; 2392215976Sjmalletttypedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t; 2393215976Sjmallett 2394215976Sjmallett/** 2395215976Sjmallett * cvmx_mio_boot_pin_defs 2396215976Sjmallett * 2397215976Sjmallett * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register 2398215976Sjmallett * 2399215976Sjmallett */ 2400232812Sjmallettunion cvmx_mio_boot_pin_defs { 2401215976Sjmallett uint64_t u64; 2402232812Sjmallett struct cvmx_mio_boot_pin_defs_s { 2403232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2404232812Sjmallett uint64_t reserved_32_63 : 32; 2405232812Sjmallett uint64_t user1 : 16; /**< BOOT_AD [31:16] latched during power up */ 2406215976Sjmallett uint64_t ale : 1; /**< Region 0 default ALE mode */ 2407215976Sjmallett uint64_t width : 1; /**< Region 0 default bus width */ 2408215976Sjmallett uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */ 2409215976Sjmallett uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2410215976Sjmallett uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2411215976Sjmallett uint64_t term : 2; /**< Selects default driver termination */ 2412215976Sjmallett uint64_t nand : 1; /**< Region 0 is NAND flash */ 2413232812Sjmallett uint64_t user0 : 8; /**< BOOT_AD [7:0] latched during power up */ 2414215976Sjmallett#else 2415232812Sjmallett uint64_t user0 : 8; 2416215976Sjmallett uint64_t nand : 1; 2417215976Sjmallett uint64_t term : 2; 2418215976Sjmallett uint64_t dmack_p0 : 1; 2419215976Sjmallett uint64_t dmack_p1 : 1; 2420215976Sjmallett uint64_t dmack_p2 : 1; 2421215976Sjmallett uint64_t width : 1; 2422215976Sjmallett uint64_t ale : 1; 2423232812Sjmallett uint64_t user1 : 16; 2424232812Sjmallett uint64_t reserved_32_63 : 32; 2425215976Sjmallett#endif 2426215976Sjmallett } s; 2427232812Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx { 2428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2429215976Sjmallett uint64_t reserved_16_63 : 48; 2430215976Sjmallett uint64_t ale : 1; /**< Region 0 default ALE mode */ 2431215976Sjmallett uint64_t width : 1; /**< Region 0 default bus width */ 2432215976Sjmallett uint64_t reserved_13_13 : 1; 2433215976Sjmallett uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2434215976Sjmallett uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2435215976Sjmallett uint64_t term : 2; /**< Selects default driver termination */ 2436215976Sjmallett uint64_t nand : 1; /**< Region 0 is NAND flash */ 2437215976Sjmallett uint64_t reserved_0_7 : 8; 2438215976Sjmallett#else 2439215976Sjmallett uint64_t reserved_0_7 : 8; 2440215976Sjmallett uint64_t nand : 1; 2441215976Sjmallett uint64_t term : 2; 2442215976Sjmallett uint64_t dmack_p0 : 1; 2443215976Sjmallett uint64_t dmack_p1 : 1; 2444215976Sjmallett uint64_t reserved_13_13 : 1; 2445215976Sjmallett uint64_t width : 1; 2446215976Sjmallett uint64_t ale : 1; 2447215976Sjmallett uint64_t reserved_16_63 : 48; 2448215976Sjmallett#endif 2449215976Sjmallett } cn52xx; 2450232812Sjmallett struct cvmx_mio_boot_pin_defs_cn56xx { 2451232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2452215976Sjmallett uint64_t reserved_16_63 : 48; 2453215976Sjmallett uint64_t ale : 1; /**< Region 0 default ALE mode */ 2454215976Sjmallett uint64_t width : 1; /**< Region 0 default bus width */ 2455215976Sjmallett uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */ 2456215976Sjmallett uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2457215976Sjmallett uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2458215976Sjmallett uint64_t term : 2; /**< Selects default driver termination */ 2459215976Sjmallett uint64_t reserved_0_8 : 9; 2460215976Sjmallett#else 2461215976Sjmallett uint64_t reserved_0_8 : 9; 2462215976Sjmallett uint64_t term : 2; 2463215976Sjmallett uint64_t dmack_p0 : 1; 2464215976Sjmallett uint64_t dmack_p1 : 1; 2465215976Sjmallett uint64_t dmack_p2 : 1; 2466215976Sjmallett uint64_t width : 1; 2467215976Sjmallett uint64_t ale : 1; 2468215976Sjmallett uint64_t reserved_16_63 : 48; 2469215976Sjmallett#endif 2470215976Sjmallett } cn56xx; 2471232812Sjmallett struct cvmx_mio_boot_pin_defs_cn61xx { 2472232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2473232812Sjmallett uint64_t reserved_32_63 : 32; 2474232812Sjmallett uint64_t user1 : 16; /**< BOOT_AD [31:16] latched during power up */ 2475232812Sjmallett uint64_t ale : 1; /**< Region 0 default ALE mode */ 2476232812Sjmallett uint64_t width : 1; /**< Region 0 default bus width */ 2477232812Sjmallett uint64_t reserved_13_13 : 1; 2478232812Sjmallett uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2479232812Sjmallett uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2480232812Sjmallett uint64_t term : 2; /**< Selects default driver termination */ 2481232812Sjmallett uint64_t nand : 1; /**< Region 0 is NAND flash */ 2482232812Sjmallett uint64_t user0 : 8; /**< BOOT_AD [7:0] latched during power up */ 2483232812Sjmallett#else 2484232812Sjmallett uint64_t user0 : 8; 2485232812Sjmallett uint64_t nand : 1; 2486232812Sjmallett uint64_t term : 2; 2487232812Sjmallett uint64_t dmack_p0 : 1; 2488232812Sjmallett uint64_t dmack_p1 : 1; 2489232812Sjmallett uint64_t reserved_13_13 : 1; 2490232812Sjmallett uint64_t width : 1; 2491232812Sjmallett uint64_t ale : 1; 2492232812Sjmallett uint64_t user1 : 16; 2493232812Sjmallett uint64_t reserved_32_63 : 32; 2494232812Sjmallett#endif 2495232812Sjmallett } cn61xx; 2496215976Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 2497215976Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 2498232812Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; 2499232812Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; 2500232812Sjmallett struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; 2501232812Sjmallett struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; 2502215976Sjmallett}; 2503215976Sjmalletttypedef union cvmx_mio_boot_pin_defs cvmx_mio_boot_pin_defs_t; 2504215976Sjmallett 2505215976Sjmallett/** 2506215976Sjmallett * cvmx_mio_boot_reg_cfg# 2507215976Sjmallett */ 2508232812Sjmallettunion cvmx_mio_boot_reg_cfgx { 2509215976Sjmallett uint64_t u64; 2510232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s { 2511232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2512215976Sjmallett uint64_t reserved_44_63 : 20; 2513215976Sjmallett uint64_t dmack : 2; /**< Region X DMACK */ 2514215976Sjmallett uint64_t tim_mult : 2; /**< Region X timing multiplier */ 2515215976Sjmallett uint64_t rd_dly : 3; /**< Region X read sample delay */ 2516215976Sjmallett uint64_t sam : 1; /**< Region X SAM mode */ 2517215976Sjmallett uint64_t we_ext : 2; /**< Region X write enable count extension */ 2518215976Sjmallett uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2519215976Sjmallett uint64_t en : 1; /**< Region X enable */ 2520215976Sjmallett uint64_t orbit : 1; /**< Region X or bit */ 2521215976Sjmallett uint64_t ale : 1; /**< Region X ALE mode */ 2522215976Sjmallett uint64_t width : 1; /**< Region X bus width */ 2523215976Sjmallett uint64_t size : 12; /**< Region X size */ 2524215976Sjmallett uint64_t base : 16; /**< Region X base address */ 2525215976Sjmallett#else 2526215976Sjmallett uint64_t base : 16; 2527215976Sjmallett uint64_t size : 12; 2528215976Sjmallett uint64_t width : 1; 2529215976Sjmallett uint64_t ale : 1; 2530215976Sjmallett uint64_t orbit : 1; 2531215976Sjmallett uint64_t en : 1; 2532215976Sjmallett uint64_t oe_ext : 2; 2533215976Sjmallett uint64_t we_ext : 2; 2534215976Sjmallett uint64_t sam : 1; 2535215976Sjmallett uint64_t rd_dly : 3; 2536215976Sjmallett uint64_t tim_mult : 2; 2537215976Sjmallett uint64_t dmack : 2; 2538215976Sjmallett uint64_t reserved_44_63 : 20; 2539215976Sjmallett#endif 2540215976Sjmallett } s; 2541232812Sjmallett struct cvmx_mio_boot_reg_cfgx_cn30xx { 2542232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2543215976Sjmallett uint64_t reserved_37_63 : 27; 2544215976Sjmallett uint64_t sam : 1; /**< Region X SAM mode */ 2545215976Sjmallett uint64_t we_ext : 2; /**< Region X write enable count extension */ 2546215976Sjmallett uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2547215976Sjmallett uint64_t en : 1; /**< Region X enable */ 2548215976Sjmallett uint64_t orbit : 1; /**< Region X or bit */ 2549215976Sjmallett uint64_t ale : 1; /**< Region X ALE mode */ 2550215976Sjmallett uint64_t width : 1; /**< Region X bus width */ 2551215976Sjmallett uint64_t size : 12; /**< Region X size */ 2552215976Sjmallett uint64_t base : 16; /**< Region X base address */ 2553215976Sjmallett#else 2554215976Sjmallett uint64_t base : 16; 2555215976Sjmallett uint64_t size : 12; 2556215976Sjmallett uint64_t width : 1; 2557215976Sjmallett uint64_t ale : 1; 2558215976Sjmallett uint64_t orbit : 1; 2559215976Sjmallett uint64_t en : 1; 2560215976Sjmallett uint64_t oe_ext : 2; 2561215976Sjmallett uint64_t we_ext : 2; 2562215976Sjmallett uint64_t sam : 1; 2563215976Sjmallett uint64_t reserved_37_63 : 27; 2564215976Sjmallett#endif 2565215976Sjmallett } cn30xx; 2566215976Sjmallett struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; 2567232812Sjmallett struct cvmx_mio_boot_reg_cfgx_cn38xx { 2568232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2569215976Sjmallett uint64_t reserved_32_63 : 32; 2570215976Sjmallett uint64_t en : 1; /**< Region X enable */ 2571215976Sjmallett uint64_t orbit : 1; /**< Region X or bit */ 2572215976Sjmallett uint64_t reserved_28_29 : 2; 2573215976Sjmallett uint64_t size : 12; /**< Region X size */ 2574215976Sjmallett uint64_t base : 16; /**< Region X base address */ 2575215976Sjmallett#else 2576215976Sjmallett uint64_t base : 16; 2577215976Sjmallett uint64_t size : 12; 2578215976Sjmallett uint64_t reserved_28_29 : 2; 2579215976Sjmallett uint64_t orbit : 1; 2580215976Sjmallett uint64_t en : 1; 2581215976Sjmallett uint64_t reserved_32_63 : 32; 2582215976Sjmallett#endif 2583215976Sjmallett } cn38xx; 2584215976Sjmallett struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; 2585232812Sjmallett struct cvmx_mio_boot_reg_cfgx_cn50xx { 2586232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2587215976Sjmallett uint64_t reserved_42_63 : 22; 2588215976Sjmallett uint64_t tim_mult : 2; /**< Region X timing multiplier */ 2589215976Sjmallett uint64_t rd_dly : 3; /**< Region X read sample delay */ 2590215976Sjmallett uint64_t sam : 1; /**< Region X SAM mode */ 2591215976Sjmallett uint64_t we_ext : 2; /**< Region X write enable count extension */ 2592215976Sjmallett uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2593215976Sjmallett uint64_t en : 1; /**< Region X enable */ 2594215976Sjmallett uint64_t orbit : 1; /**< Region X or bit */ 2595215976Sjmallett uint64_t ale : 1; /**< Region X ALE mode */ 2596215976Sjmallett uint64_t width : 1; /**< Region X bus width */ 2597215976Sjmallett uint64_t size : 12; /**< Region X size */ 2598215976Sjmallett uint64_t base : 16; /**< Region X base address */ 2599215976Sjmallett#else 2600215976Sjmallett uint64_t base : 16; 2601215976Sjmallett uint64_t size : 12; 2602215976Sjmallett uint64_t width : 1; 2603215976Sjmallett uint64_t ale : 1; 2604215976Sjmallett uint64_t orbit : 1; 2605215976Sjmallett uint64_t en : 1; 2606215976Sjmallett uint64_t oe_ext : 2; 2607215976Sjmallett uint64_t we_ext : 2; 2608215976Sjmallett uint64_t sam : 1; 2609215976Sjmallett uint64_t rd_dly : 3; 2610215976Sjmallett uint64_t tim_mult : 2; 2611215976Sjmallett uint64_t reserved_42_63 : 22; 2612215976Sjmallett#endif 2613215976Sjmallett } cn50xx; 2614215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn52xx; 2615215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; 2616215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn56xx; 2617215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 2618215976Sjmallett struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 2619215976Sjmallett struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 2620232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn61xx; 2621215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn63xx; 2622215976Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 2623232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn66xx; 2624232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn68xx; 2625232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; 2626232812Sjmallett struct cvmx_mio_boot_reg_cfgx_s cnf71xx; 2627215976Sjmallett}; 2628215976Sjmalletttypedef union cvmx_mio_boot_reg_cfgx cvmx_mio_boot_reg_cfgx_t; 2629215976Sjmallett 2630215976Sjmallett/** 2631215976Sjmallett * cvmx_mio_boot_reg_tim# 2632215976Sjmallett */ 2633232812Sjmallettunion cvmx_mio_boot_reg_timx { 2634215976Sjmallett uint64_t u64; 2635232812Sjmallett struct cvmx_mio_boot_reg_timx_s { 2636232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2637215976Sjmallett uint64_t pagem : 1; /**< Region X page mode */ 2638215976Sjmallett uint64_t waitm : 1; /**< Region X wait mode */ 2639215976Sjmallett uint64_t pages : 2; /**< Region X page size */ 2640215976Sjmallett uint64_t ale : 6; /**< Region X ALE count */ 2641215976Sjmallett uint64_t page : 6; /**< Region X page count */ 2642215976Sjmallett uint64_t wait : 6; /**< Region X wait count */ 2643215976Sjmallett uint64_t pause : 6; /**< Region X pause count */ 2644215976Sjmallett uint64_t wr_hld : 6; /**< Region X write hold count */ 2645215976Sjmallett uint64_t rd_hld : 6; /**< Region X read hold count */ 2646215976Sjmallett uint64_t we : 6; /**< Region X write enable count */ 2647215976Sjmallett uint64_t oe : 6; /**< Region X output enable count */ 2648215976Sjmallett uint64_t ce : 6; /**< Region X chip enable count */ 2649215976Sjmallett uint64_t adr : 6; /**< Region X address count */ 2650215976Sjmallett#else 2651215976Sjmallett uint64_t adr : 6; 2652215976Sjmallett uint64_t ce : 6; 2653215976Sjmallett uint64_t oe : 6; 2654215976Sjmallett uint64_t we : 6; 2655215976Sjmallett uint64_t rd_hld : 6; 2656215976Sjmallett uint64_t wr_hld : 6; 2657215976Sjmallett uint64_t pause : 6; 2658215976Sjmallett uint64_t wait : 6; 2659215976Sjmallett uint64_t page : 6; 2660215976Sjmallett uint64_t ale : 6; 2661215976Sjmallett uint64_t pages : 2; 2662215976Sjmallett uint64_t waitm : 1; 2663215976Sjmallett uint64_t pagem : 1; 2664215976Sjmallett#endif 2665215976Sjmallett } s; 2666215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn30xx; 2667215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn31xx; 2668232812Sjmallett struct cvmx_mio_boot_reg_timx_cn38xx { 2669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2670215976Sjmallett uint64_t pagem : 1; /**< Region X page mode */ 2671215976Sjmallett uint64_t waitm : 1; /**< Region X wait mode */ 2672215976Sjmallett uint64_t pages : 2; /**< Region X page size (NOT IN PASS 1) */ 2673215976Sjmallett uint64_t reserved_54_59 : 6; 2674215976Sjmallett uint64_t page : 6; /**< Region X page count */ 2675215976Sjmallett uint64_t wait : 6; /**< Region X wait count */ 2676215976Sjmallett uint64_t pause : 6; /**< Region X pause count */ 2677215976Sjmallett uint64_t wr_hld : 6; /**< Region X write hold count */ 2678215976Sjmallett uint64_t rd_hld : 6; /**< Region X read hold count */ 2679215976Sjmallett uint64_t we : 6; /**< Region X write enable count */ 2680215976Sjmallett uint64_t oe : 6; /**< Region X output enable count */ 2681215976Sjmallett uint64_t ce : 6; /**< Region X chip enable count */ 2682215976Sjmallett uint64_t adr : 6; /**< Region X address count */ 2683215976Sjmallett#else 2684215976Sjmallett uint64_t adr : 6; 2685215976Sjmallett uint64_t ce : 6; 2686215976Sjmallett uint64_t oe : 6; 2687215976Sjmallett uint64_t we : 6; 2688215976Sjmallett uint64_t rd_hld : 6; 2689215976Sjmallett uint64_t wr_hld : 6; 2690215976Sjmallett uint64_t pause : 6; 2691215976Sjmallett uint64_t wait : 6; 2692215976Sjmallett uint64_t page : 6; 2693215976Sjmallett uint64_t reserved_54_59 : 6; 2694215976Sjmallett uint64_t pages : 2; 2695215976Sjmallett uint64_t waitm : 1; 2696215976Sjmallett uint64_t pagem : 1; 2697215976Sjmallett#endif 2698215976Sjmallett } cn38xx; 2699215976Sjmallett struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; 2700215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn50xx; 2701215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn52xx; 2702215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn52xxp1; 2703215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn56xx; 2704215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn56xxp1; 2705215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn58xx; 2706215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn58xxp1; 2707232812Sjmallett struct cvmx_mio_boot_reg_timx_s cn61xx; 2708215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn63xx; 2709215976Sjmallett struct cvmx_mio_boot_reg_timx_s cn63xxp1; 2710232812Sjmallett struct cvmx_mio_boot_reg_timx_s cn66xx; 2711232812Sjmallett struct cvmx_mio_boot_reg_timx_s cn68xx; 2712232812Sjmallett struct cvmx_mio_boot_reg_timx_s cn68xxp1; 2713232812Sjmallett struct cvmx_mio_boot_reg_timx_s cnf71xx; 2714215976Sjmallett}; 2715215976Sjmalletttypedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t; 2716215976Sjmallett 2717215976Sjmallett/** 2718215976Sjmallett * cvmx_mio_boot_thr 2719215976Sjmallett * 2720215976Sjmallett * MIO_BOOT_THR = MIO Boot Threshold Register 2721215976Sjmallett * 2722215976Sjmallett * Contains MIO Boot threshold values: 2723215976Sjmallett * 2724215976Sjmallett * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for 2725215976Sjmallett * customer use). 2726215976Sjmallett * 2727215976Sjmallett * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA 2728215976Sjmallett * accesses have completed. If set to zero, only perform a DMA access when non-DMA 2729215976Sjmallett * accesses are not pending. 2730215976Sjmallett */ 2731232812Sjmallettunion cvmx_mio_boot_thr { 2732215976Sjmallett uint64_t u64; 2733232812Sjmallett struct cvmx_mio_boot_thr_s { 2734232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2735215976Sjmallett uint64_t reserved_22_63 : 42; 2736215976Sjmallett uint64_t dma_thr : 6; /**< DMA threshold */ 2737215976Sjmallett uint64_t reserved_14_15 : 2; 2738215976Sjmallett uint64_t fif_cnt : 6; /**< Current NCB FIFO count */ 2739215976Sjmallett uint64_t reserved_6_7 : 2; 2740215976Sjmallett uint64_t fif_thr : 6; /**< NCB busy threshold */ 2741215976Sjmallett#else 2742215976Sjmallett uint64_t fif_thr : 6; 2743215976Sjmallett uint64_t reserved_6_7 : 2; 2744215976Sjmallett uint64_t fif_cnt : 6; 2745215976Sjmallett uint64_t reserved_14_15 : 2; 2746215976Sjmallett uint64_t dma_thr : 6; 2747215976Sjmallett uint64_t reserved_22_63 : 42; 2748215976Sjmallett#endif 2749215976Sjmallett } s; 2750232812Sjmallett struct cvmx_mio_boot_thr_cn30xx { 2751232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2752215976Sjmallett uint64_t reserved_14_63 : 50; 2753215976Sjmallett uint64_t fif_cnt : 6; /**< Current NCB FIFO count */ 2754215976Sjmallett uint64_t reserved_6_7 : 2; 2755215976Sjmallett uint64_t fif_thr : 6; /**< NCB busy threshold */ 2756215976Sjmallett#else 2757215976Sjmallett uint64_t fif_thr : 6; 2758215976Sjmallett uint64_t reserved_6_7 : 2; 2759215976Sjmallett uint64_t fif_cnt : 6; 2760215976Sjmallett uint64_t reserved_14_63 : 50; 2761215976Sjmallett#endif 2762215976Sjmallett } cn30xx; 2763215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn31xx; 2764215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn38xx; 2765215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn38xxp2; 2766215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn50xx; 2767215976Sjmallett struct cvmx_mio_boot_thr_s cn52xx; 2768215976Sjmallett struct cvmx_mio_boot_thr_s cn52xxp1; 2769215976Sjmallett struct cvmx_mio_boot_thr_s cn56xx; 2770215976Sjmallett struct cvmx_mio_boot_thr_s cn56xxp1; 2771215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn58xx; 2772215976Sjmallett struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 2773232812Sjmallett struct cvmx_mio_boot_thr_s cn61xx; 2774215976Sjmallett struct cvmx_mio_boot_thr_s cn63xx; 2775215976Sjmallett struct cvmx_mio_boot_thr_s cn63xxp1; 2776232812Sjmallett struct cvmx_mio_boot_thr_s cn66xx; 2777232812Sjmallett struct cvmx_mio_boot_thr_s cn68xx; 2778232812Sjmallett struct cvmx_mio_boot_thr_s cn68xxp1; 2779232812Sjmallett struct cvmx_mio_boot_thr_s cnf71xx; 2780215976Sjmallett}; 2781215976Sjmalletttypedef union cvmx_mio_boot_thr cvmx_mio_boot_thr_t; 2782215976Sjmallett 2783215976Sjmallett/** 2784232812Sjmallett * cvmx_mio_emm_buf_dat 2785232812Sjmallett * 2786232812Sjmallett * MIO_EMM_BUF_DAT = MIO EMMC Data buffer access Register 2787232812Sjmallett * 2788232812Sjmallett */ 2789232812Sjmallettunion cvmx_mio_emm_buf_dat { 2790232812Sjmallett uint64_t u64; 2791232812Sjmallett struct cvmx_mio_emm_buf_dat_s { 2792232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2793232812Sjmallett uint64_t dat : 64; /**< Direct access to the 1KB data buffer memory. Address 2794232812Sjmallett specified by MIO_EMM_BUF_IDX */ 2795232812Sjmallett#else 2796232812Sjmallett uint64_t dat : 64; 2797232812Sjmallett#endif 2798232812Sjmallett } s; 2799232812Sjmallett struct cvmx_mio_emm_buf_dat_s cn61xx; 2800232812Sjmallett struct cvmx_mio_emm_buf_dat_s cnf71xx; 2801232812Sjmallett}; 2802232812Sjmalletttypedef union cvmx_mio_emm_buf_dat cvmx_mio_emm_buf_dat_t; 2803232812Sjmallett 2804232812Sjmallett/** 2805232812Sjmallett * cvmx_mio_emm_buf_idx 2806232812Sjmallett * 2807232812Sjmallett * MIO_EMM_BUF_IDX = MIO EMMC Data buffer address Register 2808232812Sjmallett * 2809232812Sjmallett */ 2810232812Sjmallettunion cvmx_mio_emm_buf_idx { 2811232812Sjmallett uint64_t u64; 2812232812Sjmallett struct cvmx_mio_emm_buf_idx_s { 2813232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2814232812Sjmallett uint64_t reserved_17_63 : 47; 2815232812Sjmallett uint64_t inc : 1; /**< Automatically advance BUF_SEL/OFFSET after each access to 2816232812Sjmallett MIO_EMM_BUF_DAT. Wraps after last offset of last data buffer. */ 2817232812Sjmallett uint64_t reserved_7_15 : 9; 2818232812Sjmallett uint64_t buf_num : 1; /**< Specify the data buffer for the next access to MIO_EMM_BUF_DAT */ 2819232812Sjmallett uint64_t offset : 6; /**< Specify the 8B data buffer offset for the next access to 2820232812Sjmallett MIO_EMM_BUF_DAT */ 2821232812Sjmallett#else 2822232812Sjmallett uint64_t offset : 6; 2823232812Sjmallett uint64_t buf_num : 1; 2824232812Sjmallett uint64_t reserved_7_15 : 9; 2825232812Sjmallett uint64_t inc : 1; 2826232812Sjmallett uint64_t reserved_17_63 : 47; 2827232812Sjmallett#endif 2828232812Sjmallett } s; 2829232812Sjmallett struct cvmx_mio_emm_buf_idx_s cn61xx; 2830232812Sjmallett struct cvmx_mio_emm_buf_idx_s cnf71xx; 2831232812Sjmallett}; 2832232812Sjmalletttypedef union cvmx_mio_emm_buf_idx cvmx_mio_emm_buf_idx_t; 2833232812Sjmallett 2834232812Sjmallett/** 2835232812Sjmallett * cvmx_mio_emm_cfg 2836232812Sjmallett * 2837232812Sjmallett * MIO_EMM_CFG = MIO EMMC Configuration Register 2838232812Sjmallett * 2839232812Sjmallett */ 2840232812Sjmallettunion cvmx_mio_emm_cfg { 2841232812Sjmallett uint64_t u64; 2842232812Sjmallett struct cvmx_mio_emm_cfg_s { 2843232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2844232812Sjmallett uint64_t reserved_17_63 : 47; 2845232812Sjmallett uint64_t boot_fail : 1; /**< SW should set BOOT_FAIL when an unrecoverable error occurs 2846232812Sjmallett while attempt to boot from eMMC or NOR Flash. When set, the 2847232812Sjmallett following pattern will be output: 2848232812Sjmallett BOOT_AD[7:0] pulled up to 1 2849232812Sjmallett BOOT_CE_N[7:0] driven to 1 2850232812Sjmallett BOOT_ALE driven to 0 2851232812Sjmallett BOOT_OE_L driven to 1 2852232812Sjmallett BOOT_WE_L driven to 1 */ 2853232812Sjmallett uint64_t reserved_4_15 : 12; 2854232812Sjmallett uint64_t bus_ena : 4; /**< eMMC bus enable mask. 2855232812Sjmallett 2856232812Sjmallett Setting bit0 of BUS_ENA causes BOOT_CE[1] to become dedicated 2857232812Sjmallett eMMC bus 0 command (ie. disabling any NOR use) 2858232812Sjmallett 2859232812Sjmallett Setting bit1 of BUS_ENA causes BOOT_CE[2] to become dedicated 2860232812Sjmallett eMMC bus 1 command (ie. disabling any NOR use). 2861232812Sjmallett 2862232812Sjmallett Setting bit2 of BUS_ENA causes BOOT_CE[3] to become dedicated 2863232812Sjmallett eMMC bus 2 command (ie. disabling any NOR use). 2864232812Sjmallett 2865232812Sjmallett Setting bit3 of BUS_ENA causes BOOT_CE[4] to become dedicated 2866232812Sjmallett eMMC bus 3 command (ie. disabling any NOR use). 2867232812Sjmallett 2868232812Sjmallett Setting any bit of BUS_ENA causes BOOT_CE[5] to become the eMMC 2869232812Sjmallett clock for both bus0 and bus1. */ 2870232812Sjmallett#else 2871232812Sjmallett uint64_t bus_ena : 4; 2872232812Sjmallett uint64_t reserved_4_15 : 12; 2873232812Sjmallett uint64_t boot_fail : 1; 2874232812Sjmallett uint64_t reserved_17_63 : 47; 2875232812Sjmallett#endif 2876232812Sjmallett } s; 2877232812Sjmallett struct cvmx_mio_emm_cfg_s cn61xx; 2878232812Sjmallett struct cvmx_mio_emm_cfg_s cnf71xx; 2879232812Sjmallett}; 2880232812Sjmalletttypedef union cvmx_mio_emm_cfg cvmx_mio_emm_cfg_t; 2881232812Sjmallett 2882232812Sjmallett/** 2883232812Sjmallett * cvmx_mio_emm_cmd 2884232812Sjmallett * 2885232812Sjmallett * MIO_EMM_CMD = MIO EMMC Command Register 2886232812Sjmallett * 2887232812Sjmallett */ 2888232812Sjmallettunion cvmx_mio_emm_cmd { 2889232812Sjmallett uint64_t u64; 2890232812Sjmallett struct cvmx_mio_emm_cmd_s { 2891232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2892232812Sjmallett uint64_t reserved_62_63 : 2; 2893232812Sjmallett uint64_t bus_id : 2; /**< Specify the eMMC bus */ 2894232812Sjmallett uint64_t cmd_val : 1; /**< Request valid. SW writes this bit to a 1. HW clears it when 2895232812Sjmallett the operation completes. */ 2896232812Sjmallett uint64_t reserved_56_58 : 3; 2897232812Sjmallett uint64_t dbuf : 1; /**< Specify the data buffer to be used for a block transfer. */ 2898232812Sjmallett uint64_t offset : 6; /**< Debug only. Specify the number of 8 byte transfers in the 2899232812Sjmallett used in the command. Value is 64-OFFSET. The block transfer 2900232812Sjmallett will still start at the first btye in the 512B data buffer. 2901232812Sjmallett SW must ensure CMD16 has updated the card block length. */ 2902232812Sjmallett uint64_t reserved_43_48 : 6; 2903232812Sjmallett uint64_t ctype_xor : 2; /**< Reserved. Must be zero */ 2904232812Sjmallett uint64_t rtype_xor : 3; /**< Reserved. Must be zero */ 2905232812Sjmallett uint64_t cmd_idx : 6; /**< eMMC command */ 2906232812Sjmallett uint64_t arg : 32; /**< eMMC command argument */ 2907232812Sjmallett#else 2908232812Sjmallett uint64_t arg : 32; 2909232812Sjmallett uint64_t cmd_idx : 6; 2910232812Sjmallett uint64_t rtype_xor : 3; 2911232812Sjmallett uint64_t ctype_xor : 2; 2912232812Sjmallett uint64_t reserved_43_48 : 6; 2913232812Sjmallett uint64_t offset : 6; 2914232812Sjmallett uint64_t dbuf : 1; 2915232812Sjmallett uint64_t reserved_56_58 : 3; 2916232812Sjmallett uint64_t cmd_val : 1; 2917232812Sjmallett uint64_t bus_id : 2; 2918232812Sjmallett uint64_t reserved_62_63 : 2; 2919232812Sjmallett#endif 2920232812Sjmallett } s; 2921232812Sjmallett struct cvmx_mio_emm_cmd_s cn61xx; 2922232812Sjmallett struct cvmx_mio_emm_cmd_s cnf71xx; 2923232812Sjmallett}; 2924232812Sjmalletttypedef union cvmx_mio_emm_cmd cvmx_mio_emm_cmd_t; 2925232812Sjmallett 2926232812Sjmallett/** 2927232812Sjmallett * cvmx_mio_emm_dma 2928232812Sjmallett * 2929232812Sjmallett * MIO_EMM_DMA = MIO EMMC DMA config Register 2930232812Sjmallett * 2931232812Sjmallett */ 2932232812Sjmallettunion cvmx_mio_emm_dma { 2933232812Sjmallett uint64_t u64; 2934232812Sjmallett struct cvmx_mio_emm_dma_s { 2935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2936232812Sjmallett uint64_t reserved_62_63 : 2; 2937232812Sjmallett uint64_t bus_id : 2; /**< Specify the eMMC bus */ 2938232812Sjmallett uint64_t dma_val : 1; /**< SW writes this bit to a 1 to indicate that HW should perform 2939232812Sjmallett the DMA transfer. HW clears when DMA operation completes or 2940232812Sjmallett is terminated. */ 2941232812Sjmallett uint64_t sector : 1; /**< Specify CARD_ADDR and eMMC are using sector (512B) addressing. */ 2942232812Sjmallett uint64_t dat_null : 1; /**< Do not perform any eMMC commands. A DMA read will return all 2943232812Sjmallett 0s. A DMA write tosses the data. In the case of a failure, 2944232812Sjmallett this can be used to unwind the DMA engine. */ 2945232812Sjmallett uint64_t thres : 6; /**< Number of 8B blocks of data that must exist in the DBUF before 2946232812Sjmallett the starting the 512B block transfer. 0 indicates to wait for 2947232812Sjmallett the entire block. */ 2948232812Sjmallett uint64_t rel_wr : 1; /**< Set the reliable write parameter when performing CMD23 2949232812Sjmallett (SET_BLOCK_COUNT) for a multiple block */ 2950232812Sjmallett uint64_t rw : 1; /**< R/W bit (0 = read, 1 = write) */ 2951232812Sjmallett uint64_t multi : 1; /**< Perform operation using a multiple block command instead of a 2952232812Sjmallett series of single block commands. */ 2953232812Sjmallett uint64_t block_cnt : 16; /**< Number of blocks to read/write. Hardware decrements the block 2954232812Sjmallett count after each successful block transfer. */ 2955232812Sjmallett uint64_t card_addr : 32; /**< Data address for media =<2GB is a 32bit byte address and data 2956232812Sjmallett address for media > 2GB is a 32bit sector (512B) address. 2957232812Sjmallett Hardware advances the card address after each successful block 2958232812Sjmallett transfer by 512 for byte addressing and by 1 for sector 2959232812Sjmallett addressing. */ 2960232812Sjmallett#else 2961232812Sjmallett uint64_t card_addr : 32; 2962232812Sjmallett uint64_t block_cnt : 16; 2963232812Sjmallett uint64_t multi : 1; 2964232812Sjmallett uint64_t rw : 1; 2965232812Sjmallett uint64_t rel_wr : 1; 2966232812Sjmallett uint64_t thres : 6; 2967232812Sjmallett uint64_t dat_null : 1; 2968232812Sjmallett uint64_t sector : 1; 2969232812Sjmallett uint64_t dma_val : 1; 2970232812Sjmallett uint64_t bus_id : 2; 2971232812Sjmallett uint64_t reserved_62_63 : 2; 2972232812Sjmallett#endif 2973232812Sjmallett } s; 2974232812Sjmallett struct cvmx_mio_emm_dma_s cn61xx; 2975232812Sjmallett struct cvmx_mio_emm_dma_s cnf71xx; 2976232812Sjmallett}; 2977232812Sjmalletttypedef union cvmx_mio_emm_dma cvmx_mio_emm_dma_t; 2978232812Sjmallett 2979232812Sjmallett/** 2980232812Sjmallett * cvmx_mio_emm_int 2981232812Sjmallett * 2982232812Sjmallett * MIO_EMM_INT = MIO EMMC Interrupt Register 2983232812Sjmallett * 2984232812Sjmallett */ 2985232812Sjmallettunion cvmx_mio_emm_int { 2986232812Sjmallett uint64_t u64; 2987232812Sjmallett struct cvmx_mio_emm_int_s { 2988232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2989232812Sjmallett uint64_t reserved_7_63 : 57; 2990232812Sjmallett uint64_t switch_err : 1; /**< Switch operation encountered an error. */ 2991232812Sjmallett uint64_t switch_done : 1; /**< Switch operation completed successfully */ 2992232812Sjmallett uint64_t dma_err : 1; /**< DMA transfer encountered an error. See MIO_EMM_RSP. */ 2993232812Sjmallett uint64_t cmd_err : 1; /**< Operation specified by MIO_EMM_CMD encountered an error. See 2994232812Sjmallett MIO_EMM_RSP. */ 2995232812Sjmallett uint64_t dma_done : 1; /**< DMA transfer completed successfully */ 2996232812Sjmallett uint64_t cmd_done : 1; /**< Operation specified by MIO_EMM_CMD completed successfully */ 2997232812Sjmallett uint64_t buf_done : 1; /**< The next 512B block transfer of a multi-block transfer has 2998232812Sjmallett completed. */ 2999232812Sjmallett#else 3000232812Sjmallett uint64_t buf_done : 1; 3001232812Sjmallett uint64_t cmd_done : 1; 3002232812Sjmallett uint64_t dma_done : 1; 3003232812Sjmallett uint64_t cmd_err : 1; 3004232812Sjmallett uint64_t dma_err : 1; 3005232812Sjmallett uint64_t switch_done : 1; 3006232812Sjmallett uint64_t switch_err : 1; 3007232812Sjmallett uint64_t reserved_7_63 : 57; 3008232812Sjmallett#endif 3009232812Sjmallett } s; 3010232812Sjmallett struct cvmx_mio_emm_int_s cn61xx; 3011232812Sjmallett struct cvmx_mio_emm_int_s cnf71xx; 3012232812Sjmallett}; 3013232812Sjmalletttypedef union cvmx_mio_emm_int cvmx_mio_emm_int_t; 3014232812Sjmallett 3015232812Sjmallett/** 3016232812Sjmallett * cvmx_mio_emm_int_en 3017232812Sjmallett * 3018232812Sjmallett * MIO_EMM_INT_EN = MIO EMMC Interrupt enable Register 3019232812Sjmallett * 3020232812Sjmallett */ 3021232812Sjmallettunion cvmx_mio_emm_int_en { 3022232812Sjmallett uint64_t u64; 3023232812Sjmallett struct cvmx_mio_emm_int_en_s { 3024232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3025232812Sjmallett uint64_t reserved_7_63 : 57; 3026232812Sjmallett uint64_t switch_err : 1; /**< Switch operation encountered an error. */ 3027232812Sjmallett uint64_t switch_done : 1; /**< Switch operation completed. */ 3028232812Sjmallett uint64_t dma_err : 1; /**< DMA transfer encountered an error. See MIO_EMM_RSP. */ 3029232812Sjmallett uint64_t cmd_err : 1; /**< Operation specified by MIO_EMM_CMD encountered an error. See 3030232812Sjmallett MIO_EMM_RSP. */ 3031232812Sjmallett uint64_t dma_done : 1; /**< DMA transfer completed */ 3032232812Sjmallett uint64_t cmd_done : 1; /**< Operation specified by MIO_EMM_CMD completed */ 3033232812Sjmallett uint64_t buf_done : 1; /**< The next 512B block transfer of a multi-block transfer has 3034232812Sjmallett completed. */ 3035232812Sjmallett#else 3036232812Sjmallett uint64_t buf_done : 1; 3037232812Sjmallett uint64_t cmd_done : 1; 3038232812Sjmallett uint64_t dma_done : 1; 3039232812Sjmallett uint64_t cmd_err : 1; 3040232812Sjmallett uint64_t dma_err : 1; 3041232812Sjmallett uint64_t switch_done : 1; 3042232812Sjmallett uint64_t switch_err : 1; 3043232812Sjmallett uint64_t reserved_7_63 : 57; 3044232812Sjmallett#endif 3045232812Sjmallett } s; 3046232812Sjmallett struct cvmx_mio_emm_int_en_s cn61xx; 3047232812Sjmallett struct cvmx_mio_emm_int_en_s cnf71xx; 3048232812Sjmallett}; 3049232812Sjmalletttypedef union cvmx_mio_emm_int_en cvmx_mio_emm_int_en_t; 3050232812Sjmallett 3051232812Sjmallett/** 3052232812Sjmallett * cvmx_mio_emm_mode# 3053232812Sjmallett * 3054232812Sjmallett * MIO_EMM_MODE = MIO EMMC Operating mode Register 3055232812Sjmallett * 3056232812Sjmallett */ 3057232812Sjmallettunion cvmx_mio_emm_modex { 3058232812Sjmallett uint64_t u64; 3059232812Sjmallett struct cvmx_mio_emm_modex_s { 3060232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3061232812Sjmallett uint64_t reserved_49_63 : 15; 3062232812Sjmallett uint64_t hs_timing : 1; /**< Current high speed timing mode. Required when CLK frequency 3063232812Sjmallett higher than 20MHz. */ 3064232812Sjmallett uint64_t reserved_43_47 : 5; 3065232812Sjmallett uint64_t bus_width : 3; /**< Current card bus mode. Out of reset, the card is in 1 bit data 3066232812Sjmallett bus mode. Select bus width. 3067232812Sjmallett 3068232812Sjmallett 0 - 1 bit data bus (power on) 3069232812Sjmallett 1 - 4 bit data bus 3070232812Sjmallett 2 - 8 bit data bus 3071232812Sjmallett 5 - 4 bit data bus (dual data rate) 3072232812Sjmallett 6 - 8 bit data bus (dual data rate) */ 3073232812Sjmallett uint64_t reserved_36_39 : 4; 3074232812Sjmallett uint64_t power_class : 4; /**< Out of reset, the card power class is 0, which is the minimum 3075232812Sjmallett current consumption class for the card. EXT_CSD bytes 3076232812Sjmallett [203:200] and [239:238] contain the power class for different 3077232812Sjmallett BUS_WITDH and CLK frequencies. Software should write this 3078232812Sjmallett field with the 4-bit field from the EXT_CSD bytes 3079232812Sjmallett corresponding to the selected operating mode. */ 3080232812Sjmallett uint64_t clk_hi : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin high */ 3081232812Sjmallett uint64_t clk_lo : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin low. */ 3082232812Sjmallett#else 3083232812Sjmallett uint64_t clk_lo : 16; 3084232812Sjmallett uint64_t clk_hi : 16; 3085232812Sjmallett uint64_t power_class : 4; 3086232812Sjmallett uint64_t reserved_36_39 : 4; 3087232812Sjmallett uint64_t bus_width : 3; 3088232812Sjmallett uint64_t reserved_43_47 : 5; 3089232812Sjmallett uint64_t hs_timing : 1; 3090232812Sjmallett uint64_t reserved_49_63 : 15; 3091232812Sjmallett#endif 3092232812Sjmallett } s; 3093232812Sjmallett struct cvmx_mio_emm_modex_s cn61xx; 3094232812Sjmallett struct cvmx_mio_emm_modex_s cnf71xx; 3095232812Sjmallett}; 3096232812Sjmalletttypedef union cvmx_mio_emm_modex cvmx_mio_emm_modex_t; 3097232812Sjmallett 3098232812Sjmallett/** 3099232812Sjmallett * cvmx_mio_emm_rca 3100232812Sjmallett */ 3101232812Sjmallettunion cvmx_mio_emm_rca { 3102232812Sjmallett uint64_t u64; 3103232812Sjmallett struct cvmx_mio_emm_rca_s { 3104232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3105232812Sjmallett uint64_t reserved_16_63 : 48; 3106232812Sjmallett uint64_t card_rca : 16; /**< Whenever SW performs CMD7, HW will update CARD_RCA with the 3107232812Sjmallett relative card address from the MIO_EMM_CMD[ARG] unless the 3108232812Sjmallett operations encounters an error. */ 3109232812Sjmallett#else 3110232812Sjmallett uint64_t card_rca : 16; 3111232812Sjmallett uint64_t reserved_16_63 : 48; 3112232812Sjmallett#endif 3113232812Sjmallett } s; 3114232812Sjmallett struct cvmx_mio_emm_rca_s cn61xx; 3115232812Sjmallett struct cvmx_mio_emm_rca_s cnf71xx; 3116232812Sjmallett}; 3117232812Sjmalletttypedef union cvmx_mio_emm_rca cvmx_mio_emm_rca_t; 3118232812Sjmallett 3119232812Sjmallett/** 3120232812Sjmallett * cvmx_mio_emm_rsp_hi 3121232812Sjmallett * 3122232812Sjmallett * MIO_EMM_RSP_HI = MIO EMMC Response data high Register 3123232812Sjmallett * 3124232812Sjmallett */ 3125232812Sjmallettunion cvmx_mio_emm_rsp_hi { 3126232812Sjmallett uint64_t u64; 3127232812Sjmallett struct cvmx_mio_emm_rsp_hi_s { 3128232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3129232812Sjmallett uint64_t dat : 64; /**< Command response (as per JEDEC eMMC spec) 3130232812Sjmallett 3131232812Sjmallett RSP_TYPE=1 - DAT[63:0] - 0x0 3132232812Sjmallett RSP_TYPE=2 - DAT[63:0] - CID[127:64] or CSD[127:64] 3133232812Sjmallett RSP_TYPE=3 - DAT[63:0] - 0x0 3134232812Sjmallett RSP_TYPE=4 - DAT[63:0] - 0x0 3135232812Sjmallett RSP_TYPE=5 - DAT[63:0] - 0x0 */ 3136232812Sjmallett#else 3137232812Sjmallett uint64_t dat : 64; 3138232812Sjmallett#endif 3139232812Sjmallett } s; 3140232812Sjmallett struct cvmx_mio_emm_rsp_hi_s cn61xx; 3141232812Sjmallett struct cvmx_mio_emm_rsp_hi_s cnf71xx; 3142232812Sjmallett}; 3143232812Sjmalletttypedef union cvmx_mio_emm_rsp_hi cvmx_mio_emm_rsp_hi_t; 3144232812Sjmallett 3145232812Sjmallett/** 3146232812Sjmallett * cvmx_mio_emm_rsp_lo 3147232812Sjmallett * 3148232812Sjmallett * MIO_EMM_RSP_LO = MIO EMMC Response data low Register 3149232812Sjmallett * 3150232812Sjmallett */ 3151232812Sjmallettunion cvmx_mio_emm_rsp_lo { 3152232812Sjmallett uint64_t u64; 3153232812Sjmallett struct cvmx_mio_emm_rsp_lo_s { 3154232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3155232812Sjmallett uint64_t dat : 64; /**< Command response (as per JEDEC eMMC spec) 3156232812Sjmallett 3157232812Sjmallett RSP_TYPE = 1 3158232812Sjmallett DAT[63:46] - 0x0 3159232812Sjmallett DAT[45:40] - Command index 3160232812Sjmallett DAT[39: 8] - Card status 3161232812Sjmallett DAT[ 7: 1] - CRC7 3162232812Sjmallett DAT[ 0] - End bit 3163232812Sjmallett 3164232812Sjmallett RSP_TYPE = 2 3165232812Sjmallett DAT[63: 1] - CID[63:1] or CSD[63:1] including CRC 3166232812Sjmallett DAT[ 0] - End bit 3167232812Sjmallett 3168232812Sjmallett RSP_TYPE = 3 3169232812Sjmallett DAT[63:46] - 0x0 3170232812Sjmallett DAT[45:40] - Check bits (0x3f) 3171232812Sjmallett DAT[39: 8] - OCR register 3172232812Sjmallett DAT[ 7: 1] - Check bits (0x7f) 3173232812Sjmallett DAT[ 0] - End bit 3174232812Sjmallett 3175232812Sjmallett RSP_TYPE = 4 3176232812Sjmallett DAT[63:46] - 0x0 3177232812Sjmallett DAT[45:40] - CMD39 ('10111') 3178232812Sjmallett DAT[39:24] - RCA[31:16] 3179232812Sjmallett DAT[ 23] - Status 3180232812Sjmallett DAT[22:16] - Register address 3181232812Sjmallett DAT[15: 8] - Register contents 3182232812Sjmallett DAT[ 7: 1] - CRC7 3183232812Sjmallett DAT[ 0] - End bit 3184232812Sjmallett 3185232812Sjmallett RSP_TYPE = 5 3186232812Sjmallett DAT[63:46] - 0x0 3187232812Sjmallett DAT[45:40] - CMD40 ('10100') 3188232812Sjmallett DAT[39:24] - RCA[31:16] 3189232812Sjmallett DAT[ 23] - Status 3190232812Sjmallett DAT[22:16] - Register address 3191232812Sjmallett DAT[15: 8] - Not defined. May be used for IRQ data 3192232812Sjmallett DAT[ 7: 1] - CRC7 3193232812Sjmallett DAT[ 0] - End bit */ 3194232812Sjmallett#else 3195232812Sjmallett uint64_t dat : 64; 3196232812Sjmallett#endif 3197232812Sjmallett } s; 3198232812Sjmallett struct cvmx_mio_emm_rsp_lo_s cn61xx; 3199232812Sjmallett struct cvmx_mio_emm_rsp_lo_s cnf71xx; 3200232812Sjmallett}; 3201232812Sjmalletttypedef union cvmx_mio_emm_rsp_lo cvmx_mio_emm_rsp_lo_t; 3202232812Sjmallett 3203232812Sjmallett/** 3204232812Sjmallett * cvmx_mio_emm_rsp_sts 3205232812Sjmallett * 3206232812Sjmallett * MIO_EMM_RSP_STS = MIO EMMC Response status Register 3207232812Sjmallett * 3208232812Sjmallett */ 3209232812Sjmallettunion cvmx_mio_emm_rsp_sts { 3210232812Sjmallett uint64_t u64; 3211232812Sjmallett struct cvmx_mio_emm_rsp_sts_s { 3212232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3213232812Sjmallett uint64_t reserved_62_63 : 2; 3214232812Sjmallett uint64_t bus_id : 2; /**< eMMC bus id to which the response status corresponds. */ 3215232812Sjmallett uint64_t cmd_val : 1; /**< Read-only copy of MIO_EMM_CMD[CMD_VAL]. CMD_VAL=1 indicates a 3216232812Sjmallett direct operation is in progress. */ 3217232812Sjmallett uint64_t switch_val : 1; /**< Read-only copy of MIO_EMM_SWITCH[SWITCH_EXE]. SWITCH_VAL=1 3218232812Sjmallett indicates a switch operation is in progress. */ 3219232812Sjmallett uint64_t dma_val : 1; /**< Read-only copy of MIO_EMM_DMA[DMA_VAL]. DMA_VAL=1 indicates a 3220232812Sjmallett DMA operation is in progress. */ 3221232812Sjmallett uint64_t dma_pend : 1; /**< The DMA engine has a pending transfer resulting from an error. 3222232812Sjmallett SW can resume the transfer by writing MIO_EMM_DMA[DMA_VAL]=1. 3223232812Sjmallett SW can terminate the transfer by writing MIO_EMM_DMA[DMA_VAL]=1 3224232812Sjmallett and MIO_EMM_DMA[NULL]=1. HW will clear DMA_PEND and perform 3225232812Sjmallett the DMA operation */ 3226232812Sjmallett uint64_t reserved_29_55 : 27; 3227232812Sjmallett uint64_t dbuf_err : 1; /**< For CMD_TYPE=1, indicates a DMA read data arrived from card 3228232812Sjmallett without a free DBUF. 3229232812Sjmallett 3230232812Sjmallett For CMD_TYPE=2, indicates a DBUF underflow occurred during a 3231232812Sjmallett DMA write. See MIO_EMM_DMA[THRES]. */ 3232232812Sjmallett uint64_t reserved_24_27 : 4; 3233232812Sjmallett uint64_t dbuf : 1; /**< DBUF corresponding to the most recently attempted block 3234232812Sjmallett transfer. */ 3235232812Sjmallett uint64_t blk_timeout : 1; /**< Timeout waiting for read data or 3bit CRC token */ 3236232812Sjmallett uint64_t blk_crc_err : 1; /**< For CMD_TYPE=1, indicates a card read data CRC mismatch. 3237232812Sjmallett MIO_EMM_RSP_STS[DBUF] indicates the failing data buffer. 3238232812Sjmallett 3239232812Sjmallett For CMD_TYPE=2, indicates card returned 3-bit CRC status token 3240232812Sjmallett indicating the card encountered a write data CRC check 3241232812Sjmallett mismatch. MIO_EMM_RSP_STS[DBUF] indicates the failing data 3242232812Sjmallett buffer. */ 3243232812Sjmallett uint64_t rsp_busybit : 1; /**< Debug only. eMMC protocol utilizes DAT0 as a busy signal 3244232812Sjmallett during block writes and R1b responses. */ 3245232812Sjmallett uint64_t stp_timeout : 1; /**< Stop transmission response timeout. */ 3246232812Sjmallett uint64_t stp_crc_err : 1; /**< Stop transmission response had a CRC error */ 3247232812Sjmallett uint64_t stp_bad_sts : 1; /**< Stop transmission response had bad status. */ 3248232812Sjmallett uint64_t stp_val : 1; /**< Stop transmission response valid. */ 3249232812Sjmallett uint64_t rsp_timeout : 1; /**< Response timeout */ 3250232812Sjmallett uint64_t rsp_crc_err : 1; /**< Response CRC error */ 3251232812Sjmallett uint64_t rsp_bad_sts : 1; /**< Response bad status */ 3252232812Sjmallett uint64_t rsp_val : 1; /**< Response id. See MIO_EMM_RSP_HI/LO */ 3253232812Sjmallett uint64_t rsp_type : 3; /**< Indicates the response type. See MIO_EMM_RSP_HI/LO */ 3254232812Sjmallett uint64_t cmd_type : 2; /**< eMMC command type (0=no data, 1=read, 2=write) */ 3255232812Sjmallett uint64_t cmd_idx : 6; /**< eMMC command index most recently attempted */ 3256232812Sjmallett uint64_t cmd_done : 1; /**< eMMC command completed. Once the command has complete, the 3257232812Sjmallett status is final and can be examined by SW. */ 3258232812Sjmallett#else 3259232812Sjmallett uint64_t cmd_done : 1; 3260232812Sjmallett uint64_t cmd_idx : 6; 3261232812Sjmallett uint64_t cmd_type : 2; 3262232812Sjmallett uint64_t rsp_type : 3; 3263232812Sjmallett uint64_t rsp_val : 1; 3264232812Sjmallett uint64_t rsp_bad_sts : 1; 3265232812Sjmallett uint64_t rsp_crc_err : 1; 3266232812Sjmallett uint64_t rsp_timeout : 1; 3267232812Sjmallett uint64_t stp_val : 1; 3268232812Sjmallett uint64_t stp_bad_sts : 1; 3269232812Sjmallett uint64_t stp_crc_err : 1; 3270232812Sjmallett uint64_t stp_timeout : 1; 3271232812Sjmallett uint64_t rsp_busybit : 1; 3272232812Sjmallett uint64_t blk_crc_err : 1; 3273232812Sjmallett uint64_t blk_timeout : 1; 3274232812Sjmallett uint64_t dbuf : 1; 3275232812Sjmallett uint64_t reserved_24_27 : 4; 3276232812Sjmallett uint64_t dbuf_err : 1; 3277232812Sjmallett uint64_t reserved_29_55 : 27; 3278232812Sjmallett uint64_t dma_pend : 1; 3279232812Sjmallett uint64_t dma_val : 1; 3280232812Sjmallett uint64_t switch_val : 1; 3281232812Sjmallett uint64_t cmd_val : 1; 3282232812Sjmallett uint64_t bus_id : 2; 3283232812Sjmallett uint64_t reserved_62_63 : 2; 3284232812Sjmallett#endif 3285232812Sjmallett } s; 3286232812Sjmallett struct cvmx_mio_emm_rsp_sts_s cn61xx; 3287232812Sjmallett struct cvmx_mio_emm_rsp_sts_s cnf71xx; 3288232812Sjmallett}; 3289232812Sjmalletttypedef union cvmx_mio_emm_rsp_sts cvmx_mio_emm_rsp_sts_t; 3290232812Sjmallett 3291232812Sjmallett/** 3292232812Sjmallett * cvmx_mio_emm_sample 3293232812Sjmallett */ 3294232812Sjmallettunion cvmx_mio_emm_sample { 3295232812Sjmallett uint64_t u64; 3296232812Sjmallett struct cvmx_mio_emm_sample_s { 3297232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3298232812Sjmallett uint64_t reserved_26_63 : 38; 3299232812Sjmallett uint64_t cmd_cnt : 10; /**< Number of SCLK cycles before the eMMC clock edge to sample the 3300232812Sjmallett command pin. */ 3301232812Sjmallett uint64_t reserved_10_15 : 6; 3302232812Sjmallett uint64_t dat_cnt : 10; /**< Number of SCLK cycles before the eMMC clock rising edge to 3303232812Sjmallett sample the data pin. */ 3304232812Sjmallett#else 3305232812Sjmallett uint64_t dat_cnt : 10; 3306232812Sjmallett uint64_t reserved_10_15 : 6; 3307232812Sjmallett uint64_t cmd_cnt : 10; 3308232812Sjmallett uint64_t reserved_26_63 : 38; 3309232812Sjmallett#endif 3310232812Sjmallett } s; 3311232812Sjmallett struct cvmx_mio_emm_sample_s cn61xx; 3312232812Sjmallett struct cvmx_mio_emm_sample_s cnf71xx; 3313232812Sjmallett}; 3314232812Sjmalletttypedef union cvmx_mio_emm_sample cvmx_mio_emm_sample_t; 3315232812Sjmallett 3316232812Sjmallett/** 3317232812Sjmallett * cvmx_mio_emm_sts_mask 3318232812Sjmallett */ 3319232812Sjmallettunion cvmx_mio_emm_sts_mask { 3320232812Sjmallett uint64_t u64; 3321232812Sjmallett struct cvmx_mio_emm_sts_mask_s { 3322232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3323232812Sjmallett uint64_t reserved_32_63 : 32; 3324232812Sjmallett uint64_t sts_msk : 32; /**< Any bit set in STS_MSK causes the corresponding bit in the card 3325232812Sjmallett status to be considered when computing response bad status. */ 3326232812Sjmallett#else 3327232812Sjmallett uint64_t sts_msk : 32; 3328232812Sjmallett uint64_t reserved_32_63 : 32; 3329232812Sjmallett#endif 3330232812Sjmallett } s; 3331232812Sjmallett struct cvmx_mio_emm_sts_mask_s cn61xx; 3332232812Sjmallett struct cvmx_mio_emm_sts_mask_s cnf71xx; 3333232812Sjmallett}; 3334232812Sjmalletttypedef union cvmx_mio_emm_sts_mask cvmx_mio_emm_sts_mask_t; 3335232812Sjmallett 3336232812Sjmallett/** 3337232812Sjmallett * cvmx_mio_emm_switch 3338232812Sjmallett * 3339232812Sjmallett * MIO_EMM_SWITCH = MIO EMMC Operating mode switch Register 3340232812Sjmallett * 3341232812Sjmallett */ 3342232812Sjmallettunion cvmx_mio_emm_switch { 3343232812Sjmallett uint64_t u64; 3344232812Sjmallett struct cvmx_mio_emm_switch_s { 3345232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3346232812Sjmallett uint64_t reserved_62_63 : 2; 3347232812Sjmallett uint64_t bus_id : 2; /**< Specify the eMMC bus */ 3348232812Sjmallett uint64_t switch_exe : 1; /**< When SWITCH_EXE is 0, the operating modes will be update 3349232812Sjmallett directly without performing any SWITCH operations. This 3350232812Sjmallett allows SW to perform the SWITCH operations manually, then 3351232812Sjmallett update the HW. 3352232812Sjmallett 3353232812Sjmallett SW writes this bit to a 1 to indicate that HW should perform 3354232812Sjmallett the necessary SWITCH operations. First, the POWER_CLASS 3355232812Sjmallett switch will be performed. If it fails, SWITCH_ERR0 will be 3356232812Sjmallett and the remaining SWITCH operations will not be performed. If 3357232812Sjmallett is succeeds, the POWER_CLASS field will be updated and the 3358232812Sjmallett HS_TIMING switch will be performed. If it fails, SWITCH_ERR1 3359232812Sjmallett will be set and the remaining SWITCH operations will not be 3360232812Sjmallett performed. If is succeeds, the HS_TIMING field will be 3361232812Sjmallett updated and the BUS_WITDH switch operation will be performed. 3362232812Sjmallett If it fails, SWITCH_ERR2 will be set. If it succeeds, the 3363232812Sjmallett BUS_WITDH will be updated. 3364232812Sjmallett 3365232812Sjmallett Changes to CLK_HI and CLK_LO are discarded if any switch error 3366232812Sjmallett occurs. */ 3367232812Sjmallett uint64_t switch_err0 : 1; /**< Error encounter while performing POWER_CLASS switch . See 3368232812Sjmallett MIO_EMM_RSP_STS */ 3369232812Sjmallett uint64_t switch_err1 : 1; /**< Error encounter while performing HS_TIMING switch . See 3370232812Sjmallett MIO_EMM_RSP_STS */ 3371232812Sjmallett uint64_t switch_err2 : 1; /**< Error encounter while performing BUS_WIDTH switch . See 3372232812Sjmallett MIO_EMM_RSP_STS */ 3373232812Sjmallett uint64_t reserved_49_55 : 7; 3374232812Sjmallett uint64_t hs_timing : 1; /**< Requested update to HS_TIMING */ 3375232812Sjmallett uint64_t reserved_43_47 : 5; 3376232812Sjmallett uint64_t bus_width : 3; /**< Requested update to BUS_WIDTH */ 3377232812Sjmallett uint64_t reserved_36_39 : 4; 3378232812Sjmallett uint64_t power_class : 4; /**< Requested update to POWER_CLASS */ 3379232812Sjmallett uint64_t clk_hi : 16; /**< Requested update to CLK_HI */ 3380232812Sjmallett uint64_t clk_lo : 16; /**< Requested update to CLK_LO */ 3381232812Sjmallett#else 3382232812Sjmallett uint64_t clk_lo : 16; 3383232812Sjmallett uint64_t clk_hi : 16; 3384232812Sjmallett uint64_t power_class : 4; 3385232812Sjmallett uint64_t reserved_36_39 : 4; 3386232812Sjmallett uint64_t bus_width : 3; 3387232812Sjmallett uint64_t reserved_43_47 : 5; 3388232812Sjmallett uint64_t hs_timing : 1; 3389232812Sjmallett uint64_t reserved_49_55 : 7; 3390232812Sjmallett uint64_t switch_err2 : 1; 3391232812Sjmallett uint64_t switch_err1 : 1; 3392232812Sjmallett uint64_t switch_err0 : 1; 3393232812Sjmallett uint64_t switch_exe : 1; 3394232812Sjmallett uint64_t bus_id : 2; 3395232812Sjmallett uint64_t reserved_62_63 : 2; 3396232812Sjmallett#endif 3397232812Sjmallett } s; 3398232812Sjmallett struct cvmx_mio_emm_switch_s cn61xx; 3399232812Sjmallett struct cvmx_mio_emm_switch_s cnf71xx; 3400232812Sjmallett}; 3401232812Sjmalletttypedef union cvmx_mio_emm_switch cvmx_mio_emm_switch_t; 3402232812Sjmallett 3403232812Sjmallett/** 3404232812Sjmallett * cvmx_mio_emm_wdog 3405232812Sjmallett * 3406232812Sjmallett * MIO_EMM_WDOG = MIO EMMC Watchdog Register 3407232812Sjmallett * 3408232812Sjmallett */ 3409232812Sjmallettunion cvmx_mio_emm_wdog { 3410232812Sjmallett uint64_t u64; 3411232812Sjmallett struct cvmx_mio_emm_wdog_s { 3412232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3413232812Sjmallett uint64_t reserved_26_63 : 38; 3414232812Sjmallett uint64_t clk_cnt : 26; /**< Number of CLK_CNT cycles to wait for the card to return a 3415232812Sjmallett response, read data, or the 3-bit CRC status token. */ 3416232812Sjmallett#else 3417232812Sjmallett uint64_t clk_cnt : 26; 3418232812Sjmallett uint64_t reserved_26_63 : 38; 3419232812Sjmallett#endif 3420232812Sjmallett } s; 3421232812Sjmallett struct cvmx_mio_emm_wdog_s cn61xx; 3422232812Sjmallett struct cvmx_mio_emm_wdog_s cnf71xx; 3423232812Sjmallett}; 3424232812Sjmalletttypedef union cvmx_mio_emm_wdog cvmx_mio_emm_wdog_t; 3425232812Sjmallett 3426232812Sjmallett/** 3427215976Sjmallett * cvmx_mio_fus_bnk_dat# 3428215976Sjmallett * 3429215976Sjmallett * Notes: 3430215976Sjmallett * The intial state of MIO_FUS_BNK_DAT* is as if bank6 was just read i.e. DAT* = fus[895:768] 3431215976Sjmallett * 3432215976Sjmallett */ 3433232812Sjmallettunion cvmx_mio_fus_bnk_datx { 3434215976Sjmallett uint64_t u64; 3435232812Sjmallett struct cvmx_mio_fus_bnk_datx_s { 3436232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3437215976Sjmallett uint64_t dat : 64; /**< Efuse bank store 3438215976Sjmallett For reads, the DAT gets the fus bank last read 3439215976Sjmallett For write, the DAT determines which fuses to blow */ 3440215976Sjmallett#else 3441215976Sjmallett uint64_t dat : 64; 3442215976Sjmallett#endif 3443215976Sjmallett } s; 3444215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn50xx; 3445215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn52xx; 3446215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn52xxp1; 3447215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn56xx; 3448215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 3449215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn58xx; 3450215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 3451232812Sjmallett struct cvmx_mio_fus_bnk_datx_s cn61xx; 3452215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn63xx; 3453215976Sjmallett struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 3454232812Sjmallett struct cvmx_mio_fus_bnk_datx_s cn66xx; 3455232812Sjmallett struct cvmx_mio_fus_bnk_datx_s cn68xx; 3456232812Sjmallett struct cvmx_mio_fus_bnk_datx_s cn68xxp1; 3457232812Sjmallett struct cvmx_mio_fus_bnk_datx_s cnf71xx; 3458215976Sjmallett}; 3459215976Sjmalletttypedef union cvmx_mio_fus_bnk_datx cvmx_mio_fus_bnk_datx_t; 3460215976Sjmallett 3461215976Sjmallett/** 3462215976Sjmallett * cvmx_mio_fus_dat0 3463215976Sjmallett */ 3464232812Sjmallettunion cvmx_mio_fus_dat0 { 3465215976Sjmallett uint64_t u64; 3466232812Sjmallett struct cvmx_mio_fus_dat0_s { 3467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3468215976Sjmallett uint64_t reserved_32_63 : 32; 3469215976Sjmallett uint64_t man_info : 32; /**< Fuse information - manufacturing info [31:0] */ 3470215976Sjmallett#else 3471215976Sjmallett uint64_t man_info : 32; 3472215976Sjmallett uint64_t reserved_32_63 : 32; 3473215976Sjmallett#endif 3474215976Sjmallett } s; 3475215976Sjmallett struct cvmx_mio_fus_dat0_s cn30xx; 3476215976Sjmallett struct cvmx_mio_fus_dat0_s cn31xx; 3477215976Sjmallett struct cvmx_mio_fus_dat0_s cn38xx; 3478215976Sjmallett struct cvmx_mio_fus_dat0_s cn38xxp2; 3479215976Sjmallett struct cvmx_mio_fus_dat0_s cn50xx; 3480215976Sjmallett struct cvmx_mio_fus_dat0_s cn52xx; 3481215976Sjmallett struct cvmx_mio_fus_dat0_s cn52xxp1; 3482215976Sjmallett struct cvmx_mio_fus_dat0_s cn56xx; 3483215976Sjmallett struct cvmx_mio_fus_dat0_s cn56xxp1; 3484215976Sjmallett struct cvmx_mio_fus_dat0_s cn58xx; 3485215976Sjmallett struct cvmx_mio_fus_dat0_s cn58xxp1; 3486232812Sjmallett struct cvmx_mio_fus_dat0_s cn61xx; 3487215976Sjmallett struct cvmx_mio_fus_dat0_s cn63xx; 3488215976Sjmallett struct cvmx_mio_fus_dat0_s cn63xxp1; 3489232812Sjmallett struct cvmx_mio_fus_dat0_s cn66xx; 3490232812Sjmallett struct cvmx_mio_fus_dat0_s cn68xx; 3491232812Sjmallett struct cvmx_mio_fus_dat0_s cn68xxp1; 3492232812Sjmallett struct cvmx_mio_fus_dat0_s cnf71xx; 3493215976Sjmallett}; 3494215976Sjmalletttypedef union cvmx_mio_fus_dat0 cvmx_mio_fus_dat0_t; 3495215976Sjmallett 3496215976Sjmallett/** 3497215976Sjmallett * cvmx_mio_fus_dat1 3498215976Sjmallett */ 3499232812Sjmallettunion cvmx_mio_fus_dat1 { 3500215976Sjmallett uint64_t u64; 3501232812Sjmallett struct cvmx_mio_fus_dat1_s { 3502232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3503215976Sjmallett uint64_t reserved_32_63 : 32; 3504215976Sjmallett uint64_t man_info : 32; /**< Fuse information - manufacturing info [63:32] */ 3505215976Sjmallett#else 3506215976Sjmallett uint64_t man_info : 32; 3507215976Sjmallett uint64_t reserved_32_63 : 32; 3508215976Sjmallett#endif 3509215976Sjmallett } s; 3510215976Sjmallett struct cvmx_mio_fus_dat1_s cn30xx; 3511215976Sjmallett struct cvmx_mio_fus_dat1_s cn31xx; 3512215976Sjmallett struct cvmx_mio_fus_dat1_s cn38xx; 3513215976Sjmallett struct cvmx_mio_fus_dat1_s cn38xxp2; 3514215976Sjmallett struct cvmx_mio_fus_dat1_s cn50xx; 3515215976Sjmallett struct cvmx_mio_fus_dat1_s cn52xx; 3516215976Sjmallett struct cvmx_mio_fus_dat1_s cn52xxp1; 3517215976Sjmallett struct cvmx_mio_fus_dat1_s cn56xx; 3518215976Sjmallett struct cvmx_mio_fus_dat1_s cn56xxp1; 3519215976Sjmallett struct cvmx_mio_fus_dat1_s cn58xx; 3520215976Sjmallett struct cvmx_mio_fus_dat1_s cn58xxp1; 3521232812Sjmallett struct cvmx_mio_fus_dat1_s cn61xx; 3522215976Sjmallett struct cvmx_mio_fus_dat1_s cn63xx; 3523215976Sjmallett struct cvmx_mio_fus_dat1_s cn63xxp1; 3524232812Sjmallett struct cvmx_mio_fus_dat1_s cn66xx; 3525232812Sjmallett struct cvmx_mio_fus_dat1_s cn68xx; 3526232812Sjmallett struct cvmx_mio_fus_dat1_s cn68xxp1; 3527232812Sjmallett struct cvmx_mio_fus_dat1_s cnf71xx; 3528215976Sjmallett}; 3529215976Sjmalletttypedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t; 3530215976Sjmallett 3531215976Sjmallett/** 3532215976Sjmallett * cvmx_mio_fus_dat2 3533215976Sjmallett * 3534215976Sjmallett * Notes: 3535215976Sjmallett * CHIP_ID is consumed in several places within Octeon. 3536215976Sjmallett * 3537215976Sjmallett * * Core COP0 ProcessorIdentification[Revision] 3538215976Sjmallett * * Core EJTAG DeviceIdentification[Version] 3539215976Sjmallett * * PCI_CFG02[RID] 3540215976Sjmallett * * JTAG controller 3541215976Sjmallett * 3542215976Sjmallett * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses. 3543215976Sjmallett * Modification to the efuses will not change what the JTAG controller reports 3544215976Sjmallett * for CHIP_ID. 3545215976Sjmallett */ 3546232812Sjmallettunion cvmx_mio_fus_dat2 { 3547215976Sjmallett uint64_t u64; 3548232812Sjmallett struct cvmx_mio_fus_dat2_s { 3549232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3550232812Sjmallett uint64_t reserved_48_63 : 16; 3551232812Sjmallett uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3552232812Sjmallett uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3553232812Sjmallett uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3554232812Sjmallett uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3555232812Sjmallett uint64_t fus318 : 1; /**< Reserved */ 3556215976Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3557215976Sjmallett uint64_t reserved_30_31 : 2; 3558215976Sjmallett uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3559215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3560215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3561232812Sjmallett uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3562232812Sjmallett together to select 1 of 4 mutually-exclusive 3563232812Sjmallett modes: 3564232812Sjmallett 3565232812Sjmallett DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3566232812Sjmallett DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3567232812Sjmallett DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3568232812Sjmallett DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3569215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3570215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3571215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3572215976Sjmallett uint64_t reserved_0_15 : 16; 3573215976Sjmallett#else 3574215976Sjmallett uint64_t reserved_0_15 : 16; 3575215976Sjmallett uint64_t chip_id : 8; 3576215976Sjmallett uint64_t bist_dis : 1; 3577215976Sjmallett uint64_t rst_sht : 1; 3578215976Sjmallett uint64_t nocrypto : 1; 3579215976Sjmallett uint64_t nomul : 1; 3580215976Sjmallett uint64_t nodfa_cp2 : 1; 3581215976Sjmallett uint64_t nokasu : 1; 3582215976Sjmallett uint64_t reserved_30_31 : 2; 3583215976Sjmallett uint64_t raid_en : 1; 3584215976Sjmallett uint64_t fus318 : 1; 3585215976Sjmallett uint64_t dorm_crypto : 1; 3586232812Sjmallett uint64_t power_limit : 2; 3587232812Sjmallett uint64_t rom_info : 10; 3588232812Sjmallett uint64_t fus118 : 1; 3589232812Sjmallett uint64_t reserved_48_63 : 16; 3590215976Sjmallett#endif 3591215976Sjmallett } s; 3592232812Sjmallett struct cvmx_mio_fus_dat2_cn30xx { 3593232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3594215976Sjmallett uint64_t reserved_29_63 : 35; 3595215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3596215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3597215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3598215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3599215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3600215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3601215976Sjmallett uint64_t pll_off : 4; /**< Fuse information - core pll offset 3602215976Sjmallett Used to compute the base offset for the core pll. 3603215976Sjmallett the offset will be (PLL_OFF ^ 8) 3604215976Sjmallett Note, these fuses can only be set from laser fuse */ 3605215976Sjmallett uint64_t reserved_1_11 : 11; 3606215976Sjmallett uint64_t pp_dis : 1; /**< Fuse information - PP_DISABLES */ 3607215976Sjmallett#else 3608215976Sjmallett uint64_t pp_dis : 1; 3609215976Sjmallett uint64_t reserved_1_11 : 11; 3610215976Sjmallett uint64_t pll_off : 4; 3611215976Sjmallett uint64_t chip_id : 8; 3612215976Sjmallett uint64_t bist_dis : 1; 3613215976Sjmallett uint64_t rst_sht : 1; 3614215976Sjmallett uint64_t nocrypto : 1; 3615215976Sjmallett uint64_t nomul : 1; 3616215976Sjmallett uint64_t nodfa_cp2 : 1; 3617215976Sjmallett uint64_t reserved_29_63 : 35; 3618215976Sjmallett#endif 3619215976Sjmallett } cn30xx; 3620232812Sjmallett struct cvmx_mio_fus_dat2_cn31xx { 3621232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3622215976Sjmallett uint64_t reserved_29_63 : 35; 3623215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3624215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3625215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3626215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3627215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3628215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3629215976Sjmallett uint64_t pll_off : 4; /**< Fuse information - core pll offset 3630215976Sjmallett Used to compute the base offset for the core pll. 3631215976Sjmallett the offset will be (PLL_OFF ^ 8) 3632215976Sjmallett Note, these fuses can only be set from laser fuse */ 3633215976Sjmallett uint64_t reserved_2_11 : 10; 3634215976Sjmallett uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */ 3635215976Sjmallett#else 3636215976Sjmallett uint64_t pp_dis : 2; 3637215976Sjmallett uint64_t reserved_2_11 : 10; 3638215976Sjmallett uint64_t pll_off : 4; 3639215976Sjmallett uint64_t chip_id : 8; 3640215976Sjmallett uint64_t bist_dis : 1; 3641215976Sjmallett uint64_t rst_sht : 1; 3642215976Sjmallett uint64_t nocrypto : 1; 3643215976Sjmallett uint64_t nomul : 1; 3644215976Sjmallett uint64_t nodfa_cp2 : 1; 3645215976Sjmallett uint64_t reserved_29_63 : 35; 3646215976Sjmallett#endif 3647215976Sjmallett } cn31xx; 3648232812Sjmallett struct cvmx_mio_fus_dat2_cn38xx { 3649232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3650215976Sjmallett uint64_t reserved_29_63 : 35; 3651215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) 3652215976Sjmallett (PASS2 Only) */ 3653215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable 3654215976Sjmallett (PASS2 Only) */ 3655215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable 3656215976Sjmallett (PASS2 Only) */ 3657215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3658215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3659215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3660215976Sjmallett uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */ 3661215976Sjmallett#else 3662215976Sjmallett uint64_t pp_dis : 16; 3663215976Sjmallett uint64_t chip_id : 8; 3664215976Sjmallett uint64_t bist_dis : 1; 3665215976Sjmallett uint64_t rst_sht : 1; 3666215976Sjmallett uint64_t nocrypto : 1; 3667215976Sjmallett uint64_t nomul : 1; 3668215976Sjmallett uint64_t nodfa_cp2 : 1; 3669215976Sjmallett uint64_t reserved_29_63 : 35; 3670215976Sjmallett#endif 3671215976Sjmallett } cn38xx; 3672215976Sjmallett struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; 3673232812Sjmallett struct cvmx_mio_fus_dat2_cn50xx { 3674232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3675215976Sjmallett uint64_t reserved_34_63 : 30; 3676215976Sjmallett uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3677215976Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled 3678215976Sjmallett (5020 does not have RAID co-processor) */ 3679215976Sjmallett uint64_t reserved_30_31 : 2; 3680215976Sjmallett uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3681215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) 3682215976Sjmallett (5020 does not have DFA co-processor) */ 3683215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3684215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3685215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3686215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3687215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3688215976Sjmallett uint64_t reserved_2_15 : 14; 3689215976Sjmallett uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */ 3690215976Sjmallett#else 3691215976Sjmallett uint64_t pp_dis : 2; 3692215976Sjmallett uint64_t reserved_2_15 : 14; 3693215976Sjmallett uint64_t chip_id : 8; 3694215976Sjmallett uint64_t bist_dis : 1; 3695215976Sjmallett uint64_t rst_sht : 1; 3696215976Sjmallett uint64_t nocrypto : 1; 3697215976Sjmallett uint64_t nomul : 1; 3698215976Sjmallett uint64_t nodfa_cp2 : 1; 3699215976Sjmallett uint64_t nokasu : 1; 3700215976Sjmallett uint64_t reserved_30_31 : 2; 3701215976Sjmallett uint64_t raid_en : 1; 3702215976Sjmallett uint64_t fus318 : 1; 3703215976Sjmallett uint64_t reserved_34_63 : 30; 3704215976Sjmallett#endif 3705215976Sjmallett } cn50xx; 3706232812Sjmallett struct cvmx_mio_fus_dat2_cn52xx { 3707232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3708215976Sjmallett uint64_t reserved_34_63 : 30; 3709215976Sjmallett uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3710215976Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3711215976Sjmallett uint64_t reserved_30_31 : 2; 3712215976Sjmallett uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3713215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3714215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3715215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3716215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3717215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3718215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3719215976Sjmallett uint64_t reserved_4_15 : 12; 3720215976Sjmallett uint64_t pp_dis : 4; /**< Fuse information - PP_DISABLES */ 3721215976Sjmallett#else 3722215976Sjmallett uint64_t pp_dis : 4; 3723215976Sjmallett uint64_t reserved_4_15 : 12; 3724215976Sjmallett uint64_t chip_id : 8; 3725215976Sjmallett uint64_t bist_dis : 1; 3726215976Sjmallett uint64_t rst_sht : 1; 3727215976Sjmallett uint64_t nocrypto : 1; 3728215976Sjmallett uint64_t nomul : 1; 3729215976Sjmallett uint64_t nodfa_cp2 : 1; 3730215976Sjmallett uint64_t nokasu : 1; 3731215976Sjmallett uint64_t reserved_30_31 : 2; 3732215976Sjmallett uint64_t raid_en : 1; 3733215976Sjmallett uint64_t fus318 : 1; 3734215976Sjmallett uint64_t reserved_34_63 : 30; 3735215976Sjmallett#endif 3736215976Sjmallett } cn52xx; 3737215976Sjmallett struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; 3738232812Sjmallett struct cvmx_mio_fus_dat2_cn56xx { 3739232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3740215976Sjmallett uint64_t reserved_34_63 : 30; 3741215976Sjmallett uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3742215976Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3743215976Sjmallett uint64_t reserved_30_31 : 2; 3744215976Sjmallett uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3745215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3746215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3747215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3748215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3749215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3750215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3751215976Sjmallett uint64_t reserved_12_15 : 4; 3752215976Sjmallett uint64_t pp_dis : 12; /**< Fuse information - PP_DISABLES */ 3753215976Sjmallett#else 3754215976Sjmallett uint64_t pp_dis : 12; 3755215976Sjmallett uint64_t reserved_12_15 : 4; 3756215976Sjmallett uint64_t chip_id : 8; 3757215976Sjmallett uint64_t bist_dis : 1; 3758215976Sjmallett uint64_t rst_sht : 1; 3759215976Sjmallett uint64_t nocrypto : 1; 3760215976Sjmallett uint64_t nomul : 1; 3761215976Sjmallett uint64_t nodfa_cp2 : 1; 3762215976Sjmallett uint64_t nokasu : 1; 3763215976Sjmallett uint64_t reserved_30_31 : 2; 3764215976Sjmallett uint64_t raid_en : 1; 3765215976Sjmallett uint64_t fus318 : 1; 3766215976Sjmallett uint64_t reserved_34_63 : 30; 3767215976Sjmallett#endif 3768215976Sjmallett } cn56xx; 3769215976Sjmallett struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; 3770232812Sjmallett struct cvmx_mio_fus_dat2_cn58xx { 3771232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3772215976Sjmallett uint64_t reserved_30_63 : 34; 3773215976Sjmallett uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3774215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3775215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3776215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3777215976Sjmallett uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3778215976Sjmallett uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3779215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3780215976Sjmallett uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */ 3781215976Sjmallett#else 3782215976Sjmallett uint64_t pp_dis : 16; 3783215976Sjmallett uint64_t chip_id : 8; 3784215976Sjmallett uint64_t bist_dis : 1; 3785215976Sjmallett uint64_t rst_sht : 1; 3786215976Sjmallett uint64_t nocrypto : 1; 3787215976Sjmallett uint64_t nomul : 1; 3788215976Sjmallett uint64_t nodfa_cp2 : 1; 3789215976Sjmallett uint64_t nokasu : 1; 3790215976Sjmallett uint64_t reserved_30_63 : 34; 3791215976Sjmallett#endif 3792215976Sjmallett } cn58xx; 3793215976Sjmallett struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 3794232812Sjmallett struct cvmx_mio_fus_dat2_cn61xx { 3795232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3796232812Sjmallett uint64_t reserved_48_63 : 16; 3797232812Sjmallett uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3798232812Sjmallett uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3799232812Sjmallett uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3800232812Sjmallett uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3801232812Sjmallett uint64_t fus318 : 1; /**< Reserved */ 3802232812Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3803232812Sjmallett uint64_t reserved_29_31 : 3; 3804232812Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3805232812Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3806232812Sjmallett uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3807232812Sjmallett together to select 1 of 4 mutually-exclusive 3808232812Sjmallett modes: 3809232812Sjmallett 3810232812Sjmallett DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3811232812Sjmallett DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3812232812Sjmallett DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3813232812Sjmallett DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3814232812Sjmallett uint64_t reserved_24_25 : 2; 3815232812Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3816232812Sjmallett uint64_t reserved_4_15 : 12; 3817232812Sjmallett uint64_t pp_dis : 4; /**< Fuse information - PP_DISABLES */ 3818232812Sjmallett#else 3819232812Sjmallett uint64_t pp_dis : 4; 3820232812Sjmallett uint64_t reserved_4_15 : 12; 3821232812Sjmallett uint64_t chip_id : 8; 3822232812Sjmallett uint64_t reserved_24_25 : 2; 3823232812Sjmallett uint64_t nocrypto : 1; 3824232812Sjmallett uint64_t nomul : 1; 3825232812Sjmallett uint64_t nodfa_cp2 : 1; 3826232812Sjmallett uint64_t reserved_29_31 : 3; 3827232812Sjmallett uint64_t raid_en : 1; 3828232812Sjmallett uint64_t fus318 : 1; 3829232812Sjmallett uint64_t dorm_crypto : 1; 3830232812Sjmallett uint64_t power_limit : 2; 3831232812Sjmallett uint64_t rom_info : 10; 3832232812Sjmallett uint64_t fus118 : 1; 3833232812Sjmallett uint64_t reserved_48_63 : 16; 3834232812Sjmallett#endif 3835232812Sjmallett } cn61xx; 3836232812Sjmallett struct cvmx_mio_fus_dat2_cn63xx { 3837232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3838215976Sjmallett uint64_t reserved_35_63 : 29; 3839215976Sjmallett uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */ 3840232812Sjmallett uint64_t fus318 : 1; /**< Reserved */ 3841215976Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3842215976Sjmallett uint64_t reserved_29_31 : 3; 3843215976Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3844215976Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3845215976Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3846215976Sjmallett uint64_t reserved_24_25 : 2; 3847215976Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3848215976Sjmallett uint64_t reserved_6_15 : 10; 3849215976Sjmallett uint64_t pp_dis : 6; /**< Fuse information - PP_DISABLES */ 3850215976Sjmallett#else 3851215976Sjmallett uint64_t pp_dis : 6; 3852215976Sjmallett uint64_t reserved_6_15 : 10; 3853215976Sjmallett uint64_t chip_id : 8; 3854215976Sjmallett uint64_t reserved_24_25 : 2; 3855215976Sjmallett uint64_t nocrypto : 1; 3856215976Sjmallett uint64_t nomul : 1; 3857215976Sjmallett uint64_t nodfa_cp2 : 1; 3858215976Sjmallett uint64_t reserved_29_31 : 3; 3859215976Sjmallett uint64_t raid_en : 1; 3860215976Sjmallett uint64_t fus318 : 1; 3861215976Sjmallett uint64_t dorm_crypto : 1; 3862215976Sjmallett uint64_t reserved_35_63 : 29; 3863215976Sjmallett#endif 3864215976Sjmallett } cn63xx; 3865215976Sjmallett struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 3866232812Sjmallett struct cvmx_mio_fus_dat2_cn66xx { 3867232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3868232812Sjmallett uint64_t reserved_48_63 : 16; 3869232812Sjmallett uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3870232812Sjmallett uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3871232812Sjmallett uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3872232812Sjmallett uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3873232812Sjmallett uint64_t fus318 : 1; /**< Reserved */ 3874232812Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3875232812Sjmallett uint64_t reserved_29_31 : 3; 3876232812Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3877232812Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3878232812Sjmallett uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3879232812Sjmallett together to select 1 of 4 mutually-exclusive 3880232812Sjmallett modes: 3881232812Sjmallett 3882232812Sjmallett DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3883232812Sjmallett DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3884232812Sjmallett DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3885232812Sjmallett DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3886232812Sjmallett uint64_t reserved_24_25 : 2; 3887232812Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3888232812Sjmallett uint64_t reserved_10_15 : 6; 3889232812Sjmallett uint64_t pp_dis : 10; /**< Fuse information - PP_DISABLES */ 3890232812Sjmallett#else 3891232812Sjmallett uint64_t pp_dis : 10; 3892232812Sjmallett uint64_t reserved_10_15 : 6; 3893232812Sjmallett uint64_t chip_id : 8; 3894232812Sjmallett uint64_t reserved_24_25 : 2; 3895232812Sjmallett uint64_t nocrypto : 1; 3896232812Sjmallett uint64_t nomul : 1; 3897232812Sjmallett uint64_t nodfa_cp2 : 1; 3898232812Sjmallett uint64_t reserved_29_31 : 3; 3899232812Sjmallett uint64_t raid_en : 1; 3900232812Sjmallett uint64_t fus318 : 1; 3901232812Sjmallett uint64_t dorm_crypto : 1; 3902232812Sjmallett uint64_t power_limit : 2; 3903232812Sjmallett uint64_t rom_info : 10; 3904232812Sjmallett uint64_t fus118 : 1; 3905232812Sjmallett uint64_t reserved_48_63 : 16; 3906232812Sjmallett#endif 3907232812Sjmallett } cn66xx; 3908232812Sjmallett struct cvmx_mio_fus_dat2_cn68xx { 3909232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3910232812Sjmallett uint64_t reserved_37_63 : 27; 3911232812Sjmallett uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3912232812Sjmallett uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */ 3913232812Sjmallett uint64_t fus318 : 1; /**< Reserved */ 3914232812Sjmallett uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3915232812Sjmallett uint64_t reserved_29_31 : 3; 3916232812Sjmallett uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3917232812Sjmallett uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3918232812Sjmallett uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3919232812Sjmallett uint64_t reserved_24_25 : 2; 3920232812Sjmallett uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3921232812Sjmallett uint64_t reserved_0_15 : 16; 3922232812Sjmallett#else 3923232812Sjmallett uint64_t reserved_0_15 : 16; 3924232812Sjmallett uint64_t chip_id : 8; 3925232812Sjmallett uint64_t reserved_24_25 : 2; 3926232812Sjmallett uint64_t nocrypto : 1; 3927232812Sjmallett uint64_t nomul : 1; 3928232812Sjmallett uint64_t nodfa_cp2 : 1; 3929232812Sjmallett uint64_t reserved_29_31 : 3; 3930232812Sjmallett uint64_t raid_en : 1; 3931232812Sjmallett uint64_t fus318 : 1; 3932232812Sjmallett uint64_t dorm_crypto : 1; 3933232812Sjmallett uint64_t power_limit : 2; 3934232812Sjmallett uint64_t reserved_37_63 : 27; 3935232812Sjmallett#endif 3936232812Sjmallett } cn68xx; 3937232812Sjmallett struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; 3938232812Sjmallett struct cvmx_mio_fus_dat2_cn61xx cnf71xx; 3939215976Sjmallett}; 3940215976Sjmalletttypedef union cvmx_mio_fus_dat2 cvmx_mio_fus_dat2_t; 3941215976Sjmallett 3942215976Sjmallett/** 3943215976Sjmallett * cvmx_mio_fus_dat3 3944215976Sjmallett */ 3945232812Sjmallettunion cvmx_mio_fus_dat3 { 3946215976Sjmallett uint64_t u64; 3947232812Sjmallett struct cvmx_mio_fus_dat3_s { 3948232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3949215976Sjmallett uint64_t reserved_58_63 : 6; 3950215976Sjmallett uint64_t pll_ctl : 10; /**< Fuse information - PLL control */ 3951215976Sjmallett uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */ 3952215976Sjmallett uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */ 3953215976Sjmallett uint64_t reserved_40_40 : 1; 3954215976Sjmallett uint64_t ema : 2; /**< Fuse information - EMA */ 3955215976Sjmallett uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */ 3956215976Sjmallett uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */ 3957215976Sjmallett uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */ 3958215976Sjmallett uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */ 3959215976Sjmallett uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 3960215976Sjmallett (laser fuse only) */ 3961215976Sjmallett uint64_t reserved_29_30 : 2; 3962215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */ 3963215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 3964215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */ 3965215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 3966215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 3967215976Sjmallett uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 3968215976Sjmallett#else 3969215976Sjmallett uint64_t icache : 24; 3970215976Sjmallett uint64_t nodfa_dte : 1; 3971215976Sjmallett uint64_t nozip : 1; 3972215976Sjmallett uint64_t efus_ign : 1; 3973215976Sjmallett uint64_t efus_lck : 1; 3974215976Sjmallett uint64_t bar2_en : 1; 3975215976Sjmallett uint64_t reserved_29_30 : 2; 3976215976Sjmallett uint64_t pll_div4 : 1; 3977215976Sjmallett uint64_t l2c_crip : 3; 3978215976Sjmallett uint64_t pll_half_dis : 1; 3979215976Sjmallett uint64_t efus_lck_man : 1; 3980215976Sjmallett uint64_t efus_lck_rsv : 1; 3981215976Sjmallett uint64_t ema : 2; 3982215976Sjmallett uint64_t reserved_40_40 : 1; 3983215976Sjmallett uint64_t dfa_info_clm : 4; 3984215976Sjmallett uint64_t dfa_info_dte : 3; 3985215976Sjmallett uint64_t pll_ctl : 10; 3986215976Sjmallett uint64_t reserved_58_63 : 6; 3987215976Sjmallett#endif 3988215976Sjmallett } s; 3989232812Sjmallett struct cvmx_mio_fus_dat3_cn30xx { 3990232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3991215976Sjmallett uint64_t reserved_32_63 : 32; 3992215976Sjmallett uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 3993215976Sjmallett (laser fuse only) */ 3994215976Sjmallett uint64_t reserved_29_30 : 2; 3995215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */ 3996215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 3997215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 3998215976Sjmallett This bit only has side effects when blown in 3999215976Sjmallett the laser fuses. It is ignore if only set in 4000215976Sjmallett efuse store. */ 4001215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4002215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4003215976Sjmallett uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4004215976Sjmallett#else 4005215976Sjmallett uint64_t icache : 24; 4006215976Sjmallett uint64_t nodfa_dte : 1; 4007215976Sjmallett uint64_t nozip : 1; 4008215976Sjmallett uint64_t efus_ign : 1; 4009215976Sjmallett uint64_t efus_lck : 1; 4010215976Sjmallett uint64_t bar2_en : 1; 4011215976Sjmallett uint64_t reserved_29_30 : 2; 4012215976Sjmallett uint64_t pll_div4 : 1; 4013215976Sjmallett uint64_t reserved_32_63 : 32; 4014215976Sjmallett#endif 4015215976Sjmallett } cn30xx; 4016232812Sjmallett struct cvmx_mio_fus_dat3_cn31xx { 4017232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4018215976Sjmallett uint64_t reserved_32_63 : 32; 4019215976Sjmallett uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 4020215976Sjmallett (laser fuse only) */ 4021215976Sjmallett uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple 4022215976Sjmallett (O2P Only) */ 4023215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */ 4024215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 4025215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4026215976Sjmallett This bit only has side effects when blown in 4027215976Sjmallett the laser fuses. It is ignore if only set in 4028215976Sjmallett efuse store. */ 4029215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4030215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4031215976Sjmallett uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4032215976Sjmallett#else 4033215976Sjmallett uint64_t icache : 24; 4034215976Sjmallett uint64_t nodfa_dte : 1; 4035215976Sjmallett uint64_t nozip : 1; 4036215976Sjmallett uint64_t efus_ign : 1; 4037215976Sjmallett uint64_t efus_lck : 1; 4038215976Sjmallett uint64_t bar2_en : 1; 4039215976Sjmallett uint64_t zip_crip : 2; 4040215976Sjmallett uint64_t pll_div4 : 1; 4041215976Sjmallett uint64_t reserved_32_63 : 32; 4042215976Sjmallett#endif 4043215976Sjmallett } cn31xx; 4044232812Sjmallett struct cvmx_mio_fus_dat3_cn38xx { 4045232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4046215976Sjmallett uint64_t reserved_31_63 : 33; 4047215976Sjmallett uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple 4048215976Sjmallett (PASS3 Only) */ 4049215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') 4050215976Sjmallett (PASS2 Only) */ 4051215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown 4052215976Sjmallett (PASS2 Only) */ 4053215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4054215976Sjmallett This bit only has side effects when blown in 4055215976Sjmallett the laser fuses. It is ignore if only set in 4056215976Sjmallett efuse store. 4057215976Sjmallett (PASS2 Only) */ 4058215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable 4059215976Sjmallett (PASS2 Only) */ 4060215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) 4061215976Sjmallett (PASS2 Only) */ 4062215976Sjmallett uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4063215976Sjmallett#else 4064215976Sjmallett uint64_t icache : 24; 4065215976Sjmallett uint64_t nodfa_dte : 1; 4066215976Sjmallett uint64_t nozip : 1; 4067215976Sjmallett uint64_t efus_ign : 1; 4068215976Sjmallett uint64_t efus_lck : 1; 4069215976Sjmallett uint64_t bar2_en : 1; 4070215976Sjmallett uint64_t zip_crip : 2; 4071215976Sjmallett uint64_t reserved_31_63 : 33; 4072215976Sjmallett#endif 4073215976Sjmallett } cn38xx; 4074232812Sjmallett struct cvmx_mio_fus_dat3_cn38xxp2 { 4075232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4076215976Sjmallett uint64_t reserved_29_63 : 35; 4077215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') 4078215976Sjmallett (PASS2 Only) */ 4079215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown 4080215976Sjmallett (PASS2 Only) */ 4081215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4082215976Sjmallett This bit only has side effects when blown in 4083215976Sjmallett the laser fuses. It is ignore if only set in 4084215976Sjmallett efuse store. 4085215976Sjmallett (PASS2 Only) */ 4086215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable 4087215976Sjmallett (PASS2 Only) */ 4088215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) 4089215976Sjmallett (PASS2 Only) */ 4090215976Sjmallett uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4091215976Sjmallett#else 4092215976Sjmallett uint64_t icache : 24; 4093215976Sjmallett uint64_t nodfa_dte : 1; 4094215976Sjmallett uint64_t nozip : 1; 4095215976Sjmallett uint64_t efus_ign : 1; 4096215976Sjmallett uint64_t efus_lck : 1; 4097215976Sjmallett uint64_t bar2_en : 1; 4098215976Sjmallett uint64_t reserved_29_63 : 35; 4099215976Sjmallett#endif 4100215976Sjmallett } cn38xxp2; 4101215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn50xx; 4102215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn52xx; 4103215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; 4104215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn56xx; 4105215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 4106215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn58xx; 4107215976Sjmallett struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 4108232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx { 4109232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4110215976Sjmallett uint64_t reserved_58_63 : 6; 4111215976Sjmallett uint64_t pll_ctl : 10; /**< Fuse information - PLL control */ 4112215976Sjmallett uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */ 4113215976Sjmallett uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */ 4114215976Sjmallett uint64_t reserved_40_40 : 1; 4115215976Sjmallett uint64_t ema : 2; /**< Fuse information - EMA */ 4116215976Sjmallett uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */ 4117215976Sjmallett uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */ 4118215976Sjmallett uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */ 4119215976Sjmallett uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */ 4120215976Sjmallett uint64_t reserved_31_31 : 1; 4121215976Sjmallett uint64_t zip_info : 2; /**< Fuse information - Zip information */ 4122215976Sjmallett uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */ 4123215976Sjmallett uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 4124215976Sjmallett uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */ 4125215976Sjmallett uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4126215976Sjmallett uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4127215976Sjmallett uint64_t reserved_0_23 : 24; 4128215976Sjmallett#else 4129215976Sjmallett uint64_t reserved_0_23 : 24; 4130215976Sjmallett uint64_t nodfa_dte : 1; 4131215976Sjmallett uint64_t nozip : 1; 4132215976Sjmallett uint64_t efus_ign : 1; 4133215976Sjmallett uint64_t efus_lck : 1; 4134215976Sjmallett uint64_t bar2_en : 1; 4135215976Sjmallett uint64_t zip_info : 2; 4136215976Sjmallett uint64_t reserved_31_31 : 1; 4137215976Sjmallett uint64_t l2c_crip : 3; 4138215976Sjmallett uint64_t pll_half_dis : 1; 4139215976Sjmallett uint64_t efus_lck_man : 1; 4140215976Sjmallett uint64_t efus_lck_rsv : 1; 4141215976Sjmallett uint64_t ema : 2; 4142215976Sjmallett uint64_t reserved_40_40 : 1; 4143215976Sjmallett uint64_t dfa_info_clm : 4; 4144215976Sjmallett uint64_t dfa_info_dte : 3; 4145215976Sjmallett uint64_t pll_ctl : 10; 4146215976Sjmallett uint64_t reserved_58_63 : 6; 4147215976Sjmallett#endif 4148232812Sjmallett } cn61xx; 4149232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cn63xx; 4150232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; 4151232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cn66xx; 4152232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cn68xx; 4153232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; 4154232812Sjmallett struct cvmx_mio_fus_dat3_cn61xx cnf71xx; 4155215976Sjmallett}; 4156215976Sjmalletttypedef union cvmx_mio_fus_dat3 cvmx_mio_fus_dat3_t; 4157215976Sjmallett 4158215976Sjmallett/** 4159215976Sjmallett * cvmx_mio_fus_ema 4160232812Sjmallett * 4161232812Sjmallett * DON'T PUT IN HRM* 4162232812Sjmallett * 4163215976Sjmallett */ 4164232812Sjmallettunion cvmx_mio_fus_ema { 4165215976Sjmallett uint64_t u64; 4166232812Sjmallett struct cvmx_mio_fus_ema_s { 4167232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4168215976Sjmallett uint64_t reserved_7_63 : 57; 4169215976Sjmallett uint64_t eff_ema : 3; /**< Reserved */ 4170215976Sjmallett uint64_t reserved_3_3 : 1; 4171215976Sjmallett uint64_t ema : 3; /**< Reserved */ 4172215976Sjmallett#else 4173215976Sjmallett uint64_t ema : 3; 4174215976Sjmallett uint64_t reserved_3_3 : 1; 4175215976Sjmallett uint64_t eff_ema : 3; 4176215976Sjmallett uint64_t reserved_7_63 : 57; 4177215976Sjmallett#endif 4178215976Sjmallett } s; 4179215976Sjmallett struct cvmx_mio_fus_ema_s cn50xx; 4180215976Sjmallett struct cvmx_mio_fus_ema_s cn52xx; 4181215976Sjmallett struct cvmx_mio_fus_ema_s cn52xxp1; 4182215976Sjmallett struct cvmx_mio_fus_ema_s cn56xx; 4183215976Sjmallett struct cvmx_mio_fus_ema_s cn56xxp1; 4184232812Sjmallett struct cvmx_mio_fus_ema_cn58xx { 4185232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4186215976Sjmallett uint64_t reserved_2_63 : 62; 4187215976Sjmallett uint64_t ema : 2; /**< EMA Settings */ 4188215976Sjmallett#else 4189215976Sjmallett uint64_t ema : 2; 4190215976Sjmallett uint64_t reserved_2_63 : 62; 4191215976Sjmallett#endif 4192215976Sjmallett } cn58xx; 4193215976Sjmallett struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 4194232812Sjmallett struct cvmx_mio_fus_ema_s cn61xx; 4195215976Sjmallett struct cvmx_mio_fus_ema_s cn63xx; 4196215976Sjmallett struct cvmx_mio_fus_ema_s cn63xxp1; 4197232812Sjmallett struct cvmx_mio_fus_ema_s cn66xx; 4198232812Sjmallett struct cvmx_mio_fus_ema_s cn68xx; 4199232812Sjmallett struct cvmx_mio_fus_ema_s cn68xxp1; 4200232812Sjmallett struct cvmx_mio_fus_ema_s cnf71xx; 4201215976Sjmallett}; 4202215976Sjmalletttypedef union cvmx_mio_fus_ema cvmx_mio_fus_ema_t; 4203215976Sjmallett 4204215976Sjmallett/** 4205215976Sjmallett * cvmx_mio_fus_pdf 4206215976Sjmallett */ 4207232812Sjmallettunion cvmx_mio_fus_pdf { 4208215976Sjmallett uint64_t u64; 4209232812Sjmallett struct cvmx_mio_fus_pdf_s { 4210232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4211215976Sjmallett uint64_t pdf : 64; /**< Fuse information - Product Definition Field */ 4212215976Sjmallett#else 4213215976Sjmallett uint64_t pdf : 64; 4214215976Sjmallett#endif 4215215976Sjmallett } s; 4216215976Sjmallett struct cvmx_mio_fus_pdf_s cn50xx; 4217215976Sjmallett struct cvmx_mio_fus_pdf_s cn52xx; 4218215976Sjmallett struct cvmx_mio_fus_pdf_s cn52xxp1; 4219215976Sjmallett struct cvmx_mio_fus_pdf_s cn56xx; 4220215976Sjmallett struct cvmx_mio_fus_pdf_s cn56xxp1; 4221215976Sjmallett struct cvmx_mio_fus_pdf_s cn58xx; 4222232812Sjmallett struct cvmx_mio_fus_pdf_s cn61xx; 4223215976Sjmallett struct cvmx_mio_fus_pdf_s cn63xx; 4224215976Sjmallett struct cvmx_mio_fus_pdf_s cn63xxp1; 4225232812Sjmallett struct cvmx_mio_fus_pdf_s cn66xx; 4226232812Sjmallett struct cvmx_mio_fus_pdf_s cn68xx; 4227232812Sjmallett struct cvmx_mio_fus_pdf_s cn68xxp1; 4228232812Sjmallett struct cvmx_mio_fus_pdf_s cnf71xx; 4229215976Sjmallett}; 4230215976Sjmalletttypedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t; 4231215976Sjmallett 4232215976Sjmallett/** 4233215976Sjmallett * cvmx_mio_fus_pll 4234215976Sjmallett * 4235215976Sjmallett * Notes: 4236215976Sjmallett * The core clkout postscaler should be placed in reset at least 10 ref clocks prior to changing 4237215976Sjmallett * the core clkout select. The core clkout postscaler should remain under reset for at least 10 4238215976Sjmallett * ref clocks after the core clkout select changes. 4239215976Sjmallett * 4240215976Sjmallett * The pnr clkout postscaler should be placed in reset at least 10 ref clocks prior to changing 4241215976Sjmallett * the pnr clkout select. The pnr clkout postscaler should remain under reset for at least 10 4242215976Sjmallett * ref clocks after the pnr clkout select changes. 4243215976Sjmallett */ 4244232812Sjmallettunion cvmx_mio_fus_pll { 4245215976Sjmallett uint64_t u64; 4246232812Sjmallett struct cvmx_mio_fus_pll_s { 4247232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4248232812Sjmallett uint64_t reserved_48_63 : 16; 4249232812Sjmallett uint64_t rclk_align_r : 8; /**< RCLK right alignment settings */ 4250232812Sjmallett uint64_t rclk_align_l : 8; /**< RCLK left alignment settings */ 4251232812Sjmallett uint64_t reserved_8_31 : 24; 4252215976Sjmallett uint64_t c_cout_rst : 1; /**< Core clkout postscaler reset */ 4253215976Sjmallett uint64_t c_cout_sel : 2; /**< Core clkout select 4254232812Sjmallett 0=RCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4255232812Sjmallett (***Pass 1.x: 3=GND) */ 4256215976Sjmallett uint64_t pnr_cout_rst : 1; /**< PNR clkout postscaler reset */ 4257215976Sjmallett uint64_t pnr_cout_sel : 2; /**< PNR clkout select 4258232812Sjmallett 0=SCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4259232812Sjmallett (***Pass 1.x: 3=GND) */ 4260215976Sjmallett uint64_t rfslip : 1; /**< Reserved */ 4261215976Sjmallett uint64_t fbslip : 1; /**< Reserved */ 4262215976Sjmallett#else 4263215976Sjmallett uint64_t fbslip : 1; 4264215976Sjmallett uint64_t rfslip : 1; 4265215976Sjmallett uint64_t pnr_cout_sel : 2; 4266215976Sjmallett uint64_t pnr_cout_rst : 1; 4267215976Sjmallett uint64_t c_cout_sel : 2; 4268215976Sjmallett uint64_t c_cout_rst : 1; 4269232812Sjmallett uint64_t reserved_8_31 : 24; 4270232812Sjmallett uint64_t rclk_align_l : 8; 4271232812Sjmallett uint64_t rclk_align_r : 8; 4272232812Sjmallett uint64_t reserved_48_63 : 16; 4273215976Sjmallett#endif 4274215976Sjmallett } s; 4275232812Sjmallett struct cvmx_mio_fus_pll_cn50xx { 4276232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4277215976Sjmallett uint64_t reserved_2_63 : 62; 4278215976Sjmallett uint64_t rfslip : 1; /**< PLL reference clock slip */ 4279215976Sjmallett uint64_t fbslip : 1; /**< PLL feedback clock slip */ 4280215976Sjmallett#else 4281215976Sjmallett uint64_t fbslip : 1; 4282215976Sjmallett uint64_t rfslip : 1; 4283215976Sjmallett uint64_t reserved_2_63 : 62; 4284215976Sjmallett#endif 4285215976Sjmallett } cn50xx; 4286215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn52xx; 4287215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn52xxp1; 4288215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn56xx; 4289215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 4290215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn58xx; 4291215976Sjmallett struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 4292232812Sjmallett struct cvmx_mio_fus_pll_cn61xx { 4293232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4294232812Sjmallett uint64_t reserved_8_63 : 56; 4295232812Sjmallett uint64_t c_cout_rst : 1; /**< Core clkout postscaler reset */ 4296232812Sjmallett uint64_t c_cout_sel : 2; /**< Core clkout select 4297232812Sjmallett 0=RCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4298232812Sjmallett (***Pass 1.x: 3=GND) */ 4299232812Sjmallett uint64_t pnr_cout_rst : 1; /**< PNR clkout postscaler reset */ 4300232812Sjmallett uint64_t pnr_cout_sel : 2; /**< PNR clkout select 4301232812Sjmallett 0=SCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4302232812Sjmallett (***Pass 1.x: 3=GND) */ 4303232812Sjmallett uint64_t rfslip : 1; /**< Reserved */ 4304232812Sjmallett uint64_t fbslip : 1; /**< Reserved */ 4305232812Sjmallett#else 4306232812Sjmallett uint64_t fbslip : 1; 4307232812Sjmallett uint64_t rfslip : 1; 4308232812Sjmallett uint64_t pnr_cout_sel : 2; 4309232812Sjmallett uint64_t pnr_cout_rst : 1; 4310232812Sjmallett uint64_t c_cout_sel : 2; 4311232812Sjmallett uint64_t c_cout_rst : 1; 4312232812Sjmallett uint64_t reserved_8_63 : 56; 4313232812Sjmallett#endif 4314232812Sjmallett } cn61xx; 4315232812Sjmallett struct cvmx_mio_fus_pll_cn61xx cn63xx; 4316232812Sjmallett struct cvmx_mio_fus_pll_cn61xx cn63xxp1; 4317232812Sjmallett struct cvmx_mio_fus_pll_cn61xx cn66xx; 4318232812Sjmallett struct cvmx_mio_fus_pll_s cn68xx; 4319232812Sjmallett struct cvmx_mio_fus_pll_s cn68xxp1; 4320232812Sjmallett struct cvmx_mio_fus_pll_cn61xx cnf71xx; 4321215976Sjmallett}; 4322215976Sjmalletttypedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t; 4323215976Sjmallett 4324215976Sjmallett/** 4325215976Sjmallett * cvmx_mio_fus_prog 4326215976Sjmallett * 4327215976Sjmallett * DON'T PUT IN HRM* 4328215976Sjmallett * 4329215976Sjmallett * 4330215976Sjmallett * Notes: 4331215976Sjmallett * This CSR is not present in the HRM. 4332215976Sjmallett * 4333215976Sjmallett * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be 4334215976Sjmallett * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which 4335215976Sjmallett * fuses to blow. Once ADDR, and DAT are setup, SW can write to 4336215976Sjmallett * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG. Once PROG is 4337215976Sjmallett * clear, the bank write is complete. 4338215976Sjmallett * 4339215976Sjmallett * A soft blow is still subject to lockdown fuses. After a soft/warm reset, the 4340215976Sjmallett * chip will behave as though the fuses were actually blown. A cold reset restores 4341215976Sjmallett * the actual fuse valuse. 4342215976Sjmallett */ 4343232812Sjmallettunion cvmx_mio_fus_prog { 4344215976Sjmallett uint64_t u64; 4345232812Sjmallett struct cvmx_mio_fus_prog_s { 4346232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4347215976Sjmallett uint64_t reserved_2_63 : 62; 4348215976Sjmallett uint64_t soft : 1; /**< When set with PROG, causes only the local storeage 4349215976Sjmallett to change. Will not really blow any fuses. HW 4350215976Sjmallett will clear when the program operation is complete */ 4351215976Sjmallett uint64_t prog : 1; /**< Blow the fuse bank 4352215976Sjmallett SW will set PROG, and then the HW will clear 4353215976Sjmallett when the program operation is complete */ 4354215976Sjmallett#else 4355215976Sjmallett uint64_t prog : 1; 4356215976Sjmallett uint64_t soft : 1; 4357215976Sjmallett uint64_t reserved_2_63 : 62; 4358215976Sjmallett#endif 4359215976Sjmallett } s; 4360232812Sjmallett struct cvmx_mio_fus_prog_cn30xx { 4361232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4362215976Sjmallett uint64_t reserved_1_63 : 63; 4363215976Sjmallett uint64_t prog : 1; /**< Blow the fuse 4364215976Sjmallett SW will set PROG, hold it for 10us, then clear it */ 4365215976Sjmallett#else 4366215976Sjmallett uint64_t prog : 1; 4367215976Sjmallett uint64_t reserved_1_63 : 63; 4368215976Sjmallett#endif 4369215976Sjmallett } cn30xx; 4370215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn31xx; 4371215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn38xx; 4372215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn38xxp2; 4373215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn50xx; 4374215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn52xx; 4375215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn52xxp1; 4376215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn56xx; 4377215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 4378215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn58xx; 4379215976Sjmallett struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 4380232812Sjmallett struct cvmx_mio_fus_prog_s cn61xx; 4381215976Sjmallett struct cvmx_mio_fus_prog_s cn63xx; 4382215976Sjmallett struct cvmx_mio_fus_prog_s cn63xxp1; 4383232812Sjmallett struct cvmx_mio_fus_prog_s cn66xx; 4384232812Sjmallett struct cvmx_mio_fus_prog_s cn68xx; 4385232812Sjmallett struct cvmx_mio_fus_prog_s cn68xxp1; 4386232812Sjmallett struct cvmx_mio_fus_prog_s cnf71xx; 4387215976Sjmallett}; 4388215976Sjmalletttypedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t; 4389215976Sjmallett 4390215976Sjmallett/** 4391215976Sjmallett * cvmx_mio_fus_prog_times 4392215976Sjmallett * 4393215976Sjmallett * DON'T PUT IN HRM* 4394215976Sjmallett * 4395215976Sjmallett * 4396215976Sjmallett * Notes: 4397215976Sjmallett * This CSR is not present in the HRM. 4398215976Sjmallett * 4399215976Sjmallett * All values must be > 0 for correct electrical operation. 4400215976Sjmallett * 4401215976Sjmallett * IFB fuses are 0..1791 4402215976Sjmallett * L6G fuses are 1792 to 2047 4403215976Sjmallett * 4404215976Sjmallett * The reset values are for IFB fuses for ref_clk of 100MHZ 4405215976Sjmallett */ 4406232812Sjmallettunion cvmx_mio_fus_prog_times { 4407215976Sjmallett uint64_t u64; 4408232812Sjmallett struct cvmx_mio_fus_prog_times_s { 4409232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4410215976Sjmallett uint64_t reserved_35_63 : 29; 4411215976Sjmallett uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */ 4412215976Sjmallett uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */ 4413215976Sjmallett uint64_t prog_pin : 1; /**< efuse program pin (IFB) */ 4414215976Sjmallett uint64_t reserved_6_31 : 26; 4415215976Sjmallett uint64_t setup : 6; /**< efuse timing param 4416215976Sjmallett 4417215976Sjmallett SETUP = (tWRS/refclk period)-1 4418215976Sjmallett 4419215976Sjmallett For IFB: tWRS = 20ns 4420215976Sjmallett For L6G: tWRS = 20ns */ 4421215976Sjmallett#else 4422215976Sjmallett uint64_t setup : 6; 4423215976Sjmallett uint64_t reserved_6_31 : 26; 4424215976Sjmallett uint64_t prog_pin : 1; 4425215976Sjmallett uint64_t fsrc_pin : 1; 4426215976Sjmallett uint64_t vgate_pin : 1; 4427215976Sjmallett uint64_t reserved_35_63 : 29; 4428215976Sjmallett#endif 4429215976Sjmallett } s; 4430232812Sjmallett struct cvmx_mio_fus_prog_times_cn50xx { 4431232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4432215976Sjmallett uint64_t reserved_33_63 : 31; 4433215976Sjmallett uint64_t prog_pin : 1; /**< efuse program pin */ 4434215976Sjmallett uint64_t out : 8; /**< efuse timing param (ref_clks to delay 10ns) */ 4435215976Sjmallett uint64_t sclk_lo : 4; /**< efuse timing param (ref_clks to delay 5ns) */ 4436215976Sjmallett uint64_t sclk_hi : 12; /**< efuse timing param (ref_clks to delay 1000ns) */ 4437215976Sjmallett uint64_t setup : 8; /**< efuse timing param (ref_clks to delay 10ns) */ 4438215976Sjmallett#else 4439215976Sjmallett uint64_t setup : 8; 4440215976Sjmallett uint64_t sclk_hi : 12; 4441215976Sjmallett uint64_t sclk_lo : 4; 4442215976Sjmallett uint64_t out : 8; 4443215976Sjmallett uint64_t prog_pin : 1; 4444215976Sjmallett uint64_t reserved_33_63 : 31; 4445215976Sjmallett#endif 4446215976Sjmallett } cn50xx; 4447215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn52xx; 4448215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; 4449215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn56xx; 4450215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 4451215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 4452215976Sjmallett struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 4453232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx { 4454232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4455215976Sjmallett uint64_t reserved_35_63 : 29; 4456215976Sjmallett uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */ 4457215976Sjmallett uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */ 4458215976Sjmallett uint64_t prog_pin : 1; /**< efuse program pin (IFB) */ 4459215976Sjmallett uint64_t out : 7; /**< efuse timing param 4460215976Sjmallett 4461215976Sjmallett OUT = (tOUT/refclk period)-1 4462215976Sjmallett 4463215976Sjmallett For IFB: tOUT = 20ns 4464215976Sjmallett For L6G: tOUT = 20ns */ 4465215976Sjmallett uint64_t sclk_lo : 4; /**< efuse timing param 4466215976Sjmallett 4467215976Sjmallett SCLK_LO=(tSLO/refclk period)-1 4468215976Sjmallett 4469215976Sjmallett For IFB: tSLO = 20ns 4470215976Sjmallett For L6G: tSLO = 20ns */ 4471215976Sjmallett uint64_t sclk_hi : 15; /**< efuse timing param 4472215976Sjmallett ***NOTE: Pass 1.x reset value is 20000 4473215976Sjmallett 4474215976Sjmallett SCLK_HI=(tSHI/refclk period)-1 4475215976Sjmallett 4476215976Sjmallett For IFB: tSHI = 200us 4477215976Sjmallett For L6G: tSHI = 25us */ 4478215976Sjmallett uint64_t setup : 6; /**< efuse timing param 4479215976Sjmallett 4480215976Sjmallett SETUP = (tWRS/refclk period)-1 4481215976Sjmallett 4482215976Sjmallett For IFB: tWRS = 20ns 4483215976Sjmallett For L6G: tWRS = 20ns */ 4484215976Sjmallett#else 4485215976Sjmallett uint64_t setup : 6; 4486215976Sjmallett uint64_t sclk_hi : 15; 4487215976Sjmallett uint64_t sclk_lo : 4; 4488215976Sjmallett uint64_t out : 7; 4489215976Sjmallett uint64_t prog_pin : 1; 4490215976Sjmallett uint64_t fsrc_pin : 1; 4491215976Sjmallett uint64_t vgate_pin : 1; 4492215976Sjmallett uint64_t reserved_35_63 : 29; 4493215976Sjmallett#endif 4494232812Sjmallett } cn61xx; 4495232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cn63xx; 4496232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; 4497232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cn66xx; 4498232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cn68xx; 4499232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; 4500232812Sjmallett struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; 4501215976Sjmallett}; 4502215976Sjmalletttypedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t; 4503215976Sjmallett 4504215976Sjmallett/** 4505215976Sjmallett * cvmx_mio_fus_rcmd 4506215976Sjmallett * 4507215976Sjmallett * Notes: 4508215976Sjmallett * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of 4509215976Sjmallett * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND]. When PEND is 4510215976Sjmallett * clear, then MIO_FUS_RCMD[DAT] is valid. In addition, if the efuse read went 4511215976Sjmallett * to the efuse banks (eg. ((ADDR/16) not [0,1,7]) || EFUSE) SW can read 4512215976Sjmallett * MIO_FUS_BNK_DATX which contains all 128 fuses in the bank associated in 4513215976Sjmallett * ADDR. 4514215976Sjmallett */ 4515232812Sjmallettunion cvmx_mio_fus_rcmd { 4516215976Sjmallett uint64_t u64; 4517232812Sjmallett struct cvmx_mio_fus_rcmd_s { 4518232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4519215976Sjmallett uint64_t reserved_24_63 : 40; 4520215976Sjmallett uint64_t dat : 8; /**< 8bits of fuse data */ 4521215976Sjmallett uint64_t reserved_13_15 : 3; 4522215976Sjmallett uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read 4523215976Sjmallett operation. HW clears when read is complete and 4524215976Sjmallett the DAT is valid */ 4525215976Sjmallett uint64_t reserved_9_11 : 3; 4526215976Sjmallett uint64_t efuse : 1; /**< When set, return data from the efuse storage 4527215976Sjmallett rather than the local storage */ 4528215976Sjmallett uint64_t addr : 8; /**< The byte address of the fuse to read */ 4529215976Sjmallett#else 4530215976Sjmallett uint64_t addr : 8; 4531215976Sjmallett uint64_t efuse : 1; 4532215976Sjmallett uint64_t reserved_9_11 : 3; 4533215976Sjmallett uint64_t pend : 1; 4534215976Sjmallett uint64_t reserved_13_15 : 3; 4535215976Sjmallett uint64_t dat : 8; 4536215976Sjmallett uint64_t reserved_24_63 : 40; 4537215976Sjmallett#endif 4538215976Sjmallett } s; 4539232812Sjmallett struct cvmx_mio_fus_rcmd_cn30xx { 4540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4541215976Sjmallett uint64_t reserved_24_63 : 40; 4542215976Sjmallett uint64_t dat : 8; /**< 8bits of fuse data */ 4543215976Sjmallett uint64_t reserved_13_15 : 3; 4544215976Sjmallett uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read 4545215976Sjmallett operation. HW clears when read is complete and 4546215976Sjmallett the DAT is valid */ 4547215976Sjmallett uint64_t reserved_9_11 : 3; 4548215976Sjmallett uint64_t efuse : 1; /**< When set, return data from the efuse storage 4549215976Sjmallett rather than the local storage for the 320 HW fuses */ 4550215976Sjmallett uint64_t reserved_7_7 : 1; 4551215976Sjmallett uint64_t addr : 7; /**< The byte address of the fuse to read */ 4552215976Sjmallett#else 4553215976Sjmallett uint64_t addr : 7; 4554215976Sjmallett uint64_t reserved_7_7 : 1; 4555215976Sjmallett uint64_t efuse : 1; 4556215976Sjmallett uint64_t reserved_9_11 : 3; 4557215976Sjmallett uint64_t pend : 1; 4558215976Sjmallett uint64_t reserved_13_15 : 3; 4559215976Sjmallett uint64_t dat : 8; 4560215976Sjmallett uint64_t reserved_24_63 : 40; 4561215976Sjmallett#endif 4562215976Sjmallett } cn30xx; 4563215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn31xx; 4564215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn38xx; 4565215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; 4566215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn50xx; 4567215976Sjmallett struct cvmx_mio_fus_rcmd_s cn52xx; 4568215976Sjmallett struct cvmx_mio_fus_rcmd_s cn52xxp1; 4569215976Sjmallett struct cvmx_mio_fus_rcmd_s cn56xx; 4570215976Sjmallett struct cvmx_mio_fus_rcmd_s cn56xxp1; 4571215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 4572215976Sjmallett struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 4573232812Sjmallett struct cvmx_mio_fus_rcmd_s cn61xx; 4574215976Sjmallett struct cvmx_mio_fus_rcmd_s cn63xx; 4575215976Sjmallett struct cvmx_mio_fus_rcmd_s cn63xxp1; 4576232812Sjmallett struct cvmx_mio_fus_rcmd_s cn66xx; 4577232812Sjmallett struct cvmx_mio_fus_rcmd_s cn68xx; 4578232812Sjmallett struct cvmx_mio_fus_rcmd_s cn68xxp1; 4579232812Sjmallett struct cvmx_mio_fus_rcmd_s cnf71xx; 4580215976Sjmallett}; 4581215976Sjmalletttypedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t; 4582215976Sjmallett 4583215976Sjmallett/** 4584215976Sjmallett * cvmx_mio_fus_read_times 4585215976Sjmallett * 4586215976Sjmallett * Notes: 4587215976Sjmallett * IFB fuses are 0..1791 4588215976Sjmallett * L6G fuses are 1792 to 2047 4589215976Sjmallett * 4590215976Sjmallett * The reset values are for IFB fuses for refclk up to 100MHZ when core PLL is enagaged 4591215976Sjmallett * 4592215976Sjmallett * If any of the formulas above result in a value less than zero, the corresponding 4593215976Sjmallett * timing parameter should be set to zero. 4594215976Sjmallett * 4595215976Sjmallett * Prior to issuing a read to the fuse banks (via. MIO_FUS_RCMD), this register 4596215976Sjmallett * should be written with the timing parameters which correspond to the fuse bank type (IFB vs L6G) 4597215976Sjmallett * that will be read. 4598215976Sjmallett * 4599215976Sjmallett * This register should not be written while MIO_FUS_RCMD[PEND]=1. 4600215976Sjmallett */ 4601232812Sjmallettunion cvmx_mio_fus_read_times { 4602215976Sjmallett uint64_t u64; 4603232812Sjmallett struct cvmx_mio_fus_read_times_s { 4604232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4605215976Sjmallett uint64_t reserved_26_63 : 38; 4606215976Sjmallett uint64_t sch : 4; /**< Hold CS for (SCH+1) refclks after FSET desserts 4607215976Sjmallett 4608215976Sjmallett SCH = (tSCH/refclk period)-1 4609215976Sjmallett 4610215976Sjmallett For IFB: tSCH = 160ns 4611215976Sjmallett For L6G: tSCH = 10ns */ 4612215976Sjmallett uint64_t fsh : 4; /**< Hold FSET for (FSH+1) refclks after PRCHG deasserts 4613215976Sjmallett 4614215976Sjmallett FSH = (tFSH/refclk period)-1 4615215976Sjmallett 4616215976Sjmallett For IFB: tFSH = 160ns 4617215976Sjmallett For L6G: tFSH = 10ns */ 4618215976Sjmallett uint64_t prh : 4; /**< Assert PRCHG (PRH+1) refclks after SIGDEV deasserts 4619215976Sjmallett 4620215976Sjmallett PRH = (tPRH/refclk period)-1 4621215976Sjmallett 4622215976Sjmallett For IFB: tPRH = 70ns 4623215976Sjmallett For L6G: tPRH = 10ns */ 4624215976Sjmallett uint64_t sdh : 4; /**< Hold SIGDEV for (SDH+1) refclks after FSET asserts 4625215976Sjmallett 4626215976Sjmallett SDH = (tSDH/refclk period)-1 4627215976Sjmallett 4628215976Sjmallett For IFB: tPRH = 10ns 4629215976Sjmallett For L6G: tPRH = 10ns */ 4630215976Sjmallett uint64_t setup : 10; /**< Assert CS for (SETUP+1) refclks before asserting 4631215976Sjmallett SIGDEV, FSET, or PRCHG 4632215976Sjmallett 4633215976Sjmallett SETUP=(tRDS/refclk period)-1 4634215976Sjmallett 4635215976Sjmallett For IFB: tRDS = 10000ns 4636215976Sjmallett For L6G: tRDS = max(tSCS,tSDS,tPRS) 4637215976Sjmallett where tSCS = 10ns 4638215976Sjmallett tSDS = 10ns 4639215976Sjmallett tPRS = 10ns */ 4640215976Sjmallett#else 4641215976Sjmallett uint64_t setup : 10; 4642215976Sjmallett uint64_t sdh : 4; 4643215976Sjmallett uint64_t prh : 4; 4644215976Sjmallett uint64_t fsh : 4; 4645215976Sjmallett uint64_t sch : 4; 4646215976Sjmallett uint64_t reserved_26_63 : 38; 4647215976Sjmallett#endif 4648215976Sjmallett } s; 4649232812Sjmallett struct cvmx_mio_fus_read_times_s cn61xx; 4650215976Sjmallett struct cvmx_mio_fus_read_times_s cn63xx; 4651215976Sjmallett struct cvmx_mio_fus_read_times_s cn63xxp1; 4652232812Sjmallett struct cvmx_mio_fus_read_times_s cn66xx; 4653232812Sjmallett struct cvmx_mio_fus_read_times_s cn68xx; 4654232812Sjmallett struct cvmx_mio_fus_read_times_s cn68xxp1; 4655232812Sjmallett struct cvmx_mio_fus_read_times_s cnf71xx; 4656215976Sjmallett}; 4657215976Sjmalletttypedef union cvmx_mio_fus_read_times cvmx_mio_fus_read_times_t; 4658215976Sjmallett 4659215976Sjmallett/** 4660215976Sjmallett * cvmx_mio_fus_repair_res0 4661215976Sjmallett */ 4662232812Sjmallettunion cvmx_mio_fus_repair_res0 { 4663215976Sjmallett uint64_t u64; 4664232812Sjmallett struct cvmx_mio_fus_repair_res0_s { 4665232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4666215976Sjmallett uint64_t reserved_55_63 : 9; 4667215976Sjmallett uint64_t too_many : 1; /**< Too many defects */ 4668215976Sjmallett uint64_t repair2 : 18; /**< BISR Results */ 4669215976Sjmallett uint64_t repair1 : 18; /**< BISR Results */ 4670215976Sjmallett uint64_t repair0 : 18; /**< BISR Results */ 4671215976Sjmallett#else 4672215976Sjmallett uint64_t repair0 : 18; 4673215976Sjmallett uint64_t repair1 : 18; 4674215976Sjmallett uint64_t repair2 : 18; 4675215976Sjmallett uint64_t too_many : 1; 4676215976Sjmallett uint64_t reserved_55_63 : 9; 4677215976Sjmallett#endif 4678215976Sjmallett } s; 4679232812Sjmallett struct cvmx_mio_fus_repair_res0_s cn61xx; 4680215976Sjmallett struct cvmx_mio_fus_repair_res0_s cn63xx; 4681215976Sjmallett struct cvmx_mio_fus_repair_res0_s cn63xxp1; 4682232812Sjmallett struct cvmx_mio_fus_repair_res0_s cn66xx; 4683232812Sjmallett struct cvmx_mio_fus_repair_res0_s cn68xx; 4684232812Sjmallett struct cvmx_mio_fus_repair_res0_s cn68xxp1; 4685232812Sjmallett struct cvmx_mio_fus_repair_res0_s cnf71xx; 4686215976Sjmallett}; 4687215976Sjmalletttypedef union cvmx_mio_fus_repair_res0 cvmx_mio_fus_repair_res0_t; 4688215976Sjmallett 4689215976Sjmallett/** 4690215976Sjmallett * cvmx_mio_fus_repair_res1 4691215976Sjmallett */ 4692232812Sjmallettunion cvmx_mio_fus_repair_res1 { 4693215976Sjmallett uint64_t u64; 4694232812Sjmallett struct cvmx_mio_fus_repair_res1_s { 4695232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4696215976Sjmallett uint64_t reserved_54_63 : 10; 4697215976Sjmallett uint64_t repair5 : 18; /**< BISR Results */ 4698215976Sjmallett uint64_t repair4 : 18; /**< BISR Results */ 4699215976Sjmallett uint64_t repair3 : 18; /**< BISR Results */ 4700215976Sjmallett#else 4701215976Sjmallett uint64_t repair3 : 18; 4702215976Sjmallett uint64_t repair4 : 18; 4703215976Sjmallett uint64_t repair5 : 18; 4704215976Sjmallett uint64_t reserved_54_63 : 10; 4705215976Sjmallett#endif 4706215976Sjmallett } s; 4707232812Sjmallett struct cvmx_mio_fus_repair_res1_s cn61xx; 4708215976Sjmallett struct cvmx_mio_fus_repair_res1_s cn63xx; 4709215976Sjmallett struct cvmx_mio_fus_repair_res1_s cn63xxp1; 4710232812Sjmallett struct cvmx_mio_fus_repair_res1_s cn66xx; 4711232812Sjmallett struct cvmx_mio_fus_repair_res1_s cn68xx; 4712232812Sjmallett struct cvmx_mio_fus_repair_res1_s cn68xxp1; 4713232812Sjmallett struct cvmx_mio_fus_repair_res1_s cnf71xx; 4714215976Sjmallett}; 4715215976Sjmalletttypedef union cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res1_t; 4716215976Sjmallett 4717215976Sjmallett/** 4718215976Sjmallett * cvmx_mio_fus_repair_res2 4719215976Sjmallett */ 4720232812Sjmallettunion cvmx_mio_fus_repair_res2 { 4721215976Sjmallett uint64_t u64; 4722232812Sjmallett struct cvmx_mio_fus_repair_res2_s { 4723232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4724215976Sjmallett uint64_t reserved_18_63 : 46; 4725215976Sjmallett uint64_t repair6 : 18; /**< BISR Results */ 4726215976Sjmallett#else 4727215976Sjmallett uint64_t repair6 : 18; 4728215976Sjmallett uint64_t reserved_18_63 : 46; 4729215976Sjmallett#endif 4730215976Sjmallett } s; 4731232812Sjmallett struct cvmx_mio_fus_repair_res2_s cn61xx; 4732215976Sjmallett struct cvmx_mio_fus_repair_res2_s cn63xx; 4733215976Sjmallett struct cvmx_mio_fus_repair_res2_s cn63xxp1; 4734232812Sjmallett struct cvmx_mio_fus_repair_res2_s cn66xx; 4735232812Sjmallett struct cvmx_mio_fus_repair_res2_s cn68xx; 4736232812Sjmallett struct cvmx_mio_fus_repair_res2_s cn68xxp1; 4737232812Sjmallett struct cvmx_mio_fus_repair_res2_s cnf71xx; 4738215976Sjmallett}; 4739215976Sjmalletttypedef union cvmx_mio_fus_repair_res2 cvmx_mio_fus_repair_res2_t; 4740215976Sjmallett 4741215976Sjmallett/** 4742215976Sjmallett * cvmx_mio_fus_spr_repair_res 4743215976Sjmallett * 4744232812Sjmallett * DON'T PUT IN HRM* 4745215976Sjmallett * 4746215976Sjmallett */ 4747232812Sjmallettunion cvmx_mio_fus_spr_repair_res { 4748215976Sjmallett uint64_t u64; 4749232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s { 4750232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4751215976Sjmallett uint64_t reserved_42_63 : 22; 4752215976Sjmallett uint64_t repair2 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4753215976Sjmallett uint64_t repair1 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4754215976Sjmallett uint64_t repair0 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4755215976Sjmallett#else 4756215976Sjmallett uint64_t repair0 : 14; 4757215976Sjmallett uint64_t repair1 : 14; 4758215976Sjmallett uint64_t repair2 : 14; 4759215976Sjmallett uint64_t reserved_42_63 : 22; 4760215976Sjmallett#endif 4761215976Sjmallett } s; 4762215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn30xx; 4763215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn31xx; 4764215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn38xx; 4765215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn50xx; 4766215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn52xx; 4767215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; 4768215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn56xx; 4769215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 4770215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn58xx; 4771215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 4772232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn61xx; 4773215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn63xx; 4774215976Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 4775232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn66xx; 4776232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn68xx; 4777232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; 4778232812Sjmallett struct cvmx_mio_fus_spr_repair_res_s cnf71xx; 4779215976Sjmallett}; 4780215976Sjmalletttypedef union cvmx_mio_fus_spr_repair_res cvmx_mio_fus_spr_repair_res_t; 4781215976Sjmallett 4782215976Sjmallett/** 4783215976Sjmallett * cvmx_mio_fus_spr_repair_sum 4784215976Sjmallett * 4785232812Sjmallett * DON'T PUT IN HRM* 4786215976Sjmallett * 4787215976Sjmallett */ 4788232812Sjmallettunion cvmx_mio_fus_spr_repair_sum { 4789215976Sjmallett uint64_t u64; 4790232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s { 4791232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4792215976Sjmallett uint64_t reserved_1_63 : 63; 4793215976Sjmallett uint64_t too_many : 1; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4794215976Sjmallett#else 4795215976Sjmallett uint64_t too_many : 1; 4796215976Sjmallett uint64_t reserved_1_63 : 63; 4797215976Sjmallett#endif 4798215976Sjmallett } s; 4799215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn30xx; 4800215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn31xx; 4801215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn38xx; 4802215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn50xx; 4803215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn52xx; 4804215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; 4805215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn56xx; 4806215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 4807215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 4808215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 4809232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn61xx; 4810215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 4811215976Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 4812232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn66xx; 4813232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn68xx; 4814232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; 4815232812Sjmallett struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; 4816215976Sjmallett}; 4817215976Sjmalletttypedef union cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_spr_repair_sum_t; 4818215976Sjmallett 4819215976Sjmallett/** 4820232812Sjmallett * cvmx_mio_fus_tgg 4821232812Sjmallett * 4822232812Sjmallett * Notes: 4823232812Sjmallett * The TGG fuses are fuses[831:768]. The valid bit (TGG[63]) is fuse[831]. 4824232812Sjmallett * 4825232812Sjmallett */ 4826232812Sjmallettunion cvmx_mio_fus_tgg { 4827232812Sjmallett uint64_t u64; 4828232812Sjmallett struct cvmx_mio_fus_tgg_s { 4829232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4830232812Sjmallett uint64_t val : 1; /**< Out of reset, VAL will return the TGG[63] fuse. 4831232812Sjmallett Software may write this CSR bit to zero (to hide 4832232812Sjmallett the value of the TGG fuses). Software cannot write 4833232812Sjmallett the valid bit to a one, so it is not possible to 4834232812Sjmallett read the value of the TGG fuses after the valid 4835232812Sjmallett bit is clear. 4836232812Sjmallett 4837232812Sjmallett It is never possible to read the value of the TGG 4838232812Sjmallett fuses directly (ie. the only way to read the value 4839232812Sjmallett of the TGG fuses is via the MIO_FUS_TGG CSR.) 4840232812Sjmallett 4841232812Sjmallett Whenever the fuse corresponding to the valid bit 4842232812Sjmallett (ie. TGG[63]) is blown, it is not possible to blow 4843232812Sjmallett the other 63 TGG fuses. (ie. only when the TGG[63] 4844232812Sjmallett fuse is not blown, the other 63 TGG fuses can be 4845232812Sjmallett blown. The TGG[63] fuse is the one and only fuse 4846232812Sjmallett lockdown bit for the other 63 fuses TGG fuses. No 4847232812Sjmallett other fuse lockdown bits can prevent blowing the 63 4848232812Sjmallett fuses. */ 4849232812Sjmallett uint64_t dat : 63; /**< Whenever VAL is clear, DAT will always read as 4850232812Sjmallett zero, regardless of the value of the TGG[62:0] 4851232812Sjmallett fuses. 4852232812Sjmallett 4853232812Sjmallett Whenever VAL is set, DAT will match the value of 4854232812Sjmallett other 63 TGG fuses (ie. TGG[62:0]) */ 4855232812Sjmallett#else 4856232812Sjmallett uint64_t dat : 63; 4857232812Sjmallett uint64_t val : 1; 4858232812Sjmallett#endif 4859232812Sjmallett } s; 4860232812Sjmallett struct cvmx_mio_fus_tgg_s cn61xx; 4861232812Sjmallett struct cvmx_mio_fus_tgg_s cn66xx; 4862232812Sjmallett struct cvmx_mio_fus_tgg_s cnf71xx; 4863232812Sjmallett}; 4864232812Sjmalletttypedef union cvmx_mio_fus_tgg cvmx_mio_fus_tgg_t; 4865232812Sjmallett 4866232812Sjmallett/** 4867215976Sjmallett * cvmx_mio_fus_unlock 4868215976Sjmallett */ 4869232812Sjmallettunion cvmx_mio_fus_unlock { 4870215976Sjmallett uint64_t u64; 4871232812Sjmallett struct cvmx_mio_fus_unlock_s { 4872232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4873215976Sjmallett uint64_t reserved_24_63 : 40; 4874215976Sjmallett uint64_t key : 24; /**< When set to the typical value, allows SW to 4875215976Sjmallett program the efuses */ 4876215976Sjmallett#else 4877215976Sjmallett uint64_t key : 24; 4878215976Sjmallett uint64_t reserved_24_63 : 40; 4879215976Sjmallett#endif 4880215976Sjmallett } s; 4881215976Sjmallett struct cvmx_mio_fus_unlock_s cn30xx; 4882215976Sjmallett struct cvmx_mio_fus_unlock_s cn31xx; 4883215976Sjmallett}; 4884215976Sjmalletttypedef union cvmx_mio_fus_unlock cvmx_mio_fus_unlock_t; 4885215976Sjmallett 4886215976Sjmallett/** 4887215976Sjmallett * cvmx_mio_fus_wadr 4888215976Sjmallett */ 4889232812Sjmallettunion cvmx_mio_fus_wadr { 4890215976Sjmallett uint64_t u64; 4891232812Sjmallett struct cvmx_mio_fus_wadr_s { 4892232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4893215976Sjmallett uint64_t reserved_10_63 : 54; 4894215976Sjmallett uint64_t addr : 10; /**< Which of the banks of 128 fuses to blow */ 4895215976Sjmallett#else 4896215976Sjmallett uint64_t addr : 10; 4897215976Sjmallett uint64_t reserved_10_63 : 54; 4898215976Sjmallett#endif 4899215976Sjmallett } s; 4900215976Sjmallett struct cvmx_mio_fus_wadr_s cn30xx; 4901215976Sjmallett struct cvmx_mio_fus_wadr_s cn31xx; 4902215976Sjmallett struct cvmx_mio_fus_wadr_s cn38xx; 4903215976Sjmallett struct cvmx_mio_fus_wadr_s cn38xxp2; 4904232812Sjmallett struct cvmx_mio_fus_wadr_cn50xx { 4905232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4906215976Sjmallett uint64_t reserved_2_63 : 62; 4907215976Sjmallett uint64_t addr : 2; /**< Which of the four banks of 256 fuses to blow */ 4908215976Sjmallett#else 4909215976Sjmallett uint64_t addr : 2; 4910215976Sjmallett uint64_t reserved_2_63 : 62; 4911215976Sjmallett#endif 4912215976Sjmallett } cn50xx; 4913232812Sjmallett struct cvmx_mio_fus_wadr_cn52xx { 4914232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4915215976Sjmallett uint64_t reserved_3_63 : 61; 4916215976Sjmallett uint64_t addr : 3; /**< Which of the four banks of 256 fuses to blow */ 4917215976Sjmallett#else 4918215976Sjmallett uint64_t addr : 3; 4919215976Sjmallett uint64_t reserved_3_63 : 61; 4920215976Sjmallett#endif 4921215976Sjmallett } cn52xx; 4922215976Sjmallett struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; 4923215976Sjmallett struct cvmx_mio_fus_wadr_cn52xx cn56xx; 4924215976Sjmallett struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 4925215976Sjmallett struct cvmx_mio_fus_wadr_cn50xx cn58xx; 4926215976Sjmallett struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 4927232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx { 4928232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4929215976Sjmallett uint64_t reserved_4_63 : 60; 4930215976Sjmallett uint64_t addr : 4; /**< Which of the banks of 128 fuses to blow */ 4931215976Sjmallett#else 4932215976Sjmallett uint64_t addr : 4; 4933215976Sjmallett uint64_t reserved_4_63 : 60; 4934215976Sjmallett#endif 4935232812Sjmallett } cn61xx; 4936232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cn63xx; 4937232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; 4938232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cn66xx; 4939232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cn68xx; 4940232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; 4941232812Sjmallett struct cvmx_mio_fus_wadr_cn61xx cnf71xx; 4942215976Sjmallett}; 4943215976Sjmalletttypedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t; 4944215976Sjmallett 4945215976Sjmallett/** 4946215976Sjmallett * cvmx_mio_gpio_comp 4947215976Sjmallett * 4948215976Sjmallett * MIO_GPIO_COMP = MIO GPIO Compensation Register 4949215976Sjmallett * 4950215976Sjmallett */ 4951232812Sjmallettunion cvmx_mio_gpio_comp { 4952215976Sjmallett uint64_t u64; 4953232812Sjmallett struct cvmx_mio_gpio_comp_s { 4954232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4955215976Sjmallett uint64_t reserved_12_63 : 52; 4956215976Sjmallett uint64_t pctl : 6; /**< GPIO bus PCTL */ 4957215976Sjmallett uint64_t nctl : 6; /**< GPIO bus NCTL */ 4958215976Sjmallett#else 4959215976Sjmallett uint64_t nctl : 6; 4960215976Sjmallett uint64_t pctl : 6; 4961215976Sjmallett uint64_t reserved_12_63 : 52; 4962215976Sjmallett#endif 4963215976Sjmallett } s; 4964232812Sjmallett struct cvmx_mio_gpio_comp_s cn61xx; 4965215976Sjmallett struct cvmx_mio_gpio_comp_s cn63xx; 4966215976Sjmallett struct cvmx_mio_gpio_comp_s cn63xxp1; 4967232812Sjmallett struct cvmx_mio_gpio_comp_s cn66xx; 4968232812Sjmallett struct cvmx_mio_gpio_comp_s cn68xx; 4969232812Sjmallett struct cvmx_mio_gpio_comp_s cn68xxp1; 4970232812Sjmallett struct cvmx_mio_gpio_comp_s cnf71xx; 4971215976Sjmallett}; 4972215976Sjmalletttypedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t; 4973215976Sjmallett 4974215976Sjmallett/** 4975215976Sjmallett * cvmx_mio_ndf_dma_cfg 4976215976Sjmallett * 4977215976Sjmallett * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register 4978215976Sjmallett * 4979215976Sjmallett * SIZE is specified in number of 64 bit transfers (encoded in -1 notation). 4980215976Sjmallett * 4981215976Sjmallett * ADR must be 64 bit aligned. 4982215976Sjmallett */ 4983232812Sjmallettunion cvmx_mio_ndf_dma_cfg { 4984215976Sjmallett uint64_t u64; 4985232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s { 4986232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4987215976Sjmallett uint64_t en : 1; /**< DMA Engine enable */ 4988215976Sjmallett uint64_t rw : 1; /**< DMA Engine R/W bit (0 = read, 1 = write) */ 4989215976Sjmallett uint64_t clr : 1; /**< DMA Engine clear EN on device terminated burst */ 4990215976Sjmallett uint64_t reserved_60_60 : 1; 4991215976Sjmallett uint64_t swap32 : 1; /**< DMA Engine 32 bit swap */ 4992215976Sjmallett uint64_t swap16 : 1; /**< DMA Engine 16 bit swap */ 4993215976Sjmallett uint64_t swap8 : 1; /**< DMA Engine 8 bit swap */ 4994215976Sjmallett uint64_t endian : 1; /**< DMA Engine NCB endian mode (0 = big, 1 = little) */ 4995215976Sjmallett uint64_t size : 20; /**< DMA Engine size */ 4996215976Sjmallett uint64_t adr : 36; /**< DMA Engine address */ 4997215976Sjmallett#else 4998215976Sjmallett uint64_t adr : 36; 4999215976Sjmallett uint64_t size : 20; 5000215976Sjmallett uint64_t endian : 1; 5001215976Sjmallett uint64_t swap8 : 1; 5002215976Sjmallett uint64_t swap16 : 1; 5003215976Sjmallett uint64_t swap32 : 1; 5004215976Sjmallett uint64_t reserved_60_60 : 1; 5005215976Sjmallett uint64_t clr : 1; 5006215976Sjmallett uint64_t rw : 1; 5007215976Sjmallett uint64_t en : 1; 5008215976Sjmallett#endif 5009215976Sjmallett } s; 5010215976Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn52xx; 5011232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn61xx; 5012215976Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn63xx; 5013215976Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 5014232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn66xx; 5015232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn68xx; 5016232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; 5017232812Sjmallett struct cvmx_mio_ndf_dma_cfg_s cnf71xx; 5018215976Sjmallett}; 5019215976Sjmalletttypedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t; 5020215976Sjmallett 5021215976Sjmallett/** 5022215976Sjmallett * cvmx_mio_ndf_dma_int 5023215976Sjmallett * 5024215976Sjmallett * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register 5025215976Sjmallett * 5026215976Sjmallett */ 5027232812Sjmallettunion cvmx_mio_ndf_dma_int { 5028215976Sjmallett uint64_t u64; 5029232812Sjmallett struct cvmx_mio_ndf_dma_int_s { 5030232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5031215976Sjmallett uint64_t reserved_1_63 : 63; 5032215976Sjmallett uint64_t done : 1; /**< DMA Engine request completion interrupt */ 5033215976Sjmallett#else 5034215976Sjmallett uint64_t done : 1; 5035215976Sjmallett uint64_t reserved_1_63 : 63; 5036215976Sjmallett#endif 5037215976Sjmallett } s; 5038215976Sjmallett struct cvmx_mio_ndf_dma_int_s cn52xx; 5039232812Sjmallett struct cvmx_mio_ndf_dma_int_s cn61xx; 5040215976Sjmallett struct cvmx_mio_ndf_dma_int_s cn63xx; 5041215976Sjmallett struct cvmx_mio_ndf_dma_int_s cn63xxp1; 5042232812Sjmallett struct cvmx_mio_ndf_dma_int_s cn66xx; 5043232812Sjmallett struct cvmx_mio_ndf_dma_int_s cn68xx; 5044232812Sjmallett struct cvmx_mio_ndf_dma_int_s cn68xxp1; 5045232812Sjmallett struct cvmx_mio_ndf_dma_int_s cnf71xx; 5046215976Sjmallett}; 5047215976Sjmalletttypedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t; 5048215976Sjmallett 5049215976Sjmallett/** 5050215976Sjmallett * cvmx_mio_ndf_dma_int_en 5051215976Sjmallett * 5052215976Sjmallett * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register 5053215976Sjmallett * 5054215976Sjmallett */ 5055232812Sjmallettunion cvmx_mio_ndf_dma_int_en { 5056215976Sjmallett uint64_t u64; 5057232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s { 5058232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5059215976Sjmallett uint64_t reserved_1_63 : 63; 5060215976Sjmallett uint64_t done : 1; /**< DMA Engine request completion interrupt enable */ 5061215976Sjmallett#else 5062215976Sjmallett uint64_t done : 1; 5063215976Sjmallett uint64_t reserved_1_63 : 63; 5064215976Sjmallett#endif 5065215976Sjmallett } s; 5066215976Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn52xx; 5067232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn61xx; 5068215976Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn63xx; 5069215976Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 5070232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn66xx; 5071232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn68xx; 5072232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; 5073232812Sjmallett struct cvmx_mio_ndf_dma_int_en_s cnf71xx; 5074215976Sjmallett}; 5075215976Sjmalletttypedef union cvmx_mio_ndf_dma_int_en cvmx_mio_ndf_dma_int_en_t; 5076215976Sjmallett 5077215976Sjmallett/** 5078215976Sjmallett * cvmx_mio_pll_ctl 5079215976Sjmallett */ 5080232812Sjmallettunion cvmx_mio_pll_ctl { 5081215976Sjmallett uint64_t u64; 5082232812Sjmallett struct cvmx_mio_pll_ctl_s { 5083232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5084215976Sjmallett uint64_t reserved_5_63 : 59; 5085215976Sjmallett uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */ 5086215976Sjmallett#else 5087215976Sjmallett uint64_t bw_ctl : 5; 5088215976Sjmallett uint64_t reserved_5_63 : 59; 5089215976Sjmallett#endif 5090215976Sjmallett } s; 5091215976Sjmallett struct cvmx_mio_pll_ctl_s cn30xx; 5092215976Sjmallett struct cvmx_mio_pll_ctl_s cn31xx; 5093215976Sjmallett}; 5094215976Sjmalletttypedef union cvmx_mio_pll_ctl cvmx_mio_pll_ctl_t; 5095215976Sjmallett 5096215976Sjmallett/** 5097215976Sjmallett * cvmx_mio_pll_setting 5098215976Sjmallett */ 5099232812Sjmallettunion cvmx_mio_pll_setting { 5100215976Sjmallett uint64_t u64; 5101232812Sjmallett struct cvmx_mio_pll_setting_s { 5102232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5103215976Sjmallett uint64_t reserved_17_63 : 47; 5104215976Sjmallett uint64_t setting : 17; /**< Core PLL setting */ 5105215976Sjmallett#else 5106215976Sjmallett uint64_t setting : 17; 5107215976Sjmallett uint64_t reserved_17_63 : 47; 5108215976Sjmallett#endif 5109215976Sjmallett } s; 5110215976Sjmallett struct cvmx_mio_pll_setting_s cn30xx; 5111215976Sjmallett struct cvmx_mio_pll_setting_s cn31xx; 5112215976Sjmallett}; 5113215976Sjmalletttypedef union cvmx_mio_pll_setting cvmx_mio_pll_setting_t; 5114215976Sjmallett 5115215976Sjmallett/** 5116232812Sjmallett * cvmx_mio_ptp_ckout_hi_incr 5117232812Sjmallett * 5118232812Sjmallett * MIO_PTP_CKOUT_HI_INCR = PTP Clock Out Hi Increment 5119232812Sjmallett * 5120232812Sjmallett */ 5121232812Sjmallettunion cvmx_mio_ptp_ckout_hi_incr { 5122232812Sjmallett uint64_t u64; 5123232812Sjmallett struct cvmx_mio_ptp_ckout_hi_incr_s { 5124232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5125232812Sjmallett uint64_t nanosec : 32; /**< Nanoseconds */ 5126232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5127232812Sjmallett#else 5128232812Sjmallett uint64_t frnanosec : 32; 5129232812Sjmallett uint64_t nanosec : 32; 5130232812Sjmallett#endif 5131232812Sjmallett } s; 5132232812Sjmallett struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; 5133232812Sjmallett struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; 5134232812Sjmallett struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; 5135232812Sjmallett struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; 5136232812Sjmallett}; 5137232812Sjmalletttypedef union cvmx_mio_ptp_ckout_hi_incr cvmx_mio_ptp_ckout_hi_incr_t; 5138232812Sjmallett 5139232812Sjmallett/** 5140232812Sjmallett * cvmx_mio_ptp_ckout_lo_incr 5141232812Sjmallett * 5142232812Sjmallett * MIO_PTP_CKOUT_LO_INCR = PTP Clock Out Lo Increment 5143232812Sjmallett * 5144232812Sjmallett */ 5145232812Sjmallettunion cvmx_mio_ptp_ckout_lo_incr { 5146232812Sjmallett uint64_t u64; 5147232812Sjmallett struct cvmx_mio_ptp_ckout_lo_incr_s { 5148232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5149232812Sjmallett uint64_t nanosec : 32; /**< Nanoseconds */ 5150232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5151232812Sjmallett#else 5152232812Sjmallett uint64_t frnanosec : 32; 5153232812Sjmallett uint64_t nanosec : 32; 5154232812Sjmallett#endif 5155232812Sjmallett } s; 5156232812Sjmallett struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; 5157232812Sjmallett struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; 5158232812Sjmallett struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; 5159232812Sjmallett struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; 5160232812Sjmallett}; 5161232812Sjmalletttypedef union cvmx_mio_ptp_ckout_lo_incr cvmx_mio_ptp_ckout_lo_incr_t; 5162232812Sjmallett 5163232812Sjmallett/** 5164232812Sjmallett * cvmx_mio_ptp_ckout_thresh_hi 5165232812Sjmallett * 5166232812Sjmallett * MIO_PTP_CKOUT_THRESH_HI = Hi bytes of PTP Clock Out 5167232812Sjmallett * 5168232812Sjmallett * Writes to MIO_PTP_CKOUT_THRESH_HI also clear MIO_PTP_CKOUT_THRESH_LO. To update all 96 bits, write MIO_PTP_CKOUT_THRESH_HI followed 5169232812Sjmallett * by MIO_PTP_CKOUT_THRESH_LO 5170232812Sjmallett */ 5171232812Sjmallettunion cvmx_mio_ptp_ckout_thresh_hi { 5172232812Sjmallett uint64_t u64; 5173232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_hi_s { 5174232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5175232812Sjmallett uint64_t nanosec : 64; /**< Nanoseconds */ 5176232812Sjmallett#else 5177232812Sjmallett uint64_t nanosec : 64; 5178232812Sjmallett#endif 5179232812Sjmallett } s; 5180232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; 5181232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; 5182232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; 5183232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; 5184232812Sjmallett}; 5185232812Sjmalletttypedef union cvmx_mio_ptp_ckout_thresh_hi cvmx_mio_ptp_ckout_thresh_hi_t; 5186232812Sjmallett 5187232812Sjmallett/** 5188232812Sjmallett * cvmx_mio_ptp_ckout_thresh_lo 5189232812Sjmallett * 5190232812Sjmallett * MIO_PTP_CKOUT_THRESH_LO = Lo bytes of PTP Clock Out 5191232812Sjmallett * 5192232812Sjmallett */ 5193232812Sjmallettunion cvmx_mio_ptp_ckout_thresh_lo { 5194232812Sjmallett uint64_t u64; 5195232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_lo_s { 5196232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5197232812Sjmallett uint64_t reserved_32_63 : 32; 5198232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5199232812Sjmallett#else 5200232812Sjmallett uint64_t frnanosec : 32; 5201232812Sjmallett uint64_t reserved_32_63 : 32; 5202232812Sjmallett#endif 5203232812Sjmallett } s; 5204232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; 5205232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; 5206232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; 5207232812Sjmallett struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; 5208232812Sjmallett}; 5209232812Sjmalletttypedef union cvmx_mio_ptp_ckout_thresh_lo cvmx_mio_ptp_ckout_thresh_lo_t; 5210232812Sjmallett 5211232812Sjmallett/** 5212215976Sjmallett * cvmx_mio_ptp_clock_cfg 5213215976Sjmallett * 5214215976Sjmallett * MIO_PTP_CLOCK_CFG = Configuration 5215215976Sjmallett * 5216215976Sjmallett */ 5217232812Sjmallettunion cvmx_mio_ptp_clock_cfg { 5218215976Sjmallett uint64_t u64; 5219232812Sjmallett struct cvmx_mio_ptp_clock_cfg_s { 5220232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5221232812Sjmallett uint64_t reserved_42_63 : 22; 5222232812Sjmallett uint64_t pps : 1; /**< PTP PPS Output 5223232812Sjmallett reflects ptp__pps after PPS_INV inverter */ 5224232812Sjmallett uint64_t ckout : 1; /**< PTP Clock Output 5225232812Sjmallett reflects ptp__ckout after CKOUT_INV inverter */ 5226232812Sjmallett uint64_t ext_clk_edge : 2; /**< External Clock input edge 5227232812Sjmallett 00 = rising edge 5228232812Sjmallett 01 = falling edge 5229232812Sjmallett 10 = both rising & falling edge 5230232812Sjmallett 11 = reserved */ 5231232812Sjmallett uint64_t ckout_out4 : 1; /**< Destination for PTP Clock Out output 5232232812Sjmallett See CKOUT_OUT */ 5233232812Sjmallett uint64_t pps_out : 5; /**< Destination for PTP PPS output to GPIO 5234232812Sjmallett 0-19 : GPIO[PPS_OUT[4:0]] 5235232812Sjmallett - 20:30: Reserved 5236232812Sjmallett 31 : Disabled 5237232812Sjmallett This should be different from CKOUT_OUT */ 5238232812Sjmallett uint64_t pps_inv : 1; /**< Invert PTP PPS 5239232812Sjmallett 0 = don't invert 5240232812Sjmallett 1 = invert */ 5241232812Sjmallett uint64_t pps_en : 1; /**< Enable PTP PPS */ 5242232812Sjmallett uint64_t ckout_out : 4; /**< Destination for PTP Clock Out output to GPIO 5243232812Sjmallett 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5244232812Sjmallett - 20:30: Reserved 5245232812Sjmallett 31 : Disabled 5246232812Sjmallett This should be different from PPS_OUT */ 5247232812Sjmallett uint64_t ckout_inv : 1; /**< Invert PTP Clock Out 5248232812Sjmallett 0 = don't invert 5249232812Sjmallett 1 = invert */ 5250232812Sjmallett uint64_t ckout_en : 1; /**< Enable PTP Clock Out */ 5251232812Sjmallett uint64_t evcnt_in : 6; /**< Source for event counter input 5252232812Sjmallett 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5253232812Sjmallett 0x20 : GPIO[16] 5254232812Sjmallett 0x21 : GPIO[17] 5255232812Sjmallett 0x22 : GPIO[18] 5256232812Sjmallett 0x23 : GPIO[19] 5257232812Sjmallett 0x10 : QLM0_REF_CLK 5258232812Sjmallett 0x11 : QLM1_REF_CLK 5259232812Sjmallett 0x18 : RF_MCLK (PHY pin) 5260232812Sjmallett 0x12-0x17 : Reserved 5261232812Sjmallett 0x19-0x1f : Reserved 5262232812Sjmallett 0x24-0x3f : Reserved */ 5263232812Sjmallett uint64_t evcnt_edge : 1; /**< Event counter input edge 5264232812Sjmallett 0 = falling edge 5265232812Sjmallett 1 = rising edge */ 5266232812Sjmallett uint64_t evcnt_en : 1; /**< Enable event counter */ 5267232812Sjmallett uint64_t tstmp_in : 6; /**< Source for timestamp input 5268232812Sjmallett 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5269232812Sjmallett 0x20 : GPIO[16] 5270232812Sjmallett 0x21 : GPIO[17] 5271232812Sjmallett 0x22 : GPIO[18] 5272232812Sjmallett 0x23 : GPIO[19] 5273232812Sjmallett 0x10 : QLM0_REF_CLK 5274232812Sjmallett 0x11 : QLM1_REF_CLK 5275232812Sjmallett 0x18 : RF_MCLK (PHY pin) 5276232812Sjmallett 0x12-0x17 : Reserved 5277232812Sjmallett 0x19-0x1f : Reserved 5278232812Sjmallett 0x24-0x3f : Reserved */ 5279232812Sjmallett uint64_t tstmp_edge : 1; /**< External timestamp input edge 5280232812Sjmallett 0 = falling edge 5281232812Sjmallett 1 = rising edge */ 5282232812Sjmallett uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5283232812Sjmallett uint64_t ext_clk_in : 6; /**< Source for external clock 5284232812Sjmallett 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5285232812Sjmallett 0x20 : GPIO[16] 5286232812Sjmallett 0x21 : GPIO[17] 5287232812Sjmallett 0x22 : GPIO[18] 5288232812Sjmallett 0x23 : GPIO[19] 5289232812Sjmallett 0x10 : QLM0_REF_CLK 5290232812Sjmallett 0x11 : QLM1_REF_CLK 5291232812Sjmallett 0x18 : RF_MCLK (PHY pin) 5292232812Sjmallett 0x12-0x17 : Reserved 5293232812Sjmallett 0x19-0x1f : Reserved 5294232812Sjmallett 0x24-0x3f : Reserved */ 5295232812Sjmallett uint64_t ext_clk_en : 1; /**< Use external clock */ 5296232812Sjmallett uint64_t ptp_en : 1; /**< Enable PTP Module */ 5297232812Sjmallett#else 5298232812Sjmallett uint64_t ptp_en : 1; 5299232812Sjmallett uint64_t ext_clk_en : 1; 5300232812Sjmallett uint64_t ext_clk_in : 6; 5301232812Sjmallett uint64_t tstmp_en : 1; 5302232812Sjmallett uint64_t tstmp_edge : 1; 5303232812Sjmallett uint64_t tstmp_in : 6; 5304232812Sjmallett uint64_t evcnt_en : 1; 5305232812Sjmallett uint64_t evcnt_edge : 1; 5306232812Sjmallett uint64_t evcnt_in : 6; 5307232812Sjmallett uint64_t ckout_en : 1; 5308232812Sjmallett uint64_t ckout_inv : 1; 5309232812Sjmallett uint64_t ckout_out : 4; 5310232812Sjmallett uint64_t pps_en : 1; 5311232812Sjmallett uint64_t pps_inv : 1; 5312232812Sjmallett uint64_t pps_out : 5; 5313232812Sjmallett uint64_t ckout_out4 : 1; 5314232812Sjmallett uint64_t ext_clk_edge : 2; 5315232812Sjmallett uint64_t ckout : 1; 5316232812Sjmallett uint64_t pps : 1; 5317232812Sjmallett uint64_t reserved_42_63 : 22; 5318232812Sjmallett#endif 5319232812Sjmallett } s; 5320232812Sjmallett struct cvmx_mio_ptp_clock_cfg_s cn61xx; 5321232812Sjmallett struct cvmx_mio_ptp_clock_cfg_cn63xx { 5322232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5323215976Sjmallett uint64_t reserved_24_63 : 40; 5324215976Sjmallett uint64_t evcnt_in : 6; /**< Source for event counter input 5325215976Sjmallett 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5326215976Sjmallett 0x10 : QLM0_REF_CLK 5327215976Sjmallett 0x11 : QLM1_REF_CLK 5328215976Sjmallett 0x12 : QLM2_REF_CLK 5329215976Sjmallett 0x13-0x3f : Reserved */ 5330215976Sjmallett uint64_t evcnt_edge : 1; /**< Event counter input edge 5331215976Sjmallett 0 = falling edge 5332215976Sjmallett 1 = rising edge */ 5333215976Sjmallett uint64_t evcnt_en : 1; /**< Enable event counter */ 5334215976Sjmallett uint64_t tstmp_in : 6; /**< Source for timestamp input 5335215976Sjmallett 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5336215976Sjmallett 0x10 : QLM0_REF_CLK 5337215976Sjmallett 0x11 : QLM1_REF_CLK 5338215976Sjmallett 0x12 : QLM2_REF_CLK 5339215976Sjmallett 0x13-0x3f : Reserved */ 5340215976Sjmallett uint64_t tstmp_edge : 1; /**< External timestamp input edge 5341215976Sjmallett 0 = falling edge 5342215976Sjmallett 1 = rising edge */ 5343215976Sjmallett uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5344215976Sjmallett uint64_t ext_clk_in : 6; /**< Source for external clock 5345215976Sjmallett 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5346215976Sjmallett 0x10 : QLM0_REF_CLK 5347215976Sjmallett 0x11 : QLM1_REF_CLK 5348215976Sjmallett 0x12 : QLM2_REF_CLK 5349215976Sjmallett 0x13-0x3f : Reserved */ 5350215976Sjmallett uint64_t ext_clk_en : 1; /**< Use positive edge of external clock */ 5351215976Sjmallett uint64_t ptp_en : 1; /**< Enable PTP Module */ 5352215976Sjmallett#else 5353215976Sjmallett uint64_t ptp_en : 1; 5354215976Sjmallett uint64_t ext_clk_en : 1; 5355215976Sjmallett uint64_t ext_clk_in : 6; 5356215976Sjmallett uint64_t tstmp_en : 1; 5357215976Sjmallett uint64_t tstmp_edge : 1; 5358215976Sjmallett uint64_t tstmp_in : 6; 5359215976Sjmallett uint64_t evcnt_en : 1; 5360215976Sjmallett uint64_t evcnt_edge : 1; 5361215976Sjmallett uint64_t evcnt_in : 6; 5362215976Sjmallett uint64_t reserved_24_63 : 40; 5363215976Sjmallett#endif 5364232812Sjmallett } cn63xx; 5365232812Sjmallett struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; 5366232812Sjmallett struct cvmx_mio_ptp_clock_cfg_cn66xx { 5367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5368232812Sjmallett uint64_t reserved_40_63 : 24; 5369232812Sjmallett uint64_t ext_clk_edge : 2; /**< External Clock input edge 5370232812Sjmallett 00 = rising edge 5371232812Sjmallett 01 = falling edge 5372232812Sjmallett 10 = both rising & falling edge 5373232812Sjmallett 11 = reserved */ 5374232812Sjmallett uint64_t ckout_out4 : 1; /**< Destination for PTP Clock Out output 5375232812Sjmallett 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5376232812Sjmallett This should be different from PPS_OUT */ 5377232812Sjmallett uint64_t pps_out : 5; /**< Destination for PTP PPS output 5378232812Sjmallett 0-19 : GPIO[PPS_OUT[4:0]] 5379232812Sjmallett This should be different from CKOUT_OUT */ 5380232812Sjmallett uint64_t pps_inv : 1; /**< Invert PTP PPS 5381232812Sjmallett 0 = don't invert 5382232812Sjmallett 1 = invert */ 5383232812Sjmallett uint64_t pps_en : 1; /**< Enable PTP PPS */ 5384232812Sjmallett uint64_t ckout_out : 4; /**< Destination for PTP Clock Out output 5385232812Sjmallett 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5386232812Sjmallett This should be different from PPS_OUT */ 5387232812Sjmallett uint64_t ckout_inv : 1; /**< Invert PTP Clock Out 5388232812Sjmallett 0 = don't invert 5389232812Sjmallett 1 = invert */ 5390232812Sjmallett uint64_t ckout_en : 1; /**< Enable PTP Clock Out */ 5391232812Sjmallett uint64_t evcnt_in : 6; /**< Source for event counter input 5392232812Sjmallett 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5393232812Sjmallett 0x20 : GPIO[16] 5394232812Sjmallett 0x21 : GPIO[17] 5395232812Sjmallett 0x22 : GPIO[18] 5396232812Sjmallett 0x23 : GPIO[19] 5397232812Sjmallett 0x10 : QLM0_REF_CLK 5398232812Sjmallett 0x11 : QLM1_REF_CLK 5399232812Sjmallett 0x12 : QLM2_REF_CLK 5400232812Sjmallett 0x13-0x1f : Reserved 5401232812Sjmallett 0x24-0x3f : Reserved */ 5402232812Sjmallett uint64_t evcnt_edge : 1; /**< Event counter input edge 5403232812Sjmallett 0 = falling edge 5404232812Sjmallett 1 = rising edge */ 5405232812Sjmallett uint64_t evcnt_en : 1; /**< Enable event counter */ 5406232812Sjmallett uint64_t tstmp_in : 6; /**< Source for timestamp input 5407232812Sjmallett 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5408232812Sjmallett 0x20 : GPIO[16] 5409232812Sjmallett 0x21 : GPIO[17] 5410232812Sjmallett 0x22 : GPIO[18] 5411232812Sjmallett 0x23 : GPIO[19] 5412232812Sjmallett 0x10 : QLM0_REF_CLK 5413232812Sjmallett 0x11 : QLM1_REF_CLK 5414232812Sjmallett 0x12 : QLM2_REF_CLK 5415232812Sjmallett 0x13-0x1f : Reserved 5416232812Sjmallett 0x24-0x3f : Reserved */ 5417232812Sjmallett uint64_t tstmp_edge : 1; /**< External timestamp input edge 5418232812Sjmallett 0 = falling edge 5419232812Sjmallett 1 = rising edge */ 5420232812Sjmallett uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5421232812Sjmallett uint64_t ext_clk_in : 6; /**< Source for external clock 5422232812Sjmallett 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5423232812Sjmallett 0x20 : GPIO[16] 5424232812Sjmallett 0x21 : GPIO[17] 5425232812Sjmallett 0x22 : GPIO[18] 5426232812Sjmallett 0x23 : GPIO[19] 5427232812Sjmallett 0x10 : QLM0_REF_CLK 5428232812Sjmallett 0x11 : QLM1_REF_CLK 5429232812Sjmallett 0x12 : QLM2_REF_CLK 5430232812Sjmallett 0x13-0x1f : Reserved 5431232812Sjmallett 0x24-0x3f : Reserved */ 5432232812Sjmallett uint64_t ext_clk_en : 1; /**< Use external clock */ 5433232812Sjmallett uint64_t ptp_en : 1; /**< Enable PTP Module */ 5434232812Sjmallett#else 5435232812Sjmallett uint64_t ptp_en : 1; 5436232812Sjmallett uint64_t ext_clk_en : 1; 5437232812Sjmallett uint64_t ext_clk_in : 6; 5438232812Sjmallett uint64_t tstmp_en : 1; 5439232812Sjmallett uint64_t tstmp_edge : 1; 5440232812Sjmallett uint64_t tstmp_in : 6; 5441232812Sjmallett uint64_t evcnt_en : 1; 5442232812Sjmallett uint64_t evcnt_edge : 1; 5443232812Sjmallett uint64_t evcnt_in : 6; 5444232812Sjmallett uint64_t ckout_en : 1; 5445232812Sjmallett uint64_t ckout_inv : 1; 5446232812Sjmallett uint64_t ckout_out : 4; 5447232812Sjmallett uint64_t pps_en : 1; 5448232812Sjmallett uint64_t pps_inv : 1; 5449232812Sjmallett uint64_t pps_out : 5; 5450232812Sjmallett uint64_t ckout_out4 : 1; 5451232812Sjmallett uint64_t ext_clk_edge : 2; 5452232812Sjmallett uint64_t reserved_40_63 : 24; 5453232812Sjmallett#endif 5454232812Sjmallett } cn66xx; 5455232812Sjmallett struct cvmx_mio_ptp_clock_cfg_s cn68xx; 5456232812Sjmallett struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; 5457232812Sjmallett struct cvmx_mio_ptp_clock_cfg_s cnf71xx; 5458215976Sjmallett}; 5459215976Sjmalletttypedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t; 5460215976Sjmallett 5461215976Sjmallett/** 5462215976Sjmallett * cvmx_mio_ptp_clock_comp 5463215976Sjmallett * 5464215976Sjmallett * MIO_PTP_CLOCK_COMP = Compensator 5465215976Sjmallett * 5466215976Sjmallett */ 5467232812Sjmallettunion cvmx_mio_ptp_clock_comp { 5468215976Sjmallett uint64_t u64; 5469232812Sjmallett struct cvmx_mio_ptp_clock_comp_s { 5470232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5471215976Sjmallett uint64_t nanosec : 32; /**< Nanoseconds */ 5472215976Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5473215976Sjmallett#else 5474215976Sjmallett uint64_t frnanosec : 32; 5475215976Sjmallett uint64_t nanosec : 32; 5476215976Sjmallett#endif 5477215976Sjmallett } s; 5478232812Sjmallett struct cvmx_mio_ptp_clock_comp_s cn61xx; 5479215976Sjmallett struct cvmx_mio_ptp_clock_comp_s cn63xx; 5480215976Sjmallett struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 5481232812Sjmallett struct cvmx_mio_ptp_clock_comp_s cn66xx; 5482232812Sjmallett struct cvmx_mio_ptp_clock_comp_s cn68xx; 5483232812Sjmallett struct cvmx_mio_ptp_clock_comp_s cn68xxp1; 5484232812Sjmallett struct cvmx_mio_ptp_clock_comp_s cnf71xx; 5485215976Sjmallett}; 5486215976Sjmalletttypedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t; 5487215976Sjmallett 5488215976Sjmallett/** 5489215976Sjmallett * cvmx_mio_ptp_clock_hi 5490215976Sjmallett * 5491215976Sjmallett * MIO_PTP_CLOCK_HI = Hi bytes of CLOCK 5492215976Sjmallett * 5493215976Sjmallett * Writes to MIO_PTP_CLOCK_HI also clear MIO_PTP_CLOCK_LO. To update all 96 bits, write MIO_PTP_CLOCK_HI followed 5494215976Sjmallett * by MIO_PTP_CLOCK_LO 5495215976Sjmallett */ 5496232812Sjmallettunion cvmx_mio_ptp_clock_hi { 5497215976Sjmallett uint64_t u64; 5498232812Sjmallett struct cvmx_mio_ptp_clock_hi_s { 5499232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5500215976Sjmallett uint64_t nanosec : 64; /**< Nanoseconds */ 5501215976Sjmallett#else 5502215976Sjmallett uint64_t nanosec : 64; 5503215976Sjmallett#endif 5504215976Sjmallett } s; 5505232812Sjmallett struct cvmx_mio_ptp_clock_hi_s cn61xx; 5506215976Sjmallett struct cvmx_mio_ptp_clock_hi_s cn63xx; 5507215976Sjmallett struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 5508232812Sjmallett struct cvmx_mio_ptp_clock_hi_s cn66xx; 5509232812Sjmallett struct cvmx_mio_ptp_clock_hi_s cn68xx; 5510232812Sjmallett struct cvmx_mio_ptp_clock_hi_s cn68xxp1; 5511232812Sjmallett struct cvmx_mio_ptp_clock_hi_s cnf71xx; 5512215976Sjmallett}; 5513215976Sjmalletttypedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t; 5514215976Sjmallett 5515215976Sjmallett/** 5516215976Sjmallett * cvmx_mio_ptp_clock_lo 5517215976Sjmallett * 5518215976Sjmallett * MIO_PTP_CLOCK_LO = Lo bytes of CLOCK 5519215976Sjmallett * 5520215976Sjmallett */ 5521232812Sjmallettunion cvmx_mio_ptp_clock_lo { 5522215976Sjmallett uint64_t u64; 5523232812Sjmallett struct cvmx_mio_ptp_clock_lo_s { 5524232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5525215976Sjmallett uint64_t reserved_32_63 : 32; 5526215976Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5527215976Sjmallett#else 5528215976Sjmallett uint64_t frnanosec : 32; 5529215976Sjmallett uint64_t reserved_32_63 : 32; 5530215976Sjmallett#endif 5531215976Sjmallett } s; 5532232812Sjmallett struct cvmx_mio_ptp_clock_lo_s cn61xx; 5533215976Sjmallett struct cvmx_mio_ptp_clock_lo_s cn63xx; 5534215976Sjmallett struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 5535232812Sjmallett struct cvmx_mio_ptp_clock_lo_s cn66xx; 5536232812Sjmallett struct cvmx_mio_ptp_clock_lo_s cn68xx; 5537232812Sjmallett struct cvmx_mio_ptp_clock_lo_s cn68xxp1; 5538232812Sjmallett struct cvmx_mio_ptp_clock_lo_s cnf71xx; 5539215976Sjmallett}; 5540215976Sjmalletttypedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t; 5541215976Sjmallett 5542215976Sjmallett/** 5543215976Sjmallett * cvmx_mio_ptp_evt_cnt 5544215976Sjmallett * 5545215976Sjmallett * MIO_PTP_EVT_CNT = Event Counter 5546215976Sjmallett * 5547215976Sjmallett * Writes to MIO_PTP_EVT_CNT increment this register by the written data. The register counts down by 5548215976Sjmallett * 1 for every MIO_PTP_CLOCK_CFG[EVCNT_EDGE] edge of MIO_PTP_CLOCK_CFG[EVCNT_IN]. When register equals 5549215976Sjmallett * 0, an interrupt gets gerated 5550215976Sjmallett */ 5551232812Sjmallettunion cvmx_mio_ptp_evt_cnt { 5552215976Sjmallett uint64_t u64; 5553232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s { 5554232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5555215976Sjmallett uint64_t cntr : 64; /**< Nanoseconds */ 5556215976Sjmallett#else 5557215976Sjmallett uint64_t cntr : 64; 5558215976Sjmallett#endif 5559215976Sjmallett } s; 5560232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn61xx; 5561215976Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn63xx; 5562215976Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 5563232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn66xx; 5564232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn68xx; 5565232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; 5566232812Sjmallett struct cvmx_mio_ptp_evt_cnt_s cnf71xx; 5567215976Sjmallett}; 5568215976Sjmalletttypedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t; 5569215976Sjmallett 5570215976Sjmallett/** 5571232812Sjmallett * cvmx_mio_ptp_phy_1pps_in 5572232812Sjmallett * 5573232812Sjmallett * MIO_PTP_PHY_1PPS_IN = PHY 1PPS input mux selection 5574232812Sjmallett * 5575232812Sjmallett */ 5576232812Sjmallettunion cvmx_mio_ptp_phy_1pps_in { 5577232812Sjmallett uint64_t u64; 5578232812Sjmallett struct cvmx_mio_ptp_phy_1pps_in_s { 5579232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5580232812Sjmallett uint64_t reserved_5_63 : 59; 5581232812Sjmallett uint64_t sel : 5; /**< Source for PHY 1pps input signal 5582232812Sjmallett 0-19 : GPIO[SEL[4:0]], for AGPS_1PPS 5583232812Sjmallett 24 : PPS_OUT (Enabled by PPS_EN and PPS_INV, 5584232812Sjmallett reflects ptp_pps after PPS_INV inverter) 5585232812Sjmallett - 20-23: Reserved 5586232812Sjmallett - 25-30: Reserved 5587232812Sjmallett 31 : Disabled */ 5588232812Sjmallett#else 5589232812Sjmallett uint64_t sel : 5; 5590232812Sjmallett uint64_t reserved_5_63 : 59; 5591232812Sjmallett#endif 5592232812Sjmallett } s; 5593232812Sjmallett struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; 5594232812Sjmallett}; 5595232812Sjmalletttypedef union cvmx_mio_ptp_phy_1pps_in cvmx_mio_ptp_phy_1pps_in_t; 5596232812Sjmallett 5597232812Sjmallett/** 5598232812Sjmallett * cvmx_mio_ptp_pps_hi_incr 5599232812Sjmallett * 5600232812Sjmallett * MIO_PTP_PPS_HI_INCR = PTP PPS Hi Increment 5601232812Sjmallett * 5602232812Sjmallett */ 5603232812Sjmallettunion cvmx_mio_ptp_pps_hi_incr { 5604232812Sjmallett uint64_t u64; 5605232812Sjmallett struct cvmx_mio_ptp_pps_hi_incr_s { 5606232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5607232812Sjmallett uint64_t nanosec : 32; /**< Nanoseconds */ 5608232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5609232812Sjmallett#else 5610232812Sjmallett uint64_t frnanosec : 32; 5611232812Sjmallett uint64_t nanosec : 32; 5612232812Sjmallett#endif 5613232812Sjmallett } s; 5614232812Sjmallett struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; 5615232812Sjmallett struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; 5616232812Sjmallett struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; 5617232812Sjmallett struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; 5618232812Sjmallett}; 5619232812Sjmalletttypedef union cvmx_mio_ptp_pps_hi_incr cvmx_mio_ptp_pps_hi_incr_t; 5620232812Sjmallett 5621232812Sjmallett/** 5622232812Sjmallett * cvmx_mio_ptp_pps_lo_incr 5623232812Sjmallett * 5624232812Sjmallett * MIO_PTP_PPS_LO_INCR = PTP PPS Lo Increment 5625232812Sjmallett * 5626232812Sjmallett */ 5627232812Sjmallettunion cvmx_mio_ptp_pps_lo_incr { 5628232812Sjmallett uint64_t u64; 5629232812Sjmallett struct cvmx_mio_ptp_pps_lo_incr_s { 5630232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5631232812Sjmallett uint64_t nanosec : 32; /**< Nanoseconds */ 5632232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5633232812Sjmallett#else 5634232812Sjmallett uint64_t frnanosec : 32; 5635232812Sjmallett uint64_t nanosec : 32; 5636232812Sjmallett#endif 5637232812Sjmallett } s; 5638232812Sjmallett struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; 5639232812Sjmallett struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; 5640232812Sjmallett struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; 5641232812Sjmallett struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; 5642232812Sjmallett}; 5643232812Sjmalletttypedef union cvmx_mio_ptp_pps_lo_incr cvmx_mio_ptp_pps_lo_incr_t; 5644232812Sjmallett 5645232812Sjmallett/** 5646232812Sjmallett * cvmx_mio_ptp_pps_thresh_hi 5647232812Sjmallett * 5648232812Sjmallett * MIO_PTP_PPS_THRESH_HI = Hi bytes of PTP PPS 5649232812Sjmallett * 5650232812Sjmallett * Writes to MIO_PTP_PPS_THRESH_HI also clear MIO_PTP_PPS_THRESH_LO. To update all 96 bits, write MIO_PTP_PPS_THRESH_HI followed 5651232812Sjmallett * by MIO_PTP_PPS_THRESH_LO 5652232812Sjmallett */ 5653232812Sjmallettunion cvmx_mio_ptp_pps_thresh_hi { 5654232812Sjmallett uint64_t u64; 5655232812Sjmallett struct cvmx_mio_ptp_pps_thresh_hi_s { 5656232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5657232812Sjmallett uint64_t nanosec : 64; /**< Nanoseconds */ 5658232812Sjmallett#else 5659232812Sjmallett uint64_t nanosec : 64; 5660232812Sjmallett#endif 5661232812Sjmallett } s; 5662232812Sjmallett struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; 5663232812Sjmallett struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; 5664232812Sjmallett struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; 5665232812Sjmallett struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; 5666232812Sjmallett}; 5667232812Sjmalletttypedef union cvmx_mio_ptp_pps_thresh_hi cvmx_mio_ptp_pps_thresh_hi_t; 5668232812Sjmallett 5669232812Sjmallett/** 5670232812Sjmallett * cvmx_mio_ptp_pps_thresh_lo 5671232812Sjmallett * 5672232812Sjmallett * MIO_PTP_PPS_THRESH_LO = Lo bytes of PTP PPS 5673232812Sjmallett * 5674232812Sjmallett */ 5675232812Sjmallettunion cvmx_mio_ptp_pps_thresh_lo { 5676232812Sjmallett uint64_t u64; 5677232812Sjmallett struct cvmx_mio_ptp_pps_thresh_lo_s { 5678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5679232812Sjmallett uint64_t reserved_32_63 : 32; 5680232812Sjmallett uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5681232812Sjmallett#else 5682232812Sjmallett uint64_t frnanosec : 32; 5683232812Sjmallett uint64_t reserved_32_63 : 32; 5684232812Sjmallett#endif 5685232812Sjmallett } s; 5686232812Sjmallett struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; 5687232812Sjmallett struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; 5688232812Sjmallett struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; 5689232812Sjmallett struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; 5690232812Sjmallett}; 5691232812Sjmalletttypedef union cvmx_mio_ptp_pps_thresh_lo cvmx_mio_ptp_pps_thresh_lo_t; 5692232812Sjmallett 5693232812Sjmallett/** 5694215976Sjmallett * cvmx_mio_ptp_timestamp 5695215976Sjmallett * 5696215976Sjmallett * MIO_PTP_TIMESTAMP = Timestamp latched on MIO_PTP_CLOCK_CFG[TSTMP_EDGE] edge of MIO_PTP_CLOCK_CFG[TSTMP_IN] 5697215976Sjmallett * 5698215976Sjmallett */ 5699232812Sjmallettunion cvmx_mio_ptp_timestamp { 5700215976Sjmallett uint64_t u64; 5701232812Sjmallett struct cvmx_mio_ptp_timestamp_s { 5702232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5703215976Sjmallett uint64_t nanosec : 64; /**< Nanoseconds */ 5704215976Sjmallett#else 5705215976Sjmallett uint64_t nanosec : 64; 5706215976Sjmallett#endif 5707215976Sjmallett } s; 5708232812Sjmallett struct cvmx_mio_ptp_timestamp_s cn61xx; 5709215976Sjmallett struct cvmx_mio_ptp_timestamp_s cn63xx; 5710215976Sjmallett struct cvmx_mio_ptp_timestamp_s cn63xxp1; 5711232812Sjmallett struct cvmx_mio_ptp_timestamp_s cn66xx; 5712232812Sjmallett struct cvmx_mio_ptp_timestamp_s cn68xx; 5713232812Sjmallett struct cvmx_mio_ptp_timestamp_s cn68xxp1; 5714232812Sjmallett struct cvmx_mio_ptp_timestamp_s cnf71xx; 5715215976Sjmallett}; 5716215976Sjmalletttypedef union cvmx_mio_ptp_timestamp cvmx_mio_ptp_timestamp_t; 5717215976Sjmallett 5718215976Sjmallett/** 5719232812Sjmallett * cvmx_mio_qlm#_cfg 5720232812Sjmallett * 5721232812Sjmallett * Notes: 5722232812Sjmallett * Certain QLM_SPD is valid only for certain QLM_CFG configuration, refer to HRM for valid 5723232812Sjmallett * combinations. These csrs are reset only on COLD_RESET. The Reset values for QLM_SPD and QLM_CFG 5724232812Sjmallett * are as follows: MIO_QLM0_CFG SPD=F, CFG=2 SGMII (AGX0) 5725232812Sjmallett * MIO_QLM1_CFG SPD=0, CFG=1 PCIE 2x1 (PEM0/PEM1) 5726232812Sjmallett */ 5727232812Sjmallettunion cvmx_mio_qlmx_cfg { 5728232812Sjmallett uint64_t u64; 5729232812Sjmallett struct cvmx_mio_qlmx_cfg_s { 5730232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5731232812Sjmallett uint64_t reserved_15_63 : 49; 5732232812Sjmallett uint64_t prtmode : 1; /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0] 5733232812Sjmallett 0 = port is EP mode 5734232812Sjmallett 1 = port is RC mode */ 5735232812Sjmallett uint64_t reserved_12_13 : 2; 5736232812Sjmallett uint64_t qlm_spd : 4; /**< QLM0 speed for SGMii 5737232812Sjmallett 0 = 5 Gbaud 100.00 MHz Ref 5738232812Sjmallett 1 = 2.5 Gbaud 100.00 MHz Ref 5739232812Sjmallett 2 = 2.5 Gbaud 100.00 MHz Ref 5740232812Sjmallett 3 = 1.25 Gbaud 100.00 MHz Ref 5741232812Sjmallett 4 = 1.25 Gbaud 156.25 MHz Ref 5742232812Sjmallett 5 = 6.25 Gbaud 125.00 MHz Ref 5743232812Sjmallett 6 = 5 Gbaud 125.00 MHz Ref 5744232812Sjmallett 7 = 2.5 Gbaud 156.25 MHz Ref 5745232812Sjmallett 8 = 3.125 Gbaud 125.00 MHz Ref 5746232812Sjmallett 9 = 2.5 Gbaud 125.00 MHz Ref 5747232812Sjmallett 10 = 1.25 Gbaud 125.00 MHz Ref 5748232812Sjmallett 11 = 5 Gbaud 156.25 MHz Ref 5749232812Sjmallett 12 = 6.25 Gbaud 156.25 MHz Ref 5750232812Sjmallett 13 = 3.75 Gbaud 156.25 MHz Ref 5751232812Sjmallett 14 = 3.125 Gbaud 156.25 MHz Ref 5752232812Sjmallett 15 = QLM Disabled 5753232812Sjmallett 5754232812Sjmallett QLM1 speed PEM0 PEM1 5755232812Sjmallett 0 = 2.5/5 2.5/5 Gbaud 100.00 MHz Ref 5756232812Sjmallett 1 = 2.5 2.5/5 Gbaud 100.00 MHz Ref 5757232812Sjmallett 2 = 2.5/5 2.5 Gbaud 100.00 MHz Ref 5758232812Sjmallett 3 = 2.5 2.5 Gbaud 100.00 MHz Ref 5759232812Sjmallett 4 = 2.5/5 2.5/5 Gbaud 125.00 MHz Ref 5760232812Sjmallett 6 = 2.5/5 2.5 Gbaud 125.00 MHz Ref 5761232812Sjmallett 7 = 2.5 2.5 Gbaud 125.00 MHz Ref 5762232812Sjmallett 9 = 2.5 2.5/5 Gbaud 125.00 MHz Ref 5763232812Sjmallett 15 = QLM Disabled 5764232812Sjmallett 5,8,10-14 are reserved */ 5765232812Sjmallett uint64_t reserved_4_7 : 4; 5766232812Sjmallett uint64_t qlm_cfg : 4; /**< QLM configuration mode 5767232812Sjmallett For Interface 0: 5768232812Sjmallett 00 Reserved 5769232812Sjmallett 01 Reserved 5770232812Sjmallett 10 SGMII (AGX0) 5771232812Sjmallett 11 Reserved 5772232812Sjmallett For Interface 1: 5773232812Sjmallett 00 PCIE 1x2 (PEM1) 5774232812Sjmallett 01 PCIE 2x1 (PEM0/PEM1) 5775232812Sjmallett 1x Reserved */ 5776232812Sjmallett#else 5777232812Sjmallett uint64_t qlm_cfg : 4; 5778232812Sjmallett uint64_t reserved_4_7 : 4; 5779232812Sjmallett uint64_t qlm_spd : 4; 5780232812Sjmallett uint64_t reserved_12_13 : 2; 5781232812Sjmallett uint64_t prtmode : 1; 5782232812Sjmallett uint64_t reserved_15_63 : 49; 5783232812Sjmallett#endif 5784232812Sjmallett } s; 5785232812Sjmallett struct cvmx_mio_qlmx_cfg_cn61xx { 5786232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5787232812Sjmallett uint64_t reserved_15_63 : 49; 5788232812Sjmallett uint64_t prtmode : 1; /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0] 5789232812Sjmallett 0 = port is EP mode 5790232812Sjmallett 1 = port is RC mode 5791232812Sjmallett For QLM2, HOST_MODE is always '0' because PCIe 5792232812Sjmallett is not supported. */ 5793232812Sjmallett uint64_t reserved_12_13 : 2; 5794232812Sjmallett uint64_t qlm_spd : 4; /**< QLM speed for SGMii/XAUI 5795232812Sjmallett 0 = 5 Gbaud 100.00 MHz Ref 5796232812Sjmallett 1 = 2.5 Gbaud 100.00 MHz Ref 5797232812Sjmallett 2 = 2.5 Gbaud 100.00 MHz Ref 5798232812Sjmallett 3 = 1.25 Gbaud 100.00 MHz Ref 5799232812Sjmallett 4 = 1.25 Gbaud 156.25 MHz Ref 5800232812Sjmallett 5 = 6.25 Gbaud 125.00 MHz Ref 5801232812Sjmallett 6 = 5 Gbaud 125.00 MHz Ref 5802232812Sjmallett 7 = 2.5 Gbaud 156.25 MHz Ref 5803232812Sjmallett 8 = 3.125 Gbaud 125.00 MHz Ref 5804232812Sjmallett 9 = 2.5 Gbaud 125.00 MHz Ref 5805232812Sjmallett 10 = 1.25 Gbaud 125.00 MHz Ref 5806232812Sjmallett 11 = 5 Gbaud 156.25 MHz Ref 5807232812Sjmallett 12 = 6.25 Gbaud 156.25 MHz Ref 5808232812Sjmallett 13 = 3.75 Gbaud 156.25 MHz Ref 5809232812Sjmallett 14 = 3.125 Gbaud 156.25 MHz Ref 5810232812Sjmallett 15 = QLM Disabled 5811232812Sjmallett 5812232812Sjmallett QLM speed PEM0 PEM1 5813232812Sjmallett 0 = 2.5/5 2.5/5 Gbaud 100.00 MHz Ref 5814232812Sjmallett 1 = 2.5 2.5/5 Gbaud 100.00 MHz Ref 5815232812Sjmallett 2 = 2.5/5 2.5 Gbaud 100.00 MHz Ref 5816232812Sjmallett 3 = 2.5 2.5 Gbaud 100.00 MHz Ref 5817232812Sjmallett 4 = 2.5/5 2.5/5 Gbaud 125.00 MHz Ref 5818232812Sjmallett 6 = 2.5/5 2.5 Gbaud 125.00 MHz Ref 5819232812Sjmallett 7 = 2.5 2.5 Gbaud 125.00 MHz Ref 5820232812Sjmallett 9 = 2.5 2.5/5 Gbaud 125.00 MHz Ref 5821232812Sjmallett 15 = QLM Disabled 5822232812Sjmallett 5,8,10-14 are reserved */ 5823232812Sjmallett uint64_t reserved_2_7 : 6; 5824232812Sjmallett uint64_t qlm_cfg : 2; /**< QLM configuration mode 5825232812Sjmallett For Interface 0: 5826232812Sjmallett 00 PCIE 1x4 (PEM0) 5827232812Sjmallett 01 Reserved 5828232812Sjmallett 10 SGMII (AGX1) 5829232812Sjmallett 11 XAUI (AGX1) 5830232812Sjmallett For Interface 1: 5831232812Sjmallett 00 PCIE 1x2 (PEM1) 5832232812Sjmallett 01 PCIE 2x1 (PEM0/PEM1) 5833232812Sjmallett 10 Reserved 5834232812Sjmallett 11 Reserved 5835232812Sjmallett For Interface 2: 5836232812Sjmallett 00 Reserved 5837232812Sjmallett 01 Reserved 5838232812Sjmallett 10 SGMII (AGX0) 5839232812Sjmallett 11 XAUI (AGX0) */ 5840232812Sjmallett#else 5841232812Sjmallett uint64_t qlm_cfg : 2; 5842232812Sjmallett uint64_t reserved_2_7 : 6; 5843232812Sjmallett uint64_t qlm_spd : 4; 5844232812Sjmallett uint64_t reserved_12_13 : 2; 5845232812Sjmallett uint64_t prtmode : 1; 5846232812Sjmallett uint64_t reserved_15_63 : 49; 5847232812Sjmallett#endif 5848232812Sjmallett } cn61xx; 5849232812Sjmallett struct cvmx_mio_qlmx_cfg_cn66xx { 5850232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5851232812Sjmallett uint64_t reserved_12_63 : 52; 5852232812Sjmallett uint64_t qlm_spd : 4; /**< QLM speed 5853232812Sjmallett 0 = 5 Gbaud 5854232812Sjmallett 1 = 2.5 Gbaud 5855232812Sjmallett 2 = 2.5 Gbaud 5856232812Sjmallett 3 = 1.25 Gbaud 5857232812Sjmallett 4 = 1.25 Gbaud 5858232812Sjmallett 5 = 6.25 Gbaud 5859232812Sjmallett 6 = 5 Gbaud 5860232812Sjmallett 7 = 2.5 Gbaud 5861232812Sjmallett 8 = 3.125 Gbaud 5862232812Sjmallett 9 = 2.5 Gbaud 5863232812Sjmallett 10 = 1.25 Gbaud 5864232812Sjmallett 11 = 5 Gbaud 5865232812Sjmallett 12 = 6.25 Gbaud 5866232812Sjmallett 13 = 3.75 Gbaud 5867232812Sjmallett 14 = 3.125 Gbaud 5868232812Sjmallett 15 = QLM Disabled */ 5869232812Sjmallett uint64_t reserved_4_7 : 4; 5870232812Sjmallett uint64_t qlm_cfg : 4; /**< QLM configuration mode 5871232812Sjmallett 0000 PCIE gen2 5872232812Sjmallett 0001 SRIO 1x4 short 5873232812Sjmallett 0010 PCIE gen1 only 5874232812Sjmallett 0011 SRIO 1x4 long 5875232812Sjmallett 0100 SRIO 2x2 short 5876232812Sjmallett 0101 SRIO 4x1 short 5877232812Sjmallett 0110 SRIO 2x2 long 5878232812Sjmallett 0111 SRIO 4x1 long 5879232812Sjmallett 1000 PCIE gen2 (alias) 5880232812Sjmallett 1001 SGMII 5881232812Sjmallett 1010 PCIE gen1 only (alias) 5882232812Sjmallett 1011 XAUI 5883232812Sjmallett 1100 RESERVED 5884232812Sjmallett 1101 RESERVED 5885232812Sjmallett 1110 RESERVED 5886232812Sjmallett 1111 RESERVED 5887232812Sjmallett NOTE: Internal encodings differ from QLM_MODE 5888232812Sjmallett pins encodings */ 5889232812Sjmallett#else 5890232812Sjmallett uint64_t qlm_cfg : 4; 5891232812Sjmallett uint64_t reserved_4_7 : 4; 5892232812Sjmallett uint64_t qlm_spd : 4; 5893232812Sjmallett uint64_t reserved_12_63 : 52; 5894232812Sjmallett#endif 5895232812Sjmallett } cn66xx; 5896232812Sjmallett struct cvmx_mio_qlmx_cfg_cn68xx { 5897232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5898232812Sjmallett uint64_t reserved_12_63 : 52; 5899232812Sjmallett uint64_t qlm_spd : 4; /**< QLM speed 5900232812Sjmallett 0 = 5 Gbaud 100.00 MHz Ref 5901232812Sjmallett 1 = 2.5 Gbaud 100.00 MHz Ref 5902232812Sjmallett 2 = 2.5 Gbaud 100.00 MHz Ref 5903232812Sjmallett 3 = 1.25 Gbaud 100.00 MHz Ref 5904232812Sjmallett 4 = 1.25 Gbaud 156.25 MHz Ref 5905232812Sjmallett 5 = 6.25 Gbaud 125.00 MHz Ref 5906232812Sjmallett 6 = 5 Gbaud 125.00 MHz Ref 5907232812Sjmallett 7 = 2.5 Gbaud 156.25 MHz Ref 5908232812Sjmallett 8 = 3.125 Gbaud 125.00 MHz Ref 5909232812Sjmallett 9 = 2.5 Gbaud 125.00 MHz Ref 5910232812Sjmallett 10 = 1.25 Gbaud 125.00 MHz Ref 5911232812Sjmallett 11 = 5 Gbaud 156.25 MHz Ref 5912232812Sjmallett 12 = 6.25 Gbaud 156.25 MHz Ref 5913232812Sjmallett 13 = 3.75 Gbaud 156.25 MHz Ref 5914232812Sjmallett 14 = 3.125 Gbaud 156.25 MHz Ref 5915232812Sjmallett 15 = QLM Disabled */ 5916232812Sjmallett uint64_t reserved_3_7 : 5; 5917232812Sjmallett uint64_t qlm_cfg : 3; /**< QLM configuration mode 5918232812Sjmallett 000 = PCIE 5919232812Sjmallett 001 = ILK 5920232812Sjmallett 010 = SGMII 5921232812Sjmallett 011 = XAUI 5922232812Sjmallett 100 = RESERVED 5923232812Sjmallett 101 = RESERVED 5924232812Sjmallett 110 = RESERVED 5925232812Sjmallett 111 = RXAUI 5926232812Sjmallett NOTE: Internal encodings differ from QLM_MODE 5927232812Sjmallett pins encodings */ 5928232812Sjmallett#else 5929232812Sjmallett uint64_t qlm_cfg : 3; 5930232812Sjmallett uint64_t reserved_3_7 : 5; 5931232812Sjmallett uint64_t qlm_spd : 4; 5932232812Sjmallett uint64_t reserved_12_63 : 52; 5933232812Sjmallett#endif 5934232812Sjmallett } cn68xx; 5935232812Sjmallett struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; 5936232812Sjmallett struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; 5937232812Sjmallett}; 5938232812Sjmalletttypedef union cvmx_mio_qlmx_cfg cvmx_mio_qlmx_cfg_t; 5939232812Sjmallett 5940232812Sjmallett/** 5941215976Sjmallett * cvmx_mio_rst_boot 5942232812Sjmallett * 5943232812Sjmallett * Notes: 5944232812Sjmallett * JTCSRDIS, EJTAGDIS, ROMEN reset to 1 in authentik mode; in all other modes they reset to 0. 5945232812Sjmallett * 5946215976Sjmallett */ 5947232812Sjmallettunion cvmx_mio_rst_boot { 5948215976Sjmallett uint64_t u64; 5949232812Sjmallett struct cvmx_mio_rst_boot_s { 5950232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5951232812Sjmallett uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 5952232812Sjmallett timer. When CHIPKILL=1 and the timer expires, 5953232812Sjmallett internal chip reset is asserted forever until the 5954232812Sjmallett next chip reset. The CHIPKILL timer can be 5955232812Sjmallett stopped only by a chip (cold, warm, soft) reset. 5956232812Sjmallett The length of the CHIPKILL timer is specified by 5957232812Sjmallett MIO_RST_CKILL[TIMER]. */ 5958232812Sjmallett uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 5959232812Sjmallett controller is disabled */ 5960232812Sjmallett uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 5961232812Sjmallett uint64_t romen : 1; /**< If ROMEN=1, Authentik/eMMC boot ROM is visible 5962232812Sjmallett in the boot bus address space. */ 5963232812Sjmallett uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 5964232812Sjmallett during a CHIPKILL. Writes have no effect when 5965232812Sjmallett MIO_RST_BOOT[CHIPKILL]=1. */ 5966232812Sjmallett uint64_t jt_tstmode : 1; /**< JTAG test mode */ 5967232812Sjmallett uint64_t reserved_50_57 : 8; 5968232812Sjmallett uint64_t lboot_ext : 2; /**< Reserved */ 5969232812Sjmallett uint64_t reserved_44_47 : 4; 5970232812Sjmallett uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 5971232812Sjmallett uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 5972232812Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 5973232812Sjmallett C_MUL = (core clk speed) / (ref clock speed) 5974232812Sjmallett "ref clock speed" should always be 50MHz. 5975232812Sjmallett If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 5976232812Sjmallett from PLL_REF_CLK pin. 5977232812Sjmallett If PLL_QLM_REF_CLK_EN=1, "ref clock" is 5978232812Sjmallett 1/2 speed of QLMC_REF_CLK_* pins. */ 5979232812Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 5980232812Sjmallett PNR_MUL = (coprocessor clk speed) / 5981232812Sjmallett (ref clock speed) 5982232812Sjmallett See C_MUL comments about ref clock. */ 5983232812Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */ 5984232812Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */ 5985232812Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */ 5986232812Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dcok. 5987232812Sjmallett 5988232812Sjmallett bit9 - Soft reset due to watchdog 5989232812Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 5990232812Sjmallett bit7 - Warm reset due to cntl0 link-down or 5991232812Sjmallett hot-reset 5992232812Sjmallett bit6 - Warm reset due to cntl1 link-down or 5993232812Sjmallett hot-reset 5994232812Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 5995232812Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 5996232812Sjmallett bit3 - Warm reset due to PERST1_L pin 5997232812Sjmallett bit2 - Warm reset due to PERST0_L pin 5998232812Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 5999232812Sjmallett bit0 - Cold reset due to DCOK pin */ 6000232812Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6001232812Sjmallett after chip cold/warm/soft reset. */ 6002232812Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6003232812Sjmallett#else 6004232812Sjmallett uint64_t rboot_pin : 1; 6005232812Sjmallett uint64_t rboot : 1; 6006232812Sjmallett uint64_t lboot : 10; 6007232812Sjmallett uint64_t qlm0_spd : 4; 6008232812Sjmallett uint64_t qlm1_spd : 4; 6009232812Sjmallett uint64_t qlm2_spd : 4; 6010232812Sjmallett uint64_t pnr_mul : 6; 6011232812Sjmallett uint64_t c_mul : 6; 6012232812Sjmallett uint64_t qlm3_spd : 4; 6013232812Sjmallett uint64_t qlm4_spd : 4; 6014232812Sjmallett uint64_t reserved_44_47 : 4; 6015232812Sjmallett uint64_t lboot_ext : 2; 6016232812Sjmallett uint64_t reserved_50_57 : 8; 6017232812Sjmallett uint64_t jt_tstmode : 1; 6018232812Sjmallett uint64_t ckill_ppdis : 1; 6019232812Sjmallett uint64_t romen : 1; 6020232812Sjmallett uint64_t ejtagdis : 1; 6021232812Sjmallett uint64_t jtcsrdis : 1; 6022232812Sjmallett uint64_t chipkill : 1; 6023232812Sjmallett#endif 6024232812Sjmallett } s; 6025232812Sjmallett struct cvmx_mio_rst_boot_cn61xx { 6026232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6027232812Sjmallett uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 6028232812Sjmallett timer. When CHIPKILL=1 and the timer expires, 6029232812Sjmallett internal chip reset is asserted forever until the 6030232812Sjmallett next chip reset. The CHIPKILL timer can be 6031232812Sjmallett stopped only by a chip (cold, warm, soft) reset. 6032232812Sjmallett The length of the CHIPKILL timer is specified by 6033232812Sjmallett MIO_RST_CKILL[TIMER]. */ 6034232812Sjmallett uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 6035232812Sjmallett controller is disabled */ 6036232812Sjmallett uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 6037232812Sjmallett uint64_t romen : 1; /**< If ROMEN=1, Authentik/eMMC boot ROM is visible 6038232812Sjmallett in the boot bus address space. */ 6039232812Sjmallett uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 6040232812Sjmallett during a CHIPKILL. Writes have no effect when 6041232812Sjmallett MIO_RST_BOOT[CHIPKILL]=1. */ 6042232812Sjmallett uint64_t jt_tstmode : 1; /**< JTAG test mode */ 6043232812Sjmallett uint64_t reserved_50_57 : 8; 6044232812Sjmallett uint64_t lboot_ext : 2; /**< Reserved */ 6045232812Sjmallett uint64_t reserved_36_47 : 12; 6046232812Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 6047232812Sjmallett C_MUL = (core clk speed) / (ref clock speed) 6048232812Sjmallett "ref clock speed" should always be 50MHz. 6049232812Sjmallett If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6050232812Sjmallett from PLL_REF_CLK pin. 6051232812Sjmallett If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6052232812Sjmallett 1/2 speed of QLMC_REF_CLK_* pins. */ 6053232812Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6054232812Sjmallett PNR_MUL = (coprocessor clk speed) / 6055232812Sjmallett (ref clock speed) 6056232812Sjmallett See C_MUL comments about ref clock. */ 6057232812Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */ 6058232812Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */ 6059232812Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */ 6060232812Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dcok. 6061232812Sjmallett 6062232812Sjmallett bit9 - Soft reset due to watchdog 6063232812Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 6064232812Sjmallett bit7 - Warm reset due to cntl0 link-down or 6065232812Sjmallett hot-reset 6066232812Sjmallett bit6 - Warm reset due to cntl1 link-down or 6067232812Sjmallett hot-reset 6068232812Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 6069232812Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 6070232812Sjmallett bit3 - Warm reset due to PERST1_L pin 6071232812Sjmallett bit2 - Warm reset due to PERST0_L pin 6072232812Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 6073232812Sjmallett bit0 - Cold reset due to DCOK pin */ 6074232812Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6075232812Sjmallett after chip cold/warm/soft reset. */ 6076232812Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6077232812Sjmallett#else 6078232812Sjmallett uint64_t rboot_pin : 1; 6079232812Sjmallett uint64_t rboot : 1; 6080232812Sjmallett uint64_t lboot : 10; 6081232812Sjmallett uint64_t qlm0_spd : 4; 6082232812Sjmallett uint64_t qlm1_spd : 4; 6083232812Sjmallett uint64_t qlm2_spd : 4; 6084232812Sjmallett uint64_t pnr_mul : 6; 6085232812Sjmallett uint64_t c_mul : 6; 6086232812Sjmallett uint64_t reserved_36_47 : 12; 6087232812Sjmallett uint64_t lboot_ext : 2; 6088232812Sjmallett uint64_t reserved_50_57 : 8; 6089232812Sjmallett uint64_t jt_tstmode : 1; 6090232812Sjmallett uint64_t ckill_ppdis : 1; 6091232812Sjmallett uint64_t romen : 1; 6092232812Sjmallett uint64_t ejtagdis : 1; 6093232812Sjmallett uint64_t jtcsrdis : 1; 6094232812Sjmallett uint64_t chipkill : 1; 6095232812Sjmallett#endif 6096232812Sjmallett } cn61xx; 6097232812Sjmallett struct cvmx_mio_rst_boot_cn63xx { 6098232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6099215976Sjmallett uint64_t reserved_36_63 : 28; 6100215976Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 6101215976Sjmallett C_MUL = (core clk speed) / (ref clock speed) 6102215976Sjmallett "ref clock speed" should always be 50MHz. 6103215976Sjmallett If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6104215976Sjmallett from PLL_REF_CLK pin. 6105215976Sjmallett If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6106215976Sjmallett 1/2 speed of QLMC_REF_CLK_* pins. */ 6107215976Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6108215976Sjmallett PNR_MUL = (coprocessor clk speed) / 6109215976Sjmallett (ref clock speed) 6110215976Sjmallett See C_MUL comments about ref clock. */ 6111215976Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6112215976Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6113215976Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6114215976Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6115215976Sjmallett 6116215976Sjmallett bit9 - Soft reset due to watchdog 6117215976Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 6118215976Sjmallett bit7 - Warm reset due to cntl0 link-down or 6119215976Sjmallett hot-reset 6120215976Sjmallett bit6 - Warm reset due to cntl1 link-down or 6121215976Sjmallett hot-reset 6122215976Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 6123215976Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 6124215976Sjmallett bit3 - Warm reset due to PERST1_L pin 6125215976Sjmallett bit2 - Warm reset due to PERST0_L pin 6126215976Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 6127215976Sjmallett bit0 - Cold reset due to DCOK pin */ 6128215976Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6129215976Sjmallett after chip cold/warm/soft reset. */ 6130215976Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6131215976Sjmallett#else 6132215976Sjmallett uint64_t rboot_pin : 1; 6133215976Sjmallett uint64_t rboot : 1; 6134215976Sjmallett uint64_t lboot : 10; 6135215976Sjmallett uint64_t qlm0_spd : 4; 6136215976Sjmallett uint64_t qlm1_spd : 4; 6137215976Sjmallett uint64_t qlm2_spd : 4; 6138215976Sjmallett uint64_t pnr_mul : 6; 6139215976Sjmallett uint64_t c_mul : 6; 6140215976Sjmallett uint64_t reserved_36_63 : 28; 6141215976Sjmallett#endif 6142232812Sjmallett } cn63xx; 6143232812Sjmallett struct cvmx_mio_rst_boot_cn63xx cn63xxp1; 6144232812Sjmallett struct cvmx_mio_rst_boot_cn66xx { 6145232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6146232812Sjmallett uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 6147232812Sjmallett timer. When CHIPKILL=1 and the timer expires, 6148232812Sjmallett internal chip reset is asserted forever until the 6149232812Sjmallett next chip reset. The CHIPKILL timer can be 6150232812Sjmallett stopped only by a chip (cold, warm, soft) reset. 6151232812Sjmallett The length of the CHIPKILL timer is specified by 6152232812Sjmallett MIO_RST_CKILL[TIMER]. */ 6153232812Sjmallett uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 6154232812Sjmallett controller is disabled */ 6155232812Sjmallett uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 6156232812Sjmallett uint64_t romen : 1; /**< If ROMEN=1, Authentik ROM is visible in the boot 6157232812Sjmallett bus address space. */ 6158232812Sjmallett uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 6159232812Sjmallett during a CHIPKILL. Writes have no effect when 6160232812Sjmallett MIO_RST_BOOT[CHIPKILL]=1. */ 6161232812Sjmallett uint64_t reserved_50_58 : 9; 6162232812Sjmallett uint64_t lboot_ext : 2; /**< Extended Last boot cause mask, resets only with 6163232812Sjmallett dock. 6164232812Sjmallett 6165232812Sjmallett bit1 - Warm reset due to cntl3 link-down or 6166232812Sjmallett hot-reset 6167232812Sjmallett bit0 - Warm reset due to cntl2 link-down or 6168232812Sjmallett hot-reset */ 6169232812Sjmallett uint64_t reserved_36_47 : 12; 6170232812Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 6171232812Sjmallett C_MUL = (core clk speed) / (ref clock speed) 6172232812Sjmallett "ref clock speed" should always be 50MHz. 6173232812Sjmallett If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6174232812Sjmallett from PLL_REF_CLK pin. 6175232812Sjmallett If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6176232812Sjmallett 1/2 speed of QLMC_REF_CLK_* pins. */ 6177232812Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6178232812Sjmallett PNR_MUL = (coprocessor clk speed) / 6179232812Sjmallett (ref clock speed) 6180232812Sjmallett See C_MUL comments about ref clock. */ 6181232812Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6182232812Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6183232812Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6184232812Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6185232812Sjmallett 6186232812Sjmallett bit9 - Soft reset due to watchdog 6187232812Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 6188232812Sjmallett bit7 - Warm reset due to cntl0 link-down or 6189232812Sjmallett hot-reset 6190232812Sjmallett bit6 - Warm reset due to cntl1 link-down or 6191232812Sjmallett hot-reset 6192232812Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 6193232812Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 6194232812Sjmallett bit3 - Warm reset due to PERST1_L pin 6195232812Sjmallett bit2 - Warm reset due to PERST0_L pin 6196232812Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 6197232812Sjmallett bit0 - Cold reset due to DCOK pin */ 6198232812Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6199232812Sjmallett after chip cold/warm/soft reset. */ 6200232812Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6201232812Sjmallett#else 6202232812Sjmallett uint64_t rboot_pin : 1; 6203232812Sjmallett uint64_t rboot : 1; 6204232812Sjmallett uint64_t lboot : 10; 6205232812Sjmallett uint64_t qlm0_spd : 4; 6206232812Sjmallett uint64_t qlm1_spd : 4; 6207232812Sjmallett uint64_t qlm2_spd : 4; 6208232812Sjmallett uint64_t pnr_mul : 6; 6209232812Sjmallett uint64_t c_mul : 6; 6210232812Sjmallett uint64_t reserved_36_47 : 12; 6211232812Sjmallett uint64_t lboot_ext : 2; 6212232812Sjmallett uint64_t reserved_50_58 : 9; 6213232812Sjmallett uint64_t ckill_ppdis : 1; 6214232812Sjmallett uint64_t romen : 1; 6215232812Sjmallett uint64_t ejtagdis : 1; 6216232812Sjmallett uint64_t jtcsrdis : 1; 6217232812Sjmallett uint64_t chipkill : 1; 6218232812Sjmallett#endif 6219232812Sjmallett } cn66xx; 6220232812Sjmallett struct cvmx_mio_rst_boot_cn68xx { 6221232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6222232812Sjmallett uint64_t reserved_59_63 : 5; 6223232812Sjmallett uint64_t jt_tstmode : 1; /**< JTAG test mode */ 6224232812Sjmallett uint64_t reserved_44_57 : 14; 6225232812Sjmallett uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 6226232812Sjmallett uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 6227232812Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 6228232812Sjmallett C_MUL = (core clk speed) / (ref clock speed) 6229232812Sjmallett "ref clock" is PLL_REF_CLK pin, which should 6230232812Sjmallett always be 50 MHz. */ 6231232812Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6232232812Sjmallett PNR_MUL = (coprocessor clk speed) 6233232812Sjmallett (ref clock speed) 6234232812Sjmallett See C_MUL comments about ref clock. */ 6235232812Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6236232812Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6237232812Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6238232812Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6239232812Sjmallett 6240232812Sjmallett bit9 - Soft reset due to watchdog 6241232812Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 6242232812Sjmallett bit7 - Warm reset due to cntl0 link-down or 6243232812Sjmallett hot-reset 6244232812Sjmallett bit6 - Warm reset due to cntl1 link-down or 6245232812Sjmallett hot-reset 6246232812Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 6247232812Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 6248232812Sjmallett bit3 - Warm reset due to PERST1_L pin 6249232812Sjmallett bit2 - Warm reset due to PERST0_L pin 6250232812Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 6251232812Sjmallett bit0 - Cold reset due to DCOK pin */ 6252232812Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6253232812Sjmallett after chip cold/warm/soft reset. */ 6254232812Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6255232812Sjmallett#else 6256232812Sjmallett uint64_t rboot_pin : 1; 6257232812Sjmallett uint64_t rboot : 1; 6258232812Sjmallett uint64_t lboot : 10; 6259232812Sjmallett uint64_t qlm0_spd : 4; 6260232812Sjmallett uint64_t qlm1_spd : 4; 6261232812Sjmallett uint64_t qlm2_spd : 4; 6262232812Sjmallett uint64_t pnr_mul : 6; 6263232812Sjmallett uint64_t c_mul : 6; 6264232812Sjmallett uint64_t qlm3_spd : 4; 6265232812Sjmallett uint64_t qlm4_spd : 4; 6266232812Sjmallett uint64_t reserved_44_57 : 14; 6267232812Sjmallett uint64_t jt_tstmode : 1; 6268232812Sjmallett uint64_t reserved_59_63 : 5; 6269232812Sjmallett#endif 6270232812Sjmallett } cn68xx; 6271232812Sjmallett struct cvmx_mio_rst_boot_cn68xxp1 { 6272232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6273232812Sjmallett uint64_t reserved_44_63 : 20; 6274232812Sjmallett uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 6275232812Sjmallett uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 6276232812Sjmallett uint64_t c_mul : 6; /**< Core clock multiplier: 6277232812Sjmallett C_MUL = (core clk speed) / (ref clock speed) 6278232812Sjmallett "ref clock" is PLL_REF_CLK pin, which should 6279232812Sjmallett always be 50 MHz. */ 6280232812Sjmallett uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6281232812Sjmallett PNR_MUL = (coprocessor clk speed) 6282232812Sjmallett (ref clock speed) 6283232812Sjmallett See C_MUL comments about ref clock. */ 6284232812Sjmallett uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6285232812Sjmallett uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6286232812Sjmallett uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6287232812Sjmallett uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6288232812Sjmallett 6289232812Sjmallett bit9 - Soft reset due to watchdog 6290232812Sjmallett bit8 - Soft reset due to CIU_SOFT_RST write 6291232812Sjmallett bit7 - Warm reset due to cntl0 link-down or 6292232812Sjmallett hot-reset 6293232812Sjmallett bit6 - Warm reset due to cntl1 link-down or 6294232812Sjmallett hot-reset 6295232812Sjmallett bit5 - Cntl1 reset due to PERST1_L pin 6296232812Sjmallett bit4 - Cntl0 reset due to PERST0_L pin 6297232812Sjmallett bit3 - Warm reset due to PERST1_L pin 6298232812Sjmallett bit2 - Warm reset due to PERST0_L pin 6299232812Sjmallett bit1 - Warm reset due to CHIP_RESET_L pin 6300232812Sjmallett bit0 - Cold reset due to DCOK pin */ 6301232812Sjmallett uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6302232812Sjmallett after chip cold/warm/soft reset. */ 6303232812Sjmallett uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6304232812Sjmallett#else 6305232812Sjmallett uint64_t rboot_pin : 1; 6306232812Sjmallett uint64_t rboot : 1; 6307232812Sjmallett uint64_t lboot : 10; 6308232812Sjmallett uint64_t qlm0_spd : 4; 6309232812Sjmallett uint64_t qlm1_spd : 4; 6310232812Sjmallett uint64_t qlm2_spd : 4; 6311232812Sjmallett uint64_t pnr_mul : 6; 6312232812Sjmallett uint64_t c_mul : 6; 6313232812Sjmallett uint64_t qlm3_spd : 4; 6314232812Sjmallett uint64_t qlm4_spd : 4; 6315232812Sjmallett uint64_t reserved_44_63 : 20; 6316232812Sjmallett#endif 6317232812Sjmallett } cn68xxp1; 6318232812Sjmallett struct cvmx_mio_rst_boot_cn61xx cnf71xx; 6319215976Sjmallett}; 6320215976Sjmalletttypedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t; 6321215976Sjmallett 6322215976Sjmallett/** 6323215976Sjmallett * cvmx_mio_rst_cfg 6324215976Sjmallett * 6325215976Sjmallett * Notes: 6326215976Sjmallett * Cold reset will always performs a full bist. 6327215976Sjmallett * 6328215976Sjmallett */ 6329232812Sjmallettunion cvmx_mio_rst_cfg { 6330215976Sjmallett uint64_t u64; 6331232812Sjmallett struct cvmx_mio_rst_cfg_s { 6332232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6333232812Sjmallett uint64_t reserved_3_63 : 61; 6334232812Sjmallett uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6335232812Sjmallett instead of a full bist. A warm/soft reset will 6336232812Sjmallett not change this field. */ 6337232812Sjmallett uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6338232812Sjmallett of a full bist. A warm/soft reset will not 6339232812Sjmallett change this field. */ 6340232812Sjmallett uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6341232812Sjmallett of a full bist. A warm/soft reset will not 6342232812Sjmallett change this field. */ 6343232812Sjmallett#else 6344232812Sjmallett uint64_t soft_clr_bist : 1; 6345232812Sjmallett uint64_t warm_clr_bist : 1; 6346232812Sjmallett uint64_t cntl_clr_bist : 1; 6347232812Sjmallett uint64_t reserved_3_63 : 61; 6348232812Sjmallett#endif 6349232812Sjmallett } s; 6350232812Sjmallett struct cvmx_mio_rst_cfg_cn61xx { 6351232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6352215976Sjmallett uint64_t bist_delay : 58; /**< Reserved */ 6353215976Sjmallett uint64_t reserved_3_5 : 3; 6354215976Sjmallett uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6355215976Sjmallett instead of a full bist. A warm/soft reset will 6356215976Sjmallett not change this field. */ 6357215976Sjmallett uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6358215976Sjmallett of a full bist. A warm/soft reset will not 6359215976Sjmallett change this field. */ 6360215976Sjmallett uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6361215976Sjmallett of a full bist. A warm/soft reset will not 6362215976Sjmallett change this field. */ 6363215976Sjmallett#else 6364215976Sjmallett uint64_t soft_clr_bist : 1; 6365215976Sjmallett uint64_t warm_clr_bist : 1; 6366215976Sjmallett uint64_t cntl_clr_bist : 1; 6367215976Sjmallett uint64_t reserved_3_5 : 3; 6368215976Sjmallett uint64_t bist_delay : 58; 6369215976Sjmallett#endif 6370232812Sjmallett } cn61xx; 6371232812Sjmallett struct cvmx_mio_rst_cfg_cn61xx cn63xx; 6372232812Sjmallett struct cvmx_mio_rst_cfg_cn63xxp1 { 6373232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6374215976Sjmallett uint64_t bist_delay : 58; /**< Reserved */ 6375215976Sjmallett uint64_t reserved_2_5 : 4; 6376215976Sjmallett uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6377215976Sjmallett of a full bist. A warm/soft reset will not 6378215976Sjmallett change this field. */ 6379215976Sjmallett uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6380215976Sjmallett of a full bist. A warm/soft reset will not 6381215976Sjmallett change this field. */ 6382215976Sjmallett#else 6383215976Sjmallett uint64_t soft_clr_bist : 1; 6384215976Sjmallett uint64_t warm_clr_bist : 1; 6385215976Sjmallett uint64_t reserved_2_5 : 4; 6386215976Sjmallett uint64_t bist_delay : 58; 6387215976Sjmallett#endif 6388215976Sjmallett } cn63xxp1; 6389232812Sjmallett struct cvmx_mio_rst_cfg_cn61xx cn66xx; 6390232812Sjmallett struct cvmx_mio_rst_cfg_cn68xx { 6391232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6392232812Sjmallett uint64_t bist_delay : 56; /**< Reserved */ 6393232812Sjmallett uint64_t reserved_3_7 : 5; 6394232812Sjmallett uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6395232812Sjmallett instead of a full bist. A warm/soft reset will 6396232812Sjmallett not change this field. */ 6397232812Sjmallett uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6398232812Sjmallett of a full bist. A warm/soft reset will not 6399232812Sjmallett change this field. */ 6400232812Sjmallett uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6401232812Sjmallett of a full bist. A warm/soft reset will not 6402232812Sjmallett change this field. */ 6403232812Sjmallett#else 6404232812Sjmallett uint64_t soft_clr_bist : 1; 6405232812Sjmallett uint64_t warm_clr_bist : 1; 6406232812Sjmallett uint64_t cntl_clr_bist : 1; 6407232812Sjmallett uint64_t reserved_3_7 : 5; 6408232812Sjmallett uint64_t bist_delay : 56; 6409232812Sjmallett#endif 6410232812Sjmallett } cn68xx; 6411232812Sjmallett struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; 6412232812Sjmallett struct cvmx_mio_rst_cfg_cn61xx cnf71xx; 6413215976Sjmallett}; 6414215976Sjmalletttypedef union cvmx_mio_rst_cfg cvmx_mio_rst_cfg_t; 6415215976Sjmallett 6416215976Sjmallett/** 6417232812Sjmallett * cvmx_mio_rst_ckill 6418232812Sjmallett * 6419232812Sjmallett * MIO_RST_CKILL = MIO Chipkill Timer Register 6420232812Sjmallett * 6421215976Sjmallett */ 6422232812Sjmallettunion cvmx_mio_rst_ckill { 6423215976Sjmallett uint64_t u64; 6424232812Sjmallett struct cvmx_mio_rst_ckill_s { 6425232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6426232812Sjmallett uint64_t reserved_47_63 : 17; 6427232812Sjmallett uint64_t timer : 47; /**< CHIPKILL timer measured in SCLKs. Reads return 6428232812Sjmallett the current CHIPKILL timer. Writes have no 6429232812Sjmallett effect when MIO_RST_BOOT[CHIPKILL]=1. */ 6430232812Sjmallett#else 6431232812Sjmallett uint64_t timer : 47; 6432232812Sjmallett uint64_t reserved_47_63 : 17; 6433232812Sjmallett#endif 6434232812Sjmallett } s; 6435232812Sjmallett struct cvmx_mio_rst_ckill_s cn61xx; 6436232812Sjmallett struct cvmx_mio_rst_ckill_s cn66xx; 6437232812Sjmallett struct cvmx_mio_rst_ckill_s cnf71xx; 6438232812Sjmallett}; 6439232812Sjmalletttypedef union cvmx_mio_rst_ckill cvmx_mio_rst_ckill_t; 6440232812Sjmallett 6441232812Sjmallett/** 6442232812Sjmallett * cvmx_mio_rst_cntl# 6443232812Sjmallett * 6444232812Sjmallett * Notes: 6445232812Sjmallett * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz. 6446232812Sjmallett * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz. 6447232812Sjmallett */ 6448232812Sjmallettunion cvmx_mio_rst_cntlx { 6449232812Sjmallett uint64_t u64; 6450232812Sjmallett struct cvmx_mio_rst_cntlx_s { 6451232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6452232812Sjmallett uint64_t reserved_13_63 : 51; 6453232812Sjmallett uint64_t in_rev_ln : 1; /**< RO access to corresponding pin PCIE*_REV_LANES 6454232812Sjmallett which is used for initial value for REV_LANES 6455232812Sjmallett For INT0/CNTL0: pin PCIE0_REV_LANES 6456232812Sjmallett For INT1/CNTL1: always zero as no PCIE1 pin */ 6457232812Sjmallett uint64_t rev_lanes : 1; /**< Reverse the lanes for INT*. 6458232812Sjmallett A warm/soft reset will not change this field. 6459232812Sjmallett On cold reset, this field is initialized to 6460232812Sjmallett IN_REVLANE value. 6461232812Sjmallett When QLM1_CFG=1, INT0(PEM0) REV_LANES internal 6462232812Sjmallett setting will be always forced to '0', INT1(PEM1) 6463232812Sjmallett will be forced to '1' regardless CSR value. */ 6464232812Sjmallett uint64_t gen1_only : 1; /**< Disable PCIE GEN2 Capability. This bit is 6465232812Sjmallett always unpredictable whenever the controller 6466232812Sjmallett is not attached to any SerDes lanes, and is 6467232812Sjmallett otherwise always set when SCLK is slower than 6468232812Sjmallett 550Mhz. 6469232812Sjmallett The MIO_RST_CNTL*[GEN1_ONLY] value is based on 6470232812Sjmallett the MIO_QLM1_CFG[QLM_SPD] value. */ 6471232812Sjmallett uint64_t prst_link : 1; /**< Controls whether corresponding controller 6472232812Sjmallett link-down or hot-reset causes the assertion of 6473232812Sjmallett CIU_SOFT_PRST*[SOFT_PRST] 6474232812Sjmallett 6475232812Sjmallett A warm/soft reset will not change this field. 6476232812Sjmallett On cold reset, this field is initialized to 0 */ 6477232812Sjmallett uint64_t rst_done : 1; /**< Read-only access to controller reset status 6478232812Sjmallett 6479232812Sjmallett RESET_DONE is always zero (i.e. the controller 6480232812Sjmallett is held in reset) when: 6481232812Sjmallett - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6482232812Sjmallett - RST_RCV==1 and PERST*_L pin is asserted */ 6483232812Sjmallett uint64_t rst_link : 1; /**< Controls whether corresponding controller 6484232812Sjmallett link-down or hot-reset causes a warm chip reset 6485232812Sjmallett On cold reset, this field is initialized as 6486232812Sjmallett follows: 6487232812Sjmallett 0 = when corresponding HOST_MODE=1 6488232812Sjmallett 1 = when corresponding HOST_MODE=0 6489232812Sjmallett 6490232812Sjmallett Note that a link-down or hot-reset event can 6491232812Sjmallett never cause a warm chip reset when the 6492232812Sjmallett controller is in reset (i.e. can never cause a 6493232812Sjmallett warm reset when RST_DONE==0). */ 6494232812Sjmallett uint64_t host_mode : 1; /**< RO access to corresponding strap PCIE*_HOST_MODE 6495232812Sjmallett For CNTL1/INT1, HOST_MODE is always '1' because 6496232812Sjmallett there is no PCIE1_HOST_MODE pin. */ 6497232812Sjmallett uint64_t prtmode : 2; /**< Port mode 6498232812Sjmallett 0 = port is EP mode 6499232812Sjmallett 1 = port is RC mode 6500232812Sjmallett 2,3 = Reserved 6501232812Sjmallett A warm/soft reset will not change this field. 6502232812Sjmallett On cold reset, this field is initialized as 6503232812Sjmallett HOST_MODE (corresponding strap PCIE*_HOST_MODE) */ 6504232812Sjmallett uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6505232812Sjmallett is driven by the OCTEON. A warm/soft reset 6506232812Sjmallett will not change this field. On cold reset, 6507232812Sjmallett this field is initialized as follows: 6508232812Sjmallett 0 = when corresponding HOST_MODE=0 6509232812Sjmallett 1 = when corresponding HOST_MODE=1 6510232812Sjmallett 6511232812Sjmallett When set, OCTEON drives the corresponding 6512232812Sjmallett PERST*_L pin. Otherwise, OCTEON does not drive 6513232812Sjmallett the corresponding PERST*_L pin. */ 6514232812Sjmallett uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6515232812Sjmallett is recieved by OCTEON. A warm/soft reset 6516232812Sjmallett will not change this field. On cold reset, 6517232812Sjmallett this field is initialized as follows: 6518232812Sjmallett 0 = when corresponding HOST_MODE=1 6519232812Sjmallett 1 = when corresponding HOST_MODE=0 6520232812Sjmallett 6521232812Sjmallett When RST_RCV==1, the PERST*_L value is 6522232812Sjmallett received and may be used to reset the 6523232812Sjmallett controller and (optionally, based on RST_CHIP) 6524232812Sjmallett warm reset the chip. 6525232812Sjmallett 6526232812Sjmallett When RST_RCV==1 (and RST_CHIP=0), 6527232812Sjmallett MIO_RST_INT[PERST*] gets set when the PERST*_L 6528232812Sjmallett pin asserts. (This interrupt can alert SW 6529232812Sjmallett whenever the external reset pin initiates a 6530232812Sjmallett controller reset sequence.) 6531232812Sjmallett 6532232812Sjmallett RST_VAL gives the PERST*_L pin value when 6533232812Sjmallett RST_RCV==1. 6534232812Sjmallett 6535232812Sjmallett When RST_RCV==0, the PERST*_L pin value is 6536232812Sjmallett ignored. */ 6537232812Sjmallett uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6538232812Sjmallett pin causes a chip warm reset like CHIP_RESET_L. 6539232812Sjmallett A warm/soft reset will not change this field. 6540232812Sjmallett On cold reset, this field is initialized to 0. 6541232812Sjmallett 6542232812Sjmallett RST_CHIP is not used when RST_RCV==0. 6543232812Sjmallett 6544232812Sjmallett When RST_RCV==0, RST_CHIP is ignored. 6545232812Sjmallett 6546232812Sjmallett When RST_RCV==1, RST_CHIP==1, and PERST*_L 6547232812Sjmallett asserts, a chip warm reset will be generated. */ 6548232812Sjmallett uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6549232812Sjmallett Unpredictable when RST_RCV==0. Reads as 1 when 6550232812Sjmallett RST_RCV==1 and the PERST*_L pin is asserted. 6551232812Sjmallett Reads as 0 when RST_RCV==1 and the PERST*_L 6552232812Sjmallett pin is not asserted. */ 6553232812Sjmallett#else 6554232812Sjmallett uint64_t rst_val : 1; 6555232812Sjmallett uint64_t rst_chip : 1; 6556232812Sjmallett uint64_t rst_rcv : 1; 6557232812Sjmallett uint64_t rst_drv : 1; 6558232812Sjmallett uint64_t prtmode : 2; 6559232812Sjmallett uint64_t host_mode : 1; 6560232812Sjmallett uint64_t rst_link : 1; 6561232812Sjmallett uint64_t rst_done : 1; 6562232812Sjmallett uint64_t prst_link : 1; 6563232812Sjmallett uint64_t gen1_only : 1; 6564232812Sjmallett uint64_t rev_lanes : 1; 6565232812Sjmallett uint64_t in_rev_ln : 1; 6566232812Sjmallett uint64_t reserved_13_63 : 51; 6567232812Sjmallett#endif 6568232812Sjmallett } s; 6569232812Sjmallett struct cvmx_mio_rst_cntlx_s cn61xx; 6570232812Sjmallett struct cvmx_mio_rst_cntlx_cn66xx { 6571232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6572215976Sjmallett uint64_t reserved_10_63 : 54; 6573215976Sjmallett uint64_t prst_link : 1; /**< Controls whether corresponding controller 6574215976Sjmallett link-down or hot-reset causes the assertion of 6575215976Sjmallett CIU_SOFT_PRST*[SOFT_PRST] 6576215976Sjmallett 6577215976Sjmallett A warm/soft reset will not change this field. 6578232812Sjmallett On cold reset, this field is initialized to 0 */ 6579232812Sjmallett uint64_t rst_done : 1; /**< Read-only access to controller reset status 6580232812Sjmallett 6581232812Sjmallett RESET_DONE is always zero (i.e. the controller 6582232812Sjmallett is held in reset) when: 6583232812Sjmallett - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6584232812Sjmallett - RST_RCV==1 and PERST*_L pin is asserted */ 6585232812Sjmallett uint64_t rst_link : 1; /**< Controls whether corresponding controller 6586232812Sjmallett link-down or hot-reset causes a warm chip reset 6587232812Sjmallett On cold reset, this field is initialized as 6588215976Sjmallett follows: 6589215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6590215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6591215976Sjmallett 6592232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6593232812Sjmallett is initialized to 1 on cold reset. 6594232812Sjmallett 6595232812Sjmallett Note that a link-down or hot-reset event can 6596232812Sjmallett never cause a warm chip reset when the 6597232812Sjmallett controller is in reset (i.e. can never cause a 6598232812Sjmallett warm reset when RST_DONE==0). */ 6599232812Sjmallett uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE 6600232812Sjmallett 6601232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6602232812Sjmallett is reserved/RAZ. 6603232812Sjmallett 6604232812Sjmallett QLM0_HOST_MODE corresponds to PCIe0/sRIO0 6605232812Sjmallett QLM1_HOST_MODE corresponds to PCIe1/sRIO1 */ 6606232812Sjmallett uint64_t prtmode : 2; /**< Port mode 6607232812Sjmallett 0 = port is EP mode 6608232812Sjmallett 1 = port is RC mode 6609232812Sjmallett 2,3 = Reserved 6610232812Sjmallett A warm/soft reset will not change this field. 6611232812Sjmallett On cold reset, this field is initialized as 6612232812Sjmallett follows: 6613232812Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6614232812Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 6615232812Sjmallett 6616232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6617232812Sjmallett is initialized to 0 on cold reset. */ 6618232812Sjmallett uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6619232812Sjmallett is driven by the OCTEON. A warm/soft reset 6620232812Sjmallett will not change this field. On cold reset, 6621232812Sjmallett this field is initialized as follows: 6622232812Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6623232812Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 6624232812Sjmallett 6625232812Sjmallett When set, OCTEON drives the corresponding 6626232812Sjmallett PERST*_L pin. Otherwise, OCTEON does not drive 6627232812Sjmallett the corresponding PERST*_L pin. 6628232812Sjmallett 6629232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6630232812Sjmallett is reserved/RAZ. */ 6631232812Sjmallett uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6632232812Sjmallett is recieved by OCTEON. A warm/soft reset 6633232812Sjmallett will not change this field. On cold reset, 6634232812Sjmallett this field is initialized as follows: 6635232812Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6636232812Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6637232812Sjmallett 6638232812Sjmallett When RST_RCV==1, the PERST*_L value is 6639232812Sjmallett received and may be used to reset the 6640232812Sjmallett controller and (optionally, based on RST_CHIP) 6641232812Sjmallett warm reset the chip. 6642232812Sjmallett 6643232812Sjmallett When RST_RCV==1 (and RST_CHIP=0), 6644232812Sjmallett MIO_RST_INT[PERST*] gets set when the PERST*_L 6645232812Sjmallett pin asserts. (This interrupt can alert SW 6646232812Sjmallett whenever the external reset pin initiates a 6647232812Sjmallett controller reset sequence.) 6648232812Sjmallett 6649232812Sjmallett RST_VAL gives the PERST*_L pin value when 6650232812Sjmallett RST_RCV==1. 6651232812Sjmallett 6652232812Sjmallett When RST_RCV==0, the PERST*_L pin value is 6653232812Sjmallett ignored. 6654232812Sjmallett 6655232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6656232812Sjmallett is reserved/RAZ. */ 6657232812Sjmallett uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6658232812Sjmallett pin causes a chip warm reset like CHIP_RESET_L. 6659232812Sjmallett A warm/soft reset will not change this field. 6660232812Sjmallett On cold reset, this field is initialized to 0. 6661232812Sjmallett 6662232812Sjmallett RST_CHIP is not used when RST_RCV==0. 6663232812Sjmallett 6664232812Sjmallett When RST_RCV==0, RST_CHIP is ignored. 6665232812Sjmallett 6666232812Sjmallett When RST_RCV==1, RST_CHIP==1, and PERST*_L 6667232812Sjmallett asserts, a chip warm reset will be generated. 6668232812Sjmallett 6669232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6670232812Sjmallett is reserved/RAZ. */ 6671232812Sjmallett uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6672232812Sjmallett Unpredictable when RST_RCV==0. Reads as 1 when 6673232812Sjmallett RST_RCV==1 and the PERST*_L pin is asserted. 6674232812Sjmallett Reads as 0 when RST_RCV==1 and the PERST*_L 6675232812Sjmallett pin is not asserted. 6676232812Sjmallett 6677232812Sjmallett For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6678232812Sjmallett is reserved/RAZ. */ 6679232812Sjmallett#else 6680232812Sjmallett uint64_t rst_val : 1; 6681232812Sjmallett uint64_t rst_chip : 1; 6682232812Sjmallett uint64_t rst_rcv : 1; 6683232812Sjmallett uint64_t rst_drv : 1; 6684232812Sjmallett uint64_t prtmode : 2; 6685232812Sjmallett uint64_t host_mode : 1; 6686232812Sjmallett uint64_t rst_link : 1; 6687232812Sjmallett uint64_t rst_done : 1; 6688232812Sjmallett uint64_t prst_link : 1; 6689232812Sjmallett uint64_t reserved_10_63 : 54; 6690232812Sjmallett#endif 6691232812Sjmallett } cn66xx; 6692232812Sjmallett struct cvmx_mio_rst_cntlx_cn66xx cn68xx; 6693232812Sjmallett struct cvmx_mio_rst_cntlx_s cnf71xx; 6694232812Sjmallett}; 6695232812Sjmalletttypedef union cvmx_mio_rst_cntlx cvmx_mio_rst_cntlx_t; 6696232812Sjmallett 6697232812Sjmallett/** 6698232812Sjmallett * cvmx_mio_rst_ctl# 6699232812Sjmallett * 6700232812Sjmallett * Notes: 6701232812Sjmallett * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz. 6702232812Sjmallett * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz. 6703232812Sjmallett */ 6704232812Sjmallettunion cvmx_mio_rst_ctlx { 6705232812Sjmallett uint64_t u64; 6706232812Sjmallett struct cvmx_mio_rst_ctlx_s { 6707232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6708232812Sjmallett uint64_t reserved_13_63 : 51; 6709232812Sjmallett uint64_t in_rev_ln : 1; /**< RO access to corresponding pin PCIE*_REV_LANES 6710232812Sjmallett which is used for initial value for REV_LANES 6711232812Sjmallett For INT0/CNTL0: pin PCIE0_REV_LANES 6712232812Sjmallett For INT1/CNTL1: always zero as no PCIE1 pin */ 6713232812Sjmallett uint64_t rev_lanes : 1; /**< Reverse the lanes for INT*. 6714232812Sjmallett A warm/soft reset will not change this field. 6715232812Sjmallett On cold reset, this field is initialized to 6716232812Sjmallett IN_REVLANE value. 6717232812Sjmallett When QLM1_CFG=1, INT0(PEM0) REV_LANES internal 6718232812Sjmallett setting will be always forced to '0', INT1(PEM1) 6719232812Sjmallett will be forced to '1' regardless CSR value. */ 6720232812Sjmallett uint64_t gen1_only : 1; /**< Disable PCIE GEN2 Capability. This bit is 6721232812Sjmallett always unpredictable whenever the controller 6722232812Sjmallett is not attached to any SerDes lanes, and is 6723232812Sjmallett otherwise always set when SCLK is slower than 6724232812Sjmallett 550Mhz. 6725232812Sjmallett The MIO_RST_CNTL*[GEN1_ONLY] value is based on 6726232812Sjmallett the MIO_QLM1_CFG[QLM_SPD] value. */ 6727232812Sjmallett uint64_t prst_link : 1; /**< Controls whether corresponding controller 6728232812Sjmallett link-down or hot-reset causes the assertion of 6729232812Sjmallett CIU_SOFT_PRST*[SOFT_PRST] 6730232812Sjmallett 6731232812Sjmallett A warm/soft reset will not change this field. 6732232812Sjmallett On cold reset, this field is initialized to 0 */ 6733232812Sjmallett uint64_t rst_done : 1; /**< Read-only access to controller reset status 6734232812Sjmallett 6735232812Sjmallett RESET_DONE is always zero (i.e. the controller 6736232812Sjmallett is held in reset) when: 6737232812Sjmallett - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6738232812Sjmallett - RST_RCV==1 and PERST*_L pin is asserted */ 6739232812Sjmallett uint64_t rst_link : 1; /**< Controls whether corresponding controller 6740232812Sjmallett link-down or hot-reset causes a warm chip reset 6741232812Sjmallett On cold reset, this field is initialized as 6742232812Sjmallett follows: 6743232812Sjmallett 0 = when corresponding HOST_MODE=1 6744232812Sjmallett 1 = when corresponding HOST_MODE=0 6745232812Sjmallett 6746232812Sjmallett Note that a link-down or hot-reset event can 6747232812Sjmallett never cause a warm chip reset when the 6748232812Sjmallett controller is in reset (i.e. can never cause a 6749232812Sjmallett warm reset when RST_DONE==0). */ 6750232812Sjmallett uint64_t host_mode : 1; /**< RO access to corresponding strap PCIE*_HOST_MODE 6751232812Sjmallett For CNTL1/INT1, HOST_MODE is always '1' because 6752232812Sjmallett there is no PCIE1_HOST_MODE pin. */ 6753232812Sjmallett uint64_t prtmode : 2; /**< Port mode 6754232812Sjmallett 0 = port is EP mode 6755232812Sjmallett 1 = port is RC mode 6756232812Sjmallett 2,3 = Reserved 6757232812Sjmallett A warm/soft reset will not change this field. 6758232812Sjmallett On cold reset, this field is initialized as 6759232812Sjmallett HOST_MODE (corresponding strap PCIE*_HOST_MODE) */ 6760232812Sjmallett uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6761232812Sjmallett is driven by the OCTEON. A warm/soft reset 6762232812Sjmallett will not change this field. On cold reset, 6763232812Sjmallett this field is initialized as follows: 6764232812Sjmallett 0 = when corresponding HOST_MODE=0 6765232812Sjmallett 1 = when corresponding HOST_MODE=1 6766232812Sjmallett 6767232812Sjmallett When set, OCTEON drives the corresponding 6768232812Sjmallett PERST*_L pin. Otherwise, OCTEON does not drive 6769232812Sjmallett the corresponding PERST*_L pin. */ 6770232812Sjmallett uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6771232812Sjmallett is recieved by OCTEON. A warm/soft reset 6772232812Sjmallett will not change this field. On cold reset, 6773232812Sjmallett this field is initialized as follows: 6774232812Sjmallett 0 = when corresponding HOST_MODE=1 6775232812Sjmallett 1 = when corresponding HOST_MODE=0 6776232812Sjmallett 6777232812Sjmallett When RST_RCV==1, the PERST*_L value is 6778232812Sjmallett received and may be used to reset the 6779232812Sjmallett controller and (optionally, based on RST_CHIP) 6780232812Sjmallett warm reset the chip. 6781232812Sjmallett 6782232812Sjmallett When RST_RCV==1 (and RST_CHIP=0), 6783232812Sjmallett MIO_RST_INT[PERST*] gets set when the PERST*_L 6784232812Sjmallett pin asserts. (This interrupt can alert SW 6785232812Sjmallett whenever the external reset pin initiates a 6786232812Sjmallett controller reset sequence.) 6787232812Sjmallett 6788232812Sjmallett RST_VAL gives the PERST*_L pin value when 6789232812Sjmallett RST_RCV==1. 6790232812Sjmallett 6791232812Sjmallett When RST_RCV==0, the PERST*_L pin value is 6792232812Sjmallett ignored. */ 6793232812Sjmallett uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6794232812Sjmallett pin causes a chip warm reset like CHIP_RESET_L. 6795232812Sjmallett A warm/soft reset will not change this field. 6796232812Sjmallett On cold reset, this field is initialized to 0. 6797232812Sjmallett 6798232812Sjmallett RST_CHIP is not used when RST_RCV==0. 6799232812Sjmallett 6800232812Sjmallett When RST_RCV==0, RST_CHIP is ignored. 6801232812Sjmallett 6802232812Sjmallett When RST_RCV==1, RST_CHIP==1, and PERST*_L 6803232812Sjmallett asserts, a chip warm reset will be generated. */ 6804232812Sjmallett uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6805232812Sjmallett Unpredictable when RST_RCV==0. Reads as 1 when 6806232812Sjmallett RST_RCV==1 and the PERST*_L pin is asserted. 6807232812Sjmallett Reads as 0 when RST_RCV==1 and the PERST*_L 6808232812Sjmallett pin is not asserted. */ 6809232812Sjmallett#else 6810232812Sjmallett uint64_t rst_val : 1; 6811232812Sjmallett uint64_t rst_chip : 1; 6812232812Sjmallett uint64_t rst_rcv : 1; 6813232812Sjmallett uint64_t rst_drv : 1; 6814232812Sjmallett uint64_t prtmode : 2; 6815232812Sjmallett uint64_t host_mode : 1; 6816232812Sjmallett uint64_t rst_link : 1; 6817232812Sjmallett uint64_t rst_done : 1; 6818232812Sjmallett uint64_t prst_link : 1; 6819232812Sjmallett uint64_t gen1_only : 1; 6820232812Sjmallett uint64_t rev_lanes : 1; 6821232812Sjmallett uint64_t in_rev_ln : 1; 6822232812Sjmallett uint64_t reserved_13_63 : 51; 6823232812Sjmallett#endif 6824232812Sjmallett } s; 6825232812Sjmallett struct cvmx_mio_rst_ctlx_s cn61xx; 6826232812Sjmallett struct cvmx_mio_rst_ctlx_cn63xx { 6827232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6828232812Sjmallett uint64_t reserved_10_63 : 54; 6829232812Sjmallett uint64_t prst_link : 1; /**< Controls whether corresponding controller 6830232812Sjmallett link-down or hot-reset causes the assertion of 6831232812Sjmallett CIU_SOFT_PRST*[SOFT_PRST] 6832232812Sjmallett 6833232812Sjmallett A warm/soft reset will not change this field. 6834232812Sjmallett On cold reset, this field is initialized to 0 6835232812Sjmallett 6836215976Sjmallett ***NOTE: Added in pass 2.0 */ 6837215976Sjmallett uint64_t rst_done : 1; /**< Read-only access to controller reset status 6838215976Sjmallett 6839215976Sjmallett RESET_DONE is always zero (i.e. the controller 6840215976Sjmallett is held in reset) when: 6841215976Sjmallett - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6842215976Sjmallett - RST_RCV==1 and PERST*_L pin is asserted */ 6843215976Sjmallett uint64_t rst_link : 1; /**< Controls whether corresponding controller 6844215976Sjmallett link-down or hot-reset causes a warm chip reset 6845215976Sjmallett On cold reset, this field is initialized as 6846215976Sjmallett follows: 6847215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6848215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6849215976Sjmallett 6850215976Sjmallett Note that a link-down or hot-reset event can 6851215976Sjmallett never cause a warm chip reset when the 6852215976Sjmallett controller is in reset (i.e. can never cause a 6853215976Sjmallett warm reset when RST_DONE==0). */ 6854215976Sjmallett uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */ 6855215976Sjmallett uint64_t prtmode : 2; /**< Port mode 6856215976Sjmallett 0 = port is EP mode 6857215976Sjmallett 1 = port is RC mode 6858215976Sjmallett 2,3 = Reserved 6859215976Sjmallett A warm/soft reset will not change this field. 6860215976Sjmallett On cold reset, this field is initialized as 6861215976Sjmallett follows: 6862215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6863215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 */ 6864215976Sjmallett uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6865215976Sjmallett is driven by the OCTEON. A warm/soft reset 6866215976Sjmallett will not change this field. On cold reset, 6867215976Sjmallett this field is initialized as follows: 6868215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6869215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 6870215976Sjmallett 6871215976Sjmallett When set, OCTEON drives the corresponding 6872215976Sjmallett PERST*_L pin. Otherwise, OCTEON does not drive 6873215976Sjmallett the corresponding PERST*_L pin. */ 6874215976Sjmallett uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6875215976Sjmallett is recieved by OCTEON. A warm/soft reset 6876215976Sjmallett will not change this field. On cold reset, 6877215976Sjmallett this field is initialized as follows: 6878215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6879215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6880215976Sjmallett 6881215976Sjmallett When RST_RCV==1, the PERST*_L value is 6882215976Sjmallett received and may be used to reset the 6883215976Sjmallett controller and (optionally, based on RST_CHIP) 6884215976Sjmallett warm reset the chip. 6885215976Sjmallett 6886215976Sjmallett When RST_RCV==1 (and RST_CHIP=0), 6887215976Sjmallett MIO_RST_INT[PERST*] gets set when the PERST*_L 6888215976Sjmallett pin asserts. (This interrupt can alert SW 6889215976Sjmallett whenever the external reset pin initiates a 6890215976Sjmallett controller reset sequence.) 6891215976Sjmallett 6892215976Sjmallett RST_VAL gives the PERST*_L pin value when 6893215976Sjmallett RST_RCV==1. 6894215976Sjmallett 6895215976Sjmallett When RST_RCV==0, the PERST*_L pin value is 6896215976Sjmallett ignored. */ 6897215976Sjmallett uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6898215976Sjmallett pin causes a chip warm reset like CHIP_RESET_L. 6899215976Sjmallett A warm/soft reset will not change this field. 6900215976Sjmallett On cold reset, this field is initialized to 0. 6901215976Sjmallett 6902215976Sjmallett RST_CHIP is not used when RST_RCV==0. 6903215976Sjmallett 6904215976Sjmallett When RST_RCV==0, RST_CHIP is ignored. 6905215976Sjmallett 6906215976Sjmallett When RST_RCV==1, RST_CHIP==1, and PERST*_L 6907215976Sjmallett asserts, a chip warm reset will be generated. */ 6908215976Sjmallett uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6909215976Sjmallett Unpredictable when RST_RCV==0. Reads as 1 when 6910215976Sjmallett RST_RCV==1 and the PERST*_L pin is asserted. 6911215976Sjmallett Reads as 0 when RST_RCV==1 and the PERST*_L 6912215976Sjmallett pin is not asserted. */ 6913215976Sjmallett#else 6914215976Sjmallett uint64_t rst_val : 1; 6915215976Sjmallett uint64_t rst_chip : 1; 6916215976Sjmallett uint64_t rst_rcv : 1; 6917215976Sjmallett uint64_t rst_drv : 1; 6918215976Sjmallett uint64_t prtmode : 2; 6919215976Sjmallett uint64_t host_mode : 1; 6920215976Sjmallett uint64_t rst_link : 1; 6921215976Sjmallett uint64_t rst_done : 1; 6922215976Sjmallett uint64_t prst_link : 1; 6923215976Sjmallett uint64_t reserved_10_63 : 54; 6924215976Sjmallett#endif 6925232812Sjmallett } cn63xx; 6926232812Sjmallett struct cvmx_mio_rst_ctlx_cn63xxp1 { 6927232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6928215976Sjmallett uint64_t reserved_9_63 : 55; 6929215976Sjmallett uint64_t rst_done : 1; /**< Read-only access to controller reset status 6930215976Sjmallett 6931215976Sjmallett RESET_DONE is always zero (i.e. the controller 6932215976Sjmallett is held in reset) when: 6933215976Sjmallett - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6934215976Sjmallett - RST_RCV==1 and PERST*_L pin is asserted */ 6935215976Sjmallett uint64_t rst_link : 1; /**< Controls whether corresponding controller 6936215976Sjmallett link-down or hot-reset causes a warm chip reset 6937215976Sjmallett On cold reset, this field is initialized as 6938215976Sjmallett follows: 6939215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6940215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6941215976Sjmallett 6942215976Sjmallett Note that a link-down or hot-reset event can 6943215976Sjmallett never cause a warm chip reset when the 6944215976Sjmallett controller is in reset (i.e. can never cause a 6945215976Sjmallett warm reset when RST_DONE==0). */ 6946215976Sjmallett uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */ 6947215976Sjmallett uint64_t prtmode : 2; /**< Port mode 6948215976Sjmallett 0 = port is EP mode 6949215976Sjmallett 1 = port is RC mode 6950215976Sjmallett 2,3 = Reserved 6951215976Sjmallett A warm/soft reset will not change this field. 6952215976Sjmallett On cold reset, this field is initialized as 6953215976Sjmallett follows: 6954215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6955215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 */ 6956215976Sjmallett uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6957215976Sjmallett is driven by the OCTEON. A warm/soft reset 6958215976Sjmallett will not change this field. On cold reset, 6959215976Sjmallett this field is initialized as follows: 6960215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=0 6961215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=1 6962215976Sjmallett 6963215976Sjmallett When set, OCTEON drives the corresponding 6964215976Sjmallett PERST*_L pin. Otherwise, OCTEON does not drive 6965215976Sjmallett the corresponding PERST*_L pin. */ 6966215976Sjmallett uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6967215976Sjmallett is recieved by OCTEON. A warm/soft reset 6968215976Sjmallett will not change this field. On cold reset, 6969215976Sjmallett this field is initialized as follows: 6970215976Sjmallett 0 = when corresponding strap QLM*_HOST_MODE=1 6971215976Sjmallett 1 = when corresponding strap QLM*_HOST_MODE=0 6972215976Sjmallett 6973215976Sjmallett When RST_RCV==1, the PERST*_L value is 6974215976Sjmallett received and may be used to reset the 6975215976Sjmallett controller and (optionally, based on RST_CHIP) 6976215976Sjmallett warm reset the chip. 6977215976Sjmallett 6978215976Sjmallett When RST_RCV==1 (and RST_CHIP=0), 6979215976Sjmallett MIO_RST_INT[PERST*] gets set when the PERST*_L 6980215976Sjmallett pin asserts. (This interrupt can alert SW 6981215976Sjmallett whenever the external reset pin initiates a 6982215976Sjmallett controller reset sequence.) 6983215976Sjmallett 6984215976Sjmallett RST_VAL gives the PERST*_L pin value when 6985215976Sjmallett RST_RCV==1. 6986215976Sjmallett 6987215976Sjmallett When RST_RCV==0, the PERST*_L pin value is 6988215976Sjmallett ignored. */ 6989215976Sjmallett uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6990215976Sjmallett pin causes a chip warm reset like CHIP_RESET_L. 6991215976Sjmallett A warm/soft reset will not change this field. 6992215976Sjmallett On cold reset, this field is initialized to 0. 6993215976Sjmallett 6994215976Sjmallett RST_CHIP is not used when RST_RCV==0. 6995215976Sjmallett 6996215976Sjmallett When RST_RCV==0, RST_CHIP is ignored. 6997215976Sjmallett 6998215976Sjmallett When RST_RCV==1, RST_CHIP==1, and PERST*_L 6999215976Sjmallett asserts, a chip warm reset will be generated. */ 7000215976Sjmallett uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 7001215976Sjmallett Unpredictable when RST_RCV==0. Reads as 1 when 7002215976Sjmallett RST_RCV==1 and the PERST*_L pin is asserted. 7003215976Sjmallett Reads as 0 when RST_RCV==1 and the PERST*_L 7004215976Sjmallett pin is not asserted. */ 7005215976Sjmallett#else 7006215976Sjmallett uint64_t rst_val : 1; 7007215976Sjmallett uint64_t rst_chip : 1; 7008215976Sjmallett uint64_t rst_rcv : 1; 7009215976Sjmallett uint64_t rst_drv : 1; 7010215976Sjmallett uint64_t prtmode : 2; 7011215976Sjmallett uint64_t host_mode : 1; 7012215976Sjmallett uint64_t rst_link : 1; 7013215976Sjmallett uint64_t rst_done : 1; 7014215976Sjmallett uint64_t reserved_9_63 : 55; 7015215976Sjmallett#endif 7016215976Sjmallett } cn63xxp1; 7017232812Sjmallett struct cvmx_mio_rst_ctlx_cn63xx cn66xx; 7018232812Sjmallett struct cvmx_mio_rst_ctlx_cn63xx cn68xx; 7019232812Sjmallett struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; 7020232812Sjmallett struct cvmx_mio_rst_ctlx_s cnf71xx; 7021215976Sjmallett}; 7022215976Sjmalletttypedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t; 7023215976Sjmallett 7024215976Sjmallett/** 7025215976Sjmallett * cvmx_mio_rst_delay 7026215976Sjmallett */ 7027232812Sjmallettunion cvmx_mio_rst_delay { 7028215976Sjmallett uint64_t u64; 7029232812Sjmallett struct cvmx_mio_rst_delay_s { 7030232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7031215976Sjmallett uint64_t reserved_32_63 : 32; 7032232812Sjmallett uint64_t warm_rst_dly : 16; /**< A warm reset immediately causes an early warm 7033215976Sjmallett reset notification. However, the assertion of 7034232812Sjmallett warm reset will be delayed this many sclks. 7035215976Sjmallett A warm/soft reset will not change this field. 7036215976Sjmallett NOTE: This must be at least 500 dclks */ 7037232812Sjmallett uint64_t soft_rst_dly : 16; /**< A soft reset immediately causes an early soft 7038215976Sjmallett reset notification. However, the assertion of 7039232812Sjmallett soft reset will be delayed this many sclks. 7040215976Sjmallett A warm/soft reset will not change this field. 7041215976Sjmallett NOTE: This must be at least 500 dclks */ 7042215976Sjmallett#else 7043232812Sjmallett uint64_t soft_rst_dly : 16; 7044215976Sjmallett uint64_t warm_rst_dly : 16; 7045215976Sjmallett uint64_t reserved_32_63 : 32; 7046215976Sjmallett#endif 7047215976Sjmallett } s; 7048232812Sjmallett struct cvmx_mio_rst_delay_s cn61xx; 7049215976Sjmallett struct cvmx_mio_rst_delay_s cn63xx; 7050215976Sjmallett struct cvmx_mio_rst_delay_s cn63xxp1; 7051232812Sjmallett struct cvmx_mio_rst_delay_s cn66xx; 7052232812Sjmallett struct cvmx_mio_rst_delay_s cn68xx; 7053232812Sjmallett struct cvmx_mio_rst_delay_s cn68xxp1; 7054232812Sjmallett struct cvmx_mio_rst_delay_s cnf71xx; 7055215976Sjmallett}; 7056215976Sjmalletttypedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t; 7057215976Sjmallett 7058215976Sjmallett/** 7059215976Sjmallett * cvmx_mio_rst_int 7060215976Sjmallett * 7061215976Sjmallett * MIO_RST_INT = MIO Reset Interrupt Register 7062215976Sjmallett * 7063215976Sjmallett */ 7064232812Sjmallettunion cvmx_mio_rst_int { 7065215976Sjmallett uint64_t u64; 7066232812Sjmallett struct cvmx_mio_rst_int_s { 7067232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7068215976Sjmallett uint64_t reserved_10_63 : 54; 7069215976Sjmallett uint64_t perst1 : 1; /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1 7070215976Sjmallett and MIO_RST_CTL1[RST_CHIP]=0 */ 7071215976Sjmallett uint64_t perst0 : 1; /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1 7072215976Sjmallett and MIO_RST_CTL0[RST_CHIP]=0 */ 7073232812Sjmallett uint64_t reserved_4_7 : 4; 7074232812Sjmallett uint64_t rst_link3 : 1; /**< A controller3 link-down/hot-reset occurred while 7075232812Sjmallett MIO_RST_CNTL3[RST_LINK]=0. Software must assert 7076232812Sjmallett then de-assert CIU_SOFT_PRST3[SOFT_PRST] */ 7077232812Sjmallett uint64_t rst_link2 : 1; /**< A controller2 link-down/hot-reset occurred while 7078232812Sjmallett MIO_RST_CNTL2[RST_LINK]=0. Software must assert 7079232812Sjmallett then de-assert CIU_SOFT_PRST2[SOFT_PRST] */ 7080232812Sjmallett uint64_t rst_link1 : 1; /**< A controller1 link-down/hot-reset occurred while 7081232812Sjmallett MIO_RST_CTL1[RST_LINK]=0. Software must assert 7082232812Sjmallett then de-assert CIU_SOFT_PRST1[SOFT_PRST] */ 7083232812Sjmallett uint64_t rst_link0 : 1; /**< A controller0 link-down/hot-reset occurred while 7084232812Sjmallett MIO_RST_CTL0[RST_LINK]=0. Software must assert 7085232812Sjmallett then de-assert CIU_SOFT_PRST[SOFT_PRST] */ 7086232812Sjmallett#else 7087232812Sjmallett uint64_t rst_link0 : 1; 7088232812Sjmallett uint64_t rst_link1 : 1; 7089232812Sjmallett uint64_t rst_link2 : 1; 7090232812Sjmallett uint64_t rst_link3 : 1; 7091232812Sjmallett uint64_t reserved_4_7 : 4; 7092232812Sjmallett uint64_t perst0 : 1; 7093232812Sjmallett uint64_t perst1 : 1; 7094232812Sjmallett uint64_t reserved_10_63 : 54; 7095232812Sjmallett#endif 7096232812Sjmallett } s; 7097232812Sjmallett struct cvmx_mio_rst_int_cn61xx { 7098232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7099232812Sjmallett uint64_t reserved_10_63 : 54; 7100232812Sjmallett uint64_t perst1 : 1; /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1 7101232812Sjmallett and MIO_RST_CTL1[RST_CHIP]=0 */ 7102232812Sjmallett uint64_t perst0 : 1; /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1 7103232812Sjmallett and MIO_RST_CTL0[RST_CHIP]=0 */ 7104215976Sjmallett uint64_t reserved_2_7 : 6; 7105215976Sjmallett uint64_t rst_link1 : 1; /**< A controller1 link-down/hot-reset occurred while 7106215976Sjmallett MIO_RST_CTL1[RST_LINK]=0. Software must assert 7107215976Sjmallett then de-assert CIU_SOFT_PRST1[SOFT_PRST] */ 7108215976Sjmallett uint64_t rst_link0 : 1; /**< A controller0 link-down/hot-reset occurred while 7109215976Sjmallett MIO_RST_CTL0[RST_LINK]=0. Software must assert 7110215976Sjmallett then de-assert CIU_SOFT_PRST[SOFT_PRST] */ 7111215976Sjmallett#else 7112215976Sjmallett uint64_t rst_link0 : 1; 7113215976Sjmallett uint64_t rst_link1 : 1; 7114215976Sjmallett uint64_t reserved_2_7 : 6; 7115215976Sjmallett uint64_t perst0 : 1; 7116215976Sjmallett uint64_t perst1 : 1; 7117215976Sjmallett uint64_t reserved_10_63 : 54; 7118215976Sjmallett#endif 7119232812Sjmallett } cn61xx; 7120232812Sjmallett struct cvmx_mio_rst_int_cn61xx cn63xx; 7121232812Sjmallett struct cvmx_mio_rst_int_cn61xx cn63xxp1; 7122232812Sjmallett struct cvmx_mio_rst_int_s cn66xx; 7123232812Sjmallett struct cvmx_mio_rst_int_cn61xx cn68xx; 7124232812Sjmallett struct cvmx_mio_rst_int_cn61xx cn68xxp1; 7125232812Sjmallett struct cvmx_mio_rst_int_cn61xx cnf71xx; 7126215976Sjmallett}; 7127215976Sjmalletttypedef union cvmx_mio_rst_int cvmx_mio_rst_int_t; 7128215976Sjmallett 7129215976Sjmallett/** 7130215976Sjmallett * cvmx_mio_rst_int_en 7131215976Sjmallett * 7132215976Sjmallett * MIO_RST_INT_EN = MIO Reset Interrupt Enable Register 7133215976Sjmallett * 7134215976Sjmallett */ 7135232812Sjmallettunion cvmx_mio_rst_int_en { 7136215976Sjmallett uint64_t u64; 7137232812Sjmallett struct cvmx_mio_rst_int_en_s { 7138232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7139215976Sjmallett uint64_t reserved_10_63 : 54; 7140215976Sjmallett uint64_t perst1 : 1; /**< Controller1 PERST reset interrupt enable */ 7141215976Sjmallett uint64_t perst0 : 1; /**< Controller0 PERST reset interrupt enable */ 7142232812Sjmallett uint64_t reserved_4_7 : 4; 7143232812Sjmallett uint64_t rst_link3 : 1; /**< Controller3 link-down/hot reset interrupt enable */ 7144232812Sjmallett uint64_t rst_link2 : 1; /**< Controller2 link-down/hot reset interrupt enable */ 7145232812Sjmallett uint64_t rst_link1 : 1; /**< Controller1 link-down/hot reset interrupt enable */ 7146232812Sjmallett uint64_t rst_link0 : 1; /**< Controller0 link-down/hot reset interrupt enable */ 7147232812Sjmallett#else 7148232812Sjmallett uint64_t rst_link0 : 1; 7149232812Sjmallett uint64_t rst_link1 : 1; 7150232812Sjmallett uint64_t rst_link2 : 1; 7151232812Sjmallett uint64_t rst_link3 : 1; 7152232812Sjmallett uint64_t reserved_4_7 : 4; 7153232812Sjmallett uint64_t perst0 : 1; 7154232812Sjmallett uint64_t perst1 : 1; 7155232812Sjmallett uint64_t reserved_10_63 : 54; 7156232812Sjmallett#endif 7157232812Sjmallett } s; 7158232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx { 7159232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7160232812Sjmallett uint64_t reserved_10_63 : 54; 7161232812Sjmallett uint64_t perst1 : 1; /**< Controller1 PERST reset interrupt enable */ 7162232812Sjmallett uint64_t perst0 : 1; /**< Controller0 PERST reset interrupt enable */ 7163215976Sjmallett uint64_t reserved_2_7 : 6; 7164215976Sjmallett uint64_t rst_link1 : 1; /**< Controller1 link-down/hot reset interrupt enable */ 7165215976Sjmallett uint64_t rst_link0 : 1; /**< Controller0 link-down/hot reset interrupt enable */ 7166215976Sjmallett#else 7167215976Sjmallett uint64_t rst_link0 : 1; 7168215976Sjmallett uint64_t rst_link1 : 1; 7169215976Sjmallett uint64_t reserved_2_7 : 6; 7170215976Sjmallett uint64_t perst0 : 1; 7171215976Sjmallett uint64_t perst1 : 1; 7172215976Sjmallett uint64_t reserved_10_63 : 54; 7173215976Sjmallett#endif 7174232812Sjmallett } cn61xx; 7175232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx cn63xx; 7176232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; 7177232812Sjmallett struct cvmx_mio_rst_int_en_s cn66xx; 7178232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx cn68xx; 7179232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; 7180232812Sjmallett struct cvmx_mio_rst_int_en_cn61xx cnf71xx; 7181215976Sjmallett}; 7182215976Sjmalletttypedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t; 7183215976Sjmallett 7184215976Sjmallett/** 7185215976Sjmallett * cvmx_mio_tws#_int 7186215976Sjmallett * 7187215976Sjmallett * MIO_TWSX_INT = TWSX Interrupt Register 7188215976Sjmallett * 7189215976Sjmallett * This register contains the TWSI interrupt enable mask and the interrupt source bits. Note: the 7190215976Sjmallett * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence 7191215976Sjmallett * must be written to the TWSI core to clear this interrupt. The other interrupt source bits are write- 7192215976Sjmallett * one-to-clear. TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written 7193215976Sjmallett * by a TWSI device). ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above 7194215976Sjmallett * for reasons). 7195215976Sjmallett * 7196215976Sjmallett * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored. 7197215976Sjmallett * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT / 7198215976Sjmallett * TS_INT should be ignored. 7199215976Sjmallett * 7200215976Sjmallett * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to 7201215976Sjmallett * override the current state of the TWSI bus (SCL_OVR and SDA_OVR). Setting an override bit high will 7202215976Sjmallett * result in the open drain driver being activated, thus driving the corresponding signal low. 7203215976Sjmallett */ 7204232812Sjmallettunion cvmx_mio_twsx_int { 7205215976Sjmallett uint64_t u64; 7206232812Sjmallett struct cvmx_mio_twsx_int_s { 7207232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7208215976Sjmallett uint64_t reserved_12_63 : 52; 7209215976Sjmallett uint64_t scl : 1; /**< SCL */ 7210215976Sjmallett uint64_t sda : 1; /**< SDA */ 7211215976Sjmallett uint64_t scl_ovr : 1; /**< SCL override */ 7212215976Sjmallett uint64_t sda_ovr : 1; /**< SDA override */ 7213215976Sjmallett uint64_t reserved_7_7 : 1; 7214215976Sjmallett uint64_t core_en : 1; /**< TWSI core interrupt enable */ 7215215976Sjmallett uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */ 7216215976Sjmallett uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */ 7217215976Sjmallett uint64_t reserved_3_3 : 1; 7218215976Sjmallett uint64_t core_int : 1; /**< TWSI core interrupt */ 7219215976Sjmallett uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */ 7220215976Sjmallett uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */ 7221215976Sjmallett#else 7222215976Sjmallett uint64_t st_int : 1; 7223215976Sjmallett uint64_t ts_int : 1; 7224215976Sjmallett uint64_t core_int : 1; 7225215976Sjmallett uint64_t reserved_3_3 : 1; 7226215976Sjmallett uint64_t st_en : 1; 7227215976Sjmallett uint64_t ts_en : 1; 7228215976Sjmallett uint64_t core_en : 1; 7229215976Sjmallett uint64_t reserved_7_7 : 1; 7230215976Sjmallett uint64_t sda_ovr : 1; 7231215976Sjmallett uint64_t scl_ovr : 1; 7232215976Sjmallett uint64_t sda : 1; 7233215976Sjmallett uint64_t scl : 1; 7234215976Sjmallett uint64_t reserved_12_63 : 52; 7235215976Sjmallett#endif 7236215976Sjmallett } s; 7237215976Sjmallett struct cvmx_mio_twsx_int_s cn30xx; 7238215976Sjmallett struct cvmx_mio_twsx_int_s cn31xx; 7239215976Sjmallett struct cvmx_mio_twsx_int_s cn38xx; 7240232812Sjmallett struct cvmx_mio_twsx_int_cn38xxp2 { 7241232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7242215976Sjmallett uint64_t reserved_7_63 : 57; 7243215976Sjmallett uint64_t core_en : 1; /**< TWSI core interrupt enable */ 7244215976Sjmallett uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */ 7245215976Sjmallett uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */ 7246215976Sjmallett uint64_t reserved_3_3 : 1; 7247215976Sjmallett uint64_t core_int : 1; /**< TWSI core interrupt */ 7248215976Sjmallett uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */ 7249215976Sjmallett uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */ 7250215976Sjmallett#else 7251215976Sjmallett uint64_t st_int : 1; 7252215976Sjmallett uint64_t ts_int : 1; 7253215976Sjmallett uint64_t core_int : 1; 7254215976Sjmallett uint64_t reserved_3_3 : 1; 7255215976Sjmallett uint64_t st_en : 1; 7256215976Sjmallett uint64_t ts_en : 1; 7257215976Sjmallett uint64_t core_en : 1; 7258215976Sjmallett uint64_t reserved_7_63 : 57; 7259215976Sjmallett#endif 7260215976Sjmallett } cn38xxp2; 7261215976Sjmallett struct cvmx_mio_twsx_int_s cn50xx; 7262215976Sjmallett struct cvmx_mio_twsx_int_s cn52xx; 7263215976Sjmallett struct cvmx_mio_twsx_int_s cn52xxp1; 7264215976Sjmallett struct cvmx_mio_twsx_int_s cn56xx; 7265215976Sjmallett struct cvmx_mio_twsx_int_s cn56xxp1; 7266215976Sjmallett struct cvmx_mio_twsx_int_s cn58xx; 7267215976Sjmallett struct cvmx_mio_twsx_int_s cn58xxp1; 7268232812Sjmallett struct cvmx_mio_twsx_int_s cn61xx; 7269215976Sjmallett struct cvmx_mio_twsx_int_s cn63xx; 7270215976Sjmallett struct cvmx_mio_twsx_int_s cn63xxp1; 7271232812Sjmallett struct cvmx_mio_twsx_int_s cn66xx; 7272232812Sjmallett struct cvmx_mio_twsx_int_s cn68xx; 7273232812Sjmallett struct cvmx_mio_twsx_int_s cn68xxp1; 7274232812Sjmallett struct cvmx_mio_twsx_int_s cnf71xx; 7275215976Sjmallett}; 7276215976Sjmalletttypedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t; 7277215976Sjmallett 7278215976Sjmallett/** 7279215976Sjmallett * cvmx_mio_tws#_sw_twsi 7280215976Sjmallett * 7281215976Sjmallett * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register 7282215976Sjmallett * 7283215976Sjmallett * This register allows software to 7284215976Sjmallett * - initiate TWSI interface master-mode operations with a write and read the result with a read 7285215976Sjmallett * - load four bytes for later retrieval (slave mode) with a write and check validity with a read 7286215976Sjmallett * - launch a TWSI controller configuration read/write with a write and read the result with a read 7287215976Sjmallett * 7288215976Sjmallett * This register should be read or written by software, and read by the TWSI device. The TWSI device can 7289215976Sjmallett * use either two-byte or five-byte reads to reference this register. 7290215976Sjmallett * 7291215976Sjmallett * The TWSI device considers this register valid when V==1 and SLONLY==1. 7292215976Sjmallett */ 7293232812Sjmallettunion cvmx_mio_twsx_sw_twsi { 7294215976Sjmallett uint64_t u64; 7295232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s { 7296232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7297215976Sjmallett uint64_t v : 1; /**< Valid bit 7298215976Sjmallett - Set on a write (should always be written with 7299215976Sjmallett a 1) 7300215976Sjmallett - Cleared when a TWSI master mode op completes 7301215976Sjmallett - Cleared when a TWSI configuration register 7302215976Sjmallett access completes 7303215976Sjmallett - Cleared when the TWSI device reads the 7304215976Sjmallett register if SLONLY==1 */ 7305215976Sjmallett uint64_t slonly : 1; /**< Slave Only Mode 7306215976Sjmallett - No operation is initiated with a write when 7307215976Sjmallett this bit is set - only D field is updated in 7308215976Sjmallett this case 7309215976Sjmallett - When clear, a write initiates either a TWSI 7310215976Sjmallett master-mode operation or a TWSI configuration 7311215976Sjmallett register access */ 7312215976Sjmallett uint64_t eia : 1; /**< Extended Internal Address - send additional 7313215976Sjmallett internal address byte (MSB of IA is from IA field 7314215976Sjmallett of MIO_TWS_SW_TWSI_EXT) */ 7315215976Sjmallett uint64_t op : 4; /**< Opcode field - When the register is written with 7316215976Sjmallett SLONLY==0, initiate a read or write: 7317215976Sjmallett 0000 => 7-bit Byte Master Mode TWSI Op 7318215976Sjmallett 0001 => 7-bit Byte Combined Read Master Mode Op 7319215976Sjmallett 7-bit Byte Write w/ IA Master Mode Op 7320215976Sjmallett 0010 => 10-bit Byte Master Mode TWSI Op 7321215976Sjmallett 0011 => 10-bit Byte Combined Read Master Mode Op 7322215976Sjmallett 10-bit Byte Write w/ IA Master Mode Op 7323215976Sjmallett 0100 => TWSI Master Clock Register 7324215976Sjmallett 0110 => See EOP field 7325215976Sjmallett 1000 => 7-bit 4-byte Master Mode TWSI Op 7326215976Sjmallett 1001 => 7-bit 4-byte Comb. Read Master Mode Op 7327215976Sjmallett 7-bit 4-byte Write w/ IA Master Mode Op 7328215976Sjmallett 1010 => 10-bit 4-byte Master Mode TWSI Op 7329215976Sjmallett 1011 => 10-bit 4-byte Comb. Read Master Mode Op 7330215976Sjmallett 10-bit 4-byte Write w/ IA Master Mode Op */ 7331215976Sjmallett uint64_t r : 1; /**< Read bit or result 7332215976Sjmallett - If set on a write when SLONLY==0, the 7333215976Sjmallett operation is a read 7334215976Sjmallett - On a read, this bit returns the result 7335215976Sjmallett indication for the most recent master mode 7336215976Sjmallett operation (1 = success, 0 = fail) */ 7337215976Sjmallett uint64_t sovr : 1; /**< Size Override - if set, use the SIZE field to 7338215976Sjmallett determine Master Mode Op size rather than what 7339215976Sjmallett the Opcode field specifies. For operations 7340215976Sjmallett greater than 4 bytes, the additional data will be 7341215976Sjmallett contained in the D field of MIO_TWS_SW_TWSI_EXT */ 7342215976Sjmallett uint64_t size : 3; /**< Size in bytes of Master Mode Op if the Size 7343215976Sjmallett Override bit is set. Specified in -1 notation 7344215976Sjmallett (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes) */ 7345215976Sjmallett uint64_t scr : 2; /**< Scratch - unused, but retain state */ 7346215976Sjmallett uint64_t a : 10; /**< Address field 7347215976Sjmallett - the address of the remote device for a master 7348215976Sjmallett mode operation 7349215976Sjmallett - A<9:7> are only used for 10-bit addressing 7350215976Sjmallett Note that when mastering a 7-bit OP, A<6:0> should 7351215976Sjmallett not take any of the values 0x78, 0x79, 0x7A nor 7352215976Sjmallett 0x7B (these 7-bit addresses are reserved to 7353215976Sjmallett extend to 10-bit addressing). */ 7354215976Sjmallett uint64_t ia : 5; /**< Internal Address - Used when launching a master 7355215976Sjmallett mode combined read / write with internal address 7356215976Sjmallett (lower 3 bits are contained in the EOP_IA field) */ 7357215976Sjmallett uint64_t eop_ia : 3; /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0): 7358215976Sjmallett 000 => TWSI Slave Address Register 7359215976Sjmallett 001 => TWSI Data Register 7360215976Sjmallett 010 => TWSI Control Register 7361215976Sjmallett 011 => TWSI Clock Control Register (when R == 0) 7362215976Sjmallett 011 => TWSI Status Register (when R == 1) 7363215976Sjmallett 100 => TWSI Extended Slave Register 7364215976Sjmallett 111 => TWSI Soft Reset Register 7365215976Sjmallett Also the lower 3 bits of Internal Address when 7366215976Sjmallett launching a master mode combined read / write 7367215976Sjmallett with internal address */ 7368215976Sjmallett uint64_t d : 32; /**< Data Field 7369215976Sjmallett Used on a write when 7370215976Sjmallett - initiating a master-mode write (SLONLY==0) 7371215976Sjmallett - writing a TWSI config register (SLONLY==0) 7372215976Sjmallett - a slave mode write (SLONLY==1) 7373215976Sjmallett The read value is updated by 7374215976Sjmallett - a write to this register 7375215976Sjmallett - master mode completion (contains result or 7376215976Sjmallett error code) 7377215976Sjmallett - TWSI config register read (contains result) */ 7378215976Sjmallett#else 7379215976Sjmallett uint64_t d : 32; 7380215976Sjmallett uint64_t eop_ia : 3; 7381215976Sjmallett uint64_t ia : 5; 7382215976Sjmallett uint64_t a : 10; 7383215976Sjmallett uint64_t scr : 2; 7384215976Sjmallett uint64_t size : 3; 7385215976Sjmallett uint64_t sovr : 1; 7386215976Sjmallett uint64_t r : 1; 7387215976Sjmallett uint64_t op : 4; 7388215976Sjmallett uint64_t eia : 1; 7389215976Sjmallett uint64_t slonly : 1; 7390215976Sjmallett uint64_t v : 1; 7391215976Sjmallett#endif 7392215976Sjmallett } s; 7393215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn30xx; 7394215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn31xx; 7395215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn38xx; 7396215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; 7397215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn50xx; 7398215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn52xx; 7399215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; 7400215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn56xx; 7401215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 7402215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn58xx; 7403215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 7404232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn61xx; 7405215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn63xx; 7406215976Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 7407232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn66xx; 7408232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn68xx; 7409232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; 7410232812Sjmallett struct cvmx_mio_twsx_sw_twsi_s cnf71xx; 7411215976Sjmallett}; 7412215976Sjmalletttypedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t; 7413215976Sjmallett 7414215976Sjmallett/** 7415215976Sjmallett * cvmx_mio_tws#_sw_twsi_ext 7416215976Sjmallett * 7417215976Sjmallett * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register 7418215976Sjmallett * 7419215976Sjmallett * This register contains an additional byte of internal address and 4 additional bytes of data to be 7420215976Sjmallett * used with TWSI master mode operations. IA will be sent as the first byte of internal address when 7421215976Sjmallett * performing master mode combined read / write with internal address operations and the EIA bit of 7422215976Sjmallett * MIO_TWS_SW_TWSI is set. D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR 7423215976Sjmallett * must be set to perform operations greater than 4 bytes). 7424215976Sjmallett */ 7425232812Sjmallettunion cvmx_mio_twsx_sw_twsi_ext { 7426215976Sjmallett uint64_t u64; 7427232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s { 7428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7429215976Sjmallett uint64_t reserved_40_63 : 24; 7430215976Sjmallett uint64_t ia : 8; /**< Extended Internal Address */ 7431215976Sjmallett uint64_t d : 32; /**< Extended Data Field */ 7432215976Sjmallett#else 7433215976Sjmallett uint64_t d : 32; 7434215976Sjmallett uint64_t ia : 8; 7435215976Sjmallett uint64_t reserved_40_63 : 24; 7436215976Sjmallett#endif 7437215976Sjmallett } s; 7438215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; 7439215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; 7440215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; 7441215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; 7442215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; 7443215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; 7444215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; 7445215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; 7446215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 7447215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 7448215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 7449232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx; 7450215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 7451215976Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 7452232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; 7453232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; 7454232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; 7455232812Sjmallett struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; 7456215976Sjmallett}; 7457215976Sjmalletttypedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t; 7458215976Sjmallett 7459215976Sjmallett/** 7460215976Sjmallett * cvmx_mio_tws#_twsi_sw 7461215976Sjmallett * 7462215976Sjmallett * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register 7463215976Sjmallett * 7464215976Sjmallett * This register allows the TWSI device to transfer data to software and later check that software has 7465215976Sjmallett * received the information. 7466215976Sjmallett * 7467215976Sjmallett * This register should be read or written by the TWSI device, and read by software. The TWSI device can 7468215976Sjmallett * use one-byte or four-byte payload writes, and two-byte payload reads. 7469215976Sjmallett * 7470215976Sjmallett * The TWSI device considers this register valid when V==1. 7471215976Sjmallett */ 7472232812Sjmallettunion cvmx_mio_twsx_twsi_sw { 7473215976Sjmallett uint64_t u64; 7474232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s { 7475232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7476215976Sjmallett uint64_t v : 2; /**< Valid Bits 7477215976Sjmallett - Not directly writable 7478215976Sjmallett - Set to 1 on any write by the TWSI device 7479215976Sjmallett - Cleared on any read by software */ 7480215976Sjmallett uint64_t reserved_32_61 : 30; 7481215976Sjmallett uint64_t d : 32; /**< Data Field - updated on a write by the TWSI device */ 7482215976Sjmallett#else 7483215976Sjmallett uint64_t d : 32; 7484215976Sjmallett uint64_t reserved_32_61 : 30; 7485215976Sjmallett uint64_t v : 2; 7486215976Sjmallett#endif 7487215976Sjmallett } s; 7488215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn30xx; 7489215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn31xx; 7490215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn38xx; 7491215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; 7492215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn50xx; 7493215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn52xx; 7494215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; 7495215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn56xx; 7496215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 7497215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn58xx; 7498215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 7499232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn61xx; 7500215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn63xx; 7501215976Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 7502232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn66xx; 7503232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn68xx; 7504232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; 7505232812Sjmallett struct cvmx_mio_twsx_twsi_sw_s cnf71xx; 7506215976Sjmallett}; 7507215976Sjmalletttypedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t; 7508215976Sjmallett 7509215976Sjmallett/** 7510215976Sjmallett * cvmx_mio_uart#_dlh 7511215976Sjmallett * 7512215976Sjmallett * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register 7513215976Sjmallett * 7514215976Sjmallett * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a 7515215976Sjmallett * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is 7516215976Sjmallett * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud 7517215976Sjmallett * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as 7518215976Sjmallett * follows: baud rate = eclk / (16 * divisor). 7519215976Sjmallett * 7520215976Sjmallett * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this 7521215976Sjmallett * register. BUSY bit is always clear in PASS3. 7522215976Sjmallett * 7523215976Sjmallett * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled 7524215976Sjmallett * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles 7525215976Sjmallett * of eclk should be allowed to pass before transmitting or receiving data. 7526215976Sjmallett * 7527215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7528215976Sjmallett * IER and DLH registers are the same. 7529215976Sjmallett */ 7530232812Sjmallettunion cvmx_mio_uartx_dlh { 7531215976Sjmallett uint64_t u64; 7532232812Sjmallett struct cvmx_mio_uartx_dlh_s { 7533232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7534215976Sjmallett uint64_t reserved_8_63 : 56; 7535215976Sjmallett uint64_t dlh : 8; /**< Divisor Latch High Register */ 7536215976Sjmallett#else 7537215976Sjmallett uint64_t dlh : 8; 7538215976Sjmallett uint64_t reserved_8_63 : 56; 7539215976Sjmallett#endif 7540215976Sjmallett } s; 7541215976Sjmallett struct cvmx_mio_uartx_dlh_s cn30xx; 7542215976Sjmallett struct cvmx_mio_uartx_dlh_s cn31xx; 7543215976Sjmallett struct cvmx_mio_uartx_dlh_s cn38xx; 7544215976Sjmallett struct cvmx_mio_uartx_dlh_s cn38xxp2; 7545215976Sjmallett struct cvmx_mio_uartx_dlh_s cn50xx; 7546215976Sjmallett struct cvmx_mio_uartx_dlh_s cn52xx; 7547215976Sjmallett struct cvmx_mio_uartx_dlh_s cn52xxp1; 7548215976Sjmallett struct cvmx_mio_uartx_dlh_s cn56xx; 7549215976Sjmallett struct cvmx_mio_uartx_dlh_s cn56xxp1; 7550215976Sjmallett struct cvmx_mio_uartx_dlh_s cn58xx; 7551215976Sjmallett struct cvmx_mio_uartx_dlh_s cn58xxp1; 7552232812Sjmallett struct cvmx_mio_uartx_dlh_s cn61xx; 7553215976Sjmallett struct cvmx_mio_uartx_dlh_s cn63xx; 7554215976Sjmallett struct cvmx_mio_uartx_dlh_s cn63xxp1; 7555232812Sjmallett struct cvmx_mio_uartx_dlh_s cn66xx; 7556232812Sjmallett struct cvmx_mio_uartx_dlh_s cn68xx; 7557232812Sjmallett struct cvmx_mio_uartx_dlh_s cn68xxp1; 7558232812Sjmallett struct cvmx_mio_uartx_dlh_s cnf71xx; 7559215976Sjmallett}; 7560215976Sjmalletttypedef union cvmx_mio_uartx_dlh cvmx_mio_uartx_dlh_t; 7561215976Sjmalletttypedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t; 7562215976Sjmallett 7563215976Sjmallett/** 7564215976Sjmallett * cvmx_mio_uart#_dll 7565215976Sjmallett * 7566215976Sjmallett * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register 7567215976Sjmallett * 7568215976Sjmallett * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a 7569215976Sjmallett * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is 7570215976Sjmallett * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud 7571215976Sjmallett * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as 7572215976Sjmallett * follows: baud rate = eclk / (16 * divisor). 7573215976Sjmallett * 7574215976Sjmallett * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this 7575215976Sjmallett * register. BUSY bit is always clear in PASS3. 7576215976Sjmallett * 7577215976Sjmallett * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled 7578215976Sjmallett * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles 7579215976Sjmallett * of eclk should be allowed to pass before transmitting or receiving data. 7580215976Sjmallett * 7581215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7582215976Sjmallett * RBR, THR, and DLL registers are the same. 7583215976Sjmallett */ 7584232812Sjmallettunion cvmx_mio_uartx_dll { 7585215976Sjmallett uint64_t u64; 7586232812Sjmallett struct cvmx_mio_uartx_dll_s { 7587232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7588215976Sjmallett uint64_t reserved_8_63 : 56; 7589215976Sjmallett uint64_t dll : 8; /**< Divisor Latch Low Register */ 7590215976Sjmallett#else 7591215976Sjmallett uint64_t dll : 8; 7592215976Sjmallett uint64_t reserved_8_63 : 56; 7593215976Sjmallett#endif 7594215976Sjmallett } s; 7595215976Sjmallett struct cvmx_mio_uartx_dll_s cn30xx; 7596215976Sjmallett struct cvmx_mio_uartx_dll_s cn31xx; 7597215976Sjmallett struct cvmx_mio_uartx_dll_s cn38xx; 7598215976Sjmallett struct cvmx_mio_uartx_dll_s cn38xxp2; 7599215976Sjmallett struct cvmx_mio_uartx_dll_s cn50xx; 7600215976Sjmallett struct cvmx_mio_uartx_dll_s cn52xx; 7601215976Sjmallett struct cvmx_mio_uartx_dll_s cn52xxp1; 7602215976Sjmallett struct cvmx_mio_uartx_dll_s cn56xx; 7603215976Sjmallett struct cvmx_mio_uartx_dll_s cn56xxp1; 7604215976Sjmallett struct cvmx_mio_uartx_dll_s cn58xx; 7605215976Sjmallett struct cvmx_mio_uartx_dll_s cn58xxp1; 7606232812Sjmallett struct cvmx_mio_uartx_dll_s cn61xx; 7607215976Sjmallett struct cvmx_mio_uartx_dll_s cn63xx; 7608215976Sjmallett struct cvmx_mio_uartx_dll_s cn63xxp1; 7609232812Sjmallett struct cvmx_mio_uartx_dll_s cn66xx; 7610232812Sjmallett struct cvmx_mio_uartx_dll_s cn68xx; 7611232812Sjmallett struct cvmx_mio_uartx_dll_s cn68xxp1; 7612232812Sjmallett struct cvmx_mio_uartx_dll_s cnf71xx; 7613215976Sjmallett}; 7614215976Sjmalletttypedef union cvmx_mio_uartx_dll cvmx_mio_uartx_dll_t; 7615215976Sjmalletttypedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t; 7616215976Sjmallett 7617215976Sjmallett/** 7618215976Sjmallett * cvmx_mio_uart#_far 7619215976Sjmallett * 7620215976Sjmallett * MIO_UARTX_FAR = MIO UARTX FIFO Access Register 7621215976Sjmallett * 7622215976Sjmallett * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive 7623215976Sjmallett * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are 7624215976Sjmallett * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read 7625215976Sjmallett * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the 7626215976Sjmallett * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. 7627215976Sjmallett */ 7628232812Sjmallettunion cvmx_mio_uartx_far { 7629215976Sjmallett uint64_t u64; 7630232812Sjmallett struct cvmx_mio_uartx_far_s { 7631232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7632215976Sjmallett uint64_t reserved_1_63 : 63; 7633215976Sjmallett uint64_t far : 1; /**< FIFO Access Register */ 7634215976Sjmallett#else 7635215976Sjmallett uint64_t far : 1; 7636215976Sjmallett uint64_t reserved_1_63 : 63; 7637215976Sjmallett#endif 7638215976Sjmallett } s; 7639215976Sjmallett struct cvmx_mio_uartx_far_s cn30xx; 7640215976Sjmallett struct cvmx_mio_uartx_far_s cn31xx; 7641215976Sjmallett struct cvmx_mio_uartx_far_s cn38xx; 7642215976Sjmallett struct cvmx_mio_uartx_far_s cn38xxp2; 7643215976Sjmallett struct cvmx_mio_uartx_far_s cn50xx; 7644215976Sjmallett struct cvmx_mio_uartx_far_s cn52xx; 7645215976Sjmallett struct cvmx_mio_uartx_far_s cn52xxp1; 7646215976Sjmallett struct cvmx_mio_uartx_far_s cn56xx; 7647215976Sjmallett struct cvmx_mio_uartx_far_s cn56xxp1; 7648215976Sjmallett struct cvmx_mio_uartx_far_s cn58xx; 7649215976Sjmallett struct cvmx_mio_uartx_far_s cn58xxp1; 7650232812Sjmallett struct cvmx_mio_uartx_far_s cn61xx; 7651215976Sjmallett struct cvmx_mio_uartx_far_s cn63xx; 7652215976Sjmallett struct cvmx_mio_uartx_far_s cn63xxp1; 7653232812Sjmallett struct cvmx_mio_uartx_far_s cn66xx; 7654232812Sjmallett struct cvmx_mio_uartx_far_s cn68xx; 7655232812Sjmallett struct cvmx_mio_uartx_far_s cn68xxp1; 7656232812Sjmallett struct cvmx_mio_uartx_far_s cnf71xx; 7657215976Sjmallett}; 7658215976Sjmalletttypedef union cvmx_mio_uartx_far cvmx_mio_uartx_far_t; 7659215976Sjmalletttypedef cvmx_mio_uartx_far_t cvmx_uart_far_t; 7660215976Sjmallett 7661215976Sjmallett/** 7662215976Sjmallett * cvmx_mio_uart#_fcr 7663215976Sjmallett * 7664215976Sjmallett * MIO_UARTX_FCR = MIO UARTX FIFO Control Register 7665215976Sjmallett * 7666215976Sjmallett * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO 7667215976Sjmallett * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls 7668215976Sjmallett * the THRE Interrupt empty threshold level. 7669215976Sjmallett * 7670215976Sjmallett * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is 7671215976Sjmallett * changed both the TX and RX FIFOs will be reset. 7672215976Sjmallett * 7673215976Sjmallett * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is 7674215976Sjmallett * self-clearing and it is not necessary to clear this bit. 7675215976Sjmallett * 7676215976Sjmallett * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is 7677215976Sjmallett * self-clearing and it is not necessary to clear this bit. 7678215976Sjmallett * 7679215976Sjmallett * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty 7680215976Sjmallett * threshold level at which THRE Interrupts are generated when the mode is active. See the following 7681215976Sjmallett * table for encodings: 7682215976Sjmallett * 7683215976Sjmallett * TX Trigger 7684215976Sjmallett * ---------- 7685215976Sjmallett * 00 = empty FIFO 7686215976Sjmallett * 01 = 2 chars in FIFO 7687215976Sjmallett * 10 = FIFO 1/4 full 7688215976Sjmallett * 11 = FIFO 1/2 full 7689215976Sjmallett * 7690215976Sjmallett * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7 7691215976Sjmallett * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI). 7692215976Sjmallett * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted. 7693215976Sjmallett * See the following table for encodings: 7694215976Sjmallett * 7695215976Sjmallett * RX Trigger 7696215976Sjmallett * ---------- 7697215976Sjmallett * 00 = 1 char in FIFO 7698215976Sjmallett * 01 = FIFO 1/4 full 7699215976Sjmallett * 10 = FIFO 1/2 full 7700215976Sjmallett * 11 = FIFO 2 chars less than full 7701215976Sjmallett * 7702215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7703215976Sjmallett * IIR and FCR registers are the same. 7704215976Sjmallett */ 7705232812Sjmallettunion cvmx_mio_uartx_fcr { 7706215976Sjmallett uint64_t u64; 7707232812Sjmallett struct cvmx_mio_uartx_fcr_s { 7708232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7709215976Sjmallett uint64_t reserved_8_63 : 56; 7710215976Sjmallett uint64_t rxtrig : 2; /**< RX Trigger */ 7711215976Sjmallett uint64_t txtrig : 2; /**< TX Trigger */ 7712215976Sjmallett uint64_t reserved_3_3 : 1; 7713215976Sjmallett uint64_t txfr : 1; /**< TX FIFO reset */ 7714215976Sjmallett uint64_t rxfr : 1; /**< RX FIFO reset */ 7715215976Sjmallett uint64_t en : 1; /**< FIFO enable */ 7716215976Sjmallett#else 7717215976Sjmallett uint64_t en : 1; 7718215976Sjmallett uint64_t rxfr : 1; 7719215976Sjmallett uint64_t txfr : 1; 7720215976Sjmallett uint64_t reserved_3_3 : 1; 7721215976Sjmallett uint64_t txtrig : 2; 7722215976Sjmallett uint64_t rxtrig : 2; 7723215976Sjmallett uint64_t reserved_8_63 : 56; 7724215976Sjmallett#endif 7725215976Sjmallett } s; 7726215976Sjmallett struct cvmx_mio_uartx_fcr_s cn30xx; 7727215976Sjmallett struct cvmx_mio_uartx_fcr_s cn31xx; 7728215976Sjmallett struct cvmx_mio_uartx_fcr_s cn38xx; 7729215976Sjmallett struct cvmx_mio_uartx_fcr_s cn38xxp2; 7730215976Sjmallett struct cvmx_mio_uartx_fcr_s cn50xx; 7731215976Sjmallett struct cvmx_mio_uartx_fcr_s cn52xx; 7732215976Sjmallett struct cvmx_mio_uartx_fcr_s cn52xxp1; 7733215976Sjmallett struct cvmx_mio_uartx_fcr_s cn56xx; 7734215976Sjmallett struct cvmx_mio_uartx_fcr_s cn56xxp1; 7735215976Sjmallett struct cvmx_mio_uartx_fcr_s cn58xx; 7736215976Sjmallett struct cvmx_mio_uartx_fcr_s cn58xxp1; 7737232812Sjmallett struct cvmx_mio_uartx_fcr_s cn61xx; 7738215976Sjmallett struct cvmx_mio_uartx_fcr_s cn63xx; 7739215976Sjmallett struct cvmx_mio_uartx_fcr_s cn63xxp1; 7740232812Sjmallett struct cvmx_mio_uartx_fcr_s cn66xx; 7741232812Sjmallett struct cvmx_mio_uartx_fcr_s cn68xx; 7742232812Sjmallett struct cvmx_mio_uartx_fcr_s cn68xxp1; 7743232812Sjmallett struct cvmx_mio_uartx_fcr_s cnf71xx; 7744215976Sjmallett}; 7745215976Sjmalletttypedef union cvmx_mio_uartx_fcr cvmx_mio_uartx_fcr_t; 7746215976Sjmalletttypedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t; 7747215976Sjmallett 7748215976Sjmallett/** 7749215976Sjmallett * cvmx_mio_uart#_htx 7750215976Sjmallett * 7751215976Sjmallett * MIO_UARTX_HTX = MIO UARTX Halt TX Register 7752215976Sjmallett * 7753215976Sjmallett * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be 7754215976Sjmallett * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will 7755215976Sjmallett * have no effect. 7756215976Sjmallett */ 7757232812Sjmallettunion cvmx_mio_uartx_htx { 7758215976Sjmallett uint64_t u64; 7759232812Sjmallett struct cvmx_mio_uartx_htx_s { 7760232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7761215976Sjmallett uint64_t reserved_1_63 : 63; 7762215976Sjmallett uint64_t htx : 1; /**< Halt TX */ 7763215976Sjmallett#else 7764215976Sjmallett uint64_t htx : 1; 7765215976Sjmallett uint64_t reserved_1_63 : 63; 7766215976Sjmallett#endif 7767215976Sjmallett } s; 7768215976Sjmallett struct cvmx_mio_uartx_htx_s cn30xx; 7769215976Sjmallett struct cvmx_mio_uartx_htx_s cn31xx; 7770215976Sjmallett struct cvmx_mio_uartx_htx_s cn38xx; 7771215976Sjmallett struct cvmx_mio_uartx_htx_s cn38xxp2; 7772215976Sjmallett struct cvmx_mio_uartx_htx_s cn50xx; 7773215976Sjmallett struct cvmx_mio_uartx_htx_s cn52xx; 7774215976Sjmallett struct cvmx_mio_uartx_htx_s cn52xxp1; 7775215976Sjmallett struct cvmx_mio_uartx_htx_s cn56xx; 7776215976Sjmallett struct cvmx_mio_uartx_htx_s cn56xxp1; 7777215976Sjmallett struct cvmx_mio_uartx_htx_s cn58xx; 7778215976Sjmallett struct cvmx_mio_uartx_htx_s cn58xxp1; 7779232812Sjmallett struct cvmx_mio_uartx_htx_s cn61xx; 7780215976Sjmallett struct cvmx_mio_uartx_htx_s cn63xx; 7781215976Sjmallett struct cvmx_mio_uartx_htx_s cn63xxp1; 7782232812Sjmallett struct cvmx_mio_uartx_htx_s cn66xx; 7783232812Sjmallett struct cvmx_mio_uartx_htx_s cn68xx; 7784232812Sjmallett struct cvmx_mio_uartx_htx_s cn68xxp1; 7785232812Sjmallett struct cvmx_mio_uartx_htx_s cnf71xx; 7786215976Sjmallett}; 7787215976Sjmalletttypedef union cvmx_mio_uartx_htx cvmx_mio_uartx_htx_t; 7788215976Sjmalletttypedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t; 7789215976Sjmallett 7790215976Sjmallett/** 7791215976Sjmallett * cvmx_mio_uart#_ier 7792215976Sjmallett * 7793215976Sjmallett * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register 7794215976Sjmallett * 7795215976Sjmallett * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable 7796215976Sjmallett * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt 7797215976Sjmallett * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line 7798215976Sjmallett * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI). 7799215976Sjmallett * 7800215976Sjmallett * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode. 7801215976Sjmallett * 7802215976Sjmallett * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 7803215976Sjmallett * this register. 7804215976Sjmallett * 7805215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7806215976Sjmallett * IER and DLH registers are the same. 7807215976Sjmallett */ 7808232812Sjmallettunion cvmx_mio_uartx_ier { 7809215976Sjmallett uint64_t u64; 7810232812Sjmallett struct cvmx_mio_uartx_ier_s { 7811232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7812215976Sjmallett uint64_t reserved_8_63 : 56; 7813215976Sjmallett uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */ 7814215976Sjmallett uint64_t reserved_4_6 : 3; 7815215976Sjmallett uint64_t edssi : 1; /**< Enable Modem Status Interrupt */ 7816215976Sjmallett uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */ 7817215976Sjmallett uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */ 7818215976Sjmallett uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */ 7819215976Sjmallett#else 7820215976Sjmallett uint64_t erbfi : 1; 7821215976Sjmallett uint64_t etbei : 1; 7822215976Sjmallett uint64_t elsi : 1; 7823215976Sjmallett uint64_t edssi : 1; 7824215976Sjmallett uint64_t reserved_4_6 : 3; 7825215976Sjmallett uint64_t ptime : 1; 7826215976Sjmallett uint64_t reserved_8_63 : 56; 7827215976Sjmallett#endif 7828215976Sjmallett } s; 7829215976Sjmallett struct cvmx_mio_uartx_ier_s cn30xx; 7830215976Sjmallett struct cvmx_mio_uartx_ier_s cn31xx; 7831215976Sjmallett struct cvmx_mio_uartx_ier_s cn38xx; 7832215976Sjmallett struct cvmx_mio_uartx_ier_s cn38xxp2; 7833215976Sjmallett struct cvmx_mio_uartx_ier_s cn50xx; 7834215976Sjmallett struct cvmx_mio_uartx_ier_s cn52xx; 7835215976Sjmallett struct cvmx_mio_uartx_ier_s cn52xxp1; 7836215976Sjmallett struct cvmx_mio_uartx_ier_s cn56xx; 7837215976Sjmallett struct cvmx_mio_uartx_ier_s cn56xxp1; 7838215976Sjmallett struct cvmx_mio_uartx_ier_s cn58xx; 7839215976Sjmallett struct cvmx_mio_uartx_ier_s cn58xxp1; 7840232812Sjmallett struct cvmx_mio_uartx_ier_s cn61xx; 7841215976Sjmallett struct cvmx_mio_uartx_ier_s cn63xx; 7842215976Sjmallett struct cvmx_mio_uartx_ier_s cn63xxp1; 7843232812Sjmallett struct cvmx_mio_uartx_ier_s cn66xx; 7844232812Sjmallett struct cvmx_mio_uartx_ier_s cn68xx; 7845232812Sjmallett struct cvmx_mio_uartx_ier_s cn68xxp1; 7846232812Sjmallett struct cvmx_mio_uartx_ier_s cnf71xx; 7847215976Sjmallett}; 7848215976Sjmalletttypedef union cvmx_mio_uartx_ier cvmx_mio_uartx_ier_t; 7849215976Sjmalletttypedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t; 7850215976Sjmallett 7851215976Sjmallett/** 7852215976Sjmallett * cvmx_mio_uart#_iir 7853215976Sjmallett * 7854215976Sjmallett * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register 7855215976Sjmallett * 7856215976Sjmallett * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an 7857215976Sjmallett * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs 7858215976Sjmallett * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending 7859215976Sjmallett * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt 7860215976Sjmallett * reset control: 7861215976Sjmallett * 7862215976Sjmallett * Interrupt Priority Interrupt Interrupt Interrupt 7863215976Sjmallett * ID Level Type Source Reset By 7864215976Sjmallett * --------------------------------------------------------------------------------------------------------------------------------- 7865215976Sjmallett * 0001 - None None - 7866215976Sjmallett * 7867215976Sjmallett * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register 7868215976Sjmallett * Status interrupt 7869215976Sjmallett * 7870215976Sjmallett * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register 7871215976Sjmallett * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below 7872215976Sjmallett * enabled) the trigger level (FIFOs enabled) 7873215976Sjmallett * 7874215976Sjmallett * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register 7875215976Sjmallett * Timeout during the last 4 character times and there 7876215976Sjmallett * Indication is at least 1 character in it during this 7877215976Sjmallett * time 7878215976Sjmallett * 7879215976Sjmallett * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register 7880215976Sjmallett * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into 7881215976Sjmallett * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX 7882215976Sjmallett * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE 7883215976Sjmallett * Mode enabled) 7884215976Sjmallett * 7885215976Sjmallett * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register 7886215976Sjmallett * Changed or Ring Indicator (RI) or Data Carrier 7887215976Sjmallett * Detect (DCD) changed (note: if auto flow 7888215976Sjmallett * control mode is enabled, a change in CTS 7889215976Sjmallett * will not cause an interrupt) 7890215976Sjmallett * 7891215976Sjmallett * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register 7892215976Sjmallett * Indication Control Register while the BUSY bit of the 7893215976Sjmallett * UART Status Register was set 7894215976Sjmallett * 7895215976Sjmallett * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert. 7896215976Sjmallett * 7897215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7898215976Sjmallett * IIR and FCR registers are the same. 7899215976Sjmallett */ 7900232812Sjmallettunion cvmx_mio_uartx_iir { 7901215976Sjmallett uint64_t u64; 7902232812Sjmallett struct cvmx_mio_uartx_iir_s { 7903232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7904215976Sjmallett uint64_t reserved_8_63 : 56; 7905215976Sjmallett uint64_t fen : 2; /**< FIFO-enabled bits */ 7906215976Sjmallett uint64_t reserved_4_5 : 2; 7907215976Sjmallett cvmx_uart_iid_t iid : 4; /**< Interrupt ID */ 7908215976Sjmallett#else 7909215976Sjmallett cvmx_uart_iid_t iid : 4; 7910215976Sjmallett uint64_t reserved_4_5 : 2; 7911215976Sjmallett uint64_t fen : 2; 7912215976Sjmallett uint64_t reserved_8_63 : 56; 7913215976Sjmallett#endif 7914215976Sjmallett } s; 7915215976Sjmallett struct cvmx_mio_uartx_iir_s cn30xx; 7916215976Sjmallett struct cvmx_mio_uartx_iir_s cn31xx; 7917215976Sjmallett struct cvmx_mio_uartx_iir_s cn38xx; 7918215976Sjmallett struct cvmx_mio_uartx_iir_s cn38xxp2; 7919215976Sjmallett struct cvmx_mio_uartx_iir_s cn50xx; 7920215976Sjmallett struct cvmx_mio_uartx_iir_s cn52xx; 7921215976Sjmallett struct cvmx_mio_uartx_iir_s cn52xxp1; 7922215976Sjmallett struct cvmx_mio_uartx_iir_s cn56xx; 7923215976Sjmallett struct cvmx_mio_uartx_iir_s cn56xxp1; 7924215976Sjmallett struct cvmx_mio_uartx_iir_s cn58xx; 7925215976Sjmallett struct cvmx_mio_uartx_iir_s cn58xxp1; 7926232812Sjmallett struct cvmx_mio_uartx_iir_s cn61xx; 7927215976Sjmallett struct cvmx_mio_uartx_iir_s cn63xx; 7928215976Sjmallett struct cvmx_mio_uartx_iir_s cn63xxp1; 7929232812Sjmallett struct cvmx_mio_uartx_iir_s cn66xx; 7930232812Sjmallett struct cvmx_mio_uartx_iir_s cn68xx; 7931232812Sjmallett struct cvmx_mio_uartx_iir_s cn68xxp1; 7932232812Sjmallett struct cvmx_mio_uartx_iir_s cnf71xx; 7933215976Sjmallett}; 7934215976Sjmalletttypedef union cvmx_mio_uartx_iir cvmx_mio_uartx_iir_t; 7935215976Sjmalletttypedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t; 7936215976Sjmallett 7937215976Sjmallett/** 7938215976Sjmallett * cvmx_mio_uart#_lcr 7939215976Sjmallett * 7940215976Sjmallett * MIO_UARTX_LCR = MIO UARTX Line Control Register 7941215976Sjmallett * 7942215976Sjmallett * The Line Control Register (LCR) controls the format of the data that is transmitted and received by 7943215976Sjmallett * the UART. 7944215976Sjmallett * 7945215976Sjmallett * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of 7946215976Sjmallett * data bits per character that are transmitted and received. See the following table for encodings: 7947215976Sjmallett * 7948215976Sjmallett * CLS 7949215976Sjmallett * --- 7950215976Sjmallett * 00 = 5 bits (bits 0-4 sent) 7951215976Sjmallett * 01 = 6 bits (bits 0-5 sent) 7952215976Sjmallett * 10 = 7 bits (bits 0-6 sent) 7953215976Sjmallett * 11 = 8 bits (all bits sent) 7954215976Sjmallett * 7955215976Sjmallett * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted 7956215976Sjmallett * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are 7957215976Sjmallett * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that 7958215976Sjmallett * regardless of the number of stop bits selected the receiver will only check the first stop bit. 7959215976Sjmallett * 7960215976Sjmallett * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and 7961215976Sjmallett * detection in transmitted and received serial character respectively. 7962215976Sjmallett * 7963215976Sjmallett * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd 7964215976Sjmallett * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd 7965215976Sjmallett * number of ones is transmitted or checked. 7966215976Sjmallett * 7967215976Sjmallett * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout 7968215976Sjmallett * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback 7969215976Sjmallett * mode, the break condition is internally looped back to the receiver. 7970215976Sjmallett * 7971215976Sjmallett * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the 7972215976Sjmallett * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after 7973215976Sjmallett * initial baud rate setup in order to access other registers. 7974215976Sjmallett * 7975215976Sjmallett * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART 7976215976Sjmallett * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable 7977215976Sjmallett * because the BUSY bit is always clear. 7978215976Sjmallett */ 7979232812Sjmallettunion cvmx_mio_uartx_lcr { 7980215976Sjmallett uint64_t u64; 7981232812Sjmallett struct cvmx_mio_uartx_lcr_s { 7982232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7983215976Sjmallett uint64_t reserved_8_63 : 56; 7984215976Sjmallett uint64_t dlab : 1; /**< Divisor Latch Address bit */ 7985215976Sjmallett uint64_t brk : 1; /**< Break Control bit */ 7986215976Sjmallett uint64_t reserved_5_5 : 1; 7987215976Sjmallett uint64_t eps : 1; /**< Even Parity Select bit */ 7988215976Sjmallett uint64_t pen : 1; /**< Parity Enable bit */ 7989215976Sjmallett uint64_t stop : 1; /**< Stop Control bit */ 7990215976Sjmallett cvmx_uart_bits_t cls : 2; /**< Character Length Select */ 7991215976Sjmallett#else 7992215976Sjmallett cvmx_uart_bits_t cls : 2; 7993215976Sjmallett uint64_t stop : 1; 7994215976Sjmallett uint64_t pen : 1; 7995215976Sjmallett uint64_t eps : 1; 7996215976Sjmallett uint64_t reserved_5_5 : 1; 7997215976Sjmallett uint64_t brk : 1; 7998215976Sjmallett uint64_t dlab : 1; 7999215976Sjmallett uint64_t reserved_8_63 : 56; 8000215976Sjmallett#endif 8001215976Sjmallett } s; 8002215976Sjmallett struct cvmx_mio_uartx_lcr_s cn30xx; 8003215976Sjmallett struct cvmx_mio_uartx_lcr_s cn31xx; 8004215976Sjmallett struct cvmx_mio_uartx_lcr_s cn38xx; 8005215976Sjmallett struct cvmx_mio_uartx_lcr_s cn38xxp2; 8006215976Sjmallett struct cvmx_mio_uartx_lcr_s cn50xx; 8007215976Sjmallett struct cvmx_mio_uartx_lcr_s cn52xx; 8008215976Sjmallett struct cvmx_mio_uartx_lcr_s cn52xxp1; 8009215976Sjmallett struct cvmx_mio_uartx_lcr_s cn56xx; 8010215976Sjmallett struct cvmx_mio_uartx_lcr_s cn56xxp1; 8011215976Sjmallett struct cvmx_mio_uartx_lcr_s cn58xx; 8012215976Sjmallett struct cvmx_mio_uartx_lcr_s cn58xxp1; 8013232812Sjmallett struct cvmx_mio_uartx_lcr_s cn61xx; 8014215976Sjmallett struct cvmx_mio_uartx_lcr_s cn63xx; 8015215976Sjmallett struct cvmx_mio_uartx_lcr_s cn63xxp1; 8016232812Sjmallett struct cvmx_mio_uartx_lcr_s cn66xx; 8017232812Sjmallett struct cvmx_mio_uartx_lcr_s cn68xx; 8018232812Sjmallett struct cvmx_mio_uartx_lcr_s cn68xxp1; 8019232812Sjmallett struct cvmx_mio_uartx_lcr_s cnf71xx; 8020215976Sjmallett}; 8021215976Sjmalletttypedef union cvmx_mio_uartx_lcr cvmx_mio_uartx_lcr_t; 8022215976Sjmalletttypedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t; 8023215976Sjmallett 8024215976Sjmallett/** 8025215976Sjmallett * cvmx_mio_uart#_lsr 8026215976Sjmallett * 8027215976Sjmallett * MIO_UARTX_LSR = MIO UARTX Line Status Register 8028215976Sjmallett * 8029215976Sjmallett * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This 8030215976Sjmallett * status can be read by the user at anytime. 8031215976Sjmallett * 8032215976Sjmallett * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one 8033215976Sjmallett * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO 8034215976Sjmallett * mode, or when the receiver FIFO is empty, in FIFO mode. 8035215976Sjmallett * 8036215976Sjmallett * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred 8037215976Sjmallett * because a new data character was received before the previous data was read. In the non-FIFO mode, the 8038215976Sjmallett * OE bit is set when a new character arrives in the receiver before the previous character was read from 8039215976Sjmallett * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error 8040215976Sjmallett * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is 8041215976Sjmallett * retained and the data in the receive shift register is lost. 8042215976Sjmallett * 8043215976Sjmallett * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the 8044215976Sjmallett * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is 8045215976Sjmallett * associated with a character received, it is revealed when the character with the parity error arrives 8046215976Sjmallett * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break 8047215976Sjmallett * interrupt has occurred, as indicated by the Break Interrupt (BI) bit. 8048215976Sjmallett * 8049215976Sjmallett * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the 8050215976Sjmallett * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received 8051215976Sjmallett * data. In the FIFO mode, since the framing error is associated with a character received, it is 8052215976Sjmallett * revealed when the character with the framing error is at the top of the FIFO. When a framing error 8053215976Sjmallett * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start 8054215976Sjmallett * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and 8055215976Sjmallett * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has 8056215976Sjmallett * occurred, as indicated by the Break Interrupt (BI) bit. 8057215976Sjmallett * 8058215976Sjmallett * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed. 8059215976Sjmallett * 8060215976Sjmallett * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in 8061215976Sjmallett * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on 8062215976Sjmallett * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the 8063215976Sjmallett * FIFO mode, the character associated with the break condition is carried through the FIFO and is 8064215976Sjmallett * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non- 8065215976Sjmallett * FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 8066215976Sjmallett * 8067215976Sjmallett * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode 8068215976Sjmallett * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is 8069215976Sjmallett * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no 8070215976Sjmallett * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the 8071215976Sjmallett * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5 8072215976Sjmallett * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE 8073215976Sjmallett * Interrupts, which are then controlled by the FCR[5:4] threshold setting. 8074215976Sjmallett * 8075215976Sjmallett * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the 8076215976Sjmallett * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever 8077215976Sjmallett * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is 8078215976Sjmallett * typically used to make sure it is safe to change control registers. Changing control registers while 8079215976Sjmallett * the transmitter is busy can result in corrupt data being transmitted. 8080215976Sjmallett * 8081215976Sjmallett * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It 8082215976Sjmallett * is set when there is at least one parity error, framing error, or break indication in the FIFO. This 8083215976Sjmallett * bit is cleared when the LSR is read and the character with the error is at the top of the receiver 8084215976Sjmallett * FIFO and there are no subsequent errors in the FIFO. 8085215976Sjmallett */ 8086232812Sjmallettunion cvmx_mio_uartx_lsr { 8087215976Sjmallett uint64_t u64; 8088232812Sjmallett struct cvmx_mio_uartx_lsr_s { 8089232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8090215976Sjmallett uint64_t reserved_8_63 : 56; 8091215976Sjmallett uint64_t ferr : 1; /**< Error in Receiver FIFO bit */ 8092215976Sjmallett uint64_t temt : 1; /**< Transmitter Empty bit */ 8093215976Sjmallett uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */ 8094215976Sjmallett uint64_t bi : 1; /**< Break Interrupt bit */ 8095215976Sjmallett uint64_t fe : 1; /**< Framing Error bit */ 8096215976Sjmallett uint64_t pe : 1; /**< Parity Error bit */ 8097215976Sjmallett uint64_t oe : 1; /**< Overrun Error bit */ 8098215976Sjmallett uint64_t dr : 1; /**< Data Ready bit */ 8099215976Sjmallett#else 8100215976Sjmallett uint64_t dr : 1; 8101215976Sjmallett uint64_t oe : 1; 8102215976Sjmallett uint64_t pe : 1; 8103215976Sjmallett uint64_t fe : 1; 8104215976Sjmallett uint64_t bi : 1; 8105215976Sjmallett uint64_t thre : 1; 8106215976Sjmallett uint64_t temt : 1; 8107215976Sjmallett uint64_t ferr : 1; 8108215976Sjmallett uint64_t reserved_8_63 : 56; 8109215976Sjmallett#endif 8110215976Sjmallett } s; 8111215976Sjmallett struct cvmx_mio_uartx_lsr_s cn30xx; 8112215976Sjmallett struct cvmx_mio_uartx_lsr_s cn31xx; 8113215976Sjmallett struct cvmx_mio_uartx_lsr_s cn38xx; 8114215976Sjmallett struct cvmx_mio_uartx_lsr_s cn38xxp2; 8115215976Sjmallett struct cvmx_mio_uartx_lsr_s cn50xx; 8116215976Sjmallett struct cvmx_mio_uartx_lsr_s cn52xx; 8117215976Sjmallett struct cvmx_mio_uartx_lsr_s cn52xxp1; 8118215976Sjmallett struct cvmx_mio_uartx_lsr_s cn56xx; 8119215976Sjmallett struct cvmx_mio_uartx_lsr_s cn56xxp1; 8120215976Sjmallett struct cvmx_mio_uartx_lsr_s cn58xx; 8121215976Sjmallett struct cvmx_mio_uartx_lsr_s cn58xxp1; 8122232812Sjmallett struct cvmx_mio_uartx_lsr_s cn61xx; 8123215976Sjmallett struct cvmx_mio_uartx_lsr_s cn63xx; 8124215976Sjmallett struct cvmx_mio_uartx_lsr_s cn63xxp1; 8125232812Sjmallett struct cvmx_mio_uartx_lsr_s cn66xx; 8126232812Sjmallett struct cvmx_mio_uartx_lsr_s cn68xx; 8127232812Sjmallett struct cvmx_mio_uartx_lsr_s cn68xxp1; 8128232812Sjmallett struct cvmx_mio_uartx_lsr_s cnf71xx; 8129215976Sjmallett}; 8130215976Sjmalletttypedef union cvmx_mio_uartx_lsr cvmx_mio_uartx_lsr_t; 8131215976Sjmalletttypedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t; 8132215976Sjmallett 8133215976Sjmallett/** 8134215976Sjmallett * cvmx_mio_uart#_mcr 8135215976Sjmallett * 8136215976Sjmallett * MIO_UARTX_MCR = MIO UARTX Modem Control Register 8137215976Sjmallett * 8138215976Sjmallett * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART. 8139215976Sjmallett * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the 8140215976Sjmallett * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n. In loopback mode, these outputs are 8141215976Sjmallett * driven inactive high while the values in these locations are internally looped back to the inputs. 8142215976Sjmallett * 8143215976Sjmallett * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated 8144215976Sjmallett * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The 8145215976Sjmallett * rts_n output will be de-asserted whenever RTS (bit 1) is set low. 8146215976Sjmallett * 8147215976Sjmallett * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1 8148215976Sjmallett * and OUT2 bits still function in Loopback mode. The UART1 dtr_n, out1_n, and out2_n outputs are not 8149215976Sjmallett * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback 8150215976Sjmallett * mode. 8151215976Sjmallett * 8152215976Sjmallett * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output 8153215976Sjmallett * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This 8154215976Sjmallett * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n, 8155215976Sjmallett * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n) 8156215976Sjmallett * are looped back to the inputs, internally. 8157215976Sjmallett * 8158215976Sjmallett * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set, 8159215976Sjmallett * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled. 8160215976Sjmallett * 8161215976Sjmallett * Auto RTS becomes active when the following occurs: 8162215976Sjmallett * 1. MCR bit 1 is set 8163215976Sjmallett * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0 8164215976Sjmallett * 3. MCR bit 5 is set (must be set after FCR bit 0) 8165215976Sjmallett * 8166215976Sjmallett * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the 8167215976Sjmallett * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the 8168215976Sjmallett * other UART stops sending serial data until the receiver FIFO has available space. 8169215976Sjmallett * 8170215976Sjmallett * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one 8171215976Sjmallett * additional character may be transmitted to the UART after rts_n has become inactive (due to data 8172215976Sjmallett * already having entered the transmitter block in the other UART), setting the threshold to 2 less 8173215976Sjmallett * than full allows maximum use of the FIFO with a safety zone of one character. 8174215976Sjmallett * 8175215976Sjmallett * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n 8176215976Sjmallett * again becomes active-low, signalling the other UART to continue sending data. It is important to note 8177215976Sjmallett * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are 8178215976Sjmallett * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive, 8179215976Sjmallett * rts_n is controlled solely by MCR[1]. 8180215976Sjmallett * 8181215976Sjmallett * Auto CTS becomes active when the following occurs: 8182215976Sjmallett * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0 8183215976Sjmallett * 2. MCR bit 5 is set (must be set after FCR bit 0) 8184215976Sjmallett * 8185215976Sjmallett * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This 8186215976Sjmallett * prevents overflowing the FIFO of the receiving UART. 8187215976Sjmallett * 8188215976Sjmallett * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another 8189215976Sjmallett * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the 8190215976Sjmallett * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either 8191215976Sjmallett * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode 8192215976Sjmallett * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO 8193215976Sjmallett * full status, software can poll this before each write to the Transmitter FIFO. 8194215976Sjmallett * 8195215976Sjmallett * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the 8196215976Sjmallett * FIFO may be read through the Transmit FIFO Level (TFL) register. 8197215976Sjmallett * 8198215976Sjmallett * When the cts_n input becomes active-low again, transmission resumes. It is important to note that, 8199215976Sjmallett * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are 8200215976Sjmallett * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by 8201215976Sjmallett * cts_n. 8202215976Sjmallett */ 8203232812Sjmallettunion cvmx_mio_uartx_mcr { 8204215976Sjmallett uint64_t u64; 8205232812Sjmallett struct cvmx_mio_uartx_mcr_s { 8206232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8207215976Sjmallett uint64_t reserved_6_63 : 58; 8208215976Sjmallett uint64_t afce : 1; /**< Auto Flow Control Enable bit */ 8209215976Sjmallett uint64_t loop : 1; /**< Loopback bit */ 8210215976Sjmallett uint64_t out2 : 1; /**< OUT2 output bit */ 8211215976Sjmallett uint64_t out1 : 1; /**< OUT1 output bit */ 8212215976Sjmallett uint64_t rts : 1; /**< Request To Send output bit */ 8213215976Sjmallett uint64_t dtr : 1; /**< Data Terminal Ready output bit */ 8214215976Sjmallett#else 8215215976Sjmallett uint64_t dtr : 1; 8216215976Sjmallett uint64_t rts : 1; 8217215976Sjmallett uint64_t out1 : 1; 8218215976Sjmallett uint64_t out2 : 1; 8219215976Sjmallett uint64_t loop : 1; 8220215976Sjmallett uint64_t afce : 1; 8221215976Sjmallett uint64_t reserved_6_63 : 58; 8222215976Sjmallett#endif 8223215976Sjmallett } s; 8224215976Sjmallett struct cvmx_mio_uartx_mcr_s cn30xx; 8225215976Sjmallett struct cvmx_mio_uartx_mcr_s cn31xx; 8226215976Sjmallett struct cvmx_mio_uartx_mcr_s cn38xx; 8227215976Sjmallett struct cvmx_mio_uartx_mcr_s cn38xxp2; 8228215976Sjmallett struct cvmx_mio_uartx_mcr_s cn50xx; 8229215976Sjmallett struct cvmx_mio_uartx_mcr_s cn52xx; 8230215976Sjmallett struct cvmx_mio_uartx_mcr_s cn52xxp1; 8231215976Sjmallett struct cvmx_mio_uartx_mcr_s cn56xx; 8232215976Sjmallett struct cvmx_mio_uartx_mcr_s cn56xxp1; 8233215976Sjmallett struct cvmx_mio_uartx_mcr_s cn58xx; 8234215976Sjmallett struct cvmx_mio_uartx_mcr_s cn58xxp1; 8235232812Sjmallett struct cvmx_mio_uartx_mcr_s cn61xx; 8236215976Sjmallett struct cvmx_mio_uartx_mcr_s cn63xx; 8237215976Sjmallett struct cvmx_mio_uartx_mcr_s cn63xxp1; 8238232812Sjmallett struct cvmx_mio_uartx_mcr_s cn66xx; 8239232812Sjmallett struct cvmx_mio_uartx_mcr_s cn68xx; 8240232812Sjmallett struct cvmx_mio_uartx_mcr_s cn68xxp1; 8241232812Sjmallett struct cvmx_mio_uartx_mcr_s cnf71xx; 8242215976Sjmallett}; 8243215976Sjmalletttypedef union cvmx_mio_uartx_mcr cvmx_mio_uartx_mcr_t; 8244215976Sjmalletttypedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t; 8245215976Sjmallett 8246215976Sjmallett/** 8247215976Sjmallett * cvmx_mio_uart#_msr 8248215976Sjmallett * 8249215976Sjmallett * MIO_UARTX_MSR = MIO UARTX Modem Status Register 8250215976Sjmallett * 8251215976Sjmallett * The Modem Status Register (MSR) contains the current status of the modem control input lines and if 8252215976Sjmallett * they changed. 8253215976Sjmallett * 8254215976Sjmallett * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n, 8255215976Sjmallett * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n 8256215976Sjmallett * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In 8257215976Sjmallett * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and 8258215976Sjmallett * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state 8259215976Sjmallett * from a high to a low. 8260215976Sjmallett * 8261215976Sjmallett * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software 8262215976Sjmallett * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains 8263215976Sjmallett * asserted. 8264215976Sjmallett * 8265215976Sjmallett * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem 8266215976Sjmallett * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI 8267215976Sjmallett * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS 8268215976Sjmallett * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2 8269215976Sjmallett * (Out1), and DCD is the same as MCR bit 3 (Out2). 8270215976Sjmallett * 8271215976Sjmallett * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip. 8272215976Sjmallett * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode. The UART1 dsr_n, ri_n, and dcd_n 8273215976Sjmallett * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and 8274215976Sjmallett * DCD bits will be '0' when not in Loopback mode. 8275215976Sjmallett */ 8276232812Sjmallettunion cvmx_mio_uartx_msr { 8277215976Sjmallett uint64_t u64; 8278232812Sjmallett struct cvmx_mio_uartx_msr_s { 8279232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8280215976Sjmallett uint64_t reserved_8_63 : 56; 8281215976Sjmallett uint64_t dcd : 1; /**< Data Carrier Detect input bit */ 8282215976Sjmallett uint64_t ri : 1; /**< Ring Indicator input bit */ 8283215976Sjmallett uint64_t dsr : 1; /**< Data Set Ready input bit */ 8284215976Sjmallett uint64_t cts : 1; /**< Clear To Send input bit */ 8285215976Sjmallett uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */ 8286215976Sjmallett uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */ 8287215976Sjmallett uint64_t ddsr : 1; /**< Delta Data Set Ready bit */ 8288215976Sjmallett uint64_t dcts : 1; /**< Delta Clear To Send bit */ 8289215976Sjmallett#else 8290215976Sjmallett uint64_t dcts : 1; 8291215976Sjmallett uint64_t ddsr : 1; 8292215976Sjmallett uint64_t teri : 1; 8293215976Sjmallett uint64_t ddcd : 1; 8294215976Sjmallett uint64_t cts : 1; 8295215976Sjmallett uint64_t dsr : 1; 8296215976Sjmallett uint64_t ri : 1; 8297215976Sjmallett uint64_t dcd : 1; 8298215976Sjmallett uint64_t reserved_8_63 : 56; 8299215976Sjmallett#endif 8300215976Sjmallett } s; 8301215976Sjmallett struct cvmx_mio_uartx_msr_s cn30xx; 8302215976Sjmallett struct cvmx_mio_uartx_msr_s cn31xx; 8303215976Sjmallett struct cvmx_mio_uartx_msr_s cn38xx; 8304215976Sjmallett struct cvmx_mio_uartx_msr_s cn38xxp2; 8305215976Sjmallett struct cvmx_mio_uartx_msr_s cn50xx; 8306215976Sjmallett struct cvmx_mio_uartx_msr_s cn52xx; 8307215976Sjmallett struct cvmx_mio_uartx_msr_s cn52xxp1; 8308215976Sjmallett struct cvmx_mio_uartx_msr_s cn56xx; 8309215976Sjmallett struct cvmx_mio_uartx_msr_s cn56xxp1; 8310215976Sjmallett struct cvmx_mio_uartx_msr_s cn58xx; 8311215976Sjmallett struct cvmx_mio_uartx_msr_s cn58xxp1; 8312232812Sjmallett struct cvmx_mio_uartx_msr_s cn61xx; 8313215976Sjmallett struct cvmx_mio_uartx_msr_s cn63xx; 8314215976Sjmallett struct cvmx_mio_uartx_msr_s cn63xxp1; 8315232812Sjmallett struct cvmx_mio_uartx_msr_s cn66xx; 8316232812Sjmallett struct cvmx_mio_uartx_msr_s cn68xx; 8317232812Sjmallett struct cvmx_mio_uartx_msr_s cn68xxp1; 8318232812Sjmallett struct cvmx_mio_uartx_msr_s cnf71xx; 8319215976Sjmallett}; 8320215976Sjmalletttypedef union cvmx_mio_uartx_msr cvmx_mio_uartx_msr_t; 8321215976Sjmalletttypedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t; 8322215976Sjmallett 8323215976Sjmallett/** 8324215976Sjmallett * cvmx_mio_uart#_rbr 8325215976Sjmallett * 8326215976Sjmallett * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register 8327215976Sjmallett * 8328215976Sjmallett * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the 8329215976Sjmallett * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the 8330215976Sjmallett * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be 8331215976Sjmallett * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When 8332215976Sjmallett * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO 8333215976Sjmallett * is full (64 characters) and this register is not read before the next data character arrives, then the 8334215976Sjmallett * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs. 8335215976Sjmallett * 8336215976Sjmallett * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 8337215976Sjmallett * this register. 8338215976Sjmallett * 8339215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 8340215976Sjmallett * RBR, THR, and DLL registers are the same. 8341215976Sjmallett */ 8342232812Sjmallettunion cvmx_mio_uartx_rbr { 8343215976Sjmallett uint64_t u64; 8344232812Sjmallett struct cvmx_mio_uartx_rbr_s { 8345232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8346215976Sjmallett uint64_t reserved_8_63 : 56; 8347215976Sjmallett uint64_t rbr : 8; /**< Receive Buffer Register */ 8348215976Sjmallett#else 8349215976Sjmallett uint64_t rbr : 8; 8350215976Sjmallett uint64_t reserved_8_63 : 56; 8351215976Sjmallett#endif 8352215976Sjmallett } s; 8353215976Sjmallett struct cvmx_mio_uartx_rbr_s cn30xx; 8354215976Sjmallett struct cvmx_mio_uartx_rbr_s cn31xx; 8355215976Sjmallett struct cvmx_mio_uartx_rbr_s cn38xx; 8356215976Sjmallett struct cvmx_mio_uartx_rbr_s cn38xxp2; 8357215976Sjmallett struct cvmx_mio_uartx_rbr_s cn50xx; 8358215976Sjmallett struct cvmx_mio_uartx_rbr_s cn52xx; 8359215976Sjmallett struct cvmx_mio_uartx_rbr_s cn52xxp1; 8360215976Sjmallett struct cvmx_mio_uartx_rbr_s cn56xx; 8361215976Sjmallett struct cvmx_mio_uartx_rbr_s cn56xxp1; 8362215976Sjmallett struct cvmx_mio_uartx_rbr_s cn58xx; 8363215976Sjmallett struct cvmx_mio_uartx_rbr_s cn58xxp1; 8364232812Sjmallett struct cvmx_mio_uartx_rbr_s cn61xx; 8365215976Sjmallett struct cvmx_mio_uartx_rbr_s cn63xx; 8366215976Sjmallett struct cvmx_mio_uartx_rbr_s cn63xxp1; 8367232812Sjmallett struct cvmx_mio_uartx_rbr_s cn66xx; 8368232812Sjmallett struct cvmx_mio_uartx_rbr_s cn68xx; 8369232812Sjmallett struct cvmx_mio_uartx_rbr_s cn68xxp1; 8370232812Sjmallett struct cvmx_mio_uartx_rbr_s cnf71xx; 8371215976Sjmallett}; 8372215976Sjmalletttypedef union cvmx_mio_uartx_rbr cvmx_mio_uartx_rbr_t; 8373215976Sjmalletttypedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t; 8374215976Sjmallett 8375215976Sjmallett/** 8376215976Sjmallett * cvmx_mio_uart#_rfl 8377215976Sjmallett * 8378215976Sjmallett * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register 8379215976Sjmallett * 8380215976Sjmallett * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO. 8381215976Sjmallett */ 8382232812Sjmallettunion cvmx_mio_uartx_rfl { 8383215976Sjmallett uint64_t u64; 8384232812Sjmallett struct cvmx_mio_uartx_rfl_s { 8385232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8386215976Sjmallett uint64_t reserved_7_63 : 57; 8387215976Sjmallett uint64_t rfl : 7; /**< Receive FIFO Level Register */ 8388215976Sjmallett#else 8389215976Sjmallett uint64_t rfl : 7; 8390215976Sjmallett uint64_t reserved_7_63 : 57; 8391215976Sjmallett#endif 8392215976Sjmallett } s; 8393215976Sjmallett struct cvmx_mio_uartx_rfl_s cn30xx; 8394215976Sjmallett struct cvmx_mio_uartx_rfl_s cn31xx; 8395215976Sjmallett struct cvmx_mio_uartx_rfl_s cn38xx; 8396215976Sjmallett struct cvmx_mio_uartx_rfl_s cn38xxp2; 8397215976Sjmallett struct cvmx_mio_uartx_rfl_s cn50xx; 8398215976Sjmallett struct cvmx_mio_uartx_rfl_s cn52xx; 8399215976Sjmallett struct cvmx_mio_uartx_rfl_s cn52xxp1; 8400215976Sjmallett struct cvmx_mio_uartx_rfl_s cn56xx; 8401215976Sjmallett struct cvmx_mio_uartx_rfl_s cn56xxp1; 8402215976Sjmallett struct cvmx_mio_uartx_rfl_s cn58xx; 8403215976Sjmallett struct cvmx_mio_uartx_rfl_s cn58xxp1; 8404232812Sjmallett struct cvmx_mio_uartx_rfl_s cn61xx; 8405215976Sjmallett struct cvmx_mio_uartx_rfl_s cn63xx; 8406215976Sjmallett struct cvmx_mio_uartx_rfl_s cn63xxp1; 8407232812Sjmallett struct cvmx_mio_uartx_rfl_s cn66xx; 8408232812Sjmallett struct cvmx_mio_uartx_rfl_s cn68xx; 8409232812Sjmallett struct cvmx_mio_uartx_rfl_s cn68xxp1; 8410232812Sjmallett struct cvmx_mio_uartx_rfl_s cnf71xx; 8411215976Sjmallett}; 8412215976Sjmalletttypedef union cvmx_mio_uartx_rfl cvmx_mio_uartx_rfl_t; 8413215976Sjmalletttypedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t; 8414215976Sjmallett 8415215976Sjmallett/** 8416215976Sjmallett * cvmx_mio_uart#_rfw 8417215976Sjmallett * 8418215976Sjmallett * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register 8419215976Sjmallett * 8420215976Sjmallett * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is 8421215976Sjmallett * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each 8422215976Sjmallett * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are 8423215976Sjmallett * not enabled, this register is used to write data to the RBR. 8424215976Sjmallett */ 8425232812Sjmallettunion cvmx_mio_uartx_rfw { 8426215976Sjmallett uint64_t u64; 8427232812Sjmallett struct cvmx_mio_uartx_rfw_s { 8428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8429215976Sjmallett uint64_t reserved_10_63 : 54; 8430215976Sjmallett uint64_t rffe : 1; /**< Receive FIFO Framing Error */ 8431215976Sjmallett uint64_t rfpe : 1; /**< Receive FIFO Parity Error */ 8432215976Sjmallett uint64_t rfwd : 8; /**< Receive FIFO Write Data */ 8433215976Sjmallett#else 8434215976Sjmallett uint64_t rfwd : 8; 8435215976Sjmallett uint64_t rfpe : 1; 8436215976Sjmallett uint64_t rffe : 1; 8437215976Sjmallett uint64_t reserved_10_63 : 54; 8438215976Sjmallett#endif 8439215976Sjmallett } s; 8440215976Sjmallett struct cvmx_mio_uartx_rfw_s cn30xx; 8441215976Sjmallett struct cvmx_mio_uartx_rfw_s cn31xx; 8442215976Sjmallett struct cvmx_mio_uartx_rfw_s cn38xx; 8443215976Sjmallett struct cvmx_mio_uartx_rfw_s cn38xxp2; 8444215976Sjmallett struct cvmx_mio_uartx_rfw_s cn50xx; 8445215976Sjmallett struct cvmx_mio_uartx_rfw_s cn52xx; 8446215976Sjmallett struct cvmx_mio_uartx_rfw_s cn52xxp1; 8447215976Sjmallett struct cvmx_mio_uartx_rfw_s cn56xx; 8448215976Sjmallett struct cvmx_mio_uartx_rfw_s cn56xxp1; 8449215976Sjmallett struct cvmx_mio_uartx_rfw_s cn58xx; 8450215976Sjmallett struct cvmx_mio_uartx_rfw_s cn58xxp1; 8451232812Sjmallett struct cvmx_mio_uartx_rfw_s cn61xx; 8452215976Sjmallett struct cvmx_mio_uartx_rfw_s cn63xx; 8453215976Sjmallett struct cvmx_mio_uartx_rfw_s cn63xxp1; 8454232812Sjmallett struct cvmx_mio_uartx_rfw_s cn66xx; 8455232812Sjmallett struct cvmx_mio_uartx_rfw_s cn68xx; 8456232812Sjmallett struct cvmx_mio_uartx_rfw_s cn68xxp1; 8457232812Sjmallett struct cvmx_mio_uartx_rfw_s cnf71xx; 8458215976Sjmallett}; 8459215976Sjmalletttypedef union cvmx_mio_uartx_rfw cvmx_mio_uartx_rfw_t; 8460215976Sjmalletttypedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t; 8461215976Sjmallett 8462215976Sjmallett/** 8463215976Sjmallett * cvmx_mio_uart#_sbcr 8464215976Sjmallett * 8465215976Sjmallett * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register 8466215976Sjmallett * 8467215976Sjmallett * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can 8468215976Sjmallett * be used to remove the burden of having to perform a read-modify-write on the LCR. 8469215976Sjmallett */ 8470232812Sjmallettunion cvmx_mio_uartx_sbcr { 8471215976Sjmallett uint64_t u64; 8472232812Sjmallett struct cvmx_mio_uartx_sbcr_s { 8473232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8474215976Sjmallett uint64_t reserved_1_63 : 63; 8475215976Sjmallett uint64_t sbcr : 1; /**< Shadow Break Control */ 8476215976Sjmallett#else 8477215976Sjmallett uint64_t sbcr : 1; 8478215976Sjmallett uint64_t reserved_1_63 : 63; 8479215976Sjmallett#endif 8480215976Sjmallett } s; 8481215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn30xx; 8482215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn31xx; 8483215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn38xx; 8484215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn38xxp2; 8485215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn50xx; 8486215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn52xx; 8487215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn52xxp1; 8488215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn56xx; 8489215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn56xxp1; 8490215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn58xx; 8491215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn58xxp1; 8492232812Sjmallett struct cvmx_mio_uartx_sbcr_s cn61xx; 8493215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn63xx; 8494215976Sjmallett struct cvmx_mio_uartx_sbcr_s cn63xxp1; 8495232812Sjmallett struct cvmx_mio_uartx_sbcr_s cn66xx; 8496232812Sjmallett struct cvmx_mio_uartx_sbcr_s cn68xx; 8497232812Sjmallett struct cvmx_mio_uartx_sbcr_s cn68xxp1; 8498232812Sjmallett struct cvmx_mio_uartx_sbcr_s cnf71xx; 8499215976Sjmallett}; 8500215976Sjmalletttypedef union cvmx_mio_uartx_sbcr cvmx_mio_uartx_sbcr_t; 8501215976Sjmalletttypedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t; 8502215976Sjmallett 8503215976Sjmallett/** 8504215976Sjmallett * cvmx_mio_uart#_scr 8505215976Sjmallett * 8506215976Sjmallett * MIO_UARTX_SCR = MIO UARTX Scratchpad Register 8507215976Sjmallett * 8508215976Sjmallett * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary 8509215976Sjmallett * storage space. 8510215976Sjmallett */ 8511232812Sjmallettunion cvmx_mio_uartx_scr { 8512215976Sjmallett uint64_t u64; 8513232812Sjmallett struct cvmx_mio_uartx_scr_s { 8514232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8515215976Sjmallett uint64_t reserved_8_63 : 56; 8516215976Sjmallett uint64_t scr : 8; /**< Scratchpad Register */ 8517215976Sjmallett#else 8518215976Sjmallett uint64_t scr : 8; 8519215976Sjmallett uint64_t reserved_8_63 : 56; 8520215976Sjmallett#endif 8521215976Sjmallett } s; 8522215976Sjmallett struct cvmx_mio_uartx_scr_s cn30xx; 8523215976Sjmallett struct cvmx_mio_uartx_scr_s cn31xx; 8524215976Sjmallett struct cvmx_mio_uartx_scr_s cn38xx; 8525215976Sjmallett struct cvmx_mio_uartx_scr_s cn38xxp2; 8526215976Sjmallett struct cvmx_mio_uartx_scr_s cn50xx; 8527215976Sjmallett struct cvmx_mio_uartx_scr_s cn52xx; 8528215976Sjmallett struct cvmx_mio_uartx_scr_s cn52xxp1; 8529215976Sjmallett struct cvmx_mio_uartx_scr_s cn56xx; 8530215976Sjmallett struct cvmx_mio_uartx_scr_s cn56xxp1; 8531215976Sjmallett struct cvmx_mio_uartx_scr_s cn58xx; 8532215976Sjmallett struct cvmx_mio_uartx_scr_s cn58xxp1; 8533232812Sjmallett struct cvmx_mio_uartx_scr_s cn61xx; 8534215976Sjmallett struct cvmx_mio_uartx_scr_s cn63xx; 8535215976Sjmallett struct cvmx_mio_uartx_scr_s cn63xxp1; 8536232812Sjmallett struct cvmx_mio_uartx_scr_s cn66xx; 8537232812Sjmallett struct cvmx_mio_uartx_scr_s cn68xx; 8538232812Sjmallett struct cvmx_mio_uartx_scr_s cn68xxp1; 8539232812Sjmallett struct cvmx_mio_uartx_scr_s cnf71xx; 8540215976Sjmallett}; 8541215976Sjmalletttypedef union cvmx_mio_uartx_scr cvmx_mio_uartx_scr_t; 8542215976Sjmalletttypedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t; 8543215976Sjmallett 8544215976Sjmallett/** 8545215976Sjmallett * cvmx_mio_uart#_sfe 8546215976Sjmallett * 8547215976Sjmallett * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register 8548215976Sjmallett * 8549215976Sjmallett * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that 8550215976Sjmallett * can be used to remove the burden of having to store the previously written value to the FCR in memory 8551215976Sjmallett * and having to mask this value so that only the FIFO enable bit gets updated. 8552215976Sjmallett */ 8553232812Sjmallettunion cvmx_mio_uartx_sfe { 8554215976Sjmallett uint64_t u64; 8555232812Sjmallett struct cvmx_mio_uartx_sfe_s { 8556232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8557215976Sjmallett uint64_t reserved_1_63 : 63; 8558215976Sjmallett uint64_t sfe : 1; /**< Shadow FIFO Enable */ 8559215976Sjmallett#else 8560215976Sjmallett uint64_t sfe : 1; 8561215976Sjmallett uint64_t reserved_1_63 : 63; 8562215976Sjmallett#endif 8563215976Sjmallett } s; 8564215976Sjmallett struct cvmx_mio_uartx_sfe_s cn30xx; 8565215976Sjmallett struct cvmx_mio_uartx_sfe_s cn31xx; 8566215976Sjmallett struct cvmx_mio_uartx_sfe_s cn38xx; 8567215976Sjmallett struct cvmx_mio_uartx_sfe_s cn38xxp2; 8568215976Sjmallett struct cvmx_mio_uartx_sfe_s cn50xx; 8569215976Sjmallett struct cvmx_mio_uartx_sfe_s cn52xx; 8570215976Sjmallett struct cvmx_mio_uartx_sfe_s cn52xxp1; 8571215976Sjmallett struct cvmx_mio_uartx_sfe_s cn56xx; 8572215976Sjmallett struct cvmx_mio_uartx_sfe_s cn56xxp1; 8573215976Sjmallett struct cvmx_mio_uartx_sfe_s cn58xx; 8574215976Sjmallett struct cvmx_mio_uartx_sfe_s cn58xxp1; 8575232812Sjmallett struct cvmx_mio_uartx_sfe_s cn61xx; 8576215976Sjmallett struct cvmx_mio_uartx_sfe_s cn63xx; 8577215976Sjmallett struct cvmx_mio_uartx_sfe_s cn63xxp1; 8578232812Sjmallett struct cvmx_mio_uartx_sfe_s cn66xx; 8579232812Sjmallett struct cvmx_mio_uartx_sfe_s cn68xx; 8580232812Sjmallett struct cvmx_mio_uartx_sfe_s cn68xxp1; 8581232812Sjmallett struct cvmx_mio_uartx_sfe_s cnf71xx; 8582215976Sjmallett}; 8583215976Sjmalletttypedef union cvmx_mio_uartx_sfe cvmx_mio_uartx_sfe_t; 8584215976Sjmalletttypedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t; 8585215976Sjmallett 8586215976Sjmallett/** 8587215976Sjmallett * cvmx_mio_uart#_srr 8588215976Sjmallett * 8589215976Sjmallett * MIO_UARTX_SRR = MIO UARTX Software Reset Register 8590215976Sjmallett * 8591215976Sjmallett * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive 8592215976Sjmallett * FIFO and/or the transmit FIFO. 8593215976Sjmallett * 8594215976Sjmallett * Bit 0 of the SRR is the UART Soft Reset (USR) bit. Setting this bit resets the UART. 8595215976Sjmallett * 8596215976Sjmallett * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove 8597215976Sjmallett * the burden on software having to store previously written FCR values (which are pretty static) just 8598215976Sjmallett * to reset the receive FIFO. 8599215976Sjmallett * 8600215976Sjmallett * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove 8601215976Sjmallett * the burden on software having to store previously written FCR values (which are pretty static) just 8602215976Sjmallett * to reset the transmit FIFO. 8603215976Sjmallett */ 8604232812Sjmallettunion cvmx_mio_uartx_srr { 8605215976Sjmallett uint64_t u64; 8606232812Sjmallett struct cvmx_mio_uartx_srr_s { 8607232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8608215976Sjmallett uint64_t reserved_3_63 : 61; 8609215976Sjmallett uint64_t stfr : 1; /**< Shadow TX FIFO Reset */ 8610215976Sjmallett uint64_t srfr : 1; /**< Shadow RX FIFO Reset */ 8611215976Sjmallett uint64_t usr : 1; /**< UART Soft Reset */ 8612215976Sjmallett#else 8613215976Sjmallett uint64_t usr : 1; 8614215976Sjmallett uint64_t srfr : 1; 8615215976Sjmallett uint64_t stfr : 1; 8616215976Sjmallett uint64_t reserved_3_63 : 61; 8617215976Sjmallett#endif 8618215976Sjmallett } s; 8619215976Sjmallett struct cvmx_mio_uartx_srr_s cn30xx; 8620215976Sjmallett struct cvmx_mio_uartx_srr_s cn31xx; 8621215976Sjmallett struct cvmx_mio_uartx_srr_s cn38xx; 8622215976Sjmallett struct cvmx_mio_uartx_srr_s cn38xxp2; 8623215976Sjmallett struct cvmx_mio_uartx_srr_s cn50xx; 8624215976Sjmallett struct cvmx_mio_uartx_srr_s cn52xx; 8625215976Sjmallett struct cvmx_mio_uartx_srr_s cn52xxp1; 8626215976Sjmallett struct cvmx_mio_uartx_srr_s cn56xx; 8627215976Sjmallett struct cvmx_mio_uartx_srr_s cn56xxp1; 8628215976Sjmallett struct cvmx_mio_uartx_srr_s cn58xx; 8629215976Sjmallett struct cvmx_mio_uartx_srr_s cn58xxp1; 8630232812Sjmallett struct cvmx_mio_uartx_srr_s cn61xx; 8631215976Sjmallett struct cvmx_mio_uartx_srr_s cn63xx; 8632215976Sjmallett struct cvmx_mio_uartx_srr_s cn63xxp1; 8633232812Sjmallett struct cvmx_mio_uartx_srr_s cn66xx; 8634232812Sjmallett struct cvmx_mio_uartx_srr_s cn68xx; 8635232812Sjmallett struct cvmx_mio_uartx_srr_s cn68xxp1; 8636232812Sjmallett struct cvmx_mio_uartx_srr_s cnf71xx; 8637215976Sjmallett}; 8638215976Sjmalletttypedef union cvmx_mio_uartx_srr cvmx_mio_uartx_srr_t; 8639215976Sjmalletttypedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t; 8640215976Sjmallett 8641215976Sjmallett/** 8642215976Sjmallett * cvmx_mio_uart#_srt 8643215976Sjmallett * 8644215976Sjmallett * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register 8645215976Sjmallett * 8646215976Sjmallett * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that 8647215976Sjmallett * can be used to remove the burden of having to store the previously written value to the FCR in memory 8648215976Sjmallett * and having to mask this value so that only the RX Trigger bits get updated. 8649215976Sjmallett */ 8650232812Sjmallettunion cvmx_mio_uartx_srt { 8651215976Sjmallett uint64_t u64; 8652232812Sjmallett struct cvmx_mio_uartx_srt_s { 8653232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8654215976Sjmallett uint64_t reserved_2_63 : 62; 8655215976Sjmallett uint64_t srt : 2; /**< Shadow RX Trigger */ 8656215976Sjmallett#else 8657215976Sjmallett uint64_t srt : 2; 8658215976Sjmallett uint64_t reserved_2_63 : 62; 8659215976Sjmallett#endif 8660215976Sjmallett } s; 8661215976Sjmallett struct cvmx_mio_uartx_srt_s cn30xx; 8662215976Sjmallett struct cvmx_mio_uartx_srt_s cn31xx; 8663215976Sjmallett struct cvmx_mio_uartx_srt_s cn38xx; 8664215976Sjmallett struct cvmx_mio_uartx_srt_s cn38xxp2; 8665215976Sjmallett struct cvmx_mio_uartx_srt_s cn50xx; 8666215976Sjmallett struct cvmx_mio_uartx_srt_s cn52xx; 8667215976Sjmallett struct cvmx_mio_uartx_srt_s cn52xxp1; 8668215976Sjmallett struct cvmx_mio_uartx_srt_s cn56xx; 8669215976Sjmallett struct cvmx_mio_uartx_srt_s cn56xxp1; 8670215976Sjmallett struct cvmx_mio_uartx_srt_s cn58xx; 8671215976Sjmallett struct cvmx_mio_uartx_srt_s cn58xxp1; 8672232812Sjmallett struct cvmx_mio_uartx_srt_s cn61xx; 8673215976Sjmallett struct cvmx_mio_uartx_srt_s cn63xx; 8674215976Sjmallett struct cvmx_mio_uartx_srt_s cn63xxp1; 8675232812Sjmallett struct cvmx_mio_uartx_srt_s cn66xx; 8676232812Sjmallett struct cvmx_mio_uartx_srt_s cn68xx; 8677232812Sjmallett struct cvmx_mio_uartx_srt_s cn68xxp1; 8678232812Sjmallett struct cvmx_mio_uartx_srt_s cnf71xx; 8679215976Sjmallett}; 8680215976Sjmalletttypedef union cvmx_mio_uartx_srt cvmx_mio_uartx_srt_t; 8681215976Sjmalletttypedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t; 8682215976Sjmallett 8683215976Sjmallett/** 8684215976Sjmallett * cvmx_mio_uart#_srts 8685215976Sjmallett * 8686215976Sjmallett * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register 8687215976Sjmallett * 8688215976Sjmallett * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can 8689215976Sjmallett * be used to remove the burden of having to perform a read-modify-write on the MCR. 8690215976Sjmallett */ 8691232812Sjmallettunion cvmx_mio_uartx_srts { 8692215976Sjmallett uint64_t u64; 8693232812Sjmallett struct cvmx_mio_uartx_srts_s { 8694232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8695215976Sjmallett uint64_t reserved_1_63 : 63; 8696215976Sjmallett uint64_t srts : 1; /**< Shadow Request To Send */ 8697215976Sjmallett#else 8698215976Sjmallett uint64_t srts : 1; 8699215976Sjmallett uint64_t reserved_1_63 : 63; 8700215976Sjmallett#endif 8701215976Sjmallett } s; 8702215976Sjmallett struct cvmx_mio_uartx_srts_s cn30xx; 8703215976Sjmallett struct cvmx_mio_uartx_srts_s cn31xx; 8704215976Sjmallett struct cvmx_mio_uartx_srts_s cn38xx; 8705215976Sjmallett struct cvmx_mio_uartx_srts_s cn38xxp2; 8706215976Sjmallett struct cvmx_mio_uartx_srts_s cn50xx; 8707215976Sjmallett struct cvmx_mio_uartx_srts_s cn52xx; 8708215976Sjmallett struct cvmx_mio_uartx_srts_s cn52xxp1; 8709215976Sjmallett struct cvmx_mio_uartx_srts_s cn56xx; 8710215976Sjmallett struct cvmx_mio_uartx_srts_s cn56xxp1; 8711215976Sjmallett struct cvmx_mio_uartx_srts_s cn58xx; 8712215976Sjmallett struct cvmx_mio_uartx_srts_s cn58xxp1; 8713232812Sjmallett struct cvmx_mio_uartx_srts_s cn61xx; 8714215976Sjmallett struct cvmx_mio_uartx_srts_s cn63xx; 8715215976Sjmallett struct cvmx_mio_uartx_srts_s cn63xxp1; 8716232812Sjmallett struct cvmx_mio_uartx_srts_s cn66xx; 8717232812Sjmallett struct cvmx_mio_uartx_srts_s cn68xx; 8718232812Sjmallett struct cvmx_mio_uartx_srts_s cn68xxp1; 8719232812Sjmallett struct cvmx_mio_uartx_srts_s cnf71xx; 8720215976Sjmallett}; 8721215976Sjmalletttypedef union cvmx_mio_uartx_srts cvmx_mio_uartx_srts_t; 8722215976Sjmalletttypedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t; 8723215976Sjmallett 8724215976Sjmallett/** 8725215976Sjmallett * cvmx_mio_uart#_stt 8726215976Sjmallett * 8727215976Sjmallett * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register 8728215976Sjmallett * 8729215976Sjmallett * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that 8730215976Sjmallett * can be used to remove the burden of having to store the previously written value to the FCR in memory 8731215976Sjmallett * and having to mask this value so that only the TX Trigger bits get updated. 8732215976Sjmallett */ 8733232812Sjmallettunion cvmx_mio_uartx_stt { 8734215976Sjmallett uint64_t u64; 8735232812Sjmallett struct cvmx_mio_uartx_stt_s { 8736232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8737215976Sjmallett uint64_t reserved_2_63 : 62; 8738215976Sjmallett uint64_t stt : 2; /**< Shadow TX Trigger */ 8739215976Sjmallett#else 8740215976Sjmallett uint64_t stt : 2; 8741215976Sjmallett uint64_t reserved_2_63 : 62; 8742215976Sjmallett#endif 8743215976Sjmallett } s; 8744215976Sjmallett struct cvmx_mio_uartx_stt_s cn30xx; 8745215976Sjmallett struct cvmx_mio_uartx_stt_s cn31xx; 8746215976Sjmallett struct cvmx_mio_uartx_stt_s cn38xx; 8747215976Sjmallett struct cvmx_mio_uartx_stt_s cn38xxp2; 8748215976Sjmallett struct cvmx_mio_uartx_stt_s cn50xx; 8749215976Sjmallett struct cvmx_mio_uartx_stt_s cn52xx; 8750215976Sjmallett struct cvmx_mio_uartx_stt_s cn52xxp1; 8751215976Sjmallett struct cvmx_mio_uartx_stt_s cn56xx; 8752215976Sjmallett struct cvmx_mio_uartx_stt_s cn56xxp1; 8753215976Sjmallett struct cvmx_mio_uartx_stt_s cn58xx; 8754215976Sjmallett struct cvmx_mio_uartx_stt_s cn58xxp1; 8755232812Sjmallett struct cvmx_mio_uartx_stt_s cn61xx; 8756215976Sjmallett struct cvmx_mio_uartx_stt_s cn63xx; 8757215976Sjmallett struct cvmx_mio_uartx_stt_s cn63xxp1; 8758232812Sjmallett struct cvmx_mio_uartx_stt_s cn66xx; 8759232812Sjmallett struct cvmx_mio_uartx_stt_s cn68xx; 8760232812Sjmallett struct cvmx_mio_uartx_stt_s cn68xxp1; 8761232812Sjmallett struct cvmx_mio_uartx_stt_s cnf71xx; 8762215976Sjmallett}; 8763215976Sjmalletttypedef union cvmx_mio_uartx_stt cvmx_mio_uartx_stt_t; 8764215976Sjmalletttypedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t; 8765215976Sjmallett 8766215976Sjmallett/** 8767215976Sjmallett * cvmx_mio_uart#_tfl 8768215976Sjmallett * 8769215976Sjmallett * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register 8770215976Sjmallett * 8771215976Sjmallett * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO. 8772215976Sjmallett */ 8773232812Sjmallettunion cvmx_mio_uartx_tfl { 8774215976Sjmallett uint64_t u64; 8775232812Sjmallett struct cvmx_mio_uartx_tfl_s { 8776232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8777215976Sjmallett uint64_t reserved_7_63 : 57; 8778215976Sjmallett uint64_t tfl : 7; /**< Transmit FIFO Level Register */ 8779215976Sjmallett#else 8780215976Sjmallett uint64_t tfl : 7; 8781215976Sjmallett uint64_t reserved_7_63 : 57; 8782215976Sjmallett#endif 8783215976Sjmallett } s; 8784215976Sjmallett struct cvmx_mio_uartx_tfl_s cn30xx; 8785215976Sjmallett struct cvmx_mio_uartx_tfl_s cn31xx; 8786215976Sjmallett struct cvmx_mio_uartx_tfl_s cn38xx; 8787215976Sjmallett struct cvmx_mio_uartx_tfl_s cn38xxp2; 8788215976Sjmallett struct cvmx_mio_uartx_tfl_s cn50xx; 8789215976Sjmallett struct cvmx_mio_uartx_tfl_s cn52xx; 8790215976Sjmallett struct cvmx_mio_uartx_tfl_s cn52xxp1; 8791215976Sjmallett struct cvmx_mio_uartx_tfl_s cn56xx; 8792215976Sjmallett struct cvmx_mio_uartx_tfl_s cn56xxp1; 8793215976Sjmallett struct cvmx_mio_uartx_tfl_s cn58xx; 8794215976Sjmallett struct cvmx_mio_uartx_tfl_s cn58xxp1; 8795232812Sjmallett struct cvmx_mio_uartx_tfl_s cn61xx; 8796215976Sjmallett struct cvmx_mio_uartx_tfl_s cn63xx; 8797215976Sjmallett struct cvmx_mio_uartx_tfl_s cn63xxp1; 8798232812Sjmallett struct cvmx_mio_uartx_tfl_s cn66xx; 8799232812Sjmallett struct cvmx_mio_uartx_tfl_s cn68xx; 8800232812Sjmallett struct cvmx_mio_uartx_tfl_s cn68xxp1; 8801232812Sjmallett struct cvmx_mio_uartx_tfl_s cnf71xx; 8802215976Sjmallett}; 8803215976Sjmalletttypedef union cvmx_mio_uartx_tfl cvmx_mio_uartx_tfl_t; 8804215976Sjmalletttypedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t; 8805215976Sjmallett 8806215976Sjmallett/** 8807215976Sjmallett * cvmx_mio_uart#_tfr 8808215976Sjmallett * 8809215976Sjmallett * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register 8810215976Sjmallett * 8811215976Sjmallett * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is 8812215976Sjmallett * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO. 8813215976Sjmallett * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the 8814215976Sjmallett * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR. 8815215976Sjmallett */ 8816232812Sjmallettunion cvmx_mio_uartx_tfr { 8817215976Sjmallett uint64_t u64; 8818232812Sjmallett struct cvmx_mio_uartx_tfr_s { 8819232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8820215976Sjmallett uint64_t reserved_8_63 : 56; 8821215976Sjmallett uint64_t tfr : 8; /**< Transmit FIFO Read Register */ 8822215976Sjmallett#else 8823215976Sjmallett uint64_t tfr : 8; 8824215976Sjmallett uint64_t reserved_8_63 : 56; 8825215976Sjmallett#endif 8826215976Sjmallett } s; 8827215976Sjmallett struct cvmx_mio_uartx_tfr_s cn30xx; 8828215976Sjmallett struct cvmx_mio_uartx_tfr_s cn31xx; 8829215976Sjmallett struct cvmx_mio_uartx_tfr_s cn38xx; 8830215976Sjmallett struct cvmx_mio_uartx_tfr_s cn38xxp2; 8831215976Sjmallett struct cvmx_mio_uartx_tfr_s cn50xx; 8832215976Sjmallett struct cvmx_mio_uartx_tfr_s cn52xx; 8833215976Sjmallett struct cvmx_mio_uartx_tfr_s cn52xxp1; 8834215976Sjmallett struct cvmx_mio_uartx_tfr_s cn56xx; 8835215976Sjmallett struct cvmx_mio_uartx_tfr_s cn56xxp1; 8836215976Sjmallett struct cvmx_mio_uartx_tfr_s cn58xx; 8837215976Sjmallett struct cvmx_mio_uartx_tfr_s cn58xxp1; 8838232812Sjmallett struct cvmx_mio_uartx_tfr_s cn61xx; 8839215976Sjmallett struct cvmx_mio_uartx_tfr_s cn63xx; 8840215976Sjmallett struct cvmx_mio_uartx_tfr_s cn63xxp1; 8841232812Sjmallett struct cvmx_mio_uartx_tfr_s cn66xx; 8842232812Sjmallett struct cvmx_mio_uartx_tfr_s cn68xx; 8843232812Sjmallett struct cvmx_mio_uartx_tfr_s cn68xxp1; 8844232812Sjmallett struct cvmx_mio_uartx_tfr_s cnf71xx; 8845215976Sjmallett}; 8846215976Sjmalletttypedef union cvmx_mio_uartx_tfr cvmx_mio_uartx_tfr_t; 8847215976Sjmalletttypedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t; 8848215976Sjmallett 8849215976Sjmallett/** 8850215976Sjmallett * cvmx_mio_uart#_thr 8851215976Sjmallett * 8852215976Sjmallett * MIO_UARTX_THR = MIO UARTX Transmit Holding Register 8853215976Sjmallett * 8854215976Sjmallett * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the 8855215976Sjmallett * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of 8856215976Sjmallett * the Line Status Register (LSR) is set. 8857215976Sjmallett * 8858215976Sjmallett * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any 8859215976Sjmallett * additional writes to the THR before the THRE is set again causes the THR data to be overwritten. 8860215976Sjmallett * 8861215976Sjmallett * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may 8862215976Sjmallett * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results 8863215976Sjmallett * in the write data being lost. 8864215976Sjmallett * 8865215976Sjmallett * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 8866215976Sjmallett * this register. 8867215976Sjmallett * 8868215976Sjmallett * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 8869215976Sjmallett * RBR, THR, and DLL registers are the same. 8870215976Sjmallett */ 8871232812Sjmallettunion cvmx_mio_uartx_thr { 8872215976Sjmallett uint64_t u64; 8873232812Sjmallett struct cvmx_mio_uartx_thr_s { 8874232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8875215976Sjmallett uint64_t reserved_8_63 : 56; 8876215976Sjmallett uint64_t thr : 8; /**< Transmit Holding Register */ 8877215976Sjmallett#else 8878215976Sjmallett uint64_t thr : 8; 8879215976Sjmallett uint64_t reserved_8_63 : 56; 8880215976Sjmallett#endif 8881215976Sjmallett } s; 8882215976Sjmallett struct cvmx_mio_uartx_thr_s cn30xx; 8883215976Sjmallett struct cvmx_mio_uartx_thr_s cn31xx; 8884215976Sjmallett struct cvmx_mio_uartx_thr_s cn38xx; 8885215976Sjmallett struct cvmx_mio_uartx_thr_s cn38xxp2; 8886215976Sjmallett struct cvmx_mio_uartx_thr_s cn50xx; 8887215976Sjmallett struct cvmx_mio_uartx_thr_s cn52xx; 8888215976Sjmallett struct cvmx_mio_uartx_thr_s cn52xxp1; 8889215976Sjmallett struct cvmx_mio_uartx_thr_s cn56xx; 8890215976Sjmallett struct cvmx_mio_uartx_thr_s cn56xxp1; 8891215976Sjmallett struct cvmx_mio_uartx_thr_s cn58xx; 8892215976Sjmallett struct cvmx_mio_uartx_thr_s cn58xxp1; 8893232812Sjmallett struct cvmx_mio_uartx_thr_s cn61xx; 8894215976Sjmallett struct cvmx_mio_uartx_thr_s cn63xx; 8895215976Sjmallett struct cvmx_mio_uartx_thr_s cn63xxp1; 8896232812Sjmallett struct cvmx_mio_uartx_thr_s cn66xx; 8897232812Sjmallett struct cvmx_mio_uartx_thr_s cn68xx; 8898232812Sjmallett struct cvmx_mio_uartx_thr_s cn68xxp1; 8899232812Sjmallett struct cvmx_mio_uartx_thr_s cnf71xx; 8900215976Sjmallett}; 8901215976Sjmalletttypedef union cvmx_mio_uartx_thr cvmx_mio_uartx_thr_t; 8902215976Sjmalletttypedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t; 8903215976Sjmallett 8904215976Sjmallett/** 8905215976Sjmallett * cvmx_mio_uart#_usr 8906215976Sjmallett * 8907215976Sjmallett * MIO_UARTX_USR = MIO UARTX UART Status Register 8908215976Sjmallett * 8909215976Sjmallett * The UART Status Register (USR) contains UART status information. 8910215976Sjmallett * 8911215976Sjmallett * USR bit 0 is the BUSY bit. When set this bit indicates that a serial transfer is in progress, when 8912215976Sjmallett * clear it indicates that the UART is idle or inactive. 8913215976Sjmallett * 8914215976Sjmallett * Note: In PASS3, the BUSY bit will always be clear. 8915215976Sjmallett * 8916215976Sjmallett * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX 8917215976Sjmallett * FIFO Not Empty (RFNE), and RX FIFO Full (RFF). 8918215976Sjmallett */ 8919232812Sjmallettunion cvmx_mio_uartx_usr { 8920215976Sjmallett uint64_t u64; 8921232812Sjmallett struct cvmx_mio_uartx_usr_s { 8922232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8923215976Sjmallett uint64_t reserved_5_63 : 59; 8924215976Sjmallett uint64_t rff : 1; /**< RX FIFO Full */ 8925215976Sjmallett uint64_t rfne : 1; /**< RX FIFO Not Empty */ 8926215976Sjmallett uint64_t tfe : 1; /**< TX FIFO Empty */ 8927215976Sjmallett uint64_t tfnf : 1; /**< TX FIFO Not Full */ 8928215976Sjmallett uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */ 8929215976Sjmallett#else 8930215976Sjmallett uint64_t busy : 1; 8931215976Sjmallett uint64_t tfnf : 1; 8932215976Sjmallett uint64_t tfe : 1; 8933215976Sjmallett uint64_t rfne : 1; 8934215976Sjmallett uint64_t rff : 1; 8935215976Sjmallett uint64_t reserved_5_63 : 59; 8936215976Sjmallett#endif 8937215976Sjmallett } s; 8938215976Sjmallett struct cvmx_mio_uartx_usr_s cn30xx; 8939215976Sjmallett struct cvmx_mio_uartx_usr_s cn31xx; 8940215976Sjmallett struct cvmx_mio_uartx_usr_s cn38xx; 8941215976Sjmallett struct cvmx_mio_uartx_usr_s cn38xxp2; 8942215976Sjmallett struct cvmx_mio_uartx_usr_s cn50xx; 8943215976Sjmallett struct cvmx_mio_uartx_usr_s cn52xx; 8944215976Sjmallett struct cvmx_mio_uartx_usr_s cn52xxp1; 8945215976Sjmallett struct cvmx_mio_uartx_usr_s cn56xx; 8946215976Sjmallett struct cvmx_mio_uartx_usr_s cn56xxp1; 8947215976Sjmallett struct cvmx_mio_uartx_usr_s cn58xx; 8948215976Sjmallett struct cvmx_mio_uartx_usr_s cn58xxp1; 8949232812Sjmallett struct cvmx_mio_uartx_usr_s cn61xx; 8950215976Sjmallett struct cvmx_mio_uartx_usr_s cn63xx; 8951215976Sjmallett struct cvmx_mio_uartx_usr_s cn63xxp1; 8952232812Sjmallett struct cvmx_mio_uartx_usr_s cn66xx; 8953232812Sjmallett struct cvmx_mio_uartx_usr_s cn68xx; 8954232812Sjmallett struct cvmx_mio_uartx_usr_s cn68xxp1; 8955232812Sjmallett struct cvmx_mio_uartx_usr_s cnf71xx; 8956215976Sjmallett}; 8957215976Sjmalletttypedef union cvmx_mio_uartx_usr cvmx_mio_uartx_usr_t; 8958215976Sjmalletttypedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t; 8959215976Sjmallett 8960215976Sjmallett/** 8961215976Sjmallett * cvmx_mio_uart2_dlh 8962215976Sjmallett */ 8963232812Sjmallettunion cvmx_mio_uart2_dlh { 8964215976Sjmallett uint64_t u64; 8965232812Sjmallett struct cvmx_mio_uart2_dlh_s { 8966232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8967215976Sjmallett uint64_t reserved_8_63 : 56; 8968215976Sjmallett uint64_t dlh : 8; /**< Divisor Latch High Register */ 8969215976Sjmallett#else 8970215976Sjmallett uint64_t dlh : 8; 8971215976Sjmallett uint64_t reserved_8_63 : 56; 8972215976Sjmallett#endif 8973215976Sjmallett } s; 8974215976Sjmallett struct cvmx_mio_uart2_dlh_s cn52xx; 8975215976Sjmallett struct cvmx_mio_uart2_dlh_s cn52xxp1; 8976215976Sjmallett}; 8977215976Sjmalletttypedef union cvmx_mio_uart2_dlh cvmx_mio_uart2_dlh_t; 8978215976Sjmallett 8979215976Sjmallett/** 8980215976Sjmallett * cvmx_mio_uart2_dll 8981215976Sjmallett */ 8982232812Sjmallettunion cvmx_mio_uart2_dll { 8983215976Sjmallett uint64_t u64; 8984232812Sjmallett struct cvmx_mio_uart2_dll_s { 8985232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 8986215976Sjmallett uint64_t reserved_8_63 : 56; 8987215976Sjmallett uint64_t dll : 8; /**< Divisor Latch Low Register */ 8988215976Sjmallett#else 8989215976Sjmallett uint64_t dll : 8; 8990215976Sjmallett uint64_t reserved_8_63 : 56; 8991215976Sjmallett#endif 8992215976Sjmallett } s; 8993215976Sjmallett struct cvmx_mio_uart2_dll_s cn52xx; 8994215976Sjmallett struct cvmx_mio_uart2_dll_s cn52xxp1; 8995215976Sjmallett}; 8996215976Sjmalletttypedef union cvmx_mio_uart2_dll cvmx_mio_uart2_dll_t; 8997215976Sjmallett 8998215976Sjmallett/** 8999215976Sjmallett * cvmx_mio_uart2_far 9000215976Sjmallett */ 9001232812Sjmallettunion cvmx_mio_uart2_far { 9002215976Sjmallett uint64_t u64; 9003232812Sjmallett struct cvmx_mio_uart2_far_s { 9004232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9005215976Sjmallett uint64_t reserved_1_63 : 63; 9006215976Sjmallett uint64_t far : 1; /**< FIFO Access Register */ 9007215976Sjmallett#else 9008215976Sjmallett uint64_t far : 1; 9009215976Sjmallett uint64_t reserved_1_63 : 63; 9010215976Sjmallett#endif 9011215976Sjmallett } s; 9012215976Sjmallett struct cvmx_mio_uart2_far_s cn52xx; 9013215976Sjmallett struct cvmx_mio_uart2_far_s cn52xxp1; 9014215976Sjmallett}; 9015215976Sjmalletttypedef union cvmx_mio_uart2_far cvmx_mio_uart2_far_t; 9016215976Sjmallett 9017215976Sjmallett/** 9018215976Sjmallett * cvmx_mio_uart2_fcr 9019215976Sjmallett */ 9020232812Sjmallettunion cvmx_mio_uart2_fcr { 9021215976Sjmallett uint64_t u64; 9022232812Sjmallett struct cvmx_mio_uart2_fcr_s { 9023232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9024215976Sjmallett uint64_t reserved_8_63 : 56; 9025215976Sjmallett uint64_t rxtrig : 2; /**< RX Trigger */ 9026215976Sjmallett uint64_t txtrig : 2; /**< TX Trigger */ 9027215976Sjmallett uint64_t reserved_3_3 : 1; 9028215976Sjmallett uint64_t txfr : 1; /**< TX FIFO reset */ 9029215976Sjmallett uint64_t rxfr : 1; /**< RX FIFO reset */ 9030215976Sjmallett uint64_t en : 1; /**< FIFO enable */ 9031215976Sjmallett#else 9032215976Sjmallett uint64_t en : 1; 9033215976Sjmallett uint64_t rxfr : 1; 9034215976Sjmallett uint64_t txfr : 1; 9035215976Sjmallett uint64_t reserved_3_3 : 1; 9036215976Sjmallett uint64_t txtrig : 2; 9037215976Sjmallett uint64_t rxtrig : 2; 9038215976Sjmallett uint64_t reserved_8_63 : 56; 9039215976Sjmallett#endif 9040215976Sjmallett } s; 9041215976Sjmallett struct cvmx_mio_uart2_fcr_s cn52xx; 9042215976Sjmallett struct cvmx_mio_uart2_fcr_s cn52xxp1; 9043215976Sjmallett}; 9044215976Sjmalletttypedef union cvmx_mio_uart2_fcr cvmx_mio_uart2_fcr_t; 9045215976Sjmallett 9046215976Sjmallett/** 9047215976Sjmallett * cvmx_mio_uart2_htx 9048215976Sjmallett */ 9049232812Sjmallettunion cvmx_mio_uart2_htx { 9050215976Sjmallett uint64_t u64; 9051232812Sjmallett struct cvmx_mio_uart2_htx_s { 9052232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9053215976Sjmallett uint64_t reserved_1_63 : 63; 9054215976Sjmallett uint64_t htx : 1; /**< Halt TX */ 9055215976Sjmallett#else 9056215976Sjmallett uint64_t htx : 1; 9057215976Sjmallett uint64_t reserved_1_63 : 63; 9058215976Sjmallett#endif 9059215976Sjmallett } s; 9060215976Sjmallett struct cvmx_mio_uart2_htx_s cn52xx; 9061215976Sjmallett struct cvmx_mio_uart2_htx_s cn52xxp1; 9062215976Sjmallett}; 9063215976Sjmalletttypedef union cvmx_mio_uart2_htx cvmx_mio_uart2_htx_t; 9064215976Sjmallett 9065215976Sjmallett/** 9066215976Sjmallett * cvmx_mio_uart2_ier 9067215976Sjmallett */ 9068232812Sjmallettunion cvmx_mio_uart2_ier { 9069215976Sjmallett uint64_t u64; 9070232812Sjmallett struct cvmx_mio_uart2_ier_s { 9071232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9072215976Sjmallett uint64_t reserved_8_63 : 56; 9073215976Sjmallett uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */ 9074215976Sjmallett uint64_t reserved_4_6 : 3; 9075215976Sjmallett uint64_t edssi : 1; /**< Enable Modem Status Interrupt */ 9076215976Sjmallett uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */ 9077215976Sjmallett uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */ 9078215976Sjmallett uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */ 9079215976Sjmallett#else 9080215976Sjmallett uint64_t erbfi : 1; 9081215976Sjmallett uint64_t etbei : 1; 9082215976Sjmallett uint64_t elsi : 1; 9083215976Sjmallett uint64_t edssi : 1; 9084215976Sjmallett uint64_t reserved_4_6 : 3; 9085215976Sjmallett uint64_t ptime : 1; 9086215976Sjmallett uint64_t reserved_8_63 : 56; 9087215976Sjmallett#endif 9088215976Sjmallett } s; 9089215976Sjmallett struct cvmx_mio_uart2_ier_s cn52xx; 9090215976Sjmallett struct cvmx_mio_uart2_ier_s cn52xxp1; 9091215976Sjmallett}; 9092215976Sjmalletttypedef union cvmx_mio_uart2_ier cvmx_mio_uart2_ier_t; 9093215976Sjmallett 9094215976Sjmallett/** 9095215976Sjmallett * cvmx_mio_uart2_iir 9096215976Sjmallett */ 9097232812Sjmallettunion cvmx_mio_uart2_iir { 9098215976Sjmallett uint64_t u64; 9099232812Sjmallett struct cvmx_mio_uart2_iir_s { 9100232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9101215976Sjmallett uint64_t reserved_8_63 : 56; 9102215976Sjmallett uint64_t fen : 2; /**< FIFO-enabled bits */ 9103215976Sjmallett uint64_t reserved_4_5 : 2; 9104215976Sjmallett uint64_t iid : 4; /**< Interrupt ID */ 9105215976Sjmallett#else 9106215976Sjmallett uint64_t iid : 4; 9107215976Sjmallett uint64_t reserved_4_5 : 2; 9108215976Sjmallett uint64_t fen : 2; 9109215976Sjmallett uint64_t reserved_8_63 : 56; 9110215976Sjmallett#endif 9111215976Sjmallett } s; 9112215976Sjmallett struct cvmx_mio_uart2_iir_s cn52xx; 9113215976Sjmallett struct cvmx_mio_uart2_iir_s cn52xxp1; 9114215976Sjmallett}; 9115215976Sjmalletttypedef union cvmx_mio_uart2_iir cvmx_mio_uart2_iir_t; 9116215976Sjmallett 9117215976Sjmallett/** 9118215976Sjmallett * cvmx_mio_uart2_lcr 9119215976Sjmallett */ 9120232812Sjmallettunion cvmx_mio_uart2_lcr { 9121215976Sjmallett uint64_t u64; 9122232812Sjmallett struct cvmx_mio_uart2_lcr_s { 9123232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9124215976Sjmallett uint64_t reserved_8_63 : 56; 9125215976Sjmallett uint64_t dlab : 1; /**< Divisor Latch Address bit */ 9126215976Sjmallett uint64_t brk : 1; /**< Break Control bit */ 9127215976Sjmallett uint64_t reserved_5_5 : 1; 9128215976Sjmallett uint64_t eps : 1; /**< Even Parity Select bit */ 9129215976Sjmallett uint64_t pen : 1; /**< Parity Enable bit */ 9130215976Sjmallett uint64_t stop : 1; /**< Stop Control bit */ 9131215976Sjmallett uint64_t cls : 2; /**< Character Length Select */ 9132215976Sjmallett#else 9133215976Sjmallett uint64_t cls : 2; 9134215976Sjmallett uint64_t stop : 1; 9135215976Sjmallett uint64_t pen : 1; 9136215976Sjmallett uint64_t eps : 1; 9137215976Sjmallett uint64_t reserved_5_5 : 1; 9138215976Sjmallett uint64_t brk : 1; 9139215976Sjmallett uint64_t dlab : 1; 9140215976Sjmallett uint64_t reserved_8_63 : 56; 9141215976Sjmallett#endif 9142215976Sjmallett } s; 9143215976Sjmallett struct cvmx_mio_uart2_lcr_s cn52xx; 9144215976Sjmallett struct cvmx_mio_uart2_lcr_s cn52xxp1; 9145215976Sjmallett}; 9146215976Sjmalletttypedef union cvmx_mio_uart2_lcr cvmx_mio_uart2_lcr_t; 9147215976Sjmallett 9148215976Sjmallett/** 9149215976Sjmallett * cvmx_mio_uart2_lsr 9150215976Sjmallett */ 9151232812Sjmallettunion cvmx_mio_uart2_lsr { 9152215976Sjmallett uint64_t u64; 9153232812Sjmallett struct cvmx_mio_uart2_lsr_s { 9154232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9155215976Sjmallett uint64_t reserved_8_63 : 56; 9156215976Sjmallett uint64_t ferr : 1; /**< Error in Receiver FIFO bit */ 9157215976Sjmallett uint64_t temt : 1; /**< Transmitter Empty bit */ 9158215976Sjmallett uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */ 9159215976Sjmallett uint64_t bi : 1; /**< Break Interrupt bit */ 9160215976Sjmallett uint64_t fe : 1; /**< Framing Error bit */ 9161215976Sjmallett uint64_t pe : 1; /**< Parity Error bit */ 9162215976Sjmallett uint64_t oe : 1; /**< Overrun Error bit */ 9163215976Sjmallett uint64_t dr : 1; /**< Data Ready bit */ 9164215976Sjmallett#else 9165215976Sjmallett uint64_t dr : 1; 9166215976Sjmallett uint64_t oe : 1; 9167215976Sjmallett uint64_t pe : 1; 9168215976Sjmallett uint64_t fe : 1; 9169215976Sjmallett uint64_t bi : 1; 9170215976Sjmallett uint64_t thre : 1; 9171215976Sjmallett uint64_t temt : 1; 9172215976Sjmallett uint64_t ferr : 1; 9173215976Sjmallett uint64_t reserved_8_63 : 56; 9174215976Sjmallett#endif 9175215976Sjmallett } s; 9176215976Sjmallett struct cvmx_mio_uart2_lsr_s cn52xx; 9177215976Sjmallett struct cvmx_mio_uart2_lsr_s cn52xxp1; 9178215976Sjmallett}; 9179215976Sjmalletttypedef union cvmx_mio_uart2_lsr cvmx_mio_uart2_lsr_t; 9180215976Sjmallett 9181215976Sjmallett/** 9182215976Sjmallett * cvmx_mio_uart2_mcr 9183215976Sjmallett */ 9184232812Sjmallettunion cvmx_mio_uart2_mcr { 9185215976Sjmallett uint64_t u64; 9186232812Sjmallett struct cvmx_mio_uart2_mcr_s { 9187232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9188215976Sjmallett uint64_t reserved_6_63 : 58; 9189215976Sjmallett uint64_t afce : 1; /**< Auto Flow Control Enable bit */ 9190215976Sjmallett uint64_t loop : 1; /**< Loopback bit */ 9191215976Sjmallett uint64_t out2 : 1; /**< OUT2 output bit */ 9192215976Sjmallett uint64_t out1 : 1; /**< OUT1 output bit */ 9193215976Sjmallett uint64_t rts : 1; /**< Request To Send output bit */ 9194215976Sjmallett uint64_t dtr : 1; /**< Data Terminal Ready output bit */ 9195215976Sjmallett#else 9196215976Sjmallett uint64_t dtr : 1; 9197215976Sjmallett uint64_t rts : 1; 9198215976Sjmallett uint64_t out1 : 1; 9199215976Sjmallett uint64_t out2 : 1; 9200215976Sjmallett uint64_t loop : 1; 9201215976Sjmallett uint64_t afce : 1; 9202215976Sjmallett uint64_t reserved_6_63 : 58; 9203215976Sjmallett#endif 9204215976Sjmallett } s; 9205215976Sjmallett struct cvmx_mio_uart2_mcr_s cn52xx; 9206215976Sjmallett struct cvmx_mio_uart2_mcr_s cn52xxp1; 9207215976Sjmallett}; 9208215976Sjmalletttypedef union cvmx_mio_uart2_mcr cvmx_mio_uart2_mcr_t; 9209215976Sjmallett 9210215976Sjmallett/** 9211215976Sjmallett * cvmx_mio_uart2_msr 9212215976Sjmallett */ 9213232812Sjmallettunion cvmx_mio_uart2_msr { 9214215976Sjmallett uint64_t u64; 9215232812Sjmallett struct cvmx_mio_uart2_msr_s { 9216232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9217215976Sjmallett uint64_t reserved_8_63 : 56; 9218215976Sjmallett uint64_t dcd : 1; /**< Data Carrier Detect input bit */ 9219215976Sjmallett uint64_t ri : 1; /**< Ring Indicator input bit */ 9220215976Sjmallett uint64_t dsr : 1; /**< Data Set Ready input bit */ 9221215976Sjmallett uint64_t cts : 1; /**< Clear To Send input bit */ 9222215976Sjmallett uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */ 9223215976Sjmallett uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */ 9224215976Sjmallett uint64_t ddsr : 1; /**< Delta Data Set Ready bit */ 9225215976Sjmallett uint64_t dcts : 1; /**< Delta Clear To Send bit */ 9226215976Sjmallett#else 9227215976Sjmallett uint64_t dcts : 1; 9228215976Sjmallett uint64_t ddsr : 1; 9229215976Sjmallett uint64_t teri : 1; 9230215976Sjmallett uint64_t ddcd : 1; 9231215976Sjmallett uint64_t cts : 1; 9232215976Sjmallett uint64_t dsr : 1; 9233215976Sjmallett uint64_t ri : 1; 9234215976Sjmallett uint64_t dcd : 1; 9235215976Sjmallett uint64_t reserved_8_63 : 56; 9236215976Sjmallett#endif 9237215976Sjmallett } s; 9238215976Sjmallett struct cvmx_mio_uart2_msr_s cn52xx; 9239215976Sjmallett struct cvmx_mio_uart2_msr_s cn52xxp1; 9240215976Sjmallett}; 9241215976Sjmalletttypedef union cvmx_mio_uart2_msr cvmx_mio_uart2_msr_t; 9242215976Sjmallett 9243215976Sjmallett/** 9244215976Sjmallett * cvmx_mio_uart2_rbr 9245215976Sjmallett */ 9246232812Sjmallettunion cvmx_mio_uart2_rbr { 9247215976Sjmallett uint64_t u64; 9248232812Sjmallett struct cvmx_mio_uart2_rbr_s { 9249232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9250215976Sjmallett uint64_t reserved_8_63 : 56; 9251215976Sjmallett uint64_t rbr : 8; /**< Receive Buffer Register */ 9252215976Sjmallett#else 9253215976Sjmallett uint64_t rbr : 8; 9254215976Sjmallett uint64_t reserved_8_63 : 56; 9255215976Sjmallett#endif 9256215976Sjmallett } s; 9257215976Sjmallett struct cvmx_mio_uart2_rbr_s cn52xx; 9258215976Sjmallett struct cvmx_mio_uart2_rbr_s cn52xxp1; 9259215976Sjmallett}; 9260215976Sjmalletttypedef union cvmx_mio_uart2_rbr cvmx_mio_uart2_rbr_t; 9261215976Sjmallett 9262215976Sjmallett/** 9263215976Sjmallett * cvmx_mio_uart2_rfl 9264215976Sjmallett */ 9265232812Sjmallettunion cvmx_mio_uart2_rfl { 9266215976Sjmallett uint64_t u64; 9267232812Sjmallett struct cvmx_mio_uart2_rfl_s { 9268232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9269215976Sjmallett uint64_t reserved_7_63 : 57; 9270215976Sjmallett uint64_t rfl : 7; /**< Receive FIFO Level Register */ 9271215976Sjmallett#else 9272215976Sjmallett uint64_t rfl : 7; 9273215976Sjmallett uint64_t reserved_7_63 : 57; 9274215976Sjmallett#endif 9275215976Sjmallett } s; 9276215976Sjmallett struct cvmx_mio_uart2_rfl_s cn52xx; 9277215976Sjmallett struct cvmx_mio_uart2_rfl_s cn52xxp1; 9278215976Sjmallett}; 9279215976Sjmalletttypedef union cvmx_mio_uart2_rfl cvmx_mio_uart2_rfl_t; 9280215976Sjmallett 9281215976Sjmallett/** 9282215976Sjmallett * cvmx_mio_uart2_rfw 9283215976Sjmallett */ 9284232812Sjmallettunion cvmx_mio_uart2_rfw { 9285215976Sjmallett uint64_t u64; 9286232812Sjmallett struct cvmx_mio_uart2_rfw_s { 9287232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9288215976Sjmallett uint64_t reserved_10_63 : 54; 9289215976Sjmallett uint64_t rffe : 1; /**< Receive FIFO Framing Error */ 9290215976Sjmallett uint64_t rfpe : 1; /**< Receive FIFO Parity Error */ 9291215976Sjmallett uint64_t rfwd : 8; /**< Receive FIFO Write Data */ 9292215976Sjmallett#else 9293215976Sjmallett uint64_t rfwd : 8; 9294215976Sjmallett uint64_t rfpe : 1; 9295215976Sjmallett uint64_t rffe : 1; 9296215976Sjmallett uint64_t reserved_10_63 : 54; 9297215976Sjmallett#endif 9298215976Sjmallett } s; 9299215976Sjmallett struct cvmx_mio_uart2_rfw_s cn52xx; 9300215976Sjmallett struct cvmx_mio_uart2_rfw_s cn52xxp1; 9301215976Sjmallett}; 9302215976Sjmalletttypedef union cvmx_mio_uart2_rfw cvmx_mio_uart2_rfw_t; 9303215976Sjmallett 9304215976Sjmallett/** 9305215976Sjmallett * cvmx_mio_uart2_sbcr 9306215976Sjmallett */ 9307232812Sjmallettunion cvmx_mio_uart2_sbcr { 9308215976Sjmallett uint64_t u64; 9309232812Sjmallett struct cvmx_mio_uart2_sbcr_s { 9310232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9311215976Sjmallett uint64_t reserved_1_63 : 63; 9312215976Sjmallett uint64_t sbcr : 1; /**< Shadow Break Control */ 9313215976Sjmallett#else 9314215976Sjmallett uint64_t sbcr : 1; 9315215976Sjmallett uint64_t reserved_1_63 : 63; 9316215976Sjmallett#endif 9317215976Sjmallett } s; 9318215976Sjmallett struct cvmx_mio_uart2_sbcr_s cn52xx; 9319215976Sjmallett struct cvmx_mio_uart2_sbcr_s cn52xxp1; 9320215976Sjmallett}; 9321215976Sjmalletttypedef union cvmx_mio_uart2_sbcr cvmx_mio_uart2_sbcr_t; 9322215976Sjmallett 9323215976Sjmallett/** 9324215976Sjmallett * cvmx_mio_uart2_scr 9325215976Sjmallett */ 9326232812Sjmallettunion cvmx_mio_uart2_scr { 9327215976Sjmallett uint64_t u64; 9328232812Sjmallett struct cvmx_mio_uart2_scr_s { 9329232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9330215976Sjmallett uint64_t reserved_8_63 : 56; 9331215976Sjmallett uint64_t scr : 8; /**< Scratchpad Register */ 9332215976Sjmallett#else 9333215976Sjmallett uint64_t scr : 8; 9334215976Sjmallett uint64_t reserved_8_63 : 56; 9335215976Sjmallett#endif 9336215976Sjmallett } s; 9337215976Sjmallett struct cvmx_mio_uart2_scr_s cn52xx; 9338215976Sjmallett struct cvmx_mio_uart2_scr_s cn52xxp1; 9339215976Sjmallett}; 9340215976Sjmalletttypedef union cvmx_mio_uart2_scr cvmx_mio_uart2_scr_t; 9341215976Sjmallett 9342215976Sjmallett/** 9343215976Sjmallett * cvmx_mio_uart2_sfe 9344215976Sjmallett */ 9345232812Sjmallettunion cvmx_mio_uart2_sfe { 9346215976Sjmallett uint64_t u64; 9347232812Sjmallett struct cvmx_mio_uart2_sfe_s { 9348232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9349215976Sjmallett uint64_t reserved_1_63 : 63; 9350215976Sjmallett uint64_t sfe : 1; /**< Shadow FIFO Enable */ 9351215976Sjmallett#else 9352215976Sjmallett uint64_t sfe : 1; 9353215976Sjmallett uint64_t reserved_1_63 : 63; 9354215976Sjmallett#endif 9355215976Sjmallett } s; 9356215976Sjmallett struct cvmx_mio_uart2_sfe_s cn52xx; 9357215976Sjmallett struct cvmx_mio_uart2_sfe_s cn52xxp1; 9358215976Sjmallett}; 9359215976Sjmalletttypedef union cvmx_mio_uart2_sfe cvmx_mio_uart2_sfe_t; 9360215976Sjmallett 9361215976Sjmallett/** 9362215976Sjmallett * cvmx_mio_uart2_srr 9363215976Sjmallett */ 9364232812Sjmallettunion cvmx_mio_uart2_srr { 9365215976Sjmallett uint64_t u64; 9366232812Sjmallett struct cvmx_mio_uart2_srr_s { 9367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9368215976Sjmallett uint64_t reserved_3_63 : 61; 9369215976Sjmallett uint64_t stfr : 1; /**< Shadow TX FIFO Reset */ 9370215976Sjmallett uint64_t srfr : 1; /**< Shadow RX FIFO Reset */ 9371215976Sjmallett uint64_t usr : 1; /**< UART Soft Reset */ 9372215976Sjmallett#else 9373215976Sjmallett uint64_t usr : 1; 9374215976Sjmallett uint64_t srfr : 1; 9375215976Sjmallett uint64_t stfr : 1; 9376215976Sjmallett uint64_t reserved_3_63 : 61; 9377215976Sjmallett#endif 9378215976Sjmallett } s; 9379215976Sjmallett struct cvmx_mio_uart2_srr_s cn52xx; 9380215976Sjmallett struct cvmx_mio_uart2_srr_s cn52xxp1; 9381215976Sjmallett}; 9382215976Sjmalletttypedef union cvmx_mio_uart2_srr cvmx_mio_uart2_srr_t; 9383215976Sjmallett 9384215976Sjmallett/** 9385215976Sjmallett * cvmx_mio_uart2_srt 9386215976Sjmallett */ 9387232812Sjmallettunion cvmx_mio_uart2_srt { 9388215976Sjmallett uint64_t u64; 9389232812Sjmallett struct cvmx_mio_uart2_srt_s { 9390232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9391215976Sjmallett uint64_t reserved_2_63 : 62; 9392215976Sjmallett uint64_t srt : 2; /**< Shadow RX Trigger */ 9393215976Sjmallett#else 9394215976Sjmallett uint64_t srt : 2; 9395215976Sjmallett uint64_t reserved_2_63 : 62; 9396215976Sjmallett#endif 9397215976Sjmallett } s; 9398215976Sjmallett struct cvmx_mio_uart2_srt_s cn52xx; 9399215976Sjmallett struct cvmx_mio_uart2_srt_s cn52xxp1; 9400215976Sjmallett}; 9401215976Sjmalletttypedef union cvmx_mio_uart2_srt cvmx_mio_uart2_srt_t; 9402215976Sjmallett 9403215976Sjmallett/** 9404215976Sjmallett * cvmx_mio_uart2_srts 9405215976Sjmallett */ 9406232812Sjmallettunion cvmx_mio_uart2_srts { 9407215976Sjmallett uint64_t u64; 9408232812Sjmallett struct cvmx_mio_uart2_srts_s { 9409232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9410215976Sjmallett uint64_t reserved_1_63 : 63; 9411215976Sjmallett uint64_t srts : 1; /**< Shadow Request To Send */ 9412215976Sjmallett#else 9413215976Sjmallett uint64_t srts : 1; 9414215976Sjmallett uint64_t reserved_1_63 : 63; 9415215976Sjmallett#endif 9416215976Sjmallett } s; 9417215976Sjmallett struct cvmx_mio_uart2_srts_s cn52xx; 9418215976Sjmallett struct cvmx_mio_uart2_srts_s cn52xxp1; 9419215976Sjmallett}; 9420215976Sjmalletttypedef union cvmx_mio_uart2_srts cvmx_mio_uart2_srts_t; 9421215976Sjmallett 9422215976Sjmallett/** 9423215976Sjmallett * cvmx_mio_uart2_stt 9424215976Sjmallett */ 9425232812Sjmallettunion cvmx_mio_uart2_stt { 9426215976Sjmallett uint64_t u64; 9427232812Sjmallett struct cvmx_mio_uart2_stt_s { 9428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9429215976Sjmallett uint64_t reserved_2_63 : 62; 9430215976Sjmallett uint64_t stt : 2; /**< Shadow TX Trigger */ 9431215976Sjmallett#else 9432215976Sjmallett uint64_t stt : 2; 9433215976Sjmallett uint64_t reserved_2_63 : 62; 9434215976Sjmallett#endif 9435215976Sjmallett } s; 9436215976Sjmallett struct cvmx_mio_uart2_stt_s cn52xx; 9437215976Sjmallett struct cvmx_mio_uart2_stt_s cn52xxp1; 9438215976Sjmallett}; 9439215976Sjmalletttypedef union cvmx_mio_uart2_stt cvmx_mio_uart2_stt_t; 9440215976Sjmallett 9441215976Sjmallett/** 9442215976Sjmallett * cvmx_mio_uart2_tfl 9443215976Sjmallett */ 9444232812Sjmallettunion cvmx_mio_uart2_tfl { 9445215976Sjmallett uint64_t u64; 9446232812Sjmallett struct cvmx_mio_uart2_tfl_s { 9447232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9448215976Sjmallett uint64_t reserved_7_63 : 57; 9449215976Sjmallett uint64_t tfl : 7; /**< Transmit FIFO Level Register */ 9450215976Sjmallett#else 9451215976Sjmallett uint64_t tfl : 7; 9452215976Sjmallett uint64_t reserved_7_63 : 57; 9453215976Sjmallett#endif 9454215976Sjmallett } s; 9455215976Sjmallett struct cvmx_mio_uart2_tfl_s cn52xx; 9456215976Sjmallett struct cvmx_mio_uart2_tfl_s cn52xxp1; 9457215976Sjmallett}; 9458215976Sjmalletttypedef union cvmx_mio_uart2_tfl cvmx_mio_uart2_tfl_t; 9459215976Sjmallett 9460215976Sjmallett/** 9461215976Sjmallett * cvmx_mio_uart2_tfr 9462215976Sjmallett */ 9463232812Sjmallettunion cvmx_mio_uart2_tfr { 9464215976Sjmallett uint64_t u64; 9465232812Sjmallett struct cvmx_mio_uart2_tfr_s { 9466232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9467215976Sjmallett uint64_t reserved_8_63 : 56; 9468215976Sjmallett uint64_t tfr : 8; /**< Transmit FIFO Read Register */ 9469215976Sjmallett#else 9470215976Sjmallett uint64_t tfr : 8; 9471215976Sjmallett uint64_t reserved_8_63 : 56; 9472215976Sjmallett#endif 9473215976Sjmallett } s; 9474215976Sjmallett struct cvmx_mio_uart2_tfr_s cn52xx; 9475215976Sjmallett struct cvmx_mio_uart2_tfr_s cn52xxp1; 9476215976Sjmallett}; 9477215976Sjmalletttypedef union cvmx_mio_uart2_tfr cvmx_mio_uart2_tfr_t; 9478215976Sjmallett 9479215976Sjmallett/** 9480215976Sjmallett * cvmx_mio_uart2_thr 9481215976Sjmallett */ 9482232812Sjmallettunion cvmx_mio_uart2_thr { 9483215976Sjmallett uint64_t u64; 9484232812Sjmallett struct cvmx_mio_uart2_thr_s { 9485232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9486215976Sjmallett uint64_t reserved_8_63 : 56; 9487215976Sjmallett uint64_t thr : 8; /**< Transmit Holding Register */ 9488215976Sjmallett#else 9489215976Sjmallett uint64_t thr : 8; 9490215976Sjmallett uint64_t reserved_8_63 : 56; 9491215976Sjmallett#endif 9492215976Sjmallett } s; 9493215976Sjmallett struct cvmx_mio_uart2_thr_s cn52xx; 9494215976Sjmallett struct cvmx_mio_uart2_thr_s cn52xxp1; 9495215976Sjmallett}; 9496215976Sjmalletttypedef union cvmx_mio_uart2_thr cvmx_mio_uart2_thr_t; 9497215976Sjmallett 9498215976Sjmallett/** 9499215976Sjmallett * cvmx_mio_uart2_usr 9500215976Sjmallett */ 9501232812Sjmallettunion cvmx_mio_uart2_usr { 9502215976Sjmallett uint64_t u64; 9503232812Sjmallett struct cvmx_mio_uart2_usr_s { 9504232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 9505215976Sjmallett uint64_t reserved_5_63 : 59; 9506215976Sjmallett uint64_t rff : 1; /**< RX FIFO Full */ 9507215976Sjmallett uint64_t rfne : 1; /**< RX FIFO Not Empty */ 9508215976Sjmallett uint64_t tfe : 1; /**< TX FIFO Empty */ 9509215976Sjmallett uint64_t tfnf : 1; /**< TX FIFO Not Full */ 9510215976Sjmallett uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */ 9511215976Sjmallett#else 9512215976Sjmallett uint64_t busy : 1; 9513215976Sjmallett uint64_t tfnf : 1; 9514215976Sjmallett uint64_t tfe : 1; 9515215976Sjmallett uint64_t rfne : 1; 9516215976Sjmallett uint64_t rff : 1; 9517215976Sjmallett uint64_t reserved_5_63 : 59; 9518215976Sjmallett#endif 9519215976Sjmallett } s; 9520215976Sjmallett struct cvmx_mio_uart2_usr_s cn52xx; 9521215976Sjmallett struct cvmx_mio_uart2_usr_s cn52xxp1; 9522215976Sjmallett}; 9523215976Sjmalletttypedef union cvmx_mio_uart2_usr cvmx_mio_uart2_usr_t; 9524215976Sjmallett 9525215976Sjmallett#endif 9526