1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Support functions for managing the MII management port 50 * 51 * <hr>$Revision: 70030 $<hr> 52 */ 53#include "cvmx.h" 54#include "cvmx-bootmem.h" 55#include "cvmx-spinlock.h" 56#include "cvmx-mdio.h" 57#include "cvmx-mgmt-port.h" 58#include "cvmx-sysinfo.h" 59#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL) 60#include "cvmx-error.h" 61#endif 62 63/** 64 * Enum of MIX interface modes 65 */ 66typedef enum 67{ 68 CVMX_MGMT_PORT_NONE = 0, 69 CVMX_MGMT_PORT_MII_MODE, 70 CVMX_MGMT_PORT_RGMII_MODE, 71} cvmx_mgmt_port_mode_t; 72 73/** 74 * Format of the TX/RX ring buffer entries 75 */ 76typedef union 77{ 78 uint64_t u64; 79 struct 80 { 81 uint64_t reserved_62_63 : 2; 82 uint64_t len : 14; /* Length of the buffer/packet in bytes */ 83 uint64_t tstamp : 1; /* For TX, signals that the packet should be timestamped */ 84 uint64_t code : 7; /* The RX error code */ 85 uint64_t addr : 40; /* Physical address of the buffer */ 86 } s; 87} cvmx_mgmt_port_ring_entry_t; 88 89/** 90 * Per port state required for each mgmt port 91 */ 92typedef struct 93{ 94 cvmx_spinlock_t lock; /* Used for exclusive access to this structure */ 95 int tx_write_index; /* Where the next TX will write in the tx_ring and tx_buffers */ 96 int rx_read_index; /* Where the next RX will be in the rx_ring and rx_buffers */ 97 int port; /* Port to use. (This is the 'fake' IPD port number */ 98 uint64_t mac; /* Our MAC address */ 99 cvmx_mgmt_port_ring_entry_t tx_ring[CVMX_MGMT_PORT_NUM_TX_BUFFERS]; 100 cvmx_mgmt_port_ring_entry_t rx_ring[CVMX_MGMT_PORT_NUM_RX_BUFFERS]; 101 char tx_buffers[CVMX_MGMT_PORT_NUM_TX_BUFFERS][CVMX_MGMT_PORT_TX_BUFFER_SIZE]; 102 char rx_buffers[CVMX_MGMT_PORT_NUM_RX_BUFFERS][CVMX_MGMT_PORT_RX_BUFFER_SIZE]; 103 cvmx_mgmt_port_mode_t mode; /* Mode of the interface */ 104} cvmx_mgmt_port_state_t; 105 106/** 107 * Pointers to each mgmt port's state 108 */ 109CVMX_SHARED cvmx_mgmt_port_state_t *cvmx_mgmt_port_state_ptr = NULL; 110 111 112/** 113 * Return the number of management ports supported by this chip 114 * 115 * @return Number of ports 116 */ 117static int __cvmx_mgmt_port_num_ports(void) 118{ 119#if defined(OCTEON_VENDOR_GEFES) 120 return 0; /* none of the GEFES boards have mgmt ports */ 121#else 122 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) 123 return 1; 124 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX)) 125 return 2; 126 else 127 return 0; 128#endif 129} 130 131 132/** 133 * Return the number of management ports supported on this board. 134 * 135 * @return Number of ports 136 */ 137int cvmx_mgmt_port_num_ports(void) 138{ 139 return __cvmx_mgmt_port_num_ports(); 140} 141 142 143/** 144 * Called to initialize a management port for use. Multiple calls 145 * to this function across applications is safe. 146 * 147 * @param port Port to initialize 148 * 149 * @return CVMX_MGMT_PORT_SUCCESS or an error code 150 */ 151cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port) 152{ 153 char *alloc_name = "cvmx_mgmt_port"; 154 cvmx_mixx_oring1_t oring1; 155 cvmx_mixx_ctl_t mix_ctl; 156 157 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 158 return CVMX_MGMT_PORT_INVALID_PARAM; 159 160 cvmx_mgmt_port_state_ptr = cvmx_bootmem_alloc_named_flags(CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t), 128, alloc_name, CVMX_BOOTMEM_FLAG_END_ALLOC); 161 if (cvmx_mgmt_port_state_ptr) 162 { 163 memset(cvmx_mgmt_port_state_ptr, 0, CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t)); 164 } 165 else 166 { 167 const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name); 168 if (block_desc) 169 cvmx_mgmt_port_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr); 170 else 171 { 172 cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Unable to get named block %s on MIX%d.\n", alloc_name, port); 173 return CVMX_MGMT_PORT_NO_MEMORY; 174 } 175 } 176 177 /* Reset the MIX block if the previous user had a different TX ring size, or if 178 ** we allocated a new (and blank) state structure. */ 179 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 180 if (!mix_ctl.s.reset) 181 { 182 oring1.u64 = cvmx_read_csr(CVMX_MIXX_ORING1(port)); 183 if (oring1.s.osize != CVMX_MGMT_PORT_NUM_TX_BUFFERS || cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0) 184 { 185 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 186 mix_ctl.s.en = 0; 187 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 188 do 189 { 190 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 191 } while (mix_ctl.s.busy); 192 mix_ctl.s.reset = 1; 193 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 194 cvmx_read_csr(CVMX_MIXX_CTL(port)); 195 memset(cvmx_mgmt_port_state_ptr + port, 0, sizeof(cvmx_mgmt_port_state_t)); 196 } 197 } 198 199 if (cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0) 200 { 201 cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port; 202 int i; 203 cvmx_mixx_bist_t mix_bist; 204 cvmx_agl_gmx_bist_t agl_gmx_bist; 205 cvmx_mixx_oring1_t oring1; 206 cvmx_mixx_iring1_t iring1; 207 cvmx_mixx_ctl_t mix_ctl; 208 cvmx_agl_prtx_ctl_t agl_prtx_ctl; 209 210 /* Make sure BIST passed */ 211 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(port)); 212 if (mix_bist.u64) 213 cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port MIX failed BIST (0x%016llx) on MIX%d\n", CAST64(mix_bist.u64), port); 214 215 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST); 216 if (agl_gmx_bist.u64) 217 cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port AGL failed BIST (0x%016llx) on MIX%d\n", CAST64(agl_gmx_bist.u64), port); 218 219 /* Clear all state information */ 220 memset(state, 0, sizeof(*state)); 221 222 /* Take the control logic out of reset */ 223 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 224 mix_ctl.s.reset = 0; 225 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 226 227 /* Read until reset == 0. Timeout should never happen... */ 228 if (CVMX_WAIT_FOR_FIELD64(CVMX_MIXX_CTL(port), cvmx_mixx_ctl_t, reset, ==, 0, 300000000)) 229 { 230 cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Timeout waiting for MIX(%d) reset.\n", port); 231 return CVMX_MGMT_PORT_INIT_ERROR; 232 } 233 234 /* Set the PHY address and mode of the interface (RGMII/MII mode). */ 235 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) 236 { 237 state->port = -1; 238 state->mode = CVMX_MGMT_PORT_MII_MODE; 239 } 240 else 241 { 242 int port_num = CVMX_HELPER_BOARD_MGMT_IPD_PORT + port; 243 int phy_addr = cvmx_helper_board_get_mii_address(port_num); 244 if (phy_addr != -1) 245 { 246 cvmx_mdio_phy_reg_status_t phy_status; 247 /* Read PHY status register to find the mode of the interface. */ 248 phy_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS); 249 if (phy_status.s.capable_extended_status == 0) // MII mode 250 state->mode = CVMX_MGMT_PORT_MII_MODE; 251 else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) 252 && phy_status.s.capable_extended_status) // RGMII mode 253 state->mode = CVMX_MGMT_PORT_RGMII_MODE; 254 else 255 state->mode = CVMX_MGMT_PORT_NONE; 256 } 257 else 258 { 259 cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Not able to read the PHY on MIX%d\n", port); 260 return CVMX_MGMT_PORT_INVALID_PARAM; 261 } 262 state->port = port_num; 263 } 264 265 /* All interfaces should be configured in same mode */ 266 for (i = 0; i < __cvmx_mgmt_port_num_ports(); i++) 267 { 268 if (i != port 269 && cvmx_mgmt_port_state_ptr[i].mode != CVMX_MGMT_PORT_NONE 270 && cvmx_mgmt_port_state_ptr[i].mode != state->mode) 271 { 272 cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: All ports in MIX interface are not configured in same mode.\n \ 273 Port %d is configured as %d\n \ 274 And Port %d is configured as %d\n", port, state->mode, i, cvmx_mgmt_port_state_ptr[i].mode); 275 return CVMX_MGMT_PORT_INVALID_PARAM; 276 } 277 } 278 279 /* Create a default MAC address */ 280 state->mac = 0x000000dead000000ull; 281 state->mac += 0xffffff & CAST64(state); 282 283 /* Setup the TX ring */ 284 for (i=0; i<CVMX_MGMT_PORT_NUM_TX_BUFFERS; i++) 285 { 286 state->tx_ring[i].s.len = CVMX_MGMT_PORT_TX_BUFFER_SIZE; 287 state->tx_ring[i].s.addr = cvmx_ptr_to_phys(state->tx_buffers[i]); 288 } 289 290 /* Tell the HW where the TX ring is */ 291 oring1.u64 = 0; 292 oring1.s.obase = cvmx_ptr_to_phys(state->tx_ring)>>3; 293 oring1.s.osize = CVMX_MGMT_PORT_NUM_TX_BUFFERS; 294 CVMX_SYNCWS; 295 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); 296 297 /* Setup the RX ring */ 298 for (i=0; i<CVMX_MGMT_PORT_NUM_RX_BUFFERS; i++) 299 { 300 /* This size is -8 due to an errata for CN56XX pass 1 */ 301 state->rx_ring[i].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8; 302 state->rx_ring[i].s.addr = cvmx_ptr_to_phys(state->rx_buffers[i]); 303 } 304 305 /* Tell the HW where the RX ring is */ 306 iring1.u64 = 0; 307 iring1.s.ibase = cvmx_ptr_to_phys(state->rx_ring)>>3; 308 iring1.s.isize = CVMX_MGMT_PORT_NUM_RX_BUFFERS; 309 CVMX_SYNCWS; 310 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); 311 cvmx_write_csr(CVMX_MIXX_IRING2(port), CVMX_MGMT_PORT_NUM_RX_BUFFERS); 312 313 /* Disable the external input/output */ 314 cvmx_mgmt_port_disable(port); 315 316 /* Set the MAC address filtering up */ 317 cvmx_mgmt_port_set_mac(port, state->mac); 318 319 /* Set the default max size to an MTU of 1500 with L2 and VLAN */ 320 cvmx_mgmt_port_set_max_packet_size(port, 1518); 321 322 /* Enable the port HW. Packets are not allowed until cvmx_mgmt_port_enable() is called */ 323 mix_ctl.u64 = 0; 324 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ 325 mix_ctl.s.en = 1; /* Enable the port */ 326 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ 327 mix_ctl.s.mrq_hwm = 1; /* MII CB-request FIFO programmable high watermark */ 328 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 329 330 /* Select the mode of operation for the interface. */ 331 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 332 { 333 agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); 334 335 if (state->mode == CVMX_MGMT_PORT_RGMII_MODE) 336 agl_prtx_ctl.s.mode = 0; 337 else if (state->mode == CVMX_MGMT_PORT_MII_MODE) 338 agl_prtx_ctl.s.mode = 1; 339 else 340 { 341 cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Invalid mode for MIX(%d)\n", port); 342 return CVMX_MGMT_PORT_INVALID_PARAM; 343 } 344 345 cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 346 } 347 348 /* Initialize the physical layer. */ 349 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 350 { 351 /* MII clocks counts are based on the 125Mhz reference, so our 352 delays need to be scaled to match the core clock rate. The 353 "+1" is to make sure rounding always waits a little too 354 long. */ 355 uint64_t clock_scale = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 125000000 + 1; 356 357 /* Take the DLL and clock tree out of reset */ 358 agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); 359 agl_prtx_ctl.s.clkrst = 0; 360 if (state->mode == CVMX_MGMT_PORT_RGMII_MODE) // RGMII Initialization 361 { 362 agl_prtx_ctl.s.dllrst = 0; 363 agl_prtx_ctl.s.clktx_byp = 0; 364 } 365 cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 366 cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); /* Force write out before wait */ 367 368 /* Wait for the DLL to lock. External 125 MHz reference clock must be stable at this point. */ 369 cvmx_wait(256 * clock_scale); 370 371 /* The rest of the config is common between RGMII/MII */ 372 373 /* Enable the interface */ 374 agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); 375 agl_prtx_ctl.s.enable = 1; 376 cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 377 378 /* Read the value back to force the previous write */ 379 agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); 380 381 /* Enable the componsation controller */ 382 agl_prtx_ctl.s.comp = 1; 383 agl_prtx_ctl.s.drv_byp = 0; 384 cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64); 385 cvmx_read_csr(CVMX_AGL_PRTX_CTL(port)); /* Force write out before wait */ 386 cvmx_wait(1024 * clock_scale); // for componsation state to lock. 387 } 388 else if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) 389 { 390 /* Force compensation values, as they are not determined properly by HW */ 391 cvmx_agl_gmx_drv_ctl_t drv_ctl; 392 393 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL); 394 if (port) 395 { 396 drv_ctl.s.byp_en1 = 1; 397 drv_ctl.s.nctl1 = 6; 398 drv_ctl.s.pctl1 = 6; 399 } 400 else 401 { 402 drv_ctl.s.byp_en = 1; 403 drv_ctl.s.nctl = 6; 404 drv_ctl.s.pctl = 6; 405 } 406 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64); 407 } 408 } 409#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL) 410 cvmx_error_enable_group(CVMX_ERROR_GROUP_MGMT_PORT, port); 411#endif 412 return CVMX_MGMT_PORT_SUCCESS; 413} 414 415 416/** 417 * Shutdown a management port. This currently disables packet IO 418 * but leaves all hardware and buffers. Another application can then 419 * call initialize() without redoing the hardware setup. 420 * 421 * @param port Management port 422 * 423 * @return CVMX_MGMT_PORT_SUCCESS or an error code 424 */ 425cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port) 426{ 427 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 428 return CVMX_MGMT_PORT_INVALID_PARAM; 429 430#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL) 431 cvmx_error_disable_group(CVMX_ERROR_GROUP_MGMT_PORT, port); 432#endif 433 434 /* Stop packets from comming in */ 435 cvmx_mgmt_port_disable(port); 436 437 /* We don't free any memory so the next intialize can reuse the HW setup */ 438 return CVMX_MGMT_PORT_SUCCESS; 439} 440 441 442/** 443 * Enable packet IO on a management port 444 * 445 * @param port Management port 446 * 447 * @return CVMX_MGMT_PORT_SUCCESS or an error code 448 */ 449cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port) 450{ 451 cvmx_mgmt_port_state_t *state; 452 cvmx_agl_gmx_inf_mode_t agl_gmx_inf_mode; 453 cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl; 454 455 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 456 return CVMX_MGMT_PORT_INVALID_PARAM; 457 458 state = cvmx_mgmt_port_state_ptr + port; 459 460 cvmx_spinlock_lock(&state->lock); 461 462 rxx_frm_ctl.u64 = 0; 463 rxx_frm_ctl.s.pre_align = 1; 464 rxx_frm_ctl.s.pad_len = 1; /* When set, disables the length check for non-min sized pkts with padding in the client data */ 465 rxx_frm_ctl.s.vlan_len = 1; /* When set, disables the length check for VLAN pkts */ 466 rxx_frm_ctl.s.pre_free = 1; /* When set, PREAMBLE checking is less strict */ 467 rxx_frm_ctl.s.ctl_smac = 0; /* Control Pause Frames can match station SMAC */ 468 rxx_frm_ctl.s.ctl_mcst = 1; /* Control Pause Frames can match globally assign Multicast address */ 469 rxx_frm_ctl.s.ctl_bck = 1; /* Forward pause information to TX block */ 470 rxx_frm_ctl.s.ctl_drp = 1; /* Drop Control Pause Frames */ 471 rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */ 472 rxx_frm_ctl.s.pre_chk = 1; /* This port is configured to send PREAMBLE+SFD to begin every frame. GMX checks that the PREAMBLE is sent correctly */ 473 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); 474 475 /* Enable the AGL block */ 476 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) 477 { 478 agl_gmx_inf_mode.u64 = 0; 479 agl_gmx_inf_mode.s.en = 1; 480 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); 481 } 482 483 /* Configure the port duplex and enables */ 484 cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port)); 485 486 cvmx_spinlock_unlock(&state->lock); 487 return CVMX_MGMT_PORT_SUCCESS; 488} 489 490 491/** 492 * Disable packet IO on a management port 493 * 494 * @param port Management port 495 * 496 * @return CVMX_MGMT_PORT_SUCCESS or an error code 497 */ 498cvmx_mgmt_port_result_t cvmx_mgmt_port_disable(int port) 499{ 500 cvmx_mgmt_port_state_t *state; 501 cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx; 502 503 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 504 return CVMX_MGMT_PORT_INVALID_PARAM; 505 506 state = cvmx_mgmt_port_state_ptr + port; 507 508 cvmx_spinlock_lock(&state->lock); 509 510 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 511 agl_gmx_prtx.s.en = 0; 512 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 513 514 cvmx_spinlock_unlock(&state->lock); 515 return CVMX_MGMT_PORT_SUCCESS; 516} 517 518 519/** 520 * Send a packet out the management port. The packet is copied so 521 * the input buffer isn't used after this call. 522 * 523 * @param port Management port 524 * @param packet_len Length of the packet to send. It does not include the final CRC 525 * @param buffer Packet data 526 * 527 * @return CVMX_MGMT_PORT_SUCCESS or an error code 528 */ 529cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, void *buffer) 530{ 531 cvmx_mgmt_port_state_t *state; 532 cvmx_mixx_oring2_t mix_oring2; 533 534 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 535 return CVMX_MGMT_PORT_INVALID_PARAM; 536 537 /* Max sure the packet size is valid */ 538 if ((packet_len < 1) || (packet_len > CVMX_MGMT_PORT_TX_BUFFER_SIZE)) 539 return CVMX_MGMT_PORT_INVALID_PARAM; 540 541 if (buffer == NULL) 542 return CVMX_MGMT_PORT_INVALID_PARAM; 543 544 state = cvmx_mgmt_port_state_ptr + port; 545 546 cvmx_spinlock_lock(&state->lock); 547 548 mix_oring2.u64 = cvmx_read_csr(CVMX_MIXX_ORING2(port)); 549 if (mix_oring2.s.odbell >= CVMX_MGMT_PORT_NUM_TX_BUFFERS - 1) 550 { 551 /* No room for another packet */ 552 cvmx_spinlock_unlock(&state->lock); 553 return CVMX_MGMT_PORT_NO_MEMORY; 554 } 555 else 556 { 557 /* Copy the packet into the output buffer */ 558 memcpy(state->tx_buffers[state->tx_write_index], buffer, packet_len); 559 /* Insert the source MAC */ 560 memcpy(state->tx_buffers[state->tx_write_index] + 6, ((char*)&state->mac) + 2, 6); 561 /* Update the TX ring buffer entry size */ 562 state->tx_ring[state->tx_write_index].s.len = packet_len; 563 /* This code doesn't support TX timestamps */ 564 state->tx_ring[state->tx_write_index].s.tstamp = 0; 565 /* Increment our TX index */ 566 state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS; 567 /* Ring the doorbell, sending the packet */ 568 CVMX_SYNCWS; 569 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); 570 if (cvmx_read_csr(CVMX_MIXX_ORCNT(port))) 571 cvmx_write_csr(CVMX_MIXX_ORCNT(port), cvmx_read_csr(CVMX_MIXX_ORCNT(port))); 572 573 cvmx_spinlock_unlock(&state->lock); 574 return CVMX_MGMT_PORT_SUCCESS; 575 } 576} 577 578 579#if defined(__FreeBSD__) 580/** 581 * Send a packet out the management port. The packet is copied so 582 * the input mbuf isn't used after this call. 583 * 584 * @param port Management port 585 * @param m Packet mbuf (with pkthdr) 586 * 587 * @return CVMX_MGMT_PORT_SUCCESS or an error code 588 */ 589cvmx_mgmt_port_result_t cvmx_mgmt_port_sendm(int port, const struct mbuf *m) 590{ 591 cvmx_mgmt_port_state_t *state; 592 cvmx_mixx_oring2_t mix_oring2; 593 594 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 595 return CVMX_MGMT_PORT_INVALID_PARAM; 596 597 /* Max sure the packet size is valid */ 598 if ((m->m_pkthdr.len < 1) || (m->m_pkthdr.len > CVMX_MGMT_PORT_TX_BUFFER_SIZE)) 599 return CVMX_MGMT_PORT_INVALID_PARAM; 600 601 state = cvmx_mgmt_port_state_ptr + port; 602 603 cvmx_spinlock_lock(&state->lock); 604 605 mix_oring2.u64 = cvmx_read_csr(CVMX_MIXX_ORING2(port)); 606 if (mix_oring2.s.odbell >= CVMX_MGMT_PORT_NUM_TX_BUFFERS - 1) 607 { 608 /* No room for another packet */ 609 cvmx_spinlock_unlock(&state->lock); 610 return CVMX_MGMT_PORT_NO_MEMORY; 611 } 612 else 613 { 614 /* Copy the packet into the output buffer */ 615 m_copydata(m, 0, m->m_pkthdr.len, state->tx_buffers[state->tx_write_index]); 616 /* Update the TX ring buffer entry size */ 617 state->tx_ring[state->tx_write_index].s.len = m->m_pkthdr.len; 618 /* This code doesn't support TX timestamps */ 619 state->tx_ring[state->tx_write_index].s.tstamp = 0; 620 /* Increment our TX index */ 621 state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS; 622 /* Ring the doorbell, sending the packet */ 623 CVMX_SYNCWS; 624 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); 625 if (cvmx_read_csr(CVMX_MIXX_ORCNT(port))) 626 cvmx_write_csr(CVMX_MIXX_ORCNT(port), cvmx_read_csr(CVMX_MIXX_ORCNT(port))); 627 628 cvmx_spinlock_unlock(&state->lock); 629 return CVMX_MGMT_PORT_SUCCESS; 630 } 631} 632#endif 633 634 635/** 636 * Receive a packet from the management port. 637 * 638 * @param port Management port 639 * @param buffer_len Size of the buffer to receive the packet into 640 * @param buffer Buffer to receive the packet into 641 * 642 * @return The size of the packet, or a negative erorr code on failure. Zero 643 * means that no packets were available. 644 */ 645int cvmx_mgmt_port_receive(int port, int buffer_len, uint8_t *buffer) 646{ 647 cvmx_mixx_ircnt_t mix_ircnt; 648 cvmx_mgmt_port_state_t *state; 649 int result; 650 651 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 652 return CVMX_MGMT_PORT_INVALID_PARAM; 653 654 /* Max sure the buffer size is valid */ 655 if (buffer_len < 1) 656 return CVMX_MGMT_PORT_INVALID_PARAM; 657 658 if (buffer == NULL) 659 return CVMX_MGMT_PORT_INVALID_PARAM; 660 661 state = cvmx_mgmt_port_state_ptr + port; 662 663 cvmx_spinlock_lock(&state->lock); 664 665 /* Find out how many RX packets are pending */ 666 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); 667 if (mix_ircnt.s.ircnt) 668 { 669 uint64_t *source = (void *)state->rx_buffers[state->rx_read_index]; 670 uint64_t *zero_check = source; 671 /* CN56XX pass 1 has an errata where packets might start 8 bytes 672 into the buffer instead of at their correct lcoation. If the 673 first 8 bytes is zero we assume this has happened */ 674 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && (*zero_check == 0)) 675 source++; 676 /* Start off with zero bytes received */ 677 result = 0; 678 /* While the completion code signals more data, copy the buffers 679 into the user's data */ 680 while (state->rx_ring[state->rx_read_index].s.code == 16) 681 { 682 /* Only copy what will fit in the user's buffer */ 683 int length = state->rx_ring[state->rx_read_index].s.len; 684 if (length > buffer_len) 685 length = buffer_len; 686 memcpy(buffer, source, length); 687 /* Reduce the size of the buffer to the remaining space. If we run 688 out we will signal an error when the code 15 buffer doesn't fit */ 689 buffer += length; 690 buffer_len -= length; 691 result += length; 692 /* Update this buffer for reuse in future receives. This size is 693 -8 due to an errata for CN56XX pass 1 */ 694 state->rx_ring[state->rx_read_index].s.code = 0; 695 state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8; 696 state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS; 697 /* Zero the beginning of the buffer for use by the errata check */ 698 *zero_check = 0; 699 CVMX_SYNCWS; 700 /* Increment the number of RX buffers */ 701 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); 702 source = (void *)state->rx_buffers[state->rx_read_index]; 703 zero_check = source; 704 } 705 706 /* Check for the final good completion code */ 707 if (state->rx_ring[state->rx_read_index].s.code == 15) 708 { 709 if (buffer_len >= state->rx_ring[state->rx_read_index].s.len) 710 { 711 int length = state->rx_ring[state->rx_read_index].s.len; 712 memcpy(buffer, source, length); 713 result += length; 714 } 715 else 716 { 717 /* Not enough room for the packet */ 718 cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Packet (%d) larger than supplied buffer (%d)\n", state->rx_ring[state->rx_read_index].s.len, buffer_len); 719 result = CVMX_MGMT_PORT_NO_MEMORY; 720 } 721 } 722 else 723 { 724 cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Receive error code %d. Packet dropped(Len %d), \n", 725 state->rx_ring[state->rx_read_index].s.code, state->rx_ring[state->rx_read_index].s.len + result); 726 result = -state->rx_ring[state->rx_read_index].s.code; 727 728 729 /* Check to see if we need to change the duplex. */ 730 cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port)); 731 } 732 733 /* Clean out the ring buffer entry. This size is -8 due to an errata 734 for CN56XX pass 1 */ 735 state->rx_ring[state->rx_read_index].s.code = 0; 736 state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8; 737 state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS; 738 /* Zero the beginning of the buffer for use by the errata check */ 739 *zero_check = 0; 740 CVMX_SYNCWS; 741 /* Increment the number of RX buffers */ 742 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); 743 /* Decrement the pending RX count */ 744 cvmx_write_csr(CVMX_MIXX_IRCNT(port), 1); 745 } 746 else 747 { 748 /* No packets available */ 749 result = 0; 750 } 751 cvmx_spinlock_unlock(&state->lock); 752 return result; 753} 754 755/** 756 * Set the MAC address for a management port 757 * 758 * @param port Management port 759 * @param mac New MAC address. The lower 6 bytes are used. 760 * 761 * @return CVMX_MGMT_PORT_SUCCESS or an error code 762 */ 763cvmx_mgmt_port_result_t cvmx_mgmt_port_set_mac(int port, uint64_t mac) 764{ 765 cvmx_mgmt_port_state_t *state; 766 cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl; 767 768 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 769 return CVMX_MGMT_PORT_INVALID_PARAM; 770 771 state = cvmx_mgmt_port_state_ptr + port; 772 773 cvmx_spinlock_lock(&state->lock); 774 775 agl_gmx_rxx_adr_ctl.u64 = 0; 776 agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Only accept matching MAC addresses */ 777 agl_gmx_rxx_adr_ctl.s.mcst = 0; /* Drop multicast */ 778 agl_gmx_rxx_adr_ctl.s.bcst = 1; /* Allow broadcast */ 779 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64); 780 781 /* Only using one of the CAMs */ 782 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), (mac >> 40) & 0xff); 783 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), (mac >> 32) & 0xff); 784 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), (mac >> 24) & 0xff); 785 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), (mac >> 16) & 0xff); 786 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), (mac >> 8) & 0xff); 787 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), (mac >> 0) & 0xff); 788 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1); 789 state->mac = mac; 790 791 cvmx_spinlock_unlock(&state->lock); 792 return CVMX_MGMT_PORT_SUCCESS; 793} 794 795 796/** 797 * Get the MAC address for a management port 798 * 799 * @param port Management port 800 * 801 * @return MAC address 802 */ 803uint64_t cvmx_mgmt_port_get_mac(int port) 804{ 805 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 806 return CVMX_MGMT_PORT_INVALID_PARAM; 807 808 return cvmx_mgmt_port_state_ptr[port].mac; 809} 810 811/** 812 * Set the multicast list. 813 * 814 * @param port Management port 815 * @param flags Interface flags 816 * 817 * @return 818 */ 819void cvmx_mgmt_port_set_multicast_list(int port, int flags) 820{ 821 cvmx_mgmt_port_state_t *state; 822 cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl; 823 824 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 825 return; 826 827 state = cvmx_mgmt_port_state_ptr + port; 828 829 cvmx_spinlock_lock(&state->lock); 830 831 agl_gmx_rxx_adr_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port)); 832 833 /* Allow broadcast MAC addresses */ 834 if (!agl_gmx_rxx_adr_ctl.s.bcst) 835 agl_gmx_rxx_adr_ctl.s.bcst = 1; 836 837 if ((flags & CVMX_IFF_ALLMULTI) || (flags & CVMX_IFF_PROMISC)) 838 agl_gmx_rxx_adr_ctl.s.mcst = 2; /* Force accept multicast packets */ 839 else 840 agl_gmx_rxx_adr_ctl.s.mcst = 1; /* Force reject multicast packets */ 841 842 if (flags & CVMX_IFF_PROMISC) 843 agl_gmx_rxx_adr_ctl.s.cam_mode = 0; /* Reject matches if promisc. Since CAM is shut off, should accept everything */ 844 else 845 agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Filter packets based on the CAM */ 846 847 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64); 848 849 if (flags & CVMX_IFF_PROMISC) 850 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 0); 851 else 852 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1); 853 854 cvmx_spinlock_unlock(&state->lock); 855} 856 857 858/** 859 * Set the maximum packet allowed in. Size is specified 860 * including L2 but without FCS. A normal MTU would corespond 861 * to 1514 assuming the standard 14 byte L2 header. 862 * 863 * @param port Management port 864 * @param size_without_fcs 865 * Size in bytes without FCS 866 */ 867void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs) 868{ 869 cvmx_mgmt_port_state_t *state; 870 871 if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports())) 872 return; 873 874 state = cvmx_mgmt_port_state_ptr + port; 875 876 cvmx_spinlock_lock(&state->lock); 877 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); 878 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), (size_without_fcs+7) & 0xfff8); 879 cvmx_spinlock_unlock(&state->lock); 880} 881 882/** 883 * Return the link state of an RGMII/MII port as returned by 884 * auto negotiation. The result of this function may not match 885 * Octeon's link config if auto negotiation has changed since 886 * the last call to cvmx_mgmt_port_link_set(). 887 * 888 * @param port The RGMII/MII interface port to query 889 * 890 * @return Link state 891 */ 892cvmx_helper_link_info_t cvmx_mgmt_port_link_get(int port) 893{ 894 cvmx_mgmt_port_state_t *state; 895 cvmx_helper_link_info_t result; 896 897 state = cvmx_mgmt_port_state_ptr + port; 898 result.u64 = 0; 899 900 if (port > __cvmx_mgmt_port_num_ports()) 901 { 902 cvmx_dprintf("WARNING: Invalid port %d\n", port); 903 return result; 904 } 905 906 if (state->port != -1) 907 return __cvmx_helper_board_link_get(state->port); 908 else // Simulator does not have PHY, use some defaults. 909 { 910 result.s.full_duplex = 1; 911 result.s.link_up = 1; 912 result.s.speed = 100; 913 return result; 914 } 915 return result; 916} 917 918/** 919 * Configure RGMII/MII port for the specified link state. This 920 * function does not influence auto negotiation at the PHY level. 921 * 922 * @param port RGMII/MII interface port 923 * @param link_info The new link state 924 * 925 * @return Zero on success, negative on failure 926 */ 927int cvmx_mgmt_port_link_set(int port, cvmx_helper_link_info_t link_info) 928{ 929 cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx; 930 931 /* Disable GMX before we make any changes. */ 932 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 933 agl_gmx_prtx.s.en = 0; 934 agl_gmx_prtx.s.tx_en = 0; 935 agl_gmx_prtx.s.rx_en = 0; 936 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 937 938 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 939 { 940 uint64_t one_second = cvmx_clock_get_rate(CVMX_CLOCK_CORE); 941 /* Wait for GMX to be idle */ 942 if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==, 1, one_second) 943 || CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==, 1, one_second)) 944 { 945 cvmx_dprintf("MIX%d: Timeout waiting for GMX to be idle\n", port); 946 return -1; 947 } 948 } 949 950 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 951 952 /* Set duplex mode */ 953 if (!link_info.s.link_up) 954 agl_gmx_prtx.s.duplex = 1; /* Force full duplex on down links */ 955 else 956 agl_gmx_prtx.s.duplex = link_info.s.full_duplex; 957 958 switch(link_info.s.speed) 959 { 960 case 10: 961 agl_gmx_prtx.s.speed = 0; 962 agl_gmx_prtx.s.slottime = 0; 963 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 964 { 965 agl_gmx_prtx.s.speed_msb = 1; 966 agl_gmx_prtx.s.burst = 1; 967 } 968 break; 969 970 case 100: 971 agl_gmx_prtx.s.speed = 0; 972 agl_gmx_prtx.s.slottime = 0; 973 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 974 { 975 agl_gmx_prtx.s.speed_msb = 0; 976 agl_gmx_prtx.s.burst = 1; 977 } 978 break; 979 980 case 1000: 981 /* 1000 MBits is only supported on 6XXX chips */ 982 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 983 { 984 agl_gmx_prtx.s.speed_msb = 0; 985 agl_gmx_prtx.s.speed = 1; 986 agl_gmx_prtx.s.slottime = 1; /* Only matters for half-duplex */ 987 agl_gmx_prtx.s.burst = agl_gmx_prtx.s.duplex; 988 } 989 break; 990 991 /* No link */ 992 case 0: 993 default: 994 break; 995 } 996 997 /* Write the new GMX setting with the port still disabled. */ 998 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 999 1000 /* Read GMX CFG again to make sure the config is completed. */ 1001 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 1002 1003 1004 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 1005 { 1006 cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port; 1007 cvmx_agl_gmx_txx_clk_t agl_clk; 1008 agl_clk.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_CLK(port)); 1009 agl_clk.s.clk_cnt = 1; /* MII (both speeds) and RGMII 1000 setting */ 1010 if (state->mode == CVMX_MGMT_PORT_RGMII_MODE) 1011 { 1012 if (link_info.s.speed == 10) 1013 agl_clk.s.clk_cnt = 50; 1014 else if (link_info.s.speed == 100) 1015 agl_clk.s.clk_cnt = 5; 1016 } 1017 cvmx_write_csr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64); 1018 } 1019 1020 /* Enable transmit and receive ports */ 1021 agl_gmx_prtx.s.tx_en = 1; 1022 agl_gmx_prtx.s.rx_en = 1; 1023 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 1024 1025 /* Enable the link. */ 1026 agl_gmx_prtx.s.en = 1; 1027 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 1028 return 0; 1029} 1030