1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-agl-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon agl. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_AGL_DEFS_H__ 53232812Sjmallett#define __CVMX_AGL_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60215976Sjmallett cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000518ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71215976Sjmallett cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000400ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 82215976Sjmallett cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007F0ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 93215976Sjmallett cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007F8ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 105232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 106232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 109215976Sjmallett cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 121232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 122232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 123232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 124232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 125215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset); 126215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048; 127215976Sjmallett} 128215976Sjmallett#else 129215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048) 130215976Sjmallett#endif 131215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 132215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset) 133215976Sjmallett{ 134215976Sjmallett if (!( 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 138232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 139232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 140232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 141215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset); 142215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048; 143215976Sjmallett} 144215976Sjmallett#else 145215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048) 146215976Sjmallett#endif 147215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 148215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset) 149215976Sjmallett{ 150215976Sjmallett if (!( 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 154232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 155232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 156232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 157215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset); 158215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048; 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset) 165215976Sjmallett{ 166215976Sjmallett if (!( 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 171232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 172232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 173215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset); 174215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048; 175215976Sjmallett} 176215976Sjmallett#else 177215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048) 178215976Sjmallett#endif 179215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 180215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset) 181215976Sjmallett{ 182215976Sjmallett if (!( 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 184215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 188232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 189215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset); 190215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048; 191215976Sjmallett} 192215976Sjmallett#else 193215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048) 194215976Sjmallett#endif 195215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 196215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset) 197215976Sjmallett{ 198215976Sjmallett if (!( 199215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 200215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 202232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 204232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 205215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 217232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 219232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 220232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 221215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset); 222215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048; 223215976Sjmallett} 224215976Sjmallett#else 225215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048) 226215976Sjmallett#endif 227215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 228215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset) 229215976Sjmallett{ 230215976Sjmallett if (!( 231215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 232215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 233232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 237215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset); 238215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048; 239215976Sjmallett} 240215976Sjmallett#else 241215976Sjmallett#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048) 242215976Sjmallett#endif 243215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 244215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset) 245215976Sjmallett{ 246215976Sjmallett if (!( 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 248215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 253215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset); 254215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset) 261215976Sjmallett{ 262215976Sjmallett if (!( 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 269215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048; 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset) 277215976Sjmallett{ 278215976Sjmallett if (!( 279215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 280215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 281232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 285215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset); 286215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048; 287215976Sjmallett} 288215976Sjmallett#else 289215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048) 290215976Sjmallett#endif 291215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 292215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset) 293215976Sjmallett{ 294215976Sjmallett if (!( 295215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 296215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 297232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 298232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 301215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048; 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset) 309215976Sjmallett{ 310215976Sjmallett if (!( 311215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 317215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset); 318215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset) 325215976Sjmallett{ 326215976Sjmallett if (!( 327215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 328215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 329232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 330232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 331232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 332232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 333215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset); 334215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048; 335215976Sjmallett} 336215976Sjmallett#else 337215976Sjmallett#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048) 338215976Sjmallett#endif 339215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 340215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset) 341215976Sjmallett{ 342215976Sjmallett if (!( 343215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 344215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 345232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 346232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 347232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 348232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 349215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset) 357215976Sjmallett{ 358215976Sjmallett if (!( 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 361232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 362232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 363232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 364232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 365215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset); 366215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048; 367215976Sjmallett} 368215976Sjmallett#else 369215976Sjmallett#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048) 370215976Sjmallett#endif 371215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 372215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset) 373215976Sjmallett{ 374215976Sjmallett if (!( 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 377232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 378232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 379232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 380232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 381215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset); 382215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048; 383215976Sjmallett} 384215976Sjmallett#else 385215976Sjmallett#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048) 386215976Sjmallett#endif 387215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 388215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset) 389215976Sjmallett{ 390215976Sjmallett if (!( 391215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 392215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 393232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 394232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 395232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 396232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 397215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset); 398215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048; 399215976Sjmallett} 400215976Sjmallett#else 401215976Sjmallett#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048) 402215976Sjmallett#endif 403215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 404215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset) 405215976Sjmallett{ 406215976Sjmallett if (!( 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 408232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 409232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 410232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 411215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset); 412215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048; 413215976Sjmallett} 414215976Sjmallett#else 415215976Sjmallett#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048) 416215976Sjmallett#endif 417215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset) 419215976Sjmallett{ 420215976Sjmallett if (!( 421215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 422215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 423232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 424232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 425232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 426232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 427215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset); 428215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048; 429215976Sjmallett} 430215976Sjmallett#else 431215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048) 432215976Sjmallett#endif 433215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset) 435215976Sjmallett{ 436215976Sjmallett if (!( 437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 439232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 440232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 441232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 442232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 443215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset); 444215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048; 445215976Sjmallett} 446215976Sjmallett#else 447215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048) 448215976Sjmallett#endif 449215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 450215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset) 451215976Sjmallett{ 452215976Sjmallett if (!( 453215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 454215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 455232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 456232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 457232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 458232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 459215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset); 460215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048; 461215976Sjmallett} 462215976Sjmallett#else 463215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048) 464215976Sjmallett#endif 465215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 466215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset) 467215976Sjmallett{ 468215976Sjmallett if (!( 469215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 470215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 471232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 472232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 473232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 474232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 475215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset); 476215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048; 477215976Sjmallett} 478215976Sjmallett#else 479215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048) 480215976Sjmallett#endif 481215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 482215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset) 483215976Sjmallett{ 484215976Sjmallett if (!( 485215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 486215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 487232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 488232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 489232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 490232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 491215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset); 492215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048; 493215976Sjmallett} 494215976Sjmallett#else 495215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048) 496215976Sjmallett#endif 497215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset) 499215976Sjmallett{ 500215976Sjmallett if (!( 501215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 502215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 503232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 504232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 505232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 506232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 507215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset); 508215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048; 509215976Sjmallett} 510215976Sjmallett#else 511215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048) 512215976Sjmallett#endif 513215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 514215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset) 515215976Sjmallett{ 516215976Sjmallett if (!( 517215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 519232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 520232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 521232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 522232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 523215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset); 524215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048; 525215976Sjmallett} 526215976Sjmallett#else 527215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048) 528215976Sjmallett#endif 529215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 530215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset) 531215976Sjmallett{ 532215976Sjmallett if (!( 533215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 534215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 535232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 536232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 537232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 538232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 539215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset); 540215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048; 541215976Sjmallett} 542215976Sjmallett#else 543215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048) 544215976Sjmallett#endif 545215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 546215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset) 547215976Sjmallett{ 548215976Sjmallett if (!( 549215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 550215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 551232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 552232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 553232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 555215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset); 556215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048; 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset) 563215976Sjmallett{ 564215976Sjmallett if (!( 565215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 566215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 567232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 568232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 569232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 570232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 571215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset); 572215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048; 573215976Sjmallett} 574215976Sjmallett#else 575215976Sjmallett#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048) 576215976Sjmallett#endif 577215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset) 579215976Sjmallett{ 580215976Sjmallett if (!( 581215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 582215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 583232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 584232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 585232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 586232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 587215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset); 588215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048; 589215976Sjmallett} 590215976Sjmallett#else 591215976Sjmallett#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048) 592215976Sjmallett#endif 593215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 594215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset) 595215976Sjmallett{ 596215976Sjmallett if (!( 597215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 598215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 599232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 600232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 601232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 602232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 603215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset); 604215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8; 605215976Sjmallett} 606215976Sjmallett#else 607215976Sjmallett#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8) 608215976Sjmallett#endif 609215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 610215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset) 611215976Sjmallett{ 612215976Sjmallett if (!( 613215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 614215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 615232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 616232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 617232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 618232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 619215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset); 620215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8; 621215976Sjmallett} 622215976Sjmallett#else 623215976Sjmallett#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8) 624215976Sjmallett#endif 625215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 626215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset) 627215976Sjmallett{ 628215976Sjmallett if (!( 629215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 630215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 631232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 632232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 633232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 634232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 635215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset); 636215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8; 637215976Sjmallett} 638215976Sjmallett#else 639215976Sjmallett#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8) 640215976Sjmallett#endif 641215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 642215976Sjmallett#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC() 643215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void) 644215976Sjmallett{ 645232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 646215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n"); 647215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004E8ull); 648215976Sjmallett} 649215976Sjmallett#else 650215976Sjmallett#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull)) 651215976Sjmallett#endif 652215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 653215976Sjmallett#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC() 654215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void) 655215976Sjmallett{ 656232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 657215976Sjmallett cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n"); 658215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00007E8ull); 659215976Sjmallett} 660215976Sjmallett#else 661215976Sjmallett#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull)) 662215976Sjmallett#endif 663215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 664215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset) 665215976Sjmallett{ 666215976Sjmallett if (!( 667215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 668215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 669232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 670232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 671232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 672232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 673215976Sjmallett cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset); 674215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048; 675215976Sjmallett} 676215976Sjmallett#else 677215976Sjmallett#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048) 678215976Sjmallett#endif 679215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680215976Sjmallett#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC() 681215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void) 682215976Sjmallett{ 683232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 684215976Sjmallett cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n"); 685215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000520ull); 686215976Sjmallett} 687215976Sjmallett#else 688215976Sjmallett#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull)) 689215976Sjmallett#endif 690215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 691215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset) 692215976Sjmallett{ 693215976Sjmallett if (!( 694215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 695215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 696232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 697232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 698232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 699232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 700215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset); 701215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048; 702215976Sjmallett} 703215976Sjmallett#else 704215976Sjmallett#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048) 705215976Sjmallett#endif 706215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 707215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset) 708215976Sjmallett{ 709215976Sjmallett if (!( 710232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 711232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 712232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 713232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 714215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset); 715215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048; 716215976Sjmallett} 717215976Sjmallett#else 718215976Sjmallett#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048) 719215976Sjmallett#endif 720215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 721215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset) 722215976Sjmallett{ 723215976Sjmallett if (!( 724215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 725215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 726232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 727232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 728232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 729232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 730215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset); 731215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048; 732215976Sjmallett} 733215976Sjmallett#else 734215976Sjmallett#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048) 735215976Sjmallett#endif 736215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 737215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset) 738215976Sjmallett{ 739215976Sjmallett if (!( 740215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 741215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 742232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 743232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 744232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 745232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 746215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset); 747215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048; 748215976Sjmallett} 749215976Sjmallett#else 750215976Sjmallett#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048) 751215976Sjmallett#endif 752215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset) 754215976Sjmallett{ 755215976Sjmallett if (!( 756215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 757215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 758232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 759232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 760232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 761232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 762215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset); 763215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048; 764215976Sjmallett} 765215976Sjmallett#else 766215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048) 767215976Sjmallett#endif 768215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 769215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset) 770215976Sjmallett{ 771215976Sjmallett if (!( 772215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 773215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 774232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 775232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 776232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 777232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 778215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset); 779215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048; 780215976Sjmallett} 781215976Sjmallett#else 782215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048) 783215976Sjmallett#endif 784215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 785215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset) 786215976Sjmallett{ 787215976Sjmallett if (!( 788215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 789215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 790232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 791232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 792232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 793232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 794215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset); 795215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048; 796215976Sjmallett} 797215976Sjmallett#else 798215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048) 799215976Sjmallett#endif 800215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 801215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset) 802215976Sjmallett{ 803215976Sjmallett if (!( 804215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 805215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 806232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 807232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 808232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 809232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 810215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset); 811215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048; 812215976Sjmallett} 813215976Sjmallett#else 814215976Sjmallett#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048) 815215976Sjmallett#endif 816215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 817215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset) 818215976Sjmallett{ 819215976Sjmallett if (!( 820215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 821215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 822232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 823232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 824232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 825232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 826215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset); 827215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048; 828215976Sjmallett} 829215976Sjmallett#else 830215976Sjmallett#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048) 831215976Sjmallett#endif 832215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 833215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset) 834215976Sjmallett{ 835215976Sjmallett if (!( 836215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 837215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 838232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 839232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 840232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 841232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 842215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset); 843215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048; 844215976Sjmallett} 845215976Sjmallett#else 846215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048) 847215976Sjmallett#endif 848215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 849215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset) 850215976Sjmallett{ 851215976Sjmallett if (!( 852215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 853215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 854232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 855232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 856232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 857232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 858215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset); 859215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048; 860215976Sjmallett} 861215976Sjmallett#else 862215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048) 863215976Sjmallett#endif 864215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 865215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset) 866215976Sjmallett{ 867215976Sjmallett if (!( 868215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 869215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 870232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 871232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 872232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 873232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 874215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset); 875215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048; 876215976Sjmallett} 877215976Sjmallett#else 878215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048) 879215976Sjmallett#endif 880215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 881215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset) 882215976Sjmallett{ 883215976Sjmallett if (!( 884215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 885215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 886232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 887232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 888232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 889232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 890215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset); 891215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048; 892215976Sjmallett} 893215976Sjmallett#else 894215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048) 895215976Sjmallett#endif 896215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 897215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset) 898215976Sjmallett{ 899215976Sjmallett if (!( 900215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 901215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 902232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 903232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 904232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 905232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 906215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset); 907215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048; 908215976Sjmallett} 909215976Sjmallett#else 910215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048) 911215976Sjmallett#endif 912215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 913215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset) 914215976Sjmallett{ 915215976Sjmallett if (!( 916215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 917215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 918232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 919232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 920232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 921232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 922215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset); 923215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048; 924215976Sjmallett} 925215976Sjmallett#else 926215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048) 927215976Sjmallett#endif 928215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 929215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset) 930215976Sjmallett{ 931215976Sjmallett if (!( 932215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 933215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 934232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 935232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 936232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 937232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 938215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset); 939215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048; 940215976Sjmallett} 941215976Sjmallett#else 942215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048) 943215976Sjmallett#endif 944215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 945215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset) 946215976Sjmallett{ 947215976Sjmallett if (!( 948215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 949215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 950232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 951232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 952232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 953232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 954215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset); 955215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048; 956215976Sjmallett} 957215976Sjmallett#else 958215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048) 959215976Sjmallett#endif 960215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 961215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset) 962215976Sjmallett{ 963215976Sjmallett if (!( 964215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 965215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 966232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 967232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 968232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 969232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 970215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset); 971215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048; 972215976Sjmallett} 973215976Sjmallett#else 974215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048) 975215976Sjmallett#endif 976215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 977215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset) 978215976Sjmallett{ 979215976Sjmallett if (!( 980215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 981215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 982232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 983232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 984232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 985232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 986215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset); 987215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048; 988215976Sjmallett} 989215976Sjmallett#else 990215976Sjmallett#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048) 991215976Sjmallett#endif 992215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 993215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset) 994215976Sjmallett{ 995215976Sjmallett if (!( 996215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 997215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 998232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 999232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1000232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1001232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 1002215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset); 1003215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048; 1004215976Sjmallett} 1005215976Sjmallett#else 1006215976Sjmallett#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048) 1007215976Sjmallett#endif 1008215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset) 1010215976Sjmallett{ 1011215976Sjmallett if (!( 1012215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1013215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 1014232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1015232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1016232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1017232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 1018215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset); 1019215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048; 1020215976Sjmallett} 1021215976Sjmallett#else 1022215976Sjmallett#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048) 1023215976Sjmallett#endif 1024215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1025215976Sjmallett#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC() 1026215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void) 1027215976Sjmallett{ 1028232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1029215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n"); 1030215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004D0ull); 1031215976Sjmallett} 1032215976Sjmallett#else 1033215976Sjmallett#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull)) 1034215976Sjmallett#endif 1035215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1036215976Sjmallett#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC() 1037215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void) 1038215976Sjmallett{ 1039232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1040215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n"); 1041215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000498ull); 1042215976Sjmallett} 1043215976Sjmallett#else 1044215976Sjmallett#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull)) 1045215976Sjmallett#endif 1046215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1047215976Sjmallett#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC() 1048215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void) 1049215976Sjmallett{ 1050232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1051215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n"); 1052215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000488ull); 1053215976Sjmallett} 1054215976Sjmallett#else 1055215976Sjmallett#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull)) 1056215976Sjmallett#endif 1057215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1058215976Sjmallett#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC() 1059215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void) 1060215976Sjmallett{ 1061232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1062215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n"); 1063215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000508ull); 1064215976Sjmallett} 1065215976Sjmallett#else 1066215976Sjmallett#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull)) 1067215976Sjmallett#endif 1068215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1069215976Sjmallett#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC() 1070215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void) 1071215976Sjmallett{ 1072232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1073215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n"); 1074215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000500ull); 1075215976Sjmallett} 1076215976Sjmallett#else 1077215976Sjmallett#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull)) 1078215976Sjmallett#endif 1079215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1080215976Sjmallett#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC() 1081215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void) 1082215976Sjmallett{ 1083232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1084215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n"); 1085215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0000490ull); 1086215976Sjmallett} 1087215976Sjmallett#else 1088215976Sjmallett#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull)) 1089215976Sjmallett#endif 1090215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1091215976Sjmallett#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC() 1092215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void) 1093215976Sjmallett{ 1094232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1095215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n"); 1096215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004F8ull); 1097215976Sjmallett} 1098215976Sjmallett#else 1099215976Sjmallett#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull)) 1100215976Sjmallett#endif 1101215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1102215976Sjmallett#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC() 1103215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void) 1104215976Sjmallett{ 1105232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1106215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n"); 1107215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004C8ull); 1108215976Sjmallett} 1109215976Sjmallett#else 1110215976Sjmallett#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull)) 1111215976Sjmallett#endif 1112215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1113215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC() 1114215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void) 1115215976Sjmallett{ 1116232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1117215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n"); 1118215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004A0ull); 1119215976Sjmallett} 1120215976Sjmallett#else 1121215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull)) 1122215976Sjmallett#endif 1123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1124215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC() 1125215976Sjmallettstatic inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void) 1126215976Sjmallett{ 1127232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 1128215976Sjmallett cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n"); 1129215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E00004A8ull); 1130215976Sjmallett} 1131215976Sjmallett#else 1132215976Sjmallett#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull)) 1133215976Sjmallett#endif 1134215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1135215976Sjmallettstatic inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset) 1136215976Sjmallett{ 1137215976Sjmallett if (!( 1138232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1139232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1140232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1141232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 1142215976Sjmallett cvmx_warn("CVMX_AGL_PRTX_CTL(%lu) is invalid on this chip\n", offset); 1143215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8; 1144215976Sjmallett} 1145215976Sjmallett#else 1146215976Sjmallett#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8) 1147215976Sjmallett#endif 1148215976Sjmallett 1149215976Sjmallett/** 1150215976Sjmallett * cvmx_agl_gmx_bad_reg 1151215976Sjmallett * 1152215976Sjmallett * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong 1153215976Sjmallett * 1154215976Sjmallett * 1155215976Sjmallett * Notes: 1156215976Sjmallett * OUT_OVR[0], LOSTSTAT[0], OVRFLW, TXPOP, TXPSH will be reset when MIX0_CTL[RESET] is set to 1. 1157215976Sjmallett * OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1. 1158215976Sjmallett * STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1. 1159215976Sjmallett */ 1160232812Sjmallettunion cvmx_agl_gmx_bad_reg { 1161215976Sjmallett uint64_t u64; 1162232812Sjmallett struct cvmx_agl_gmx_bad_reg_s { 1163232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1164215976Sjmallett uint64_t reserved_38_63 : 26; 1165215976Sjmallett uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */ 1166215976Sjmallett uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */ 1167215976Sjmallett uint64_t ovrflw1 : 1; /**< RX FIFO overflow (MII1) */ 1168215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow (MII0) */ 1169215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow (MII0) */ 1170215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow (MII0) */ 1171215976Sjmallett uint64_t reserved_27_31 : 5; 1172215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1173215976Sjmallett uint64_t reserved_24_25 : 2; 1174215976Sjmallett uint64_t loststat : 2; /**< TX Statistics data was over-written 1175215976Sjmallett In MII/RGMII, one bit per port 1176215976Sjmallett TX Stats are corrupted */ 1177215976Sjmallett uint64_t reserved_4_21 : 18; 1178215976Sjmallett uint64_t out_ovr : 2; /**< Outbound data FIFO overflow */ 1179215976Sjmallett uint64_t reserved_0_1 : 2; 1180215976Sjmallett#else 1181215976Sjmallett uint64_t reserved_0_1 : 2; 1182215976Sjmallett uint64_t out_ovr : 2; 1183215976Sjmallett uint64_t reserved_4_21 : 18; 1184215976Sjmallett uint64_t loststat : 2; 1185215976Sjmallett uint64_t reserved_24_25 : 2; 1186215976Sjmallett uint64_t statovr : 1; 1187215976Sjmallett uint64_t reserved_27_31 : 5; 1188215976Sjmallett uint64_t ovrflw : 1; 1189215976Sjmallett uint64_t txpop : 1; 1190215976Sjmallett uint64_t txpsh : 1; 1191215976Sjmallett uint64_t ovrflw1 : 1; 1192215976Sjmallett uint64_t txpop1 : 1; 1193215976Sjmallett uint64_t txpsh1 : 1; 1194215976Sjmallett uint64_t reserved_38_63 : 26; 1195215976Sjmallett#endif 1196215976Sjmallett } s; 1197232812Sjmallett struct cvmx_agl_gmx_bad_reg_cn52xx { 1198232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1199215976Sjmallett uint64_t reserved_38_63 : 26; 1200215976Sjmallett uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */ 1201215976Sjmallett uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */ 1202215976Sjmallett uint64_t ovrflw1 : 1; /**< RX FIFO overflow (MII1) */ 1203215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow (MII0) */ 1204215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow (MII0) */ 1205215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow (MII0) */ 1206215976Sjmallett uint64_t reserved_27_31 : 5; 1207215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1208215976Sjmallett uint64_t reserved_23_25 : 3; 1209215976Sjmallett uint64_t loststat : 1; /**< TX Statistics data was over-written 1210215976Sjmallett TX Stats are corrupted */ 1211215976Sjmallett uint64_t reserved_4_21 : 18; 1212215976Sjmallett uint64_t out_ovr : 2; /**< Outbound data FIFO overflow */ 1213215976Sjmallett uint64_t reserved_0_1 : 2; 1214215976Sjmallett#else 1215215976Sjmallett uint64_t reserved_0_1 : 2; 1216215976Sjmallett uint64_t out_ovr : 2; 1217215976Sjmallett uint64_t reserved_4_21 : 18; 1218215976Sjmallett uint64_t loststat : 1; 1219215976Sjmallett uint64_t reserved_23_25 : 3; 1220215976Sjmallett uint64_t statovr : 1; 1221215976Sjmallett uint64_t reserved_27_31 : 5; 1222215976Sjmallett uint64_t ovrflw : 1; 1223215976Sjmallett uint64_t txpop : 1; 1224215976Sjmallett uint64_t txpsh : 1; 1225215976Sjmallett uint64_t ovrflw1 : 1; 1226215976Sjmallett uint64_t txpop1 : 1; 1227215976Sjmallett uint64_t txpsh1 : 1; 1228215976Sjmallett uint64_t reserved_38_63 : 26; 1229215976Sjmallett#endif 1230215976Sjmallett } cn52xx; 1231215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1; 1232232812Sjmallett struct cvmx_agl_gmx_bad_reg_cn56xx { 1233232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1234215976Sjmallett uint64_t reserved_35_63 : 29; 1235215976Sjmallett uint64_t txpsh : 1; /**< TX FIFO overflow */ 1236215976Sjmallett uint64_t txpop : 1; /**< TX FIFO underflow */ 1237215976Sjmallett uint64_t ovrflw : 1; /**< RX FIFO overflow */ 1238215976Sjmallett uint64_t reserved_27_31 : 5; 1239215976Sjmallett uint64_t statovr : 1; /**< TX Statistics overflow */ 1240215976Sjmallett uint64_t reserved_23_25 : 3; 1241215976Sjmallett uint64_t loststat : 1; /**< TX Statistics data was over-written 1242215976Sjmallett TX Stats are corrupted */ 1243215976Sjmallett uint64_t reserved_3_21 : 19; 1244215976Sjmallett uint64_t out_ovr : 1; /**< Outbound data FIFO overflow */ 1245215976Sjmallett uint64_t reserved_0_1 : 2; 1246215976Sjmallett#else 1247215976Sjmallett uint64_t reserved_0_1 : 2; 1248215976Sjmallett uint64_t out_ovr : 1; 1249215976Sjmallett uint64_t reserved_3_21 : 19; 1250215976Sjmallett uint64_t loststat : 1; 1251215976Sjmallett uint64_t reserved_23_25 : 3; 1252215976Sjmallett uint64_t statovr : 1; 1253215976Sjmallett uint64_t reserved_27_31 : 5; 1254215976Sjmallett uint64_t ovrflw : 1; 1255215976Sjmallett uint64_t txpop : 1; 1256215976Sjmallett uint64_t txpsh : 1; 1257215976Sjmallett uint64_t reserved_35_63 : 29; 1258215976Sjmallett#endif 1259215976Sjmallett } cn56xx; 1260215976Sjmallett struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 1261232812Sjmallett struct cvmx_agl_gmx_bad_reg_s cn61xx; 1262215976Sjmallett struct cvmx_agl_gmx_bad_reg_s cn63xx; 1263215976Sjmallett struct cvmx_agl_gmx_bad_reg_s cn63xxp1; 1264232812Sjmallett struct cvmx_agl_gmx_bad_reg_s cn66xx; 1265232812Sjmallett struct cvmx_agl_gmx_bad_reg_s cn68xx; 1266232812Sjmallett struct cvmx_agl_gmx_bad_reg_s cn68xxp1; 1267215976Sjmallett}; 1268215976Sjmalletttypedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t; 1269215976Sjmallett 1270215976Sjmallett/** 1271215976Sjmallett * cvmx_agl_gmx_bist 1272215976Sjmallett * 1273215976Sjmallett * AGL_GMX_BIST = GMX BIST Results 1274215976Sjmallett * 1275215976Sjmallett * 1276215976Sjmallett * Notes: 1277215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1278215976Sjmallett * 1279215976Sjmallett */ 1280232812Sjmallettunion cvmx_agl_gmx_bist { 1281215976Sjmallett uint64_t u64; 1282232812Sjmallett struct cvmx_agl_gmx_bist_s { 1283232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1284215976Sjmallett uint64_t reserved_25_63 : 39; 1285215976Sjmallett uint64_t status : 25; /**< BIST Results. 1286215976Sjmallett HW sets a bit in BIST for for memory that fails 1287215976Sjmallett - 0: gmx#.inb.fif_bnk0 1288215976Sjmallett - 1: gmx#.inb.fif_bnk1 1289215976Sjmallett - 2: gmx#.inb.fif_bnk2 1290215976Sjmallett - 3: gmx#.inb.fif_bnk3 1291215976Sjmallett - 4: gmx#.inb.fif_bnk_ext0 1292215976Sjmallett - 5: gmx#.inb.fif_bnk_ext1 1293215976Sjmallett - 6: gmx#.inb.fif_bnk_ext2 1294215976Sjmallett - 7: gmx#.inb.fif_bnk_ext3 1295215976Sjmallett - 8: gmx#.outb.fif.fif_bnk0 1296215976Sjmallett - 9: gmx#.outb.fif.fif_bnk1 1297215976Sjmallett - 10: RAZ 1298215976Sjmallett - 11: RAZ 1299215976Sjmallett - 12: gmx#.outb.fif.fif_bnk_ext0 1300215976Sjmallett - 13: gmx#.outb.fif.fif_bnk_ext1 1301215976Sjmallett - 14: RAZ 1302215976Sjmallett - 15: RAZ 1303232812Sjmallett - 16: RAZ 1304232812Sjmallett - 17: RAZ 1305215976Sjmallett - 18: RAZ 1306215976Sjmallett - 19: RAZ 1307215976Sjmallett - 20: gmx#.csr.drf20x32m2_bist 1308215976Sjmallett - 21: gmx#.csr.drf20x48m2_bist 1309215976Sjmallett - 22: gmx#.outb.stat.drf16x27m1_bist 1310215976Sjmallett - 23: gmx#.outb.stat.drf40x64m1_bist 1311215976Sjmallett - 24: RAZ */ 1312215976Sjmallett#else 1313215976Sjmallett uint64_t status : 25; 1314215976Sjmallett uint64_t reserved_25_63 : 39; 1315215976Sjmallett#endif 1316215976Sjmallett } s; 1317232812Sjmallett struct cvmx_agl_gmx_bist_cn52xx { 1318232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1319215976Sjmallett uint64_t reserved_10_63 : 54; 1320215976Sjmallett uint64_t status : 10; /**< BIST Results. 1321215976Sjmallett HW sets a bit in BIST for for memory that fails 1322215976Sjmallett - 0: gmx#.inb.drf128x78m1_bist 1323215976Sjmallett - 1: gmx#.outb.fif.drf128x71m1_bist 1324215976Sjmallett - 2: gmx#.csr.gmi0.srf8x64m1_bist 1325215976Sjmallett - 3: gmx#.csr.gmi1.srf8x64m1_bist 1326215976Sjmallett - 4: 0 1327215976Sjmallett - 5: 0 1328215976Sjmallett - 6: gmx#.csr.drf20x80m1_bist 1329215976Sjmallett - 7: gmx#.outb.stat.drf16x27m1_bist 1330215976Sjmallett - 8: gmx#.outb.stat.drf40x64m1_bist 1331215976Sjmallett - 9: 0 */ 1332215976Sjmallett#else 1333215976Sjmallett uint64_t status : 10; 1334215976Sjmallett uint64_t reserved_10_63 : 54; 1335215976Sjmallett#endif 1336215976Sjmallett } cn52xx; 1337215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn52xxp1; 1338215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn56xx; 1339215976Sjmallett struct cvmx_agl_gmx_bist_cn52xx cn56xxp1; 1340232812Sjmallett struct cvmx_agl_gmx_bist_s cn61xx; 1341215976Sjmallett struct cvmx_agl_gmx_bist_s cn63xx; 1342215976Sjmallett struct cvmx_agl_gmx_bist_s cn63xxp1; 1343232812Sjmallett struct cvmx_agl_gmx_bist_s cn66xx; 1344232812Sjmallett struct cvmx_agl_gmx_bist_s cn68xx; 1345232812Sjmallett struct cvmx_agl_gmx_bist_s cn68xxp1; 1346215976Sjmallett}; 1347215976Sjmalletttypedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t; 1348215976Sjmallett 1349215976Sjmallett/** 1350215976Sjmallett * cvmx_agl_gmx_drv_ctl 1351215976Sjmallett * 1352215976Sjmallett * AGL_GMX_DRV_CTL = GMX Drive Control 1353215976Sjmallett * 1354215976Sjmallett * 1355215976Sjmallett * Notes: 1356215976Sjmallett * NCTL, PCTL, BYP_EN will be reset when MIX0_CTL[RESET] is set to 1. 1357215976Sjmallett * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1. 1358215976Sjmallett */ 1359232812Sjmallettunion cvmx_agl_gmx_drv_ctl { 1360215976Sjmallett uint64_t u64; 1361232812Sjmallett struct cvmx_agl_gmx_drv_ctl_s { 1362232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1363215976Sjmallett uint64_t reserved_49_63 : 15; 1364215976Sjmallett uint64_t byp_en1 : 1; /**< Compensation Controller Bypass Enable (MII1) */ 1365215976Sjmallett uint64_t reserved_45_47 : 3; 1366215976Sjmallett uint64_t pctl1 : 5; /**< AGL PCTL (MII1) */ 1367215976Sjmallett uint64_t reserved_37_39 : 3; 1368215976Sjmallett uint64_t nctl1 : 5; /**< AGL NCTL (MII1) */ 1369215976Sjmallett uint64_t reserved_17_31 : 15; 1370215976Sjmallett uint64_t byp_en : 1; /**< Compensation Controller Bypass Enable */ 1371215976Sjmallett uint64_t reserved_13_15 : 3; 1372215976Sjmallett uint64_t pctl : 5; /**< AGL PCTL */ 1373215976Sjmallett uint64_t reserved_5_7 : 3; 1374215976Sjmallett uint64_t nctl : 5; /**< AGL NCTL */ 1375215976Sjmallett#else 1376215976Sjmallett uint64_t nctl : 5; 1377215976Sjmallett uint64_t reserved_5_7 : 3; 1378215976Sjmallett uint64_t pctl : 5; 1379215976Sjmallett uint64_t reserved_13_15 : 3; 1380215976Sjmallett uint64_t byp_en : 1; 1381215976Sjmallett uint64_t reserved_17_31 : 15; 1382215976Sjmallett uint64_t nctl1 : 5; 1383215976Sjmallett uint64_t reserved_37_39 : 3; 1384215976Sjmallett uint64_t pctl1 : 5; 1385215976Sjmallett uint64_t reserved_45_47 : 3; 1386215976Sjmallett uint64_t byp_en1 : 1; 1387215976Sjmallett uint64_t reserved_49_63 : 15; 1388215976Sjmallett#endif 1389215976Sjmallett } s; 1390215976Sjmallett struct cvmx_agl_gmx_drv_ctl_s cn52xx; 1391215976Sjmallett struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; 1392232812Sjmallett struct cvmx_agl_gmx_drv_ctl_cn56xx { 1393232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1394215976Sjmallett uint64_t reserved_17_63 : 47; 1395215976Sjmallett uint64_t byp_en : 1; /**< Compensation Controller Bypass Enable */ 1396215976Sjmallett uint64_t reserved_13_15 : 3; 1397215976Sjmallett uint64_t pctl : 5; /**< AGL PCTL */ 1398215976Sjmallett uint64_t reserved_5_7 : 3; 1399215976Sjmallett uint64_t nctl : 5; /**< AGL NCTL */ 1400215976Sjmallett#else 1401215976Sjmallett uint64_t nctl : 5; 1402215976Sjmallett uint64_t reserved_5_7 : 3; 1403215976Sjmallett uint64_t pctl : 5; 1404215976Sjmallett uint64_t reserved_13_15 : 3; 1405215976Sjmallett uint64_t byp_en : 1; 1406215976Sjmallett uint64_t reserved_17_63 : 47; 1407215976Sjmallett#endif 1408215976Sjmallett } cn56xx; 1409215976Sjmallett struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; 1410215976Sjmallett}; 1411215976Sjmalletttypedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t; 1412215976Sjmallett 1413215976Sjmallett/** 1414215976Sjmallett * cvmx_agl_gmx_inf_mode 1415215976Sjmallett * 1416215976Sjmallett * AGL_GMX_INF_MODE = Interface Mode 1417215976Sjmallett * 1418215976Sjmallett * 1419215976Sjmallett * Notes: 1420215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1421215976Sjmallett * 1422215976Sjmallett */ 1423232812Sjmallettunion cvmx_agl_gmx_inf_mode { 1424215976Sjmallett uint64_t u64; 1425232812Sjmallett struct cvmx_agl_gmx_inf_mode_s { 1426232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1427215976Sjmallett uint64_t reserved_2_63 : 62; 1428215976Sjmallett uint64_t en : 1; /**< Interface Enable */ 1429215976Sjmallett uint64_t reserved_0_0 : 1; 1430215976Sjmallett#else 1431215976Sjmallett uint64_t reserved_0_0 : 1; 1432215976Sjmallett uint64_t en : 1; 1433215976Sjmallett uint64_t reserved_2_63 : 62; 1434215976Sjmallett#endif 1435215976Sjmallett } s; 1436215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn52xx; 1437215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn52xxp1; 1438215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn56xx; 1439215976Sjmallett struct cvmx_agl_gmx_inf_mode_s cn56xxp1; 1440215976Sjmallett}; 1441215976Sjmalletttypedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t; 1442215976Sjmallett 1443215976Sjmallett/** 1444215976Sjmallett * cvmx_agl_gmx_prt#_cfg 1445215976Sjmallett * 1446215976Sjmallett * AGL_GMX_PRT_CFG = Port description 1447215976Sjmallett * 1448215976Sjmallett * 1449215976Sjmallett * Notes: 1450215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1451215976Sjmallett * 1452215976Sjmallett */ 1453232812Sjmallettunion cvmx_agl_gmx_prtx_cfg { 1454215976Sjmallett uint64_t u64; 1455232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_s { 1456232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1457215976Sjmallett uint64_t reserved_14_63 : 50; 1458215976Sjmallett uint64_t tx_idle : 1; /**< TX Machine is idle */ 1459215976Sjmallett uint64_t rx_idle : 1; /**< RX Machine is idle */ 1460215976Sjmallett uint64_t reserved_9_11 : 3; 1461215976Sjmallett uint64_t speed_msb : 1; /**< Link Speed MSB [SPEED_MSB:SPEED] 1462215976Sjmallett 10 = 10Mbs operation 1463215976Sjmallett 00 = 100Mbs operation 1464215976Sjmallett 01 = 1000Mbs operation 1465215976Sjmallett 11 = Reserved */ 1466215976Sjmallett uint64_t reserved_7_7 : 1; 1467215976Sjmallett uint64_t burst : 1; /**< Half-Duplex Burst Enable 1468215976Sjmallett Only valid for 1000Mbs half-duplex operation 1469215976Sjmallett 0 = burst length of 0x2000 (halfdup / 1000Mbs) 1470215976Sjmallett 1 = burst length of 0x0 (all other modes) */ 1471215976Sjmallett uint64_t tx_en : 1; /**< Port enable. Must be set for Octane to send 1472215976Sjmallett RMGII traffic. When this bit clear on a given 1473215976Sjmallett port, then all packet cycles will appear as 1474215976Sjmallett inter-frame cycles. */ 1475215976Sjmallett uint64_t rx_en : 1; /**< Port enable. Must be set for Octane to receive 1476215976Sjmallett RMGII traffic. When this bit clear on a given 1477215976Sjmallett port, then the all packet cycles will appear as 1478215976Sjmallett inter-frame cycles. */ 1479215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 1480215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 1481215976Sjmallett 1 = 4096 bitimes (1000Mbs operation) */ 1482215976Sjmallett uint64_t duplex : 1; /**< Duplex 1483215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 1484215976Sjmallett 1 = Full Duplex */ 1485215976Sjmallett uint64_t speed : 1; /**< Link Speed LSB [SPEED_MSB:SPEED] 1486215976Sjmallett 10 = 10Mbs operation 1487215976Sjmallett 00 = 100Mbs operation 1488215976Sjmallett 01 = 1000Mbs operation 1489215976Sjmallett 11 = Reserved */ 1490215976Sjmallett uint64_t en : 1; /**< Link Enable 1491215976Sjmallett When EN is clear, packets will not be received 1492215976Sjmallett or transmitted (including PAUSE and JAM packets). 1493215976Sjmallett If EN is cleared while a packet is currently 1494215976Sjmallett being received or transmitted, the packet will 1495215976Sjmallett be allowed to complete before the bus is idled. 1496215976Sjmallett On the RX side, subsequent packets in a burst 1497215976Sjmallett will be ignored. */ 1498215976Sjmallett#else 1499215976Sjmallett uint64_t en : 1; 1500215976Sjmallett uint64_t speed : 1; 1501215976Sjmallett uint64_t duplex : 1; 1502215976Sjmallett uint64_t slottime : 1; 1503215976Sjmallett uint64_t rx_en : 1; 1504215976Sjmallett uint64_t tx_en : 1; 1505215976Sjmallett uint64_t burst : 1; 1506215976Sjmallett uint64_t reserved_7_7 : 1; 1507215976Sjmallett uint64_t speed_msb : 1; 1508215976Sjmallett uint64_t reserved_9_11 : 3; 1509215976Sjmallett uint64_t rx_idle : 1; 1510215976Sjmallett uint64_t tx_idle : 1; 1511215976Sjmallett uint64_t reserved_14_63 : 50; 1512215976Sjmallett#endif 1513215976Sjmallett } s; 1514232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx { 1515232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1516215976Sjmallett uint64_t reserved_6_63 : 58; 1517215976Sjmallett uint64_t tx_en : 1; /**< Port enable. Must be set for Octane to send 1518215976Sjmallett RMGII traffic. When this bit clear on a given 1519215976Sjmallett port, then all MII cycles will appear as 1520215976Sjmallett inter-frame cycles. */ 1521215976Sjmallett uint64_t rx_en : 1; /**< Port enable. Must be set for Octane to receive 1522215976Sjmallett RMGII traffic. When this bit clear on a given 1523215976Sjmallett port, then the all MII cycles will appear as 1524215976Sjmallett inter-frame cycles. */ 1525215976Sjmallett uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation 1526215976Sjmallett 0 = 512 bitimes (10/100Mbs operation) 1527215976Sjmallett 1 = Reserved */ 1528215976Sjmallett uint64_t duplex : 1; /**< Duplex 1529215976Sjmallett 0 = Half Duplex (collisions/extentions/bursts) 1530215976Sjmallett 1 = Full Duplex */ 1531215976Sjmallett uint64_t speed : 1; /**< Link Speed 1532215976Sjmallett 0 = 10/100Mbs operation 1533215976Sjmallett 1 = Reserved */ 1534215976Sjmallett uint64_t en : 1; /**< Link Enable 1535215976Sjmallett When EN is clear, packets will not be received 1536215976Sjmallett or transmitted (including PAUSE and JAM packets). 1537215976Sjmallett If EN is cleared while a packet is currently 1538215976Sjmallett being received or transmitted, the packet will 1539215976Sjmallett be allowed to complete before the bus is idled. 1540215976Sjmallett On the RX side, subsequent packets in a burst 1541215976Sjmallett will be ignored. */ 1542215976Sjmallett#else 1543215976Sjmallett uint64_t en : 1; 1544215976Sjmallett uint64_t speed : 1; 1545215976Sjmallett uint64_t duplex : 1; 1546215976Sjmallett uint64_t slottime : 1; 1547215976Sjmallett uint64_t rx_en : 1; 1548215976Sjmallett uint64_t tx_en : 1; 1549215976Sjmallett uint64_t reserved_6_63 : 58; 1550215976Sjmallett#endif 1551215976Sjmallett } cn52xx; 1552215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1; 1553215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx; 1554215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1; 1555232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn61xx; 1556215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn63xx; 1557215976Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1; 1558232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn66xx; 1559232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn68xx; 1560232812Sjmallett struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1; 1561215976Sjmallett}; 1562215976Sjmalletttypedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t; 1563215976Sjmallett 1564215976Sjmallett/** 1565215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam0 1566215976Sjmallett * 1567215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1568215976Sjmallett * 1569215976Sjmallett * 1570215976Sjmallett * Notes: 1571215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1572215976Sjmallett * 1573215976Sjmallett */ 1574232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam0 { 1575215976Sjmallett uint64_t u64; 1576232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s { 1577232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1578215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1579232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1580215976Sjmallett The CAM matches against unicst or multicst DMAC 1581215976Sjmallett addresses. */ 1582215976Sjmallett#else 1583215976Sjmallett uint64_t adr : 64; 1584215976Sjmallett#endif 1585215976Sjmallett } s; 1586215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; 1587215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 1588215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 1589215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 1590232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx; 1591215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx; 1592215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1; 1593232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx; 1594232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx; 1595232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1; 1596215976Sjmallett}; 1597215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t; 1598215976Sjmallett 1599215976Sjmallett/** 1600215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam1 1601215976Sjmallett * 1602215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1603215976Sjmallett * 1604215976Sjmallett * 1605215976Sjmallett * Notes: 1606215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1607215976Sjmallett * 1608215976Sjmallett */ 1609232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam1 { 1610215976Sjmallett uint64_t u64; 1611232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s { 1612232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1613215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1614232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1615215976Sjmallett The CAM matches against unicst or multicst DMAC 1616215976Sjmallett addresses. */ 1617215976Sjmallett#else 1618215976Sjmallett uint64_t adr : 64; 1619215976Sjmallett#endif 1620215976Sjmallett } s; 1621215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; 1622215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 1623215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 1624215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 1625232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx; 1626215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx; 1627215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1; 1628232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx; 1629232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx; 1630232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1; 1631215976Sjmallett}; 1632215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t; 1633215976Sjmallett 1634215976Sjmallett/** 1635215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam2 1636215976Sjmallett * 1637215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1638215976Sjmallett * 1639215976Sjmallett * 1640215976Sjmallett * Notes: 1641215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1642215976Sjmallett * 1643215976Sjmallett */ 1644232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam2 { 1645215976Sjmallett uint64_t u64; 1646232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s { 1647232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1648215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1649232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1650215976Sjmallett The CAM matches against unicst or multicst DMAC 1651215976Sjmallett addresses. */ 1652215976Sjmallett#else 1653215976Sjmallett uint64_t adr : 64; 1654215976Sjmallett#endif 1655215976Sjmallett } s; 1656215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; 1657215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 1658215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 1659215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 1660232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx; 1661215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx; 1662215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1; 1663232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx; 1664232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx; 1665232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1; 1666215976Sjmallett}; 1667215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t; 1668215976Sjmallett 1669215976Sjmallett/** 1670215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam3 1671215976Sjmallett * 1672215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1673215976Sjmallett * 1674215976Sjmallett * 1675215976Sjmallett * Notes: 1676215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1677215976Sjmallett * 1678215976Sjmallett */ 1679232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam3 { 1680215976Sjmallett uint64_t u64; 1681232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s { 1682232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1683215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1684232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1685215976Sjmallett The CAM matches against unicst or multicst DMAC 1686215976Sjmallett addresses. */ 1687215976Sjmallett#else 1688215976Sjmallett uint64_t adr : 64; 1689215976Sjmallett#endif 1690215976Sjmallett } s; 1691215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; 1692215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 1693215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 1694215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 1695232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx; 1696215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx; 1697215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1; 1698232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx; 1699232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx; 1700232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1; 1701215976Sjmallett}; 1702215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t; 1703215976Sjmallett 1704215976Sjmallett/** 1705215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam4 1706215976Sjmallett * 1707215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1708215976Sjmallett * 1709215976Sjmallett * 1710215976Sjmallett * Notes: 1711215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1712215976Sjmallett * 1713215976Sjmallett */ 1714232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam4 { 1715215976Sjmallett uint64_t u64; 1716232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s { 1717232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1718215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1719232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1720215976Sjmallett The CAM matches against unicst or multicst DMAC 1721215976Sjmallett addresses. */ 1722215976Sjmallett#else 1723215976Sjmallett uint64_t adr : 64; 1724215976Sjmallett#endif 1725215976Sjmallett } s; 1726215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; 1727215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 1728215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 1729215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 1730232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx; 1731215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx; 1732215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1; 1733232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx; 1734232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx; 1735232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1; 1736215976Sjmallett}; 1737215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t; 1738215976Sjmallett 1739215976Sjmallett/** 1740215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam5 1741215976Sjmallett * 1742215976Sjmallett * AGL_GMX_RX_ADR_CAM = Address Filtering Control 1743215976Sjmallett * 1744215976Sjmallett * 1745215976Sjmallett * Notes: 1746215976Sjmallett * Not reset when MIX*_CTL[RESET] is set to 1. 1747215976Sjmallett * 1748215976Sjmallett */ 1749232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam5 { 1750215976Sjmallett uint64_t u64; 1751232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s { 1752232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1753215976Sjmallett uint64_t adr : 64; /**< The DMAC address to match on 1754232812Sjmallett Each entry contributes 8bits to one of 8 matchers. 1755215976Sjmallett The CAM matches against unicst or multicst DMAC 1756215976Sjmallett addresses. */ 1757215976Sjmallett#else 1758215976Sjmallett uint64_t adr : 64; 1759215976Sjmallett#endif 1760215976Sjmallett } s; 1761215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; 1762215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 1763215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 1764215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 1765232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx; 1766215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx; 1767215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1; 1768232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx; 1769232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx; 1770232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1; 1771215976Sjmallett}; 1772215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t; 1773215976Sjmallett 1774215976Sjmallett/** 1775215976Sjmallett * cvmx_agl_gmx_rx#_adr_cam_en 1776215976Sjmallett * 1777215976Sjmallett * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable 1778215976Sjmallett * 1779215976Sjmallett * 1780215976Sjmallett * Notes: 1781215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1782215976Sjmallett * 1783215976Sjmallett */ 1784232812Sjmallettunion cvmx_agl_gmx_rxx_adr_cam_en { 1785215976Sjmallett uint64_t u64; 1786232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s { 1787232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1788215976Sjmallett uint64_t reserved_8_63 : 56; 1789215976Sjmallett uint64_t en : 8; /**< CAM Entry Enables */ 1790215976Sjmallett#else 1791215976Sjmallett uint64_t en : 8; 1792215976Sjmallett uint64_t reserved_8_63 : 56; 1793215976Sjmallett#endif 1794215976Sjmallett } s; 1795215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; 1796215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 1797215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 1798215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 1799232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx; 1800215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx; 1801215976Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1; 1802232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx; 1803232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx; 1804232812Sjmallett struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1; 1805215976Sjmallett}; 1806215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t; 1807215976Sjmallett 1808215976Sjmallett/** 1809215976Sjmallett * cvmx_agl_gmx_rx#_adr_ctl 1810215976Sjmallett * 1811215976Sjmallett * AGL_GMX_RX_ADR_CTL = Address Filtering Control 1812215976Sjmallett * 1813215976Sjmallett * 1814215976Sjmallett * Notes: 1815215976Sjmallett * * ALGORITHM 1816215976Sjmallett * Here is some pseudo code that represents the address filter behavior. 1817215976Sjmallett * 1818215976Sjmallett * @verbatim 1819215976Sjmallett * bool dmac_addr_filter(uint8 prt, uint48 dmac) [ 1820215976Sjmallett * ASSERT(prt >= 0 && prt <= 3); 1821215976Sjmallett * if (is_bcst(dmac)) // broadcast accept 1822215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT); 1823215976Sjmallett * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject 1824215976Sjmallett * return REJECT; 1825215976Sjmallett * if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept 1826215976Sjmallett * return ACCEPT; 1827215976Sjmallett * 1828215976Sjmallett * cam_hit = 0; 1829215976Sjmallett * 1830215976Sjmallett * for (i=0; i<8; i++) [ 1831215976Sjmallett * if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0) 1832215976Sjmallett * continue; 1833215976Sjmallett * uint48 unswizzled_mac_adr = 0x0; 1834215976Sjmallett * for (j=5; j>=0; j--) [ 1835215976Sjmallett * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>]; 1836215976Sjmallett * ] 1837215976Sjmallett * if (unswizzled_mac_adr == dmac) [ 1838215976Sjmallett * cam_hit = 1; 1839215976Sjmallett * break; 1840215976Sjmallett * ] 1841215976Sjmallett * ] 1842215976Sjmallett * 1843215976Sjmallett * if (cam_hit) 1844215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT); 1845215976Sjmallett * else 1846215976Sjmallett * return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT); 1847215976Sjmallett * ] 1848215976Sjmallett * @endverbatim 1849215976Sjmallett * 1850215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1851215976Sjmallett */ 1852232812Sjmallettunion cvmx_agl_gmx_rxx_adr_ctl { 1853215976Sjmallett uint64_t u64; 1854232812Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s { 1855232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1856215976Sjmallett uint64_t reserved_4_63 : 60; 1857215976Sjmallett uint64_t cam_mode : 1; /**< Allow or deny DMAC address filter 1858215976Sjmallett 0 = reject the packet on DMAC address match 1859215976Sjmallett 1 = accept the packet on DMAC address match */ 1860215976Sjmallett uint64_t mcst : 2; /**< Multicast Mode 1861215976Sjmallett 0 = Use the Address Filter CAM 1862215976Sjmallett 1 = Force reject all multicast packets 1863215976Sjmallett 2 = Force accept all multicast packets 1864215976Sjmallett 3 = Reserved */ 1865215976Sjmallett uint64_t bcst : 1; /**< Accept All Broadcast Packets */ 1866215976Sjmallett#else 1867215976Sjmallett uint64_t bcst : 1; 1868215976Sjmallett uint64_t mcst : 2; 1869215976Sjmallett uint64_t cam_mode : 1; 1870215976Sjmallett uint64_t reserved_4_63 : 60; 1871215976Sjmallett#endif 1872215976Sjmallett } s; 1873215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; 1874215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 1875215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 1876215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 1877232812Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx; 1878215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx; 1879215976Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1; 1880232812Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx; 1881232812Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx; 1882232812Sjmallett struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1; 1883215976Sjmallett}; 1884215976Sjmalletttypedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t; 1885215976Sjmallett 1886215976Sjmallett/** 1887215976Sjmallett * cvmx_agl_gmx_rx#_decision 1888215976Sjmallett * 1889215976Sjmallett * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet 1890215976Sjmallett * 1891215976Sjmallett * 1892215976Sjmallett * Notes: 1893215976Sjmallett * As each byte in a packet is received by GMX, the L2 byte count is compared 1894215976Sjmallett * against the AGL_GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes 1895215976Sjmallett * from the beginning of the L2 header (DMAC). In normal operation, the L2 1896215976Sjmallett * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any 1897215976Sjmallett * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]). 1898215976Sjmallett * 1899215976Sjmallett * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the 1900215976Sjmallett * packet and would require UDD skip length to account for them. 1901215976Sjmallett * 1902215976Sjmallett * L2 Size 1903215976Sjmallett * Port Mode <=AGL_GMX_RX_DECISION bytes (default=24) >AGL_GMX_RX_DECISION bytes (default=24) 1904215976Sjmallett * 1905215976Sjmallett * MII/Full Duplex accept packet apply filters 1906215976Sjmallett * no filtering is applied accept packet based on DMAC and PAUSE packet filters 1907215976Sjmallett * 1908215976Sjmallett * MII/Half Duplex drop packet apply filters 1909215976Sjmallett * packet is unconditionally dropped accept packet based on DMAC 1910215976Sjmallett * 1911215976Sjmallett * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8) 1912215976Sjmallett * 1913215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1914215976Sjmallett */ 1915232812Sjmallettunion cvmx_agl_gmx_rxx_decision { 1916215976Sjmallett uint64_t u64; 1917232812Sjmallett struct cvmx_agl_gmx_rxx_decision_s { 1918232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1919215976Sjmallett uint64_t reserved_5_63 : 59; 1920215976Sjmallett uint64_t cnt : 5; /**< The byte count to decide when to accept or filter 1921215976Sjmallett a packet. */ 1922215976Sjmallett#else 1923215976Sjmallett uint64_t cnt : 5; 1924215976Sjmallett uint64_t reserved_5_63 : 59; 1925215976Sjmallett#endif 1926215976Sjmallett } s; 1927215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn52xx; 1928215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 1929215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn56xx; 1930215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 1931232812Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn61xx; 1932215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn63xx; 1933215976Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn63xxp1; 1934232812Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn66xx; 1935232812Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn68xx; 1936232812Sjmallett struct cvmx_agl_gmx_rxx_decision_s cn68xxp1; 1937215976Sjmallett}; 1938215976Sjmalletttypedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t; 1939215976Sjmallett 1940215976Sjmallett/** 1941215976Sjmallett * cvmx_agl_gmx_rx#_frm_chk 1942215976Sjmallett * 1943215976Sjmallett * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame 1944215976Sjmallett * 1945215976Sjmallett * 1946215976Sjmallett * Notes: 1947215976Sjmallett * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW. 1948215976Sjmallett * 1949215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 1950215976Sjmallett */ 1951232812Sjmallettunion cvmx_agl_gmx_rxx_frm_chk { 1952215976Sjmallett uint64_t u64; 1953232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s { 1954232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1955215976Sjmallett uint64_t reserved_10_63 : 54; 1956215976Sjmallett uint64_t niberr : 1; /**< Nibble error */ 1957215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 1958215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with packet data reception error */ 1959215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 1960215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 1961215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 1962215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 1963215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1964215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 1965215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1966215976Sjmallett#else 1967215976Sjmallett uint64_t minerr : 1; 1968215976Sjmallett uint64_t carext : 1; 1969215976Sjmallett uint64_t maxerr : 1; 1970215976Sjmallett uint64_t jabber : 1; 1971215976Sjmallett uint64_t fcserr : 1; 1972215976Sjmallett uint64_t alnerr : 1; 1973215976Sjmallett uint64_t lenerr : 1; 1974215976Sjmallett uint64_t rcverr : 1; 1975215976Sjmallett uint64_t skperr : 1; 1976215976Sjmallett uint64_t niberr : 1; 1977215976Sjmallett uint64_t reserved_10_63 : 54; 1978215976Sjmallett#endif 1979215976Sjmallett } s; 1980232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { 1981232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1982215976Sjmallett uint64_t reserved_9_63 : 55; 1983215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 1984215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with MII Data reception error */ 1985215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 1986215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 1987215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 1988215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 1989215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1990215976Sjmallett uint64_t reserved_1_1 : 1; 1991215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1992215976Sjmallett#else 1993215976Sjmallett uint64_t minerr : 1; 1994215976Sjmallett uint64_t reserved_1_1 : 1; 1995215976Sjmallett uint64_t maxerr : 1; 1996215976Sjmallett uint64_t jabber : 1; 1997215976Sjmallett uint64_t fcserr : 1; 1998215976Sjmallett uint64_t alnerr : 1; 1999215976Sjmallett uint64_t lenerr : 1; 2000215976Sjmallett uint64_t rcverr : 1; 2001215976Sjmallett uint64_t skperr : 1; 2002215976Sjmallett uint64_t reserved_9_63 : 55; 2003215976Sjmallett#endif 2004215976Sjmallett } cn52xx; 2005215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1; 2006215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx; 2007215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1; 2008232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx; 2009215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx; 2010215976Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1; 2011232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx; 2012232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx; 2013232812Sjmallett struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1; 2014215976Sjmallett}; 2015215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t; 2016215976Sjmallett 2017215976Sjmallett/** 2018215976Sjmallett * cvmx_agl_gmx_rx#_frm_ctl 2019215976Sjmallett * 2020215976Sjmallett * AGL_GMX_RX_FRM_CTL = Frame Control 2021215976Sjmallett * 2022215976Sjmallett * 2023215976Sjmallett * Notes: 2024215976Sjmallett * * PRE_STRP 2025215976Sjmallett * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP 2026215976Sjmallett * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane 2027215976Sjmallett * core as part of the packet. 2028215976Sjmallett * 2029215976Sjmallett * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet 2030215976Sjmallett * size when checking against the MIN and MAX bounds. Furthermore, the bytes 2031215976Sjmallett * are skipped when locating the start of the L2 header for DMAC and Control 2032215976Sjmallett * frame recognition. 2033215976Sjmallett * 2034215976Sjmallett * * CTL_BCK/CTL_DRP 2035215976Sjmallett * These bits control how the HW handles incoming PAUSE packets. Here are 2036215976Sjmallett * the most common modes of operation: 2037215976Sjmallett * CTL_BCK=1,CTL_DRP=1 - HW does it all 2038215976Sjmallett * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames 2039215976Sjmallett * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored 2040215976Sjmallett * 2041215976Sjmallett * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode. 2042215976Sjmallett * Since PAUSE packets only apply to fulldup operation, any PAUSE packet 2043215976Sjmallett * would constitute an exception which should be handled by the processing 2044215976Sjmallett * cores. PAUSE packets should not be forwarded. 2045215976Sjmallett * 2046215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2047215976Sjmallett */ 2048232812Sjmallettunion cvmx_agl_gmx_rxx_frm_ctl { 2049215976Sjmallett uint64_t u64; 2050232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s { 2051232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2052215976Sjmallett uint64_t reserved_13_63 : 51; 2053215976Sjmallett uint64_t ptp_mode : 1; /**< Timestamp mode 2054215976Sjmallett When PTP_MODE is set, a 64-bit timestamp will be 2055215976Sjmallett prepended to every incoming packet. The timestamp 2056215976Sjmallett bytes are added to the packet in such a way as to 2057215976Sjmallett not modify the packet's receive byte count. This 2058215976Sjmallett implies that the AGL_GMX_RX_JABBER, 2059215976Sjmallett AGL_GMX_RX_FRM_MIN, AGL_GMX_RX_FRM_MAX, 2060215976Sjmallett AGL_GMX_RX_DECISION, AGL_GMX_RX_UDD_SKP, and the 2061215976Sjmallett AGL_GMX_RX_STATS_* do not require any adjustment 2062215976Sjmallett as they operate on the received packet size. 2063215976Sjmallett If PTP_MODE=1 and PRE_CHK=1, PRE_STRP must be 1. */ 2064215976Sjmallett uint64_t reserved_11_11 : 1; 2065215976Sjmallett uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks 2066215976Sjmallett due to PARITAL packets */ 2067215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 2068215976Sjmallett regardless of the number of previous PREAMBLE 2069215976Sjmallett nibbles. In this mode, PRE_STRP should be set to 2070215976Sjmallett account for the variable nature of the PREAMBLE. 2071215976Sjmallett PRE_CHK must be set to enable this and all 2072215976Sjmallett PREAMBLE features. */ 2073215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 2074215976Sjmallett sized pkts with padding in the client data */ 2075215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 2076215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 2077215976Sjmallett AGL will begin the frame at the first SFD. 2078215976Sjmallett PRE_FREE must be set if PRE_ALIGN is set. 2079215976Sjmallett PRE_CHK must be set to enable this and all 2080215976Sjmallett PREAMBLE features. */ 2081215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 2082215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 2083215976Sjmallett Multicast address */ 2084215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 2085215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 2086215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 2087215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 2088215976Sjmallett 1=PREAMBLE+SFD is dropped 2089215976Sjmallett PRE_STRP must be set if PRE_ALIGN is set. 2090215976Sjmallett PRE_CHK must be set to enable this and all 2091215976Sjmallett PREAMBLE features. */ 2092215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send a valid 802.3 2093215976Sjmallett PREAMBLE to begin every frame. AGL checks that a 2094215976Sjmallett valid PREAMBLE is received (based on PRE_FREE). 2095215976Sjmallett When a problem does occur within the PREAMBLE 2096215976Sjmallett seqeunce, the frame is marked as bad and not sent 2097215976Sjmallett into the core. The AGL_GMX_RX_INT_REG[PCTERR] 2098215976Sjmallett interrupt is also raised. */ 2099215976Sjmallett#else 2100215976Sjmallett uint64_t pre_chk : 1; 2101215976Sjmallett uint64_t pre_strp : 1; 2102215976Sjmallett uint64_t ctl_drp : 1; 2103215976Sjmallett uint64_t ctl_bck : 1; 2104215976Sjmallett uint64_t ctl_mcst : 1; 2105215976Sjmallett uint64_t ctl_smac : 1; 2106215976Sjmallett uint64_t pre_free : 1; 2107215976Sjmallett uint64_t vlan_len : 1; 2108215976Sjmallett uint64_t pad_len : 1; 2109215976Sjmallett uint64_t pre_align : 1; 2110215976Sjmallett uint64_t null_dis : 1; 2111215976Sjmallett uint64_t reserved_11_11 : 1; 2112215976Sjmallett uint64_t ptp_mode : 1; 2113215976Sjmallett uint64_t reserved_13_63 : 51; 2114215976Sjmallett#endif 2115215976Sjmallett } s; 2116232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { 2117232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2118215976Sjmallett uint64_t reserved_10_63 : 54; 2119215976Sjmallett uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte 2120215976Sjmallett regardless of the number of previous PREAMBLE 2121215976Sjmallett nibbles. In this mode, PREAMBLE can be consumed 2122215976Sjmallett by the HW so when PRE_ALIGN is set, PRE_FREE, 2123215976Sjmallett PRE_STRP must be set for correct operation. 2124215976Sjmallett PRE_CHK must be set to enable this and all 2125215976Sjmallett PREAMBLE features. */ 2126215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for non-min 2127215976Sjmallett sized pkts with padding in the client data */ 2128215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 2129215976Sjmallett uint64_t pre_free : 1; /**< When set, PREAMBLE checking is less strict. 2130215976Sjmallett 0 - 254 cycles of PREAMBLE followed by SFD 2131215976Sjmallett PRE_FREE must be set if PRE_ALIGN is set. 2132215976Sjmallett PRE_CHK must be set to enable this and all 2133215976Sjmallett PREAMBLE features. */ 2134215976Sjmallett uint64_t ctl_smac : 1; /**< Control Pause Frames can match station SMAC */ 2135215976Sjmallett uint64_t ctl_mcst : 1; /**< Control Pause Frames can match globally assign 2136215976Sjmallett Multicast address */ 2137215976Sjmallett uint64_t ctl_bck : 1; /**< Forward pause information to TX block */ 2138215976Sjmallett uint64_t ctl_drp : 1; /**< Drop Control Pause Frames */ 2139215976Sjmallett uint64_t pre_strp : 1; /**< Strip off the preamble (when present) 2140215976Sjmallett 0=PREAMBLE+SFD is sent to core as part of frame 2141215976Sjmallett 1=PREAMBLE+SFD is dropped 2142215976Sjmallett PRE_STRP must be set if PRE_ALIGN is set. 2143215976Sjmallett PRE_CHK must be set to enable this and all 2144215976Sjmallett PREAMBLE features. */ 2145215976Sjmallett uint64_t pre_chk : 1; /**< This port is configured to send PREAMBLE+SFD 2146215976Sjmallett to begin every frame. GMX checks that the 2147215976Sjmallett PREAMBLE is sent correctly */ 2148215976Sjmallett#else 2149215976Sjmallett uint64_t pre_chk : 1; 2150215976Sjmallett uint64_t pre_strp : 1; 2151215976Sjmallett uint64_t ctl_drp : 1; 2152215976Sjmallett uint64_t ctl_bck : 1; 2153215976Sjmallett uint64_t ctl_mcst : 1; 2154215976Sjmallett uint64_t ctl_smac : 1; 2155215976Sjmallett uint64_t pre_free : 1; 2156215976Sjmallett uint64_t vlan_len : 1; 2157215976Sjmallett uint64_t pad_len : 1; 2158215976Sjmallett uint64_t pre_align : 1; 2159215976Sjmallett uint64_t reserved_10_63 : 54; 2160215976Sjmallett#endif 2161215976Sjmallett } cn52xx; 2162215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1; 2163215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx; 2164215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1; 2165232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx; 2166215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx; 2167215976Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1; 2168232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx; 2169232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx; 2170232812Sjmallett struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1; 2171215976Sjmallett}; 2172215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t; 2173215976Sjmallett 2174215976Sjmallett/** 2175215976Sjmallett * cvmx_agl_gmx_rx#_frm_max 2176215976Sjmallett * 2177215976Sjmallett * AGL_GMX_RX_FRM_MAX = Frame Max length 2178215976Sjmallett * 2179215976Sjmallett * 2180215976Sjmallett * Notes: 2181215976Sjmallett * When changing the LEN field, be sure that LEN does not exceed 2182215976Sjmallett * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that 2183215976Sjmallett * are within the maximum length parameter to be rejected because they exceed 2184215976Sjmallett * the AGL_GMX_RX_JABBER[CNT] limit. 2185215976Sjmallett * 2186215976Sjmallett * Notes: 2187215976Sjmallett * 2188215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2189215976Sjmallett */ 2190232812Sjmallettunion cvmx_agl_gmx_rxx_frm_max { 2191215976Sjmallett uint64_t u64; 2192232812Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s { 2193232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2194215976Sjmallett uint64_t reserved_16_63 : 48; 2195215976Sjmallett uint64_t len : 16; /**< Byte count for Max-sized frame check 2196215976Sjmallett AGL_GMX_RXn_FRM_CHK[MAXERR] enables the check 2197215976Sjmallett for port n. 2198215976Sjmallett If enabled, failing packets set the MAXERR 2199215976Sjmallett interrupt and the MIX opcode is set to OVER_FCS 2200215976Sjmallett (0x3, if packet has bad FCS) or OVER_ERR (0x4, if 2201215976Sjmallett packet has good FCS). 2202215976Sjmallett LEN <= AGL_GMX_RX_JABBER[CNT] */ 2203215976Sjmallett#else 2204215976Sjmallett uint64_t len : 16; 2205215976Sjmallett uint64_t reserved_16_63 : 48; 2206215976Sjmallett#endif 2207215976Sjmallett } s; 2208215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; 2209215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 2210215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 2211215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 2212232812Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn61xx; 2213215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn63xx; 2214215976Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1; 2215232812Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn66xx; 2216232812Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn68xx; 2217232812Sjmallett struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1; 2218215976Sjmallett}; 2219215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t; 2220215976Sjmallett 2221215976Sjmallett/** 2222215976Sjmallett * cvmx_agl_gmx_rx#_frm_min 2223215976Sjmallett * 2224215976Sjmallett * AGL_GMX_RX_FRM_MIN = Frame Min length 2225215976Sjmallett * 2226215976Sjmallett * 2227215976Sjmallett * Notes: 2228215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2229215976Sjmallett * 2230215976Sjmallett */ 2231232812Sjmallettunion cvmx_agl_gmx_rxx_frm_min { 2232215976Sjmallett uint64_t u64; 2233232812Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s { 2234232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2235215976Sjmallett uint64_t reserved_16_63 : 48; 2236215976Sjmallett uint64_t len : 16; /**< Byte count for Min-sized frame check 2237215976Sjmallett AGL_GMX_RXn_FRM_CHK[MINERR] enables the check 2238215976Sjmallett for port n. 2239215976Sjmallett If enabled, failing packets set the MINERR 2240215976Sjmallett interrupt and the MIX opcode is set to UNDER_FCS 2241215976Sjmallett (0x6, if packet has bad FCS) or UNDER_ERR (0x8, 2242215976Sjmallett if packet has good FCS). */ 2243215976Sjmallett#else 2244215976Sjmallett uint64_t len : 16; 2245215976Sjmallett uint64_t reserved_16_63 : 48; 2246215976Sjmallett#endif 2247215976Sjmallett } s; 2248215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; 2249215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 2250215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 2251215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 2252232812Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn61xx; 2253215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn63xx; 2254215976Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1; 2255232812Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn66xx; 2256232812Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn68xx; 2257232812Sjmallett struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1; 2258215976Sjmallett}; 2259215976Sjmalletttypedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t; 2260215976Sjmallett 2261215976Sjmallett/** 2262215976Sjmallett * cvmx_agl_gmx_rx#_ifg 2263215976Sjmallett * 2264215976Sjmallett * AGL_GMX_RX_IFG = RX Min IFG 2265215976Sjmallett * 2266215976Sjmallett * 2267215976Sjmallett * Notes: 2268215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2269215976Sjmallett * 2270215976Sjmallett */ 2271232812Sjmallettunion cvmx_agl_gmx_rxx_ifg { 2272215976Sjmallett uint64_t u64; 2273232812Sjmallett struct cvmx_agl_gmx_rxx_ifg_s { 2274232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2275215976Sjmallett uint64_t reserved_4_63 : 60; 2276215976Sjmallett uint64_t ifg : 4; /**< Min IFG (in IFG*8 bits) between packets used to 2277215976Sjmallett determine IFGERR. Normally IFG is 96 bits. 2278215976Sjmallett Note in some operating modes, IFG cycles can be 2279215976Sjmallett inserted or removed in order to achieve clock rate 2280215976Sjmallett adaptation. For these reasons, the default value 2281215976Sjmallett is slightly conservative and does not check upto 2282215976Sjmallett the full 96 bits of IFG. */ 2283215976Sjmallett#else 2284215976Sjmallett uint64_t ifg : 4; 2285215976Sjmallett uint64_t reserved_4_63 : 60; 2286215976Sjmallett#endif 2287215976Sjmallett } s; 2288215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn52xx; 2289215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 2290215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 2291215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 2292232812Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn61xx; 2293215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn63xx; 2294215976Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1; 2295232812Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn66xx; 2296232812Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn68xx; 2297232812Sjmallett struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1; 2298215976Sjmallett}; 2299215976Sjmalletttypedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t; 2300215976Sjmallett 2301215976Sjmallett/** 2302215976Sjmallett * cvmx_agl_gmx_rx#_int_en 2303215976Sjmallett * 2304215976Sjmallett * AGL_GMX_RX_INT_EN = Interrupt Enable 2305215976Sjmallett * 2306215976Sjmallett * 2307215976Sjmallett * Notes: 2308215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2309215976Sjmallett * 2310215976Sjmallett */ 2311232812Sjmallettunion cvmx_agl_gmx_rxx_int_en { 2312215976Sjmallett uint64_t u64; 2313232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_s { 2314232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2315215976Sjmallett uint64_t reserved_20_63 : 44; 2316215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2317215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex | NS */ 2318215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed | NS */ 2319215976Sjmallett uint64_t phy_link : 1; /**< Change in the RMGII inbound LinkStatus | NS */ 2320215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 2321215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2322215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2323215976Sjmallett uint64_t rsverr : 1; /**< Packet reserved opcodes */ 2324215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2325215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 2326215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) | NS */ 2327215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2328215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 2329215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2330215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2331215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2332215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2333215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2334215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 2335215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2336215976Sjmallett#else 2337215976Sjmallett uint64_t minerr : 1; 2338215976Sjmallett uint64_t carext : 1; 2339215976Sjmallett uint64_t maxerr : 1; 2340215976Sjmallett uint64_t jabber : 1; 2341215976Sjmallett uint64_t fcserr : 1; 2342215976Sjmallett uint64_t alnerr : 1; 2343215976Sjmallett uint64_t lenerr : 1; 2344215976Sjmallett uint64_t rcverr : 1; 2345215976Sjmallett uint64_t skperr : 1; 2346215976Sjmallett uint64_t niberr : 1; 2347215976Sjmallett uint64_t ovrerr : 1; 2348215976Sjmallett uint64_t pcterr : 1; 2349215976Sjmallett uint64_t rsverr : 1; 2350215976Sjmallett uint64_t falerr : 1; 2351215976Sjmallett uint64_t coldet : 1; 2352215976Sjmallett uint64_t ifgerr : 1; 2353215976Sjmallett uint64_t phy_link : 1; 2354215976Sjmallett uint64_t phy_spd : 1; 2355215976Sjmallett uint64_t phy_dupx : 1; 2356215976Sjmallett uint64_t pause_drp : 1; 2357215976Sjmallett uint64_t reserved_20_63 : 44; 2358215976Sjmallett#endif 2359215976Sjmallett } s; 2360232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx { 2361232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2362215976Sjmallett uint64_t reserved_20_63 : 44; 2363215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2364215976Sjmallett uint64_t reserved_16_18 : 3; 2365215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation */ 2366215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2367215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2368215976Sjmallett uint64_t rsverr : 1; /**< MII reserved opcodes */ 2369215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2370215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow */ 2371215976Sjmallett uint64_t reserved_9_9 : 1; 2372215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2373215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with RMGII Data reception error */ 2374215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2375215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2376215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2377215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2378215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2379215976Sjmallett uint64_t reserved_1_1 : 1; 2380215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2381215976Sjmallett#else 2382215976Sjmallett uint64_t minerr : 1; 2383215976Sjmallett uint64_t reserved_1_1 : 1; 2384215976Sjmallett uint64_t maxerr : 1; 2385215976Sjmallett uint64_t jabber : 1; 2386215976Sjmallett uint64_t fcserr : 1; 2387215976Sjmallett uint64_t alnerr : 1; 2388215976Sjmallett uint64_t lenerr : 1; 2389215976Sjmallett uint64_t rcverr : 1; 2390215976Sjmallett uint64_t skperr : 1; 2391215976Sjmallett uint64_t reserved_9_9 : 1; 2392215976Sjmallett uint64_t ovrerr : 1; 2393215976Sjmallett uint64_t pcterr : 1; 2394215976Sjmallett uint64_t rsverr : 1; 2395215976Sjmallett uint64_t falerr : 1; 2396215976Sjmallett uint64_t coldet : 1; 2397215976Sjmallett uint64_t ifgerr : 1; 2398215976Sjmallett uint64_t reserved_16_18 : 3; 2399215976Sjmallett uint64_t pause_drp : 1; 2400215976Sjmallett uint64_t reserved_20_63 : 44; 2401215976Sjmallett#endif 2402215976Sjmallett } cn52xx; 2403215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1; 2404215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx; 2405215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1; 2406232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn61xx; 2407215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn63xx; 2408215976Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1; 2409232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn66xx; 2410232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn68xx; 2411232812Sjmallett struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1; 2412215976Sjmallett}; 2413215976Sjmalletttypedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t; 2414215976Sjmallett 2415215976Sjmallett/** 2416215976Sjmallett * cvmx_agl_gmx_rx#_int_reg 2417215976Sjmallett * 2418215976Sjmallett * AGL_GMX_RX_INT_REG = Interrupt Register 2419215976Sjmallett * 2420215976Sjmallett * 2421215976Sjmallett * Notes: 2422215976Sjmallett * (1) exceptions will only be raised to the control processor if the 2423215976Sjmallett * corresponding bit in the AGL_GMX_RX_INT_EN register is set. 2424215976Sjmallett * 2425215976Sjmallett * (2) exception conditions 10:0 can also set the rcv/opcode in the received 2426215976Sjmallett * packet's workQ entry. The AGL_GMX_RX_FRM_CHK register provides a bit mask 2427215976Sjmallett * for configuring which conditions set the error. 2428215976Sjmallett * 2429215976Sjmallett * (3) in half duplex operation, the expectation is that collisions will appear 2430215976Sjmallett * as MINERRs. 2431215976Sjmallett * 2432215976Sjmallett * (4) JABBER - An RX Jabber error indicates that a packet was received which 2433215976Sjmallett * is longer than the maximum allowed packet as defined by the 2434215976Sjmallett * system. GMX will truncate the packet at the JABBER count. 2435215976Sjmallett * Failure to do so could lead to system instabilty. 2436215976Sjmallett * 2437215976Sjmallett * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS > 2438215976Sjmallett * AGL_GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS 2439215976Sjmallett * > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED. 2440215976Sjmallett * 2441215976Sjmallett * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN. 2442215976Sjmallett * 2443215976Sjmallett * (8) ALNERR - Indicates that the packet received was not an integer number of 2444215976Sjmallett * bytes. If FCS checking is enabled, ALNERR will only assert if 2445215976Sjmallett * the FCS is bad. If FCS checking is disabled, ALNERR will 2446215976Sjmallett * assert in all non-integer frame cases. 2447215976Sjmallett * 2448215976Sjmallett * (9) Collisions - Collisions can only occur in half-duplex mode. A collision 2449215976Sjmallett * is assumed by the receiver when the received 2450215976Sjmallett * frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR 2451215976Sjmallett * 2452215976Sjmallett * (A) LENERR - Length errors occur when the received packet does not match the 2453215976Sjmallett * length field. LENERR is only checked for packets between 64 2454215976Sjmallett * and 1500 bytes. For untagged frames, the length must exact 2455215976Sjmallett * match. For tagged frames the length or length+4 must match. 2456215976Sjmallett * 2457215976Sjmallett * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence. 2458215976Sjmallett * Does not check the number of PREAMBLE cycles. 2459215976Sjmallett * 2460232812Sjmallett * (C) OVRERR - 2461215976Sjmallett * 2462215976Sjmallett * OVRERR is an architectural assertion check internal to GMX to 2463215976Sjmallett * make sure no assumption was violated. In a correctly operating 2464215976Sjmallett * system, this interrupt can never fire. 2465215976Sjmallett * 2466215976Sjmallett * GMX has an internal arbiter which selects which of 4 ports to 2467215976Sjmallett * buffer in the main RX FIFO. If we normally buffer 8 bytes, 2468215976Sjmallett * then each port will typically push a tick every 8 cycles - if 2469215976Sjmallett * the packet interface is going as fast as possible. If there 2470215976Sjmallett * are four ports, they push every two cycles. So that's the 2471215976Sjmallett * assumption. That the inbound module will always be able to 2472215976Sjmallett * consume the tick before another is produced. If that doesn't 2473215976Sjmallett * happen - that's when OVRERR will assert. 2474215976Sjmallett * 2475215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2476215976Sjmallett */ 2477232812Sjmallettunion cvmx_agl_gmx_rxx_int_reg { 2478215976Sjmallett uint64_t u64; 2479232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s { 2480232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2481215976Sjmallett uint64_t reserved_20_63 : 44; 2482215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2483215976Sjmallett uint64_t phy_dupx : 1; /**< Change in the RGMII inbound LinkDuplex | NS */ 2484215976Sjmallett uint64_t phy_spd : 1; /**< Change in the RGMII inbound LinkSpeed | NS */ 2485215976Sjmallett uint64_t phy_link : 1; /**< Change in the RGMII inbound LinkStatus | NS */ 2486215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 2487215976Sjmallett Does not necessarily indicate a failure */ 2488215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2489215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2490215976Sjmallett uint64_t rsverr : 1; /**< Packet reserved opcodes */ 2491215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2492215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 2493215976Sjmallett This interrupt should never assert */ 2494215976Sjmallett uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) | NS */ 2495215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2496215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with Packet Data reception error */ 2497215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2498215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2499215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2500215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2501215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2502215976Sjmallett uint64_t carext : 1; /**< Carrier extend error */ 2503215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2504215976Sjmallett#else 2505215976Sjmallett uint64_t minerr : 1; 2506215976Sjmallett uint64_t carext : 1; 2507215976Sjmallett uint64_t maxerr : 1; 2508215976Sjmallett uint64_t jabber : 1; 2509215976Sjmallett uint64_t fcserr : 1; 2510215976Sjmallett uint64_t alnerr : 1; 2511215976Sjmallett uint64_t lenerr : 1; 2512215976Sjmallett uint64_t rcverr : 1; 2513215976Sjmallett uint64_t skperr : 1; 2514215976Sjmallett uint64_t niberr : 1; 2515215976Sjmallett uint64_t ovrerr : 1; 2516215976Sjmallett uint64_t pcterr : 1; 2517215976Sjmallett uint64_t rsverr : 1; 2518215976Sjmallett uint64_t falerr : 1; 2519215976Sjmallett uint64_t coldet : 1; 2520215976Sjmallett uint64_t ifgerr : 1; 2521215976Sjmallett uint64_t phy_link : 1; 2522215976Sjmallett uint64_t phy_spd : 1; 2523215976Sjmallett uint64_t phy_dupx : 1; 2524215976Sjmallett uint64_t pause_drp : 1; 2525215976Sjmallett uint64_t reserved_20_63 : 44; 2526215976Sjmallett#endif 2527215976Sjmallett } s; 2528232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx { 2529232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2530215976Sjmallett uint64_t reserved_20_63 : 44; 2531215976Sjmallett uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */ 2532215976Sjmallett uint64_t reserved_16_18 : 3; 2533215976Sjmallett uint64_t ifgerr : 1; /**< Interframe Gap Violation 2534215976Sjmallett Does not necessarily indicate a failure */ 2535215976Sjmallett uint64_t coldet : 1; /**< Collision Detection */ 2536215976Sjmallett uint64_t falerr : 1; /**< False carrier error or extend error after slottime */ 2537215976Sjmallett uint64_t rsverr : 1; /**< MII reserved opcodes */ 2538215976Sjmallett uint64_t pcterr : 1; /**< Bad Preamble / Protocol */ 2539215976Sjmallett uint64_t ovrerr : 1; /**< Internal Data Aggregation Overflow 2540215976Sjmallett This interrupt should never assert */ 2541215976Sjmallett uint64_t reserved_9_9 : 1; 2542215976Sjmallett uint64_t skperr : 1; /**< Skipper error */ 2543215976Sjmallett uint64_t rcverr : 1; /**< Frame was received with MII Data reception error */ 2544215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2545215976Sjmallett uint64_t alnerr : 1; /**< Frame was received with an alignment error */ 2546215976Sjmallett uint64_t fcserr : 1; /**< Frame was received with FCS/CRC error */ 2547215976Sjmallett uint64_t jabber : 1; /**< Frame was received with length > sys_length */ 2548215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2549215976Sjmallett uint64_t reserved_1_1 : 1; 2550215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2551215976Sjmallett#else 2552215976Sjmallett uint64_t minerr : 1; 2553215976Sjmallett uint64_t reserved_1_1 : 1; 2554215976Sjmallett uint64_t maxerr : 1; 2555215976Sjmallett uint64_t jabber : 1; 2556215976Sjmallett uint64_t fcserr : 1; 2557215976Sjmallett uint64_t alnerr : 1; 2558215976Sjmallett uint64_t lenerr : 1; 2559215976Sjmallett uint64_t rcverr : 1; 2560215976Sjmallett uint64_t skperr : 1; 2561215976Sjmallett uint64_t reserved_9_9 : 1; 2562215976Sjmallett uint64_t ovrerr : 1; 2563215976Sjmallett uint64_t pcterr : 1; 2564215976Sjmallett uint64_t rsverr : 1; 2565215976Sjmallett uint64_t falerr : 1; 2566215976Sjmallett uint64_t coldet : 1; 2567215976Sjmallett uint64_t ifgerr : 1; 2568215976Sjmallett uint64_t reserved_16_18 : 3; 2569215976Sjmallett uint64_t pause_drp : 1; 2570215976Sjmallett uint64_t reserved_20_63 : 44; 2571215976Sjmallett#endif 2572215976Sjmallett } cn52xx; 2573215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1; 2574215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx; 2575215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1; 2576232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn61xx; 2577215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn63xx; 2578215976Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1; 2579232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn66xx; 2580232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn68xx; 2581232812Sjmallett struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1; 2582215976Sjmallett}; 2583215976Sjmalletttypedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t; 2584215976Sjmallett 2585215976Sjmallett/** 2586215976Sjmallett * cvmx_agl_gmx_rx#_jabber 2587215976Sjmallett * 2588215976Sjmallett * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate 2589215976Sjmallett * 2590215976Sjmallett * 2591215976Sjmallett * Notes: 2592215976Sjmallett * CNT must be 8-byte aligned such that CNT[2:0] == 0 2593215976Sjmallett * 2594215976Sjmallett * The packet that will be sent to the packet input logic will have an 2595215976Sjmallett * additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and 2596215976Sjmallett * AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is 2597215976Sjmallett * defined as... 2598215976Sjmallett * 2599215976Sjmallett * max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8) 2600215976Sjmallett * 2601215976Sjmallett * Be sure the CNT field value is at least as large as the 2602215976Sjmallett * AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause 2603215976Sjmallett * packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected 2604215976Sjmallett * because they exceed the CNT limit. 2605215976Sjmallett * 2606215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2607215976Sjmallett */ 2608232812Sjmallettunion cvmx_agl_gmx_rxx_jabber { 2609215976Sjmallett uint64_t u64; 2610232812Sjmallett struct cvmx_agl_gmx_rxx_jabber_s { 2611232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2612215976Sjmallett uint64_t reserved_16_63 : 48; 2613215976Sjmallett uint64_t cnt : 16; /**< Byte count for jabber check 2614215976Sjmallett Failing packets set the JABBER interrupt and are 2615215976Sjmallett optionally sent with opcode==JABBER 2616215976Sjmallett GMX will truncate the packet to CNT bytes 2617215976Sjmallett CNT >= AGL_GMX_RX_FRM_MAX[LEN] */ 2618215976Sjmallett#else 2619215976Sjmallett uint64_t cnt : 16; 2620215976Sjmallett uint64_t reserved_16_63 : 48; 2621215976Sjmallett#endif 2622215976Sjmallett } s; 2623215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn52xx; 2624215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 2625215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 2626215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 2627232812Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn61xx; 2628215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn63xx; 2629215976Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1; 2630232812Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn66xx; 2631232812Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn68xx; 2632232812Sjmallett struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1; 2633215976Sjmallett}; 2634215976Sjmalletttypedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t; 2635215976Sjmallett 2636215976Sjmallett/** 2637215976Sjmallett * cvmx_agl_gmx_rx#_pause_drop_time 2638215976Sjmallett * 2639215976Sjmallett * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition 2640215976Sjmallett * 2641215976Sjmallett * 2642215976Sjmallett * Notes: 2643215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2644215976Sjmallett * 2645215976Sjmallett */ 2646232812Sjmallettunion cvmx_agl_gmx_rxx_pause_drop_time { 2647215976Sjmallett uint64_t u64; 2648232812Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s { 2649232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2650215976Sjmallett uint64_t reserved_16_63 : 48; 2651215976Sjmallett uint64_t status : 16; /**< Time extracted from the dropped PAUSE packet */ 2652215976Sjmallett#else 2653215976Sjmallett uint64_t status : 16; 2654215976Sjmallett uint64_t reserved_16_63 : 48; 2655215976Sjmallett#endif 2656215976Sjmallett } s; 2657215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; 2658215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 2659215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 2660215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 2661232812Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx; 2662215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx; 2663215976Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1; 2664232812Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx; 2665232812Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx; 2666232812Sjmallett struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1; 2667215976Sjmallett}; 2668215976Sjmalletttypedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t; 2669215976Sjmallett 2670215976Sjmallett/** 2671215976Sjmallett * cvmx_agl_gmx_rx#_rx_inbnd 2672215976Sjmallett * 2673215976Sjmallett * AGL_GMX_RX_INBND = RGMII InBand Link Status 2674215976Sjmallett * 2675215976Sjmallett * 2676215976Sjmallett * Notes: 2677215976Sjmallett * These fields are only valid if the attached PHY is operating in RGMII mode 2678215976Sjmallett * and supports the optional in-band status (see section 3.4.1 of the RGMII 2679215976Sjmallett * specification, version 1.3 for more information). 2680215976Sjmallett * 2681215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2682215976Sjmallett */ 2683232812Sjmallettunion cvmx_agl_gmx_rxx_rx_inbnd { 2684215976Sjmallett uint64_t u64; 2685232812Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s { 2686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2687215976Sjmallett uint64_t reserved_4_63 : 60; 2688215976Sjmallett uint64_t duplex : 1; /**< RGMII Inbound LinkDuplex | NS 2689215976Sjmallett 0=half-duplex 2690215976Sjmallett 1=full-duplex */ 2691215976Sjmallett uint64_t speed : 2; /**< RGMII Inbound LinkSpeed | NS 2692215976Sjmallett 00=2.5MHz 2693215976Sjmallett 01=25MHz 2694215976Sjmallett 10=125MHz 2695215976Sjmallett 11=Reserved */ 2696215976Sjmallett uint64_t status : 1; /**< RGMII Inbound LinkStatus | NS 2697215976Sjmallett 0=down 2698215976Sjmallett 1=up */ 2699215976Sjmallett#else 2700215976Sjmallett uint64_t status : 1; 2701215976Sjmallett uint64_t speed : 2; 2702215976Sjmallett uint64_t duplex : 1; 2703215976Sjmallett uint64_t reserved_4_63 : 60; 2704215976Sjmallett#endif 2705215976Sjmallett } s; 2706232812Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx; 2707215976Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx; 2708215976Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1; 2709232812Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx; 2710232812Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx; 2711232812Sjmallett struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1; 2712215976Sjmallett}; 2713215976Sjmalletttypedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t; 2714215976Sjmallett 2715215976Sjmallett/** 2716215976Sjmallett * cvmx_agl_gmx_rx#_stats_ctl 2717215976Sjmallett * 2718215976Sjmallett * AGL_GMX_RX_STATS_CTL = RX Stats Control register 2719215976Sjmallett * 2720215976Sjmallett * 2721215976Sjmallett * Notes: 2722215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 2723215976Sjmallett * 2724215976Sjmallett */ 2725232812Sjmallettunion cvmx_agl_gmx_rxx_stats_ctl { 2726215976Sjmallett uint64_t u64; 2727232812Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s { 2728232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2729215976Sjmallett uint64_t reserved_1_63 : 63; 2730215976Sjmallett uint64_t rd_clr : 1; /**< RX Stats registers will clear on reads */ 2731215976Sjmallett#else 2732215976Sjmallett uint64_t rd_clr : 1; 2733215976Sjmallett uint64_t reserved_1_63 : 63; 2734215976Sjmallett#endif 2735215976Sjmallett } s; 2736215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; 2737215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 2738215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 2739215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 2740232812Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx; 2741215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx; 2742215976Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1; 2743232812Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx; 2744232812Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx; 2745232812Sjmallett struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1; 2746215976Sjmallett}; 2747215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t; 2748215976Sjmallett 2749215976Sjmallett/** 2750215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs 2751215976Sjmallett * 2752215976Sjmallett * Notes: 2753215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2754215976Sjmallett * - Counters will wrap 2755215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2756215976Sjmallett */ 2757232812Sjmallettunion cvmx_agl_gmx_rxx_stats_octs { 2758215976Sjmallett uint64_t u64; 2759232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s { 2760232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2761215976Sjmallett uint64_t reserved_48_63 : 16; 2762215976Sjmallett uint64_t cnt : 48; /**< Octet count of received good packets */ 2763215976Sjmallett#else 2764215976Sjmallett uint64_t cnt : 48; 2765215976Sjmallett uint64_t reserved_48_63 : 16; 2766215976Sjmallett#endif 2767215976Sjmallett } s; 2768215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; 2769215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 2770215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 2771215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 2772232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx; 2773215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx; 2774215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1; 2775232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx; 2776232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx; 2777232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1; 2778215976Sjmallett}; 2779215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t; 2780215976Sjmallett 2781215976Sjmallett/** 2782215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_ctl 2783215976Sjmallett * 2784215976Sjmallett * Notes: 2785215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2786215976Sjmallett * - Counters will wrap 2787215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2788215976Sjmallett */ 2789232812Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_ctl { 2790215976Sjmallett uint64_t u64; 2791232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { 2792232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2793215976Sjmallett uint64_t reserved_48_63 : 16; 2794215976Sjmallett uint64_t cnt : 48; /**< Octet count of received pause packets */ 2795215976Sjmallett#else 2796215976Sjmallett uint64_t cnt : 48; 2797215976Sjmallett uint64_t reserved_48_63 : 16; 2798215976Sjmallett#endif 2799215976Sjmallett } s; 2800215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; 2801215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 2802215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 2803215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 2804232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx; 2805215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx; 2806215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1; 2807232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx; 2808232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx; 2809232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1; 2810215976Sjmallett}; 2811215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t; 2812215976Sjmallett 2813215976Sjmallett/** 2814215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_dmac 2815215976Sjmallett * 2816215976Sjmallett * Notes: 2817215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2818215976Sjmallett * - Counters will wrap 2819215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2820215976Sjmallett */ 2821232812Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_dmac { 2822215976Sjmallett uint64_t u64; 2823232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { 2824232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2825215976Sjmallett uint64_t reserved_48_63 : 16; 2826215976Sjmallett uint64_t cnt : 48; /**< Octet count of filtered dmac packets */ 2827215976Sjmallett#else 2828215976Sjmallett uint64_t cnt : 48; 2829215976Sjmallett uint64_t reserved_48_63 : 16; 2830215976Sjmallett#endif 2831215976Sjmallett } s; 2832215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; 2833215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 2834215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 2835215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 2836232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx; 2837215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx; 2838215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1; 2839232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx; 2840232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx; 2841232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1; 2842215976Sjmallett}; 2843215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t; 2844215976Sjmallett 2845215976Sjmallett/** 2846215976Sjmallett * cvmx_agl_gmx_rx#_stats_octs_drp 2847215976Sjmallett * 2848215976Sjmallett * Notes: 2849215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2850215976Sjmallett * - Counters will wrap 2851215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2852215976Sjmallett */ 2853232812Sjmallettunion cvmx_agl_gmx_rxx_stats_octs_drp { 2854215976Sjmallett uint64_t u64; 2855232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s { 2856232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2857215976Sjmallett uint64_t reserved_48_63 : 16; 2858215976Sjmallett uint64_t cnt : 48; /**< Octet count of dropped packets */ 2859215976Sjmallett#else 2860215976Sjmallett uint64_t cnt : 48; 2861215976Sjmallett uint64_t reserved_48_63 : 16; 2862215976Sjmallett#endif 2863215976Sjmallett } s; 2864215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; 2865215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 2866215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 2867215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 2868232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx; 2869215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx; 2870215976Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1; 2871232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx; 2872232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx; 2873232812Sjmallett struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1; 2874215976Sjmallett}; 2875215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t; 2876215976Sjmallett 2877215976Sjmallett/** 2878215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts 2879215976Sjmallett * 2880215976Sjmallett * AGL_GMX_RX_STATS_PKTS 2881215976Sjmallett * 2882215976Sjmallett * Count of good received packets - packets that are not recognized as PAUSE 2883215976Sjmallett * packets, dropped due the DMAC filter, dropped due FIFO full status, or 2884215976Sjmallett * have any other OPCODE (FCS, Length, etc). 2885215976Sjmallett * 2886215976Sjmallett * Notes: 2887215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2888215976Sjmallett * - Counters will wrap 2889215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2890215976Sjmallett */ 2891232812Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts { 2892215976Sjmallett uint64_t u64; 2893232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s { 2894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2895215976Sjmallett uint64_t reserved_32_63 : 32; 2896215976Sjmallett uint64_t cnt : 32; /**< Count of received good packets */ 2897215976Sjmallett#else 2898215976Sjmallett uint64_t cnt : 32; 2899215976Sjmallett uint64_t reserved_32_63 : 32; 2900215976Sjmallett#endif 2901215976Sjmallett } s; 2902215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; 2903215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 2904215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 2905215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 2906232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx; 2907215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx; 2908215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1; 2909232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx; 2910232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx; 2911232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1; 2912215976Sjmallett}; 2913215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t; 2914215976Sjmallett 2915215976Sjmallett/** 2916215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_bad 2917215976Sjmallett * 2918215976Sjmallett * AGL_GMX_RX_STATS_PKTS_BAD 2919215976Sjmallett * 2920215976Sjmallett * Count of all packets received with some error that were not dropped 2921215976Sjmallett * either due to the dmac filter or lack of room in the receive FIFO. 2922215976Sjmallett * 2923215976Sjmallett * Notes: 2924215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2925215976Sjmallett * - Counters will wrap 2926215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2927215976Sjmallett */ 2928232812Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_bad { 2929215976Sjmallett uint64_t u64; 2930232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { 2931232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2932215976Sjmallett uint64_t reserved_32_63 : 32; 2933215976Sjmallett uint64_t cnt : 32; /**< Count of bad packets */ 2934215976Sjmallett#else 2935215976Sjmallett uint64_t cnt : 32; 2936215976Sjmallett uint64_t reserved_32_63 : 32; 2937215976Sjmallett#endif 2938215976Sjmallett } s; 2939215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; 2940215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 2941215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 2942215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 2943232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx; 2944215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx; 2945215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1; 2946232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx; 2947232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx; 2948232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1; 2949215976Sjmallett}; 2950215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t; 2951215976Sjmallett 2952215976Sjmallett/** 2953215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_ctl 2954215976Sjmallett * 2955215976Sjmallett * AGL_GMX_RX_STATS_PKTS_CTL 2956215976Sjmallett * 2957215976Sjmallett * Count of all packets received that were recognized as Flow Control or 2958215976Sjmallett * PAUSE packets. PAUSE packets with any kind of error are counted in 2959215976Sjmallett * AGL_GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or 2960215976Sjmallett * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit. This count 2961215976Sjmallett * increments regardless of whether the packet is dropped. Pause packets 2962215976Sjmallett * will never be counted in AGL_GMX_RX_STATS_PKTS. Packets dropped due the dmac 2963215976Sjmallett * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here. 2964215976Sjmallett * 2965215976Sjmallett * Notes: 2966215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 2967215976Sjmallett * - Counters will wrap 2968215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 2969215976Sjmallett */ 2970232812Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_ctl { 2971215976Sjmallett uint64_t u64; 2972232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { 2973232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2974215976Sjmallett uint64_t reserved_32_63 : 32; 2975215976Sjmallett uint64_t cnt : 32; /**< Count of received pause packets */ 2976215976Sjmallett#else 2977215976Sjmallett uint64_t cnt : 32; 2978215976Sjmallett uint64_t reserved_32_63 : 32; 2979215976Sjmallett#endif 2980215976Sjmallett } s; 2981215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; 2982215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 2983215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 2984215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 2985232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx; 2986215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx; 2987215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1; 2988232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx; 2989232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx; 2990232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1; 2991215976Sjmallett}; 2992215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t; 2993215976Sjmallett 2994215976Sjmallett/** 2995215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_dmac 2996215976Sjmallett * 2997215976Sjmallett * AGL_GMX_RX_STATS_PKTS_DMAC 2998215976Sjmallett * 2999215976Sjmallett * Count of all packets received that were dropped by the dmac filter. 3000215976Sjmallett * Packets that match the DMAC will be dropped and counted here regardless 3001215976Sjmallett * of if they were bad packets. These packets will never be counted in 3002215976Sjmallett * AGL_GMX_RX_STATS_PKTS. 3003215976Sjmallett * 3004215976Sjmallett * Some packets that were not able to satisify the DECISION_CNT may not 3005215976Sjmallett * actually be dropped by Octeon, but they will be counted here as if they 3006215976Sjmallett * were dropped. 3007215976Sjmallett * 3008215976Sjmallett * Notes: 3009215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 3010215976Sjmallett * - Counters will wrap 3011215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3012215976Sjmallett */ 3013232812Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_dmac { 3014215976Sjmallett uint64_t u64; 3015232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { 3016232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3017215976Sjmallett uint64_t reserved_32_63 : 32; 3018215976Sjmallett uint64_t cnt : 32; /**< Count of filtered dmac packets */ 3019215976Sjmallett#else 3020215976Sjmallett uint64_t cnt : 32; 3021215976Sjmallett uint64_t reserved_32_63 : 32; 3022215976Sjmallett#endif 3023215976Sjmallett } s; 3024215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; 3025215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 3026215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 3027215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 3028232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx; 3029215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx; 3030215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1; 3031232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx; 3032232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx; 3033232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1; 3034215976Sjmallett}; 3035215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t; 3036215976Sjmallett 3037215976Sjmallett/** 3038215976Sjmallett * cvmx_agl_gmx_rx#_stats_pkts_drp 3039215976Sjmallett * 3040215976Sjmallett * AGL_GMX_RX_STATS_PKTS_DRP 3041215976Sjmallett * 3042215976Sjmallett * Count of all packets received that were dropped due to a full receive 3043215976Sjmallett * FIFO. This counts good and bad packets received - all packets dropped by 3044215976Sjmallett * the FIFO. It does not count packets dropped by the dmac or pause packet 3045215976Sjmallett * filters. 3046215976Sjmallett * 3047215976Sjmallett * Notes: 3048215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set 3049215976Sjmallett * - Counters will wrap 3050215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3051215976Sjmallett */ 3052232812Sjmallettunion cvmx_agl_gmx_rxx_stats_pkts_drp { 3053215976Sjmallett uint64_t u64; 3054232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { 3055232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3056215976Sjmallett uint64_t reserved_32_63 : 32; 3057215976Sjmallett uint64_t cnt : 32; /**< Count of dropped packets */ 3058215976Sjmallett#else 3059215976Sjmallett uint64_t cnt : 32; 3060215976Sjmallett uint64_t reserved_32_63 : 32; 3061215976Sjmallett#endif 3062215976Sjmallett } s; 3063215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; 3064215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 3065215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 3066215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 3067232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx; 3068215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx; 3069215976Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1; 3070232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx; 3071232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx; 3072232812Sjmallett struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1; 3073215976Sjmallett}; 3074215976Sjmalletttypedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t; 3075215976Sjmallett 3076215976Sjmallett/** 3077215976Sjmallett * cvmx_agl_gmx_rx#_udd_skp 3078215976Sjmallett * 3079215976Sjmallett * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data 3080215976Sjmallett * 3081215976Sjmallett * 3082215976Sjmallett * Notes: 3083215976Sjmallett * (1) The skip bytes are part of the packet and will be sent down the NCB 3084215976Sjmallett * packet interface and will be handled by PKI. 3085215976Sjmallett * 3086215976Sjmallett * (2) The system can determine if the UDD bytes are included in the FCS check 3087215976Sjmallett * by using the FCSSEL field - if the FCS check is enabled. 3088215976Sjmallett * 3089215976Sjmallett * (3) Assume that the preamble/sfd is always at the start of the frame - even 3090215976Sjmallett * before UDD bytes. In most cases, there will be no preamble in these 3091215976Sjmallett * cases since it will be MII to MII communication without a PHY 3092215976Sjmallett * involved. 3093215976Sjmallett * 3094215976Sjmallett * (4) We can still do address filtering and control packet filtering is the 3095215976Sjmallett * user desires. 3096215976Sjmallett * 3097215976Sjmallett * (5) UDD_SKP must be 0 in half-duplex operation unless 3098215976Sjmallett * AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear. If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set, 3099215976Sjmallett * then UDD_SKP will normally be 8. 3100215976Sjmallett * 3101215976Sjmallett * (6) In all cases, the UDD bytes will be sent down the packet interface as 3102215976Sjmallett * part of the packet. The UDD bytes are never stripped from the actual 3103215976Sjmallett * packet. 3104215976Sjmallett * 3105215976Sjmallett * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero 3106215976Sjmallett * 3107215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3108215976Sjmallett */ 3109232812Sjmallettunion cvmx_agl_gmx_rxx_udd_skp { 3110215976Sjmallett uint64_t u64; 3111232812Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s { 3112232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3113215976Sjmallett uint64_t reserved_9_63 : 55; 3114215976Sjmallett uint64_t fcssel : 1; /**< Include the skip bytes in the FCS calculation 3115215976Sjmallett 0 = all skip bytes are included in FCS 3116215976Sjmallett 1 = the skip bytes are not included in FCS */ 3117215976Sjmallett uint64_t reserved_7_7 : 1; 3118215976Sjmallett uint64_t len : 7; /**< Amount of User-defined data before the start of 3119215976Sjmallett the L2 data. Zero means L2 comes first. 3120215976Sjmallett Max value is 64. */ 3121215976Sjmallett#else 3122215976Sjmallett uint64_t len : 7; 3123215976Sjmallett uint64_t reserved_7_7 : 1; 3124215976Sjmallett uint64_t fcssel : 1; 3125215976Sjmallett uint64_t reserved_9_63 : 55; 3126215976Sjmallett#endif 3127215976Sjmallett } s; 3128215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; 3129215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 3130215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 3131215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 3132232812Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx; 3133215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx; 3134215976Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1; 3135232812Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx; 3136232812Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx; 3137232812Sjmallett struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1; 3138215976Sjmallett}; 3139215976Sjmalletttypedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t; 3140215976Sjmallett 3141215976Sjmallett/** 3142215976Sjmallett * cvmx_agl_gmx_rx_bp_drop# 3143215976Sjmallett * 3144215976Sjmallett * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop 3145215976Sjmallett * 3146215976Sjmallett * 3147215976Sjmallett * Notes: 3148215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3149215976Sjmallett * 3150215976Sjmallett */ 3151232812Sjmallettunion cvmx_agl_gmx_rx_bp_dropx { 3152215976Sjmallett uint64_t u64; 3153232812Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s { 3154232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3155215976Sjmallett uint64_t reserved_6_63 : 58; 3156215976Sjmallett uint64_t mark : 6; /**< Number of 8B ticks to reserve in the RX FIFO. 3157215976Sjmallett When the FIFO exceeds this count, packets will 3158215976Sjmallett be dropped and not buffered. 3159215976Sjmallett MARK should typically be programmed to 2. 3160215976Sjmallett Failure to program correctly can lead to system 3161215976Sjmallett instability. */ 3162215976Sjmallett#else 3163215976Sjmallett uint64_t mark : 6; 3164215976Sjmallett uint64_t reserved_6_63 : 58; 3165215976Sjmallett#endif 3166215976Sjmallett } s; 3167215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; 3168215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 3169215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 3170215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 3171232812Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx; 3172215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx; 3173215976Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1; 3174232812Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx; 3175232812Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx; 3176232812Sjmallett struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1; 3177215976Sjmallett}; 3178215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t; 3179215976Sjmallett 3180215976Sjmallett/** 3181215976Sjmallett * cvmx_agl_gmx_rx_bp_off# 3182215976Sjmallett * 3183215976Sjmallett * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop 3184215976Sjmallett * 3185215976Sjmallett * 3186215976Sjmallett * Notes: 3187215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3188215976Sjmallett * 3189215976Sjmallett */ 3190232812Sjmallettunion cvmx_agl_gmx_rx_bp_offx { 3191215976Sjmallett uint64_t u64; 3192232812Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s { 3193232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3194215976Sjmallett uint64_t reserved_6_63 : 58; 3195215976Sjmallett uint64_t mark : 6; /**< Water mark (8B ticks) to deassert backpressure */ 3196215976Sjmallett#else 3197215976Sjmallett uint64_t mark : 6; 3198215976Sjmallett uint64_t reserved_6_63 : 58; 3199215976Sjmallett#endif 3200215976Sjmallett } s; 3201215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; 3202215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 3203215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 3204215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 3205232812Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn61xx; 3206215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn63xx; 3207215976Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1; 3208232812Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn66xx; 3209232812Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn68xx; 3210232812Sjmallett struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1; 3211215976Sjmallett}; 3212215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t; 3213215976Sjmallett 3214215976Sjmallett/** 3215215976Sjmallett * cvmx_agl_gmx_rx_bp_on# 3216215976Sjmallett * 3217215976Sjmallett * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure 3218215976Sjmallett * 3219215976Sjmallett * 3220215976Sjmallett * Notes: 3221215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3222215976Sjmallett * 3223215976Sjmallett */ 3224232812Sjmallettunion cvmx_agl_gmx_rx_bp_onx { 3225215976Sjmallett uint64_t u64; 3226232812Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s { 3227232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3228215976Sjmallett uint64_t reserved_9_63 : 55; 3229215976Sjmallett uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure. */ 3230215976Sjmallett#else 3231215976Sjmallett uint64_t mark : 9; 3232215976Sjmallett uint64_t reserved_9_63 : 55; 3233215976Sjmallett#endif 3234215976Sjmallett } s; 3235215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; 3236215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 3237215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 3238215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 3239232812Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn61xx; 3240215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn63xx; 3241215976Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1; 3242232812Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn66xx; 3243232812Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn68xx; 3244232812Sjmallett struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1; 3245215976Sjmallett}; 3246215976Sjmalletttypedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t; 3247215976Sjmallett 3248215976Sjmallett/** 3249215976Sjmallett * cvmx_agl_gmx_rx_prt_info 3250215976Sjmallett * 3251215976Sjmallett * AGL_GMX_RX_PRT_INFO = state information for the ports 3252215976Sjmallett * 3253215976Sjmallett * 3254215976Sjmallett * Notes: 3255215976Sjmallett * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1. 3256215976Sjmallett * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1. 3257215976Sjmallett */ 3258232812Sjmallettunion cvmx_agl_gmx_rx_prt_info { 3259215976Sjmallett uint64_t u64; 3260232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_s { 3261232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3262215976Sjmallett uint64_t reserved_18_63 : 46; 3263215976Sjmallett uint64_t drop : 2; /**< Port indication that data was dropped */ 3264215976Sjmallett uint64_t reserved_2_15 : 14; 3265215976Sjmallett uint64_t commit : 2; /**< Port indication that SOP was accepted */ 3266215976Sjmallett#else 3267215976Sjmallett uint64_t commit : 2; 3268215976Sjmallett uint64_t reserved_2_15 : 14; 3269215976Sjmallett uint64_t drop : 2; 3270215976Sjmallett uint64_t reserved_18_63 : 46; 3271215976Sjmallett#endif 3272215976Sjmallett } s; 3273215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn52xx; 3274215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; 3275232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_cn56xx { 3276232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3277215976Sjmallett uint64_t reserved_17_63 : 47; 3278215976Sjmallett uint64_t drop : 1; /**< Port indication that data was dropped */ 3279215976Sjmallett uint64_t reserved_1_15 : 15; 3280215976Sjmallett uint64_t commit : 1; /**< Port indication that SOP was accepted */ 3281215976Sjmallett#else 3282215976Sjmallett uint64_t commit : 1; 3283215976Sjmallett uint64_t reserved_1_15 : 15; 3284215976Sjmallett uint64_t drop : 1; 3285215976Sjmallett uint64_t reserved_17_63 : 47; 3286215976Sjmallett#endif 3287215976Sjmallett } cn56xx; 3288215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 3289232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn61xx; 3290215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn63xx; 3291215976Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1; 3292232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn66xx; 3293232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn68xx; 3294232812Sjmallett struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1; 3295215976Sjmallett}; 3296215976Sjmalletttypedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t; 3297215976Sjmallett 3298215976Sjmallett/** 3299215976Sjmallett * cvmx_agl_gmx_rx_tx_status 3300215976Sjmallett * 3301215976Sjmallett * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status 3302215976Sjmallett * 3303215976Sjmallett * 3304215976Sjmallett * Notes: 3305215976Sjmallett * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1. 3306215976Sjmallett * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1. 3307215976Sjmallett */ 3308232812Sjmallettunion cvmx_agl_gmx_rx_tx_status { 3309215976Sjmallett uint64_t u64; 3310232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_s { 3311232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3312215976Sjmallett uint64_t reserved_6_63 : 58; 3313215976Sjmallett uint64_t tx : 2; /**< Transmit data since last read */ 3314215976Sjmallett uint64_t reserved_2_3 : 2; 3315215976Sjmallett uint64_t rx : 2; /**< Receive data since last read */ 3316215976Sjmallett#else 3317215976Sjmallett uint64_t rx : 2; 3318215976Sjmallett uint64_t reserved_2_3 : 2; 3319215976Sjmallett uint64_t tx : 2; 3320215976Sjmallett uint64_t reserved_6_63 : 58; 3321215976Sjmallett#endif 3322215976Sjmallett } s; 3323215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn52xx; 3324215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; 3325232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_cn56xx { 3326232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3327215976Sjmallett uint64_t reserved_5_63 : 59; 3328215976Sjmallett uint64_t tx : 1; /**< Transmit data since last read */ 3329215976Sjmallett uint64_t reserved_1_3 : 3; 3330215976Sjmallett uint64_t rx : 1; /**< Receive data since last read */ 3331215976Sjmallett#else 3332215976Sjmallett uint64_t rx : 1; 3333215976Sjmallett uint64_t reserved_1_3 : 3; 3334215976Sjmallett uint64_t tx : 1; 3335215976Sjmallett uint64_t reserved_5_63 : 59; 3336215976Sjmallett#endif 3337215976Sjmallett } cn56xx; 3338215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 3339232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn61xx; 3340215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn63xx; 3341215976Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1; 3342232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn66xx; 3343232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn68xx; 3344232812Sjmallett struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1; 3345215976Sjmallett}; 3346215976Sjmalletttypedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t; 3347215976Sjmallett 3348215976Sjmallett/** 3349215976Sjmallett * cvmx_agl_gmx_smac# 3350215976Sjmallett * 3351215976Sjmallett * AGL_GMX_SMAC = Packet SMAC 3352215976Sjmallett * 3353215976Sjmallett * 3354215976Sjmallett * Notes: 3355215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3356215976Sjmallett * 3357215976Sjmallett */ 3358232812Sjmallettunion cvmx_agl_gmx_smacx { 3359215976Sjmallett uint64_t u64; 3360232812Sjmallett struct cvmx_agl_gmx_smacx_s { 3361232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3362215976Sjmallett uint64_t reserved_48_63 : 16; 3363215976Sjmallett uint64_t smac : 48; /**< The SMAC field is used for generating and 3364215976Sjmallett accepting Control Pause packets */ 3365215976Sjmallett#else 3366215976Sjmallett uint64_t smac : 48; 3367215976Sjmallett uint64_t reserved_48_63 : 16; 3368215976Sjmallett#endif 3369215976Sjmallett } s; 3370215976Sjmallett struct cvmx_agl_gmx_smacx_s cn52xx; 3371215976Sjmallett struct cvmx_agl_gmx_smacx_s cn52xxp1; 3372215976Sjmallett struct cvmx_agl_gmx_smacx_s cn56xx; 3373215976Sjmallett struct cvmx_agl_gmx_smacx_s cn56xxp1; 3374232812Sjmallett struct cvmx_agl_gmx_smacx_s cn61xx; 3375215976Sjmallett struct cvmx_agl_gmx_smacx_s cn63xx; 3376215976Sjmallett struct cvmx_agl_gmx_smacx_s cn63xxp1; 3377232812Sjmallett struct cvmx_agl_gmx_smacx_s cn66xx; 3378232812Sjmallett struct cvmx_agl_gmx_smacx_s cn68xx; 3379232812Sjmallett struct cvmx_agl_gmx_smacx_s cn68xxp1; 3380215976Sjmallett}; 3381215976Sjmalletttypedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t; 3382215976Sjmallett 3383215976Sjmallett/** 3384215976Sjmallett * cvmx_agl_gmx_stat_bp 3385215976Sjmallett * 3386215976Sjmallett * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation 3387215976Sjmallett * 3388215976Sjmallett * 3389215976Sjmallett * Notes: 3390215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 3391215976Sjmallett * 3392232812Sjmallett * 3393232812Sjmallett * 3394232812Sjmallett * It has no relationship with the TX FIFO per se. The TX engine sends packets 3395232812Sjmallett * from PKO and upon completion, sends a command to the TX stats block for an 3396232812Sjmallett * update based on the packet size. The stats operation can take a few cycles - 3397232812Sjmallett * normally not enough to be visible considering the 64B min packet size that is 3398232812Sjmallett * ethernet convention. 3399232812Sjmallett * 3400232812Sjmallett * In the rare case in which SW attempted to schedule really, really, small packets 3401232812Sjmallett * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in 3402232812Sjmallett * real time and can back up the TX engine. 3403232812Sjmallett * 3404232812Sjmallett * This counter is the number of cycles in which the TX engine was stalled. In 3405232812Sjmallett * normal operation, it should always be zeros. 3406215976Sjmallett */ 3407232812Sjmallettunion cvmx_agl_gmx_stat_bp { 3408215976Sjmallett uint64_t u64; 3409232812Sjmallett struct cvmx_agl_gmx_stat_bp_s { 3410232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3411215976Sjmallett uint64_t reserved_17_63 : 47; 3412232812Sjmallett uint64_t bp : 1; /**< Current TX stats BP state 3413232812Sjmallett When the TX stats machine cannot update the stats 3414232812Sjmallett registers quickly enough, the machine has the 3415232812Sjmallett ability to BP TX datapath. This is a rare event 3416232812Sjmallett and will not occur in normal operation. 3417232812Sjmallett 0 = no backpressure is applied 3418232812Sjmallett 1 = backpressure is applied to TX datapath to 3419232812Sjmallett allow stat update operations to complete */ 3420215976Sjmallett uint64_t cnt : 16; /**< Number of cycles that BP has been asserted 3421215976Sjmallett Saturating counter */ 3422215976Sjmallett#else 3423215976Sjmallett uint64_t cnt : 16; 3424215976Sjmallett uint64_t bp : 1; 3425215976Sjmallett uint64_t reserved_17_63 : 47; 3426215976Sjmallett#endif 3427215976Sjmallett } s; 3428215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn52xx; 3429215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 3430215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn56xx; 3431215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 3432232812Sjmallett struct cvmx_agl_gmx_stat_bp_s cn61xx; 3433215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn63xx; 3434215976Sjmallett struct cvmx_agl_gmx_stat_bp_s cn63xxp1; 3435232812Sjmallett struct cvmx_agl_gmx_stat_bp_s cn66xx; 3436232812Sjmallett struct cvmx_agl_gmx_stat_bp_s cn68xx; 3437232812Sjmallett struct cvmx_agl_gmx_stat_bp_s cn68xxp1; 3438215976Sjmallett}; 3439215976Sjmalletttypedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t; 3440215976Sjmallett 3441215976Sjmallett/** 3442215976Sjmallett * cvmx_agl_gmx_tx#_append 3443215976Sjmallett * 3444215976Sjmallett * AGL_GMX_TX_APPEND = Packet TX Append Control 3445215976Sjmallett * 3446215976Sjmallett * 3447215976Sjmallett * Notes: 3448215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3449215976Sjmallett * 3450215976Sjmallett */ 3451232812Sjmallettunion cvmx_agl_gmx_txx_append { 3452215976Sjmallett uint64_t u64; 3453232812Sjmallett struct cvmx_agl_gmx_txx_append_s { 3454232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3455215976Sjmallett uint64_t reserved_4_63 : 60; 3456215976Sjmallett uint64_t force_fcs : 1; /**< Append the Ethernet FCS on each pause packet 3457215976Sjmallett when FCS is clear. Pause packets are normally 3458215976Sjmallett padded to 60 bytes. If 3459215976Sjmallett AGL_GMX_TX_MIN_PKT[MIN_SIZE] exceeds 59, then 3460215976Sjmallett FORCE_FCS will not be used. */ 3461215976Sjmallett uint64_t fcs : 1; /**< Append the Ethernet FCS on each packet */ 3462215976Sjmallett uint64_t pad : 1; /**< Append PAD bytes such that min sized */ 3463215976Sjmallett uint64_t preamble : 1; /**< Prepend the Ethernet preamble on each transfer */ 3464215976Sjmallett#else 3465215976Sjmallett uint64_t preamble : 1; 3466215976Sjmallett uint64_t pad : 1; 3467215976Sjmallett uint64_t fcs : 1; 3468215976Sjmallett uint64_t force_fcs : 1; 3469215976Sjmallett uint64_t reserved_4_63 : 60; 3470215976Sjmallett#endif 3471215976Sjmallett } s; 3472215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn52xx; 3473215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn52xxp1; 3474215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn56xx; 3475215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn56xxp1; 3476232812Sjmallett struct cvmx_agl_gmx_txx_append_s cn61xx; 3477215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn63xx; 3478215976Sjmallett struct cvmx_agl_gmx_txx_append_s cn63xxp1; 3479232812Sjmallett struct cvmx_agl_gmx_txx_append_s cn66xx; 3480232812Sjmallett struct cvmx_agl_gmx_txx_append_s cn68xx; 3481232812Sjmallett struct cvmx_agl_gmx_txx_append_s cn68xxp1; 3482215976Sjmallett}; 3483215976Sjmalletttypedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t; 3484215976Sjmallett 3485215976Sjmallett/** 3486215976Sjmallett * cvmx_agl_gmx_tx#_clk 3487215976Sjmallett * 3488215976Sjmallett * AGL_GMX_TX_CLK = RGMII TX Clock Generation Register 3489215976Sjmallett * 3490215976Sjmallett * 3491215976Sjmallett * Notes: 3492215976Sjmallett * Normal Programming Values: 3493215976Sjmallett * (1) RGMII, 1000Mbs (AGL_GMX_PRT_CFG[SPEED]==1), CLK_CNT == 1 3494215976Sjmallett * (2) RGMII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 50/5 3495215976Sjmallett * (3) MII, 10/100Mbs (AGL_GMX_PRT_CFG[SPEED]==0), CLK_CNT == 1 3496215976Sjmallett * 3497215976Sjmallett * RGMII Example: 3498215976Sjmallett * Given a 125MHz PLL reference clock... 3499215976Sjmallett * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1) 3500215976Sjmallett * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5) 3501215976Sjmallett * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50) 3502215976Sjmallett * 3503215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3504215976Sjmallett */ 3505232812Sjmallettunion cvmx_agl_gmx_txx_clk { 3506215976Sjmallett uint64_t u64; 3507232812Sjmallett struct cvmx_agl_gmx_txx_clk_s { 3508232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3509215976Sjmallett uint64_t reserved_6_63 : 58; 3510215976Sjmallett uint64_t clk_cnt : 6; /**< Controls the RGMII TXC frequency | NS 3511215976Sjmallett TXC(period) = 3512215976Sjmallett rgm_ref_clk(period)*CLK_CNT */ 3513215976Sjmallett#else 3514215976Sjmallett uint64_t clk_cnt : 6; 3515215976Sjmallett uint64_t reserved_6_63 : 58; 3516215976Sjmallett#endif 3517215976Sjmallett } s; 3518232812Sjmallett struct cvmx_agl_gmx_txx_clk_s cn61xx; 3519215976Sjmallett struct cvmx_agl_gmx_txx_clk_s cn63xx; 3520215976Sjmallett struct cvmx_agl_gmx_txx_clk_s cn63xxp1; 3521232812Sjmallett struct cvmx_agl_gmx_txx_clk_s cn66xx; 3522232812Sjmallett struct cvmx_agl_gmx_txx_clk_s cn68xx; 3523232812Sjmallett struct cvmx_agl_gmx_txx_clk_s cn68xxp1; 3524215976Sjmallett}; 3525215976Sjmalletttypedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t; 3526215976Sjmallett 3527215976Sjmallett/** 3528215976Sjmallett * cvmx_agl_gmx_tx#_ctl 3529215976Sjmallett * 3530215976Sjmallett * AGL_GMX_TX_CTL = TX Control register 3531215976Sjmallett * 3532215976Sjmallett * 3533215976Sjmallett * Notes: 3534215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3535215976Sjmallett * 3536215976Sjmallett */ 3537232812Sjmallettunion cvmx_agl_gmx_txx_ctl { 3538215976Sjmallett uint64_t u64; 3539232812Sjmallett struct cvmx_agl_gmx_txx_ctl_s { 3540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3541215976Sjmallett uint64_t reserved_2_63 : 62; 3542215976Sjmallett uint64_t xsdef_en : 1; /**< Enables the excessive deferral check for stats 3543215976Sjmallett and interrupts */ 3544215976Sjmallett uint64_t xscol_en : 1; /**< Enables the excessive collision check for stats 3545215976Sjmallett and interrupts */ 3546215976Sjmallett#else 3547215976Sjmallett uint64_t xscol_en : 1; 3548215976Sjmallett uint64_t xsdef_en : 1; 3549215976Sjmallett uint64_t reserved_2_63 : 62; 3550215976Sjmallett#endif 3551215976Sjmallett } s; 3552215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn52xx; 3553215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 3554215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn56xx; 3555215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 3556232812Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn61xx; 3557215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn63xx; 3558215976Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn63xxp1; 3559232812Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn66xx; 3560232812Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn68xx; 3561232812Sjmallett struct cvmx_agl_gmx_txx_ctl_s cn68xxp1; 3562215976Sjmallett}; 3563215976Sjmalletttypedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t; 3564215976Sjmallett 3565215976Sjmallett/** 3566215976Sjmallett * cvmx_agl_gmx_tx#_min_pkt 3567215976Sjmallett * 3568215976Sjmallett * AGL_GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size) 3569215976Sjmallett * 3570215976Sjmallett * 3571215976Sjmallett * Notes: 3572215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3573215976Sjmallett * 3574215976Sjmallett */ 3575232812Sjmallettunion cvmx_agl_gmx_txx_min_pkt { 3576215976Sjmallett uint64_t u64; 3577232812Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s { 3578232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3579215976Sjmallett uint64_t reserved_8_63 : 56; 3580215976Sjmallett uint64_t min_size : 8; /**< Min frame in bytes before the FCS is applied 3581215976Sjmallett Padding is only appened when 3582215976Sjmallett AGL_GMX_TX_APPEND[PAD] for the coresponding packet 3583215976Sjmallett port is set. Packets will be padded to 3584215976Sjmallett MIN_SIZE+1 The reset value will pad to 60 bytes. */ 3585215976Sjmallett#else 3586215976Sjmallett uint64_t min_size : 8; 3587215976Sjmallett uint64_t reserved_8_63 : 56; 3588215976Sjmallett#endif 3589215976Sjmallett } s; 3590215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; 3591215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 3592215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 3593215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 3594232812Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn61xx; 3595215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn63xx; 3596215976Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1; 3597232812Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn66xx; 3598232812Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn68xx; 3599232812Sjmallett struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1; 3600215976Sjmallett}; 3601215976Sjmalletttypedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t; 3602215976Sjmallett 3603215976Sjmallett/** 3604215976Sjmallett * cvmx_agl_gmx_tx#_pause_pkt_interval 3605215976Sjmallett * 3606215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent 3607215976Sjmallett * 3608215976Sjmallett * 3609215976Sjmallett * Notes: 3610215976Sjmallett * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 3611215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 3612215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 3613215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 3614215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 3615215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 3616215976Sjmallett * data. 3617215976Sjmallett * 3618215976Sjmallett * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 3619215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 3620215976Sjmallett * following rule... 3621215976Sjmallett * 3622215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 3623215976Sjmallett * 3624215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 3625215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 3626215976Sjmallett * of the PAUSE packet (normally 64B). 3627215976Sjmallett * 3628215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3629215976Sjmallett */ 3630232812Sjmallettunion cvmx_agl_gmx_txx_pause_pkt_interval { 3631215976Sjmallett uint64_t u64; 3632232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s { 3633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3634215976Sjmallett uint64_t reserved_16_63 : 48; 3635215976Sjmallett uint64_t interval : 16; /**< Arbitrate for a pause packet every (INTERVAL*512) 3636215976Sjmallett bit-times. 3637215976Sjmallett Normally, 0 < INTERVAL < AGL_GMX_TX_PAUSE_PKT_TIME 3638215976Sjmallett INTERVAL=0, will only send a single PAUSE packet 3639215976Sjmallett for each backpressure event */ 3640215976Sjmallett#else 3641215976Sjmallett uint64_t interval : 16; 3642215976Sjmallett uint64_t reserved_16_63 : 48; 3643215976Sjmallett#endif 3644215976Sjmallett } s; 3645215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; 3646215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 3647215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 3648215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 3649232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx; 3650215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx; 3651215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1; 3652232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx; 3653232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx; 3654232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1; 3655215976Sjmallett}; 3656215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t; 3657215976Sjmallett 3658215976Sjmallett/** 3659215976Sjmallett * cvmx_agl_gmx_tx#_pause_pkt_time 3660215976Sjmallett * 3661215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field 3662215976Sjmallett * 3663215976Sjmallett * 3664215976Sjmallett * Notes: 3665215976Sjmallett * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and 3666215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system 3667215976Sjmallett * designer. It is suggested that TIME be much greater than INTERVAL and 3668215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE 3669215976Sjmallett * count and then when the backpressure condition is lifted, a PAUSE packet 3670215976Sjmallett * with TIME==0 will be sent indicating that Octane is ready for additional 3671215976Sjmallett * data. 3672215976Sjmallett * 3673215976Sjmallett * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is 3674215976Sjmallett * suggested that TIME and INTERVAL are programmed such that they satisify the 3675215976Sjmallett * following rule... 3676215976Sjmallett * 3677215976Sjmallett * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size) 3678215976Sjmallett * 3679215976Sjmallett * where largest_pkt_size is that largest packet that the system can send 3680215976Sjmallett * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size 3681215976Sjmallett * of the PAUSE packet (normally 64B). 3682215976Sjmallett * 3683215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3684215976Sjmallett */ 3685232812Sjmallettunion cvmx_agl_gmx_txx_pause_pkt_time { 3686215976Sjmallett uint64_t u64; 3687232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s { 3688232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3689215976Sjmallett uint64_t reserved_16_63 : 48; 3690215976Sjmallett uint64_t time : 16; /**< The pause_time field placed is outbnd pause pkts 3691215976Sjmallett pause_time is in 512 bit-times 3692215976Sjmallett Normally, TIME > AGL_GMX_TX_PAUSE_PKT_INTERVAL */ 3693215976Sjmallett#else 3694215976Sjmallett uint64_t time : 16; 3695215976Sjmallett uint64_t reserved_16_63 : 48; 3696215976Sjmallett#endif 3697215976Sjmallett } s; 3698215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; 3699215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 3700215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 3701215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 3702232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx; 3703215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx; 3704215976Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1; 3705232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx; 3706232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx; 3707232812Sjmallett struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1; 3708215976Sjmallett}; 3709215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t; 3710215976Sjmallett 3711215976Sjmallett/** 3712215976Sjmallett * cvmx_agl_gmx_tx#_pause_togo 3713215976Sjmallett * 3714215976Sjmallett * AGL_GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure 3715215976Sjmallett * 3716215976Sjmallett * 3717215976Sjmallett * Notes: 3718215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3719215976Sjmallett * 3720215976Sjmallett */ 3721232812Sjmallettunion cvmx_agl_gmx_txx_pause_togo { 3722215976Sjmallett uint64_t u64; 3723232812Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s { 3724232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3725215976Sjmallett uint64_t reserved_16_63 : 48; 3726215976Sjmallett uint64_t time : 16; /**< Amount of time remaining to backpressure */ 3727215976Sjmallett#else 3728215976Sjmallett uint64_t time : 16; 3729215976Sjmallett uint64_t reserved_16_63 : 48; 3730215976Sjmallett#endif 3731215976Sjmallett } s; 3732215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; 3733215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 3734215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 3735215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 3736232812Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn61xx; 3737215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn63xx; 3738215976Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1; 3739232812Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn66xx; 3740232812Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn68xx; 3741232812Sjmallett struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1; 3742215976Sjmallett}; 3743215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t; 3744215976Sjmallett 3745215976Sjmallett/** 3746215976Sjmallett * cvmx_agl_gmx_tx#_pause_zero 3747215976Sjmallett * 3748215976Sjmallett * AGL_GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure 3749215976Sjmallett * 3750215976Sjmallett * 3751215976Sjmallett * Notes: 3752215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3753215976Sjmallett * 3754215976Sjmallett */ 3755232812Sjmallettunion cvmx_agl_gmx_txx_pause_zero { 3756215976Sjmallett uint64_t u64; 3757232812Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s { 3758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3759215976Sjmallett uint64_t reserved_1_63 : 63; 3760215976Sjmallett uint64_t send : 1; /**< When backpressure condition clear, send PAUSE 3761215976Sjmallett packet with pause_time of zero to enable the 3762215976Sjmallett channel */ 3763215976Sjmallett#else 3764215976Sjmallett uint64_t send : 1; 3765215976Sjmallett uint64_t reserved_1_63 : 63; 3766215976Sjmallett#endif 3767215976Sjmallett } s; 3768215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; 3769215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 3770215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 3771215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 3772232812Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn61xx; 3773215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn63xx; 3774215976Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1; 3775232812Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn66xx; 3776232812Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn68xx; 3777232812Sjmallett struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1; 3778215976Sjmallett}; 3779215976Sjmalletttypedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t; 3780215976Sjmallett 3781215976Sjmallett/** 3782215976Sjmallett * cvmx_agl_gmx_tx#_soft_pause 3783215976Sjmallett * 3784215976Sjmallett * AGL_GMX_TX_SOFT_PAUSE = Packet TX Software Pause 3785215976Sjmallett * 3786215976Sjmallett * 3787215976Sjmallett * Notes: 3788215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 3789215976Sjmallett * 3790215976Sjmallett */ 3791232812Sjmallettunion cvmx_agl_gmx_txx_soft_pause { 3792215976Sjmallett uint64_t u64; 3793232812Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s { 3794232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3795215976Sjmallett uint64_t reserved_16_63 : 48; 3796215976Sjmallett uint64_t time : 16; /**< Back off the TX bus for (TIME*512) bit-times 3797215976Sjmallett for full-duplex operation only */ 3798215976Sjmallett#else 3799215976Sjmallett uint64_t time : 16; 3800215976Sjmallett uint64_t reserved_16_63 : 48; 3801215976Sjmallett#endif 3802215976Sjmallett } s; 3803215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; 3804215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 3805215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 3806215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 3807232812Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn61xx; 3808215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn63xx; 3809215976Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1; 3810232812Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn66xx; 3811232812Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn68xx; 3812232812Sjmallett struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1; 3813215976Sjmallett}; 3814215976Sjmalletttypedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t; 3815215976Sjmallett 3816215976Sjmallett/** 3817215976Sjmallett * cvmx_agl_gmx_tx#_stat0 3818215976Sjmallett * 3819215976Sjmallett * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL 3820215976Sjmallett * 3821215976Sjmallett * 3822215976Sjmallett * Notes: 3823215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3824215976Sjmallett * - Counters will wrap 3825215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3826215976Sjmallett */ 3827232812Sjmallettunion cvmx_agl_gmx_txx_stat0 { 3828215976Sjmallett uint64_t u64; 3829232812Sjmallett struct cvmx_agl_gmx_txx_stat0_s { 3830232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3831215976Sjmallett uint64_t xsdef : 32; /**< Number of packets dropped (never successfully 3832215976Sjmallett sent) due to excessive deferal */ 3833215976Sjmallett uint64_t xscol : 32; /**< Number of packets dropped (never successfully 3834215976Sjmallett sent) due to excessive collision. Defined by 3835215976Sjmallett AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */ 3836215976Sjmallett#else 3837215976Sjmallett uint64_t xscol : 32; 3838215976Sjmallett uint64_t xsdef : 32; 3839215976Sjmallett#endif 3840215976Sjmallett } s; 3841215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn52xx; 3842215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 3843215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn56xx; 3844215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 3845232812Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn61xx; 3846215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn63xx; 3847215976Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn63xxp1; 3848232812Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn66xx; 3849232812Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn68xx; 3850232812Sjmallett struct cvmx_agl_gmx_txx_stat0_s cn68xxp1; 3851215976Sjmallett}; 3852215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t; 3853215976Sjmallett 3854215976Sjmallett/** 3855215976Sjmallett * cvmx_agl_gmx_tx#_stat1 3856215976Sjmallett * 3857215976Sjmallett * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL / AGL_GMX_TX_STATS_MCOL 3858215976Sjmallett * 3859215976Sjmallett * 3860215976Sjmallett * Notes: 3861215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3862215976Sjmallett * - Counters will wrap 3863215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3864215976Sjmallett */ 3865232812Sjmallettunion cvmx_agl_gmx_txx_stat1 { 3866215976Sjmallett uint64_t u64; 3867232812Sjmallett struct cvmx_agl_gmx_txx_stat1_s { 3868232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3869215976Sjmallett uint64_t scol : 32; /**< Number of packets sent with a single collision */ 3870215976Sjmallett uint64_t mcol : 32; /**< Number of packets sent with multiple collisions 3871215976Sjmallett but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */ 3872215976Sjmallett#else 3873215976Sjmallett uint64_t mcol : 32; 3874215976Sjmallett uint64_t scol : 32; 3875215976Sjmallett#endif 3876215976Sjmallett } s; 3877215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn52xx; 3878215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 3879215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn56xx; 3880215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 3881232812Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn61xx; 3882215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn63xx; 3883215976Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn63xxp1; 3884232812Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn66xx; 3885232812Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn68xx; 3886232812Sjmallett struct cvmx_agl_gmx_txx_stat1_s cn68xxp1; 3887215976Sjmallett}; 3888215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t; 3889215976Sjmallett 3890215976Sjmallett/** 3891215976Sjmallett * cvmx_agl_gmx_tx#_stat2 3892215976Sjmallett * 3893215976Sjmallett * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS 3894215976Sjmallett * 3895215976Sjmallett * 3896215976Sjmallett * Notes: 3897215976Sjmallett * - Octect counts are the sum of all data transmitted on the wire including 3898215976Sjmallett * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect 3899215976Sjmallett * counts do not include PREAMBLE byte or EXTEND cycles. 3900215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3901215976Sjmallett * - Counters will wrap 3902215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3903215976Sjmallett */ 3904232812Sjmallettunion cvmx_agl_gmx_txx_stat2 { 3905215976Sjmallett uint64_t u64; 3906232812Sjmallett struct cvmx_agl_gmx_txx_stat2_s { 3907232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3908215976Sjmallett uint64_t reserved_48_63 : 16; 3909215976Sjmallett uint64_t octs : 48; /**< Number of total octets sent on the interface. 3910215976Sjmallett Does not count octets from frames that were 3911215976Sjmallett truncated due to collisions in halfdup mode. */ 3912215976Sjmallett#else 3913215976Sjmallett uint64_t octs : 48; 3914215976Sjmallett uint64_t reserved_48_63 : 16; 3915215976Sjmallett#endif 3916215976Sjmallett } s; 3917215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn52xx; 3918215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 3919215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn56xx; 3920215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 3921232812Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn61xx; 3922215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn63xx; 3923215976Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn63xxp1; 3924232812Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn66xx; 3925232812Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn68xx; 3926232812Sjmallett struct cvmx_agl_gmx_txx_stat2_s cn68xxp1; 3927215976Sjmallett}; 3928215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t; 3929215976Sjmallett 3930215976Sjmallett/** 3931215976Sjmallett * cvmx_agl_gmx_tx#_stat3 3932215976Sjmallett * 3933215976Sjmallett * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS 3934215976Sjmallett * 3935215976Sjmallett * 3936215976Sjmallett * Notes: 3937215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3938215976Sjmallett * - Counters will wrap 3939215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3940215976Sjmallett */ 3941232812Sjmallettunion cvmx_agl_gmx_txx_stat3 { 3942215976Sjmallett uint64_t u64; 3943232812Sjmallett struct cvmx_agl_gmx_txx_stat3_s { 3944232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3945215976Sjmallett uint64_t reserved_32_63 : 32; 3946215976Sjmallett uint64_t pkts : 32; /**< Number of total frames sent on the interface. 3947215976Sjmallett Does not count frames that were truncated due to 3948215976Sjmallett collisions in halfdup mode. */ 3949215976Sjmallett#else 3950215976Sjmallett uint64_t pkts : 32; 3951215976Sjmallett uint64_t reserved_32_63 : 32; 3952215976Sjmallett#endif 3953215976Sjmallett } s; 3954215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn52xx; 3955215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 3956215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn56xx; 3957215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 3958232812Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn61xx; 3959215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn63xx; 3960215976Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn63xxp1; 3961232812Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn66xx; 3962232812Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn68xx; 3963232812Sjmallett struct cvmx_agl_gmx_txx_stat3_s cn68xxp1; 3964215976Sjmallett}; 3965215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t; 3966215976Sjmallett 3967215976Sjmallett/** 3968215976Sjmallett * cvmx_agl_gmx_tx#_stat4 3969215976Sjmallett * 3970215976Sjmallett * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64) 3971215976Sjmallett * 3972215976Sjmallett * 3973215976Sjmallett * Notes: 3974215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 3975215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 3976215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 3977215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 3978215976Sjmallett * - Counters will wrap 3979215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 3980215976Sjmallett */ 3981232812Sjmallettunion cvmx_agl_gmx_txx_stat4 { 3982215976Sjmallett uint64_t u64; 3983232812Sjmallett struct cvmx_agl_gmx_txx_stat4_s { 3984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3985215976Sjmallett uint64_t hist1 : 32; /**< Number of packets sent with an octet count of 64. */ 3986215976Sjmallett uint64_t hist0 : 32; /**< Number of packets sent with an octet count 3987215976Sjmallett of < 64. */ 3988215976Sjmallett#else 3989215976Sjmallett uint64_t hist0 : 32; 3990215976Sjmallett uint64_t hist1 : 32; 3991215976Sjmallett#endif 3992215976Sjmallett } s; 3993215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn52xx; 3994215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 3995215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn56xx; 3996215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 3997232812Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn61xx; 3998215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn63xx; 3999215976Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn63xxp1; 4000232812Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn66xx; 4001232812Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn68xx; 4002232812Sjmallett struct cvmx_agl_gmx_txx_stat4_s cn68xxp1; 4003215976Sjmallett}; 4004215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t; 4005215976Sjmallett 4006215976Sjmallett/** 4007215976Sjmallett * cvmx_agl_gmx_tx#_stat5 4008215976Sjmallett * 4009215976Sjmallett * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127) 4010215976Sjmallett * 4011215976Sjmallett * 4012215976Sjmallett * Notes: 4013215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 4014215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 4015215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 4016215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 4017215976Sjmallett * - Counters will wrap 4018215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 4019215976Sjmallett */ 4020232812Sjmallettunion cvmx_agl_gmx_txx_stat5 { 4021215976Sjmallett uint64_t u64; 4022232812Sjmallett struct cvmx_agl_gmx_txx_stat5_s { 4023232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4024215976Sjmallett uint64_t hist3 : 32; /**< Number of packets sent with an octet count of 4025215976Sjmallett 128 - 255. */ 4026215976Sjmallett uint64_t hist2 : 32; /**< Number of packets sent with an octet count of 4027215976Sjmallett 65 - 127. */ 4028215976Sjmallett#else 4029215976Sjmallett uint64_t hist2 : 32; 4030215976Sjmallett uint64_t hist3 : 32; 4031215976Sjmallett#endif 4032215976Sjmallett } s; 4033215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn52xx; 4034215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 4035215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn56xx; 4036215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 4037232812Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn61xx; 4038215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn63xx; 4039215976Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn63xxp1; 4040232812Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn66xx; 4041232812Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn68xx; 4042232812Sjmallett struct cvmx_agl_gmx_txx_stat5_s cn68xxp1; 4043215976Sjmallett}; 4044215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t; 4045215976Sjmallett 4046215976Sjmallett/** 4047215976Sjmallett * cvmx_agl_gmx_tx#_stat6 4048215976Sjmallett * 4049215976Sjmallett * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511) 4050215976Sjmallett * 4051215976Sjmallett * 4052215976Sjmallett * Notes: 4053215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 4054215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 4055215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 4056215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 4057215976Sjmallett * - Counters will wrap 4058215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 4059215976Sjmallett */ 4060232812Sjmallettunion cvmx_agl_gmx_txx_stat6 { 4061215976Sjmallett uint64_t u64; 4062232812Sjmallett struct cvmx_agl_gmx_txx_stat6_s { 4063232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4064215976Sjmallett uint64_t hist5 : 32; /**< Number of packets sent with an octet count of 4065215976Sjmallett 512 - 1023. */ 4066215976Sjmallett uint64_t hist4 : 32; /**< Number of packets sent with an octet count of 4067215976Sjmallett 256 - 511. */ 4068215976Sjmallett#else 4069215976Sjmallett uint64_t hist4 : 32; 4070215976Sjmallett uint64_t hist5 : 32; 4071215976Sjmallett#endif 4072215976Sjmallett } s; 4073215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn52xx; 4074215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 4075215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn56xx; 4076215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 4077232812Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn61xx; 4078215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn63xx; 4079215976Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn63xxp1; 4080232812Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn66xx; 4081232812Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn68xx; 4082232812Sjmallett struct cvmx_agl_gmx_txx_stat6_s cn68xxp1; 4083215976Sjmallett}; 4084215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t; 4085215976Sjmallett 4086215976Sjmallett/** 4087215976Sjmallett * cvmx_agl_gmx_tx#_stat7 4088215976Sjmallett * 4089215976Sjmallett * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518) 4090215976Sjmallett * 4091215976Sjmallett * 4092215976Sjmallett * Notes: 4093215976Sjmallett * - Packet length is the sum of all data transmitted on the wire for the given 4094215976Sjmallett * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam 4095215976Sjmallett * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles. 4096215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 4097215976Sjmallett * - Counters will wrap 4098215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 4099215976Sjmallett */ 4100232812Sjmallettunion cvmx_agl_gmx_txx_stat7 { 4101215976Sjmallett uint64_t u64; 4102232812Sjmallett struct cvmx_agl_gmx_txx_stat7_s { 4103232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4104215976Sjmallett uint64_t hist7 : 32; /**< Number of packets sent with an octet count 4105215976Sjmallett of > 1518. */ 4106215976Sjmallett uint64_t hist6 : 32; /**< Number of packets sent with an octet count of 4107215976Sjmallett 1024 - 1518. */ 4108215976Sjmallett#else 4109215976Sjmallett uint64_t hist6 : 32; 4110215976Sjmallett uint64_t hist7 : 32; 4111215976Sjmallett#endif 4112215976Sjmallett } s; 4113215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn52xx; 4114215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 4115215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn56xx; 4116215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 4117232812Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn61xx; 4118215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn63xx; 4119215976Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn63xxp1; 4120232812Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn66xx; 4121232812Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn68xx; 4122232812Sjmallett struct cvmx_agl_gmx_txx_stat7_s cn68xxp1; 4123215976Sjmallett}; 4124215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t; 4125215976Sjmallett 4126215976Sjmallett/** 4127215976Sjmallett * cvmx_agl_gmx_tx#_stat8 4128215976Sjmallett * 4129215976Sjmallett * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST / AGL_GMX_TX_STATS_BCST 4130215976Sjmallett * 4131215976Sjmallett * 4132215976Sjmallett * Notes: 4133215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 4134215976Sjmallett * - Counters will wrap 4135215976Sjmallett * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the 4136215976Sjmallett * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet 4137215976Sjmallett * as per the 802.3 frame definition. If the system requires additional data 4138215976Sjmallett * before the L2 header, then the MCST and BCST counters may not reflect 4139215976Sjmallett * reality and should be ignored by software. 4140215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 4141215976Sjmallett */ 4142232812Sjmallettunion cvmx_agl_gmx_txx_stat8 { 4143215976Sjmallett uint64_t u64; 4144232812Sjmallett struct cvmx_agl_gmx_txx_stat8_s { 4145232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4146215976Sjmallett uint64_t mcst : 32; /**< Number of packets sent to multicast DMAC. 4147215976Sjmallett Does not include BCST packets. */ 4148215976Sjmallett uint64_t bcst : 32; /**< Number of packets sent to broadcast DMAC. 4149215976Sjmallett Does not include MCST packets. */ 4150215976Sjmallett#else 4151215976Sjmallett uint64_t bcst : 32; 4152215976Sjmallett uint64_t mcst : 32; 4153215976Sjmallett#endif 4154215976Sjmallett } s; 4155215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn52xx; 4156215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 4157215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn56xx; 4158215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 4159232812Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn61xx; 4160215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn63xx; 4161215976Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn63xxp1; 4162232812Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn66xx; 4163232812Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn68xx; 4164232812Sjmallett struct cvmx_agl_gmx_txx_stat8_s cn68xxp1; 4165215976Sjmallett}; 4166215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t; 4167215976Sjmallett 4168215976Sjmallett/** 4169215976Sjmallett * cvmx_agl_gmx_tx#_stat9 4170215976Sjmallett * 4171215976Sjmallett * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL 4172215976Sjmallett * 4173215976Sjmallett * 4174215976Sjmallett * Notes: 4175215976Sjmallett * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set 4176215976Sjmallett * - Counters will wrap 4177215976Sjmallett * - Not reset when MIX*_CTL[RESET] is set to 1. 4178215976Sjmallett */ 4179232812Sjmallettunion cvmx_agl_gmx_txx_stat9 { 4180215976Sjmallett uint64_t u64; 4181232812Sjmallett struct cvmx_agl_gmx_txx_stat9_s { 4182232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4183215976Sjmallett uint64_t undflw : 32; /**< Number of underflow packets */ 4184215976Sjmallett uint64_t ctl : 32; /**< Number of Control packets (PAUSE flow control) 4185215976Sjmallett generated by GMX. It does not include control 4186215976Sjmallett packets forwarded or generated by the PP's. */ 4187215976Sjmallett#else 4188215976Sjmallett uint64_t ctl : 32; 4189215976Sjmallett uint64_t undflw : 32; 4190215976Sjmallett#endif 4191215976Sjmallett } s; 4192215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn52xx; 4193215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 4194215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn56xx; 4195215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 4196232812Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn61xx; 4197215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn63xx; 4198215976Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn63xxp1; 4199232812Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn66xx; 4200232812Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn68xx; 4201232812Sjmallett struct cvmx_agl_gmx_txx_stat9_s cn68xxp1; 4202215976Sjmallett}; 4203215976Sjmalletttypedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t; 4204215976Sjmallett 4205215976Sjmallett/** 4206215976Sjmallett * cvmx_agl_gmx_tx#_stats_ctl 4207215976Sjmallett * 4208215976Sjmallett * AGL_GMX_TX_STATS_CTL = TX Stats Control register 4209215976Sjmallett * 4210215976Sjmallett * 4211215976Sjmallett * Notes: 4212215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 4213215976Sjmallett * 4214215976Sjmallett */ 4215232812Sjmallettunion cvmx_agl_gmx_txx_stats_ctl { 4216215976Sjmallett uint64_t u64; 4217232812Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s { 4218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4219215976Sjmallett uint64_t reserved_1_63 : 63; 4220215976Sjmallett uint64_t rd_clr : 1; /**< Stats registers will clear on reads */ 4221215976Sjmallett#else 4222215976Sjmallett uint64_t rd_clr : 1; 4223215976Sjmallett uint64_t reserved_1_63 : 63; 4224215976Sjmallett#endif 4225215976Sjmallett } s; 4226215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; 4227215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 4228215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 4229215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 4230232812Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx; 4231215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx; 4232215976Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1; 4233232812Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx; 4234232812Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx; 4235232812Sjmallett struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1; 4236215976Sjmallett}; 4237215976Sjmalletttypedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t; 4238215976Sjmallett 4239215976Sjmallett/** 4240215976Sjmallett * cvmx_agl_gmx_tx#_thresh 4241215976Sjmallett * 4242215976Sjmallett * AGL_GMX_TX_THRESH = Packet TX Threshold 4243215976Sjmallett * 4244215976Sjmallett * 4245215976Sjmallett * Notes: 4246215976Sjmallett * Additionally reset when MIX<prt>_CTL[RESET] is set to 1. 4247215976Sjmallett * 4248215976Sjmallett */ 4249232812Sjmallettunion cvmx_agl_gmx_txx_thresh { 4250215976Sjmallett uint64_t u64; 4251232812Sjmallett struct cvmx_agl_gmx_txx_thresh_s { 4252232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4253215976Sjmallett uint64_t reserved_6_63 : 58; 4254215976Sjmallett uint64_t cnt : 6; /**< Number of 16B ticks to accumulate in the TX FIFO 4255215976Sjmallett before sending on the packet interface 4256215976Sjmallett This register should be large enough to prevent 4257215976Sjmallett underflow on the packet interface and must never 4258215976Sjmallett be set below 4. This register cannot exceed the 4259215976Sjmallett the TX FIFO depth which is 128, 8B entries. */ 4260215976Sjmallett#else 4261215976Sjmallett uint64_t cnt : 6; 4262215976Sjmallett uint64_t reserved_6_63 : 58; 4263215976Sjmallett#endif 4264215976Sjmallett } s; 4265215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn52xx; 4266215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 4267215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn56xx; 4268215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 4269232812Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn61xx; 4270215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn63xx; 4271215976Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn63xxp1; 4272232812Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn66xx; 4273232812Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn68xx; 4274232812Sjmallett struct cvmx_agl_gmx_txx_thresh_s cn68xxp1; 4275215976Sjmallett}; 4276215976Sjmalletttypedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t; 4277215976Sjmallett 4278215976Sjmallett/** 4279215976Sjmallett * cvmx_agl_gmx_tx_bp 4280215976Sjmallett * 4281215976Sjmallett * AGL_GMX_TX_BP = Packet TX BackPressure Register 4282215976Sjmallett * 4283215976Sjmallett * 4284215976Sjmallett * Notes: 4285215976Sjmallett * BP[0] will be reset when MIX0_CTL[RESET] is set to 1. 4286215976Sjmallett * BP[1] will be reset when MIX1_CTL[RESET] is set to 1. 4287215976Sjmallett */ 4288232812Sjmallettunion cvmx_agl_gmx_tx_bp { 4289215976Sjmallett uint64_t u64; 4290232812Sjmallett struct cvmx_agl_gmx_tx_bp_s { 4291232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4292215976Sjmallett uint64_t reserved_2_63 : 62; 4293215976Sjmallett uint64_t bp : 2; /**< Port BackPressure status 4294215976Sjmallett 0=Port is available 4295215976Sjmallett 1=Port should be back pressured */ 4296215976Sjmallett#else 4297215976Sjmallett uint64_t bp : 2; 4298215976Sjmallett uint64_t reserved_2_63 : 62; 4299215976Sjmallett#endif 4300215976Sjmallett } s; 4301215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn52xx; 4302215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn52xxp1; 4303232812Sjmallett struct cvmx_agl_gmx_tx_bp_cn56xx { 4304232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4305215976Sjmallett uint64_t reserved_1_63 : 63; 4306215976Sjmallett uint64_t bp : 1; /**< Port BackPressure status 4307215976Sjmallett 0=Port is available 4308215976Sjmallett 1=Port should be back pressured */ 4309215976Sjmallett#else 4310215976Sjmallett uint64_t bp : 1; 4311215976Sjmallett uint64_t reserved_1_63 : 63; 4312215976Sjmallett#endif 4313215976Sjmallett } cn56xx; 4314215976Sjmallett struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 4315232812Sjmallett struct cvmx_agl_gmx_tx_bp_s cn61xx; 4316215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn63xx; 4317215976Sjmallett struct cvmx_agl_gmx_tx_bp_s cn63xxp1; 4318232812Sjmallett struct cvmx_agl_gmx_tx_bp_s cn66xx; 4319232812Sjmallett struct cvmx_agl_gmx_tx_bp_s cn68xx; 4320232812Sjmallett struct cvmx_agl_gmx_tx_bp_s cn68xxp1; 4321215976Sjmallett}; 4322215976Sjmalletttypedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t; 4323215976Sjmallett 4324215976Sjmallett/** 4325215976Sjmallett * cvmx_agl_gmx_tx_col_attempt 4326215976Sjmallett * 4327215976Sjmallett * AGL_GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame 4328215976Sjmallett * 4329215976Sjmallett * 4330215976Sjmallett * Notes: 4331215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4332215976Sjmallett * 4333215976Sjmallett */ 4334232812Sjmallettunion cvmx_agl_gmx_tx_col_attempt { 4335215976Sjmallett uint64_t u64; 4336232812Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s { 4337232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4338215976Sjmallett uint64_t reserved_5_63 : 59; 4339215976Sjmallett uint64_t limit : 5; /**< Collision Attempts */ 4340215976Sjmallett#else 4341215976Sjmallett uint64_t limit : 5; 4342215976Sjmallett uint64_t reserved_5_63 : 59; 4343215976Sjmallett#endif 4344215976Sjmallett } s; 4345215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; 4346215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 4347215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 4348215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 4349232812Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn61xx; 4350215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn63xx; 4351215976Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1; 4352232812Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn66xx; 4353232812Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn68xx; 4354232812Sjmallett struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1; 4355215976Sjmallett}; 4356215976Sjmalletttypedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t; 4357215976Sjmallett 4358215976Sjmallett/** 4359215976Sjmallett * cvmx_agl_gmx_tx_ifg 4360215976Sjmallett * 4361215976Sjmallett * Common 4362215976Sjmallett * 4363215976Sjmallett * 4364215976Sjmallett * AGL_GMX_TX_IFG = Packet TX Interframe Gap 4365215976Sjmallett * 4366215976Sjmallett * Notes: 4367215976Sjmallett * Notes: 4368215976Sjmallett * * Programming IFG1 and IFG2. 4369215976Sjmallett * 4370215976Sjmallett * For half-duplex systems that require IEEE 802.3 compatibility, IFG1 must 4371215976Sjmallett * be in the range of 1-8, IFG2 must be in the range of 4-12, and the 4372215976Sjmallett * IFG1+IFG2 sum must be 12. 4373215976Sjmallett * 4374215976Sjmallett * For full-duplex systems that require IEEE 802.3 compatibility, IFG1 must 4375215976Sjmallett * be in the range of 1-11, IFG2 must be in the range of 1-11, and the 4376215976Sjmallett * IFG1+IFG2 sum must be 12. 4377215976Sjmallett * 4378215976Sjmallett * For all other systems, IFG1 and IFG2 can be any value in the range of 4379215976Sjmallett * 1-15. Allowing for a total possible IFG sum of 2-30. 4380215976Sjmallett * 4381215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4382215976Sjmallett */ 4383232812Sjmallettunion cvmx_agl_gmx_tx_ifg { 4384215976Sjmallett uint64_t u64; 4385232812Sjmallett struct cvmx_agl_gmx_tx_ifg_s { 4386232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4387215976Sjmallett uint64_t reserved_8_63 : 56; 4388215976Sjmallett uint64_t ifg2 : 4; /**< 1/3 of the interframe gap timing 4389215976Sjmallett If CRS is detected during IFG2, then the 4390215976Sjmallett interFrameSpacing timer is not reset and a frame 4391215976Sjmallett is transmited once the timer expires. */ 4392215976Sjmallett uint64_t ifg1 : 4; /**< 2/3 of the interframe gap timing 4393215976Sjmallett If CRS is detected during IFG1, then the 4394215976Sjmallett interFrameSpacing timer is reset and a frame is 4395215976Sjmallett not transmited. */ 4396215976Sjmallett#else 4397215976Sjmallett uint64_t ifg1 : 4; 4398215976Sjmallett uint64_t ifg2 : 4; 4399215976Sjmallett uint64_t reserved_8_63 : 56; 4400215976Sjmallett#endif 4401215976Sjmallett } s; 4402215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn52xx; 4403215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 4404215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn56xx; 4405215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 4406232812Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn61xx; 4407215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn63xx; 4408215976Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn63xxp1; 4409232812Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn66xx; 4410232812Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn68xx; 4411232812Sjmallett struct cvmx_agl_gmx_tx_ifg_s cn68xxp1; 4412215976Sjmallett}; 4413215976Sjmalletttypedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t; 4414215976Sjmallett 4415215976Sjmallett/** 4416215976Sjmallett * cvmx_agl_gmx_tx_int_en 4417215976Sjmallett * 4418215976Sjmallett * AGL_GMX_TX_INT_EN = Interrupt Enable 4419215976Sjmallett * 4420215976Sjmallett * 4421215976Sjmallett * Notes: 4422215976Sjmallett * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 4423215976Sjmallett * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 4424215976Sjmallett * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 4425215976Sjmallett */ 4426232812Sjmallettunion cvmx_agl_gmx_tx_int_en { 4427215976Sjmallett uint64_t u64; 4428232812Sjmallett struct cvmx_agl_gmx_tx_int_en_s { 4429232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4430215976Sjmallett uint64_t reserved_22_63 : 42; 4431215976Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 4432215976Sjmallett sent due to XSCOL */ 4433215976Sjmallett uint64_t reserved_18_19 : 2; 4434215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4435215976Sjmallett uint64_t reserved_14_15 : 2; 4436215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (halfdup mode only) */ 4437215976Sjmallett uint64_t reserved_10_11 : 2; 4438215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (halfdup mode only) */ 4439215976Sjmallett uint64_t reserved_4_7 : 4; 4440215976Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 4441215976Sjmallett uint64_t reserved_1_1 : 1; 4442215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4443215976Sjmallett#else 4444215976Sjmallett uint64_t pko_nxa : 1; 4445215976Sjmallett uint64_t reserved_1_1 : 1; 4446215976Sjmallett uint64_t undflw : 2; 4447215976Sjmallett uint64_t reserved_4_7 : 4; 4448215976Sjmallett uint64_t xscol : 2; 4449215976Sjmallett uint64_t reserved_10_11 : 2; 4450215976Sjmallett uint64_t xsdef : 2; 4451215976Sjmallett uint64_t reserved_14_15 : 2; 4452215976Sjmallett uint64_t late_col : 2; 4453215976Sjmallett uint64_t reserved_18_19 : 2; 4454215976Sjmallett uint64_t ptp_lost : 2; 4455215976Sjmallett uint64_t reserved_22_63 : 42; 4456215976Sjmallett#endif 4457215976Sjmallett } s; 4458232812Sjmallett struct cvmx_agl_gmx_tx_int_en_cn52xx { 4459232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4460215976Sjmallett uint64_t reserved_18_63 : 46; 4461215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4462215976Sjmallett uint64_t reserved_14_15 : 2; 4463215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (MII/halfdup mode only) */ 4464215976Sjmallett uint64_t reserved_10_11 : 2; 4465215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (MII/halfdup mode only) */ 4466215976Sjmallett uint64_t reserved_4_7 : 4; 4467215976Sjmallett uint64_t undflw : 2; /**< TX Underflow (MII mode only) */ 4468215976Sjmallett uint64_t reserved_1_1 : 1; 4469215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4470215976Sjmallett#else 4471215976Sjmallett uint64_t pko_nxa : 1; 4472215976Sjmallett uint64_t reserved_1_1 : 1; 4473215976Sjmallett uint64_t undflw : 2; 4474215976Sjmallett uint64_t reserved_4_7 : 4; 4475215976Sjmallett uint64_t xscol : 2; 4476215976Sjmallett uint64_t reserved_10_11 : 2; 4477215976Sjmallett uint64_t xsdef : 2; 4478215976Sjmallett uint64_t reserved_14_15 : 2; 4479215976Sjmallett uint64_t late_col : 2; 4480215976Sjmallett uint64_t reserved_18_63 : 46; 4481215976Sjmallett#endif 4482215976Sjmallett } cn52xx; 4483215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1; 4484232812Sjmallett struct cvmx_agl_gmx_tx_int_en_cn56xx { 4485232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4486215976Sjmallett uint64_t reserved_17_63 : 47; 4487215976Sjmallett uint64_t late_col : 1; /**< TX Late Collision */ 4488215976Sjmallett uint64_t reserved_13_15 : 3; 4489215976Sjmallett uint64_t xsdef : 1; /**< TX Excessive deferral (MII/halfdup mode only) */ 4490215976Sjmallett uint64_t reserved_9_11 : 3; 4491215976Sjmallett uint64_t xscol : 1; /**< TX Excessive collisions (MII/halfdup mode only) */ 4492215976Sjmallett uint64_t reserved_3_7 : 5; 4493215976Sjmallett uint64_t undflw : 1; /**< TX Underflow (MII mode only) */ 4494215976Sjmallett uint64_t reserved_1_1 : 1; 4495215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4496215976Sjmallett#else 4497215976Sjmallett uint64_t pko_nxa : 1; 4498215976Sjmallett uint64_t reserved_1_1 : 1; 4499215976Sjmallett uint64_t undflw : 1; 4500215976Sjmallett uint64_t reserved_3_7 : 5; 4501215976Sjmallett uint64_t xscol : 1; 4502215976Sjmallett uint64_t reserved_9_11 : 3; 4503215976Sjmallett uint64_t xsdef : 1; 4504215976Sjmallett uint64_t reserved_13_15 : 3; 4505215976Sjmallett uint64_t late_col : 1; 4506215976Sjmallett uint64_t reserved_17_63 : 47; 4507215976Sjmallett#endif 4508215976Sjmallett } cn56xx; 4509215976Sjmallett struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 4510232812Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn61xx; 4511215976Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn63xx; 4512215976Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn63xxp1; 4513232812Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn66xx; 4514232812Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn68xx; 4515232812Sjmallett struct cvmx_agl_gmx_tx_int_en_s cn68xxp1; 4516215976Sjmallett}; 4517215976Sjmalletttypedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t; 4518215976Sjmallett 4519215976Sjmallett/** 4520215976Sjmallett * cvmx_agl_gmx_tx_int_reg 4521215976Sjmallett * 4522215976Sjmallett * AGL_GMX_TX_INT_REG = Interrupt Register 4523215976Sjmallett * 4524215976Sjmallett * 4525215976Sjmallett * Notes: 4526215976Sjmallett * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0], PTP_LOST[0] will be reset when MIX0_CTL[RESET] is set to 1. 4527215976Sjmallett * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1. 4528215976Sjmallett * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1. 4529215976Sjmallett */ 4530232812Sjmallettunion cvmx_agl_gmx_tx_int_reg { 4531215976Sjmallett uint64_t u64; 4532232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_s { 4533232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4534215976Sjmallett uint64_t reserved_22_63 : 42; 4535215976Sjmallett uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be 4536215976Sjmallett sent due to XSCOL */ 4537215976Sjmallett uint64_t reserved_18_19 : 2; 4538215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4539215976Sjmallett uint64_t reserved_14_15 : 2; 4540215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (halfdup mode only) */ 4541215976Sjmallett uint64_t reserved_10_11 : 2; 4542215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (halfdup mode only) */ 4543215976Sjmallett uint64_t reserved_4_7 : 4; 4544215976Sjmallett uint64_t undflw : 2; /**< TX Underflow */ 4545215976Sjmallett uint64_t reserved_1_1 : 1; 4546215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4547215976Sjmallett#else 4548215976Sjmallett uint64_t pko_nxa : 1; 4549215976Sjmallett uint64_t reserved_1_1 : 1; 4550215976Sjmallett uint64_t undflw : 2; 4551215976Sjmallett uint64_t reserved_4_7 : 4; 4552215976Sjmallett uint64_t xscol : 2; 4553215976Sjmallett uint64_t reserved_10_11 : 2; 4554215976Sjmallett uint64_t xsdef : 2; 4555215976Sjmallett uint64_t reserved_14_15 : 2; 4556215976Sjmallett uint64_t late_col : 2; 4557215976Sjmallett uint64_t reserved_18_19 : 2; 4558215976Sjmallett uint64_t ptp_lost : 2; 4559215976Sjmallett uint64_t reserved_22_63 : 42; 4560215976Sjmallett#endif 4561215976Sjmallett } s; 4562232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn52xx { 4563232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4564215976Sjmallett uint64_t reserved_18_63 : 46; 4565215976Sjmallett uint64_t late_col : 2; /**< TX Late Collision */ 4566215976Sjmallett uint64_t reserved_14_15 : 2; 4567215976Sjmallett uint64_t xsdef : 2; /**< TX Excessive deferral (MII/halfdup mode only) */ 4568215976Sjmallett uint64_t reserved_10_11 : 2; 4569215976Sjmallett uint64_t xscol : 2; /**< TX Excessive collisions (MII/halfdup mode only) */ 4570215976Sjmallett uint64_t reserved_4_7 : 4; 4571215976Sjmallett uint64_t undflw : 2; /**< TX Underflow (MII mode only) */ 4572215976Sjmallett uint64_t reserved_1_1 : 1; 4573215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4574215976Sjmallett#else 4575215976Sjmallett uint64_t pko_nxa : 1; 4576215976Sjmallett uint64_t reserved_1_1 : 1; 4577215976Sjmallett uint64_t undflw : 2; 4578215976Sjmallett uint64_t reserved_4_7 : 4; 4579215976Sjmallett uint64_t xscol : 2; 4580215976Sjmallett uint64_t reserved_10_11 : 2; 4581215976Sjmallett uint64_t xsdef : 2; 4582215976Sjmallett uint64_t reserved_14_15 : 2; 4583215976Sjmallett uint64_t late_col : 2; 4584215976Sjmallett uint64_t reserved_18_63 : 46; 4585215976Sjmallett#endif 4586215976Sjmallett } cn52xx; 4587215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1; 4588232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn56xx { 4589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4590215976Sjmallett uint64_t reserved_17_63 : 47; 4591215976Sjmallett uint64_t late_col : 1; /**< TX Late Collision */ 4592215976Sjmallett uint64_t reserved_13_15 : 3; 4593215976Sjmallett uint64_t xsdef : 1; /**< TX Excessive deferral (MII/halfdup mode only) */ 4594215976Sjmallett uint64_t reserved_9_11 : 3; 4595215976Sjmallett uint64_t xscol : 1; /**< TX Excessive collisions (MII/halfdup mode only) */ 4596215976Sjmallett uint64_t reserved_3_7 : 5; 4597215976Sjmallett uint64_t undflw : 1; /**< TX Underflow (MII mode only) */ 4598215976Sjmallett uint64_t reserved_1_1 : 1; 4599215976Sjmallett uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */ 4600215976Sjmallett#else 4601215976Sjmallett uint64_t pko_nxa : 1; 4602215976Sjmallett uint64_t reserved_1_1 : 1; 4603215976Sjmallett uint64_t undflw : 1; 4604215976Sjmallett uint64_t reserved_3_7 : 5; 4605215976Sjmallett uint64_t xscol : 1; 4606215976Sjmallett uint64_t reserved_9_11 : 3; 4607215976Sjmallett uint64_t xsdef : 1; 4608215976Sjmallett uint64_t reserved_13_15 : 3; 4609215976Sjmallett uint64_t late_col : 1; 4610215976Sjmallett uint64_t reserved_17_63 : 47; 4611215976Sjmallett#endif 4612215976Sjmallett } cn56xx; 4613215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 4614232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn61xx; 4615215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn63xx; 4616215976Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1; 4617232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn66xx; 4618232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn68xx; 4619232812Sjmallett struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1; 4620215976Sjmallett}; 4621215976Sjmalletttypedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t; 4622215976Sjmallett 4623215976Sjmallett/** 4624215976Sjmallett * cvmx_agl_gmx_tx_jam 4625215976Sjmallett * 4626215976Sjmallett * AGL_GMX_TX_JAM = Packet TX Jam Pattern 4627215976Sjmallett * 4628215976Sjmallett * 4629215976Sjmallett * Notes: 4630215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4631215976Sjmallett * 4632215976Sjmallett */ 4633232812Sjmallettunion cvmx_agl_gmx_tx_jam { 4634215976Sjmallett uint64_t u64; 4635232812Sjmallett struct cvmx_agl_gmx_tx_jam_s { 4636232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4637215976Sjmallett uint64_t reserved_8_63 : 56; 4638215976Sjmallett uint64_t jam : 8; /**< Jam pattern */ 4639215976Sjmallett#else 4640215976Sjmallett uint64_t jam : 8; 4641215976Sjmallett uint64_t reserved_8_63 : 56; 4642215976Sjmallett#endif 4643215976Sjmallett } s; 4644215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn52xx; 4645215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 4646215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn56xx; 4647215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 4648232812Sjmallett struct cvmx_agl_gmx_tx_jam_s cn61xx; 4649215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn63xx; 4650215976Sjmallett struct cvmx_agl_gmx_tx_jam_s cn63xxp1; 4651232812Sjmallett struct cvmx_agl_gmx_tx_jam_s cn66xx; 4652232812Sjmallett struct cvmx_agl_gmx_tx_jam_s cn68xx; 4653232812Sjmallett struct cvmx_agl_gmx_tx_jam_s cn68xxp1; 4654215976Sjmallett}; 4655215976Sjmalletttypedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t; 4656215976Sjmallett 4657215976Sjmallett/** 4658215976Sjmallett * cvmx_agl_gmx_tx_lfsr 4659215976Sjmallett * 4660215976Sjmallett * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff 4661215976Sjmallett * 4662215976Sjmallett * 4663215976Sjmallett * Notes: 4664215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4665215976Sjmallett * 4666215976Sjmallett */ 4667232812Sjmallettunion cvmx_agl_gmx_tx_lfsr { 4668215976Sjmallett uint64_t u64; 4669232812Sjmallett struct cvmx_agl_gmx_tx_lfsr_s { 4670232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4671215976Sjmallett uint64_t reserved_16_63 : 48; 4672215976Sjmallett uint64_t lfsr : 16; /**< The current state of the LFSR used to feed random 4673215976Sjmallett numbers to compute truncated binary exponential 4674215976Sjmallett backoff. */ 4675215976Sjmallett#else 4676215976Sjmallett uint64_t lfsr : 16; 4677215976Sjmallett uint64_t reserved_16_63 : 48; 4678215976Sjmallett#endif 4679215976Sjmallett } s; 4680215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn52xx; 4681215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 4682215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 4683215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 4684232812Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn61xx; 4685215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn63xx; 4686215976Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1; 4687232812Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn66xx; 4688232812Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn68xx; 4689232812Sjmallett struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1; 4690215976Sjmallett}; 4691215976Sjmalletttypedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t; 4692215976Sjmallett 4693215976Sjmallett/** 4694215976Sjmallett * cvmx_agl_gmx_tx_ovr_bp 4695215976Sjmallett * 4696215976Sjmallett * AGL_GMX_TX_OVR_BP = Packet TX Override BackPressure 4697215976Sjmallett * 4698215976Sjmallett * 4699215976Sjmallett * Notes: 4700215976Sjmallett * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1. 4701215976Sjmallett * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1. 4702215976Sjmallett */ 4703232812Sjmallettunion cvmx_agl_gmx_tx_ovr_bp { 4704215976Sjmallett uint64_t u64; 4705232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s { 4706232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4707215976Sjmallett uint64_t reserved_10_63 : 54; 4708215976Sjmallett uint64_t en : 2; /**< Per port Enable back pressure override */ 4709215976Sjmallett uint64_t reserved_6_7 : 2; 4710215976Sjmallett uint64_t bp : 2; /**< Port BackPressure status to use 4711215976Sjmallett 0=Port is available 4712215976Sjmallett 1=Port should be back pressured */ 4713215976Sjmallett uint64_t reserved_2_3 : 2; 4714215976Sjmallett uint64_t ign_full : 2; /**< Ignore the RX FIFO full when computing BP */ 4715215976Sjmallett#else 4716215976Sjmallett uint64_t ign_full : 2; 4717215976Sjmallett uint64_t reserved_2_3 : 2; 4718215976Sjmallett uint64_t bp : 2; 4719215976Sjmallett uint64_t reserved_6_7 : 2; 4720215976Sjmallett uint64_t en : 2; 4721215976Sjmallett uint64_t reserved_10_63 : 54; 4722215976Sjmallett#endif 4723215976Sjmallett } s; 4724215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; 4725215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; 4726232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { 4727232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4728215976Sjmallett uint64_t reserved_9_63 : 55; 4729215976Sjmallett uint64_t en : 1; /**< Per port Enable back pressure override */ 4730215976Sjmallett uint64_t reserved_5_7 : 3; 4731215976Sjmallett uint64_t bp : 1; /**< Port BackPressure status to use 4732215976Sjmallett 0=Port is available 4733215976Sjmallett 1=Port should be back pressured */ 4734215976Sjmallett uint64_t reserved_1_3 : 3; 4735215976Sjmallett uint64_t ign_full : 1; /**< Ignore the RX FIFO full when computing BP */ 4736215976Sjmallett#else 4737215976Sjmallett uint64_t ign_full : 1; 4738215976Sjmallett uint64_t reserved_1_3 : 3; 4739215976Sjmallett uint64_t bp : 1; 4740215976Sjmallett uint64_t reserved_5_7 : 3; 4741215976Sjmallett uint64_t en : 1; 4742215976Sjmallett uint64_t reserved_9_63 : 55; 4743215976Sjmallett#endif 4744215976Sjmallett } cn56xx; 4745215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 4746232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx; 4747215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx; 4748215976Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1; 4749232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx; 4750232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx; 4751232812Sjmallett struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1; 4752215976Sjmallett}; 4753215976Sjmalletttypedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t; 4754215976Sjmallett 4755215976Sjmallett/** 4756215976Sjmallett * cvmx_agl_gmx_tx_pause_pkt_dmac 4757215976Sjmallett * 4758215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field 4759215976Sjmallett * 4760215976Sjmallett * 4761215976Sjmallett * Notes: 4762215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4763215976Sjmallett * 4764215976Sjmallett */ 4765232812Sjmallettunion cvmx_agl_gmx_tx_pause_pkt_dmac { 4766215976Sjmallett uint64_t u64; 4767232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { 4768232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4769215976Sjmallett uint64_t reserved_48_63 : 16; 4770215976Sjmallett uint64_t dmac : 48; /**< The DMAC field placed is outbnd pause pkts */ 4771215976Sjmallett#else 4772215976Sjmallett uint64_t dmac : 48; 4773215976Sjmallett uint64_t reserved_48_63 : 16; 4774215976Sjmallett#endif 4775215976Sjmallett } s; 4776215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; 4777215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 4778215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 4779215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 4780232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx; 4781215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx; 4782215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1; 4783232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx; 4784232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx; 4785232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1; 4786215976Sjmallett}; 4787215976Sjmalletttypedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t; 4788215976Sjmallett 4789215976Sjmallett/** 4790215976Sjmallett * cvmx_agl_gmx_tx_pause_pkt_type 4791215976Sjmallett * 4792215976Sjmallett * AGL_GMX_TX_PAUSE_PKT_TYPE = Packet TX Pause Packet TYPE field 4793215976Sjmallett * 4794215976Sjmallett * 4795215976Sjmallett * Notes: 4796215976Sjmallett * Additionally reset when both MIX0/1_CTL[RESET] are set to 1. 4797215976Sjmallett * 4798215976Sjmallett */ 4799232812Sjmallettunion cvmx_agl_gmx_tx_pause_pkt_type { 4800215976Sjmallett uint64_t u64; 4801232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s { 4802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4803215976Sjmallett uint64_t reserved_16_63 : 48; 4804215976Sjmallett uint64_t type : 16; /**< The TYPE field placed is outbnd pause pkts */ 4805215976Sjmallett#else 4806215976Sjmallett uint64_t type : 16; 4807215976Sjmallett uint64_t reserved_16_63 : 48; 4808215976Sjmallett#endif 4809215976Sjmallett } s; 4810215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; 4811215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 4812215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 4813215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 4814232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx; 4815215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx; 4816215976Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1; 4817232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx; 4818232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx; 4819232812Sjmallett struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1; 4820215976Sjmallett}; 4821215976Sjmalletttypedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t; 4822215976Sjmallett 4823215976Sjmallett/** 4824215976Sjmallett * cvmx_agl_prt#_ctl 4825215976Sjmallett * 4826215976Sjmallett * AGL_PRT_CTL = AGL Port Control 4827215976Sjmallett * 4828215976Sjmallett * 4829215976Sjmallett * Notes: 4830232812Sjmallett * The RGMII timing specification requires that devices transmit clock and 4831232812Sjmallett * data synchronously. The specification requires external sources (namely 4832232812Sjmallett * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of 4833232812Sjmallett * delay. 4834232812Sjmallett * 4835232812Sjmallett * To eliminate the need for the PC board delays, the MIX RGMII interface 4836232812Sjmallett * has optional onboard DLL's for both transmit and receive. For correct 4837232812Sjmallett * operation, at most one of the transmitter, board, or receiver involved 4838232812Sjmallett * in an RGMII link should introduce delay. By default/reset, 4839232812Sjmallett * the MIX RGMII receivers delay the received clock, and the MIX 4840232812Sjmallett * RGMII transmitters do not delay the transmitted clock. Whether this 4841232812Sjmallett * default works as-is with a given link partner depends on the behavior 4842232812Sjmallett * of the link partner and the PC board. 4843232812Sjmallett * 4844232812Sjmallett * These are the possible modes of MIX RGMII receive operation: 4845232812Sjmallett * o AGL_PRTx_CTL[CLKRX_BYP] = 0 (reset value) - The OCTEON MIX RGMII 4846232812Sjmallett * receive interface introduces clock delay using its internal DLL. 4847232812Sjmallett * This mode is appropriate if neither the remote 4848232812Sjmallett * transmitter nor the PC board delays the clock. 4849232812Sjmallett * o AGL_PRTx_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The OCTEON MIX 4850232812Sjmallett * RGMII receive interface introduces no clock delay. This mode 4851232812Sjmallett * is appropriate if either the remote transmitter or the PC board 4852232812Sjmallett * delays the clock. 4853232812Sjmallett * 4854232812Sjmallett * These are the possible modes of MIX RGMII transmit operation: 4855232812Sjmallett * o AGL_PRTx_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) - 4856232812Sjmallett * The OCTEON MIX RGMII transmit interface introduces no clock 4857232812Sjmallett * delay. This mode is appropriate is either the remote receiver 4858232812Sjmallett * or the PC board delays the clock. 4859232812Sjmallett * o AGL_PRTx_CTL[CLKTX_BYP] = 0 - The OCTEON MIX RGMII transmit 4860232812Sjmallett * interface introduces clock delay using its internal DLL. 4861232812Sjmallett * This mode is appropriate if neither the remote receiver 4862232812Sjmallett * nor the PC board delays the clock. 4863232812Sjmallett * 4864215976Sjmallett * AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1. 4865215976Sjmallett * AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1. 4866215976Sjmallett */ 4867232812Sjmallettunion cvmx_agl_prtx_ctl { 4868215976Sjmallett uint64_t u64; 4869232812Sjmallett struct cvmx_agl_prtx_ctl_s { 4870232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4871215976Sjmallett uint64_t drv_byp : 1; /**< Bypass the compensation controller and use 4872232812Sjmallett DRV_NCTL and DRV_PCTL */ 4873215976Sjmallett uint64_t reserved_62_62 : 1; 4874215976Sjmallett uint64_t cmp_pctl : 6; /**< PCTL drive strength from the compensation ctl */ 4875215976Sjmallett uint64_t reserved_54_55 : 2; 4876215976Sjmallett uint64_t cmp_nctl : 6; /**< NCTL drive strength from the compensation ctl */ 4877215976Sjmallett uint64_t reserved_46_47 : 2; 4878215976Sjmallett uint64_t drv_pctl : 6; /**< PCTL drive strength to use in bypass mode 4879215976Sjmallett Reset value of 19 is for 50 ohm termination */ 4880215976Sjmallett uint64_t reserved_38_39 : 2; 4881215976Sjmallett uint64_t drv_nctl : 6; /**< NCTL drive strength to use in bypass mode 4882215976Sjmallett Reset value of 15 is for 50 ohm termination */ 4883215976Sjmallett uint64_t reserved_29_31 : 3; 4884215976Sjmallett uint64_t clk_set : 5; /**< The clock delay as determined by the DLL */ 4885215976Sjmallett uint64_t clkrx_byp : 1; /**< Bypass the RX clock delay setting 4886215976Sjmallett Skews RXC from RXD,RXCTL in RGMII mode 4887215976Sjmallett By default, HW internally shifts the RXC clock 4888215976Sjmallett to sample RXD,RXCTL assuming clock and data and 4889215976Sjmallett sourced synchronously from the link partner. 4890215976Sjmallett In MII mode, the CLKRX_BYP is forced to 1. */ 4891215976Sjmallett uint64_t reserved_21_22 : 2; 4892215976Sjmallett uint64_t clkrx_set : 5; /**< RX clock delay setting to use in bypass mode 4893215976Sjmallett Skews RXC from RXD in RGMII mode */ 4894215976Sjmallett uint64_t clktx_byp : 1; /**< Bypass the TX clock delay setting 4895215976Sjmallett Skews TXC from TXD,TXCTL in RGMII mode 4896215976Sjmallett By default, clock and data and sourced 4897215976Sjmallett synchronously. 4898215976Sjmallett In MII mode, the CLKRX_BYP is forced to 1. */ 4899215976Sjmallett uint64_t reserved_13_14 : 2; 4900215976Sjmallett uint64_t clktx_set : 5; /**< TX clock delay setting to use in bypass mode 4901215976Sjmallett Skews TXC from TXD in RGMII mode */ 4902215976Sjmallett uint64_t reserved_5_7 : 3; 4903215976Sjmallett uint64_t dllrst : 1; /**< DLL Reset */ 4904215976Sjmallett uint64_t comp : 1; /**< Compensation Enable */ 4905232812Sjmallett uint64_t enable : 1; /**< Port Enable */ 4906215976Sjmallett uint64_t clkrst : 1; /**< Clock Tree Reset */ 4907215976Sjmallett uint64_t mode : 1; /**< Port Mode 4908215976Sjmallett MODE must be set the same for all ports in which 4909215976Sjmallett AGL_PRTx_CTL[ENABLE] is set. 4910215976Sjmallett 0=RGMII 4911215976Sjmallett 1=MII */ 4912215976Sjmallett#else 4913215976Sjmallett uint64_t mode : 1; 4914215976Sjmallett uint64_t clkrst : 1; 4915215976Sjmallett uint64_t enable : 1; 4916215976Sjmallett uint64_t comp : 1; 4917215976Sjmallett uint64_t dllrst : 1; 4918215976Sjmallett uint64_t reserved_5_7 : 3; 4919215976Sjmallett uint64_t clktx_set : 5; 4920215976Sjmallett uint64_t reserved_13_14 : 2; 4921215976Sjmallett uint64_t clktx_byp : 1; 4922215976Sjmallett uint64_t clkrx_set : 5; 4923215976Sjmallett uint64_t reserved_21_22 : 2; 4924215976Sjmallett uint64_t clkrx_byp : 1; 4925215976Sjmallett uint64_t clk_set : 5; 4926215976Sjmallett uint64_t reserved_29_31 : 3; 4927215976Sjmallett uint64_t drv_nctl : 6; 4928215976Sjmallett uint64_t reserved_38_39 : 2; 4929215976Sjmallett uint64_t drv_pctl : 6; 4930215976Sjmallett uint64_t reserved_46_47 : 2; 4931215976Sjmallett uint64_t cmp_nctl : 6; 4932215976Sjmallett uint64_t reserved_54_55 : 2; 4933215976Sjmallett uint64_t cmp_pctl : 6; 4934215976Sjmallett uint64_t reserved_62_62 : 1; 4935215976Sjmallett uint64_t drv_byp : 1; 4936215976Sjmallett#endif 4937215976Sjmallett } s; 4938232812Sjmallett struct cvmx_agl_prtx_ctl_s cn61xx; 4939215976Sjmallett struct cvmx_agl_prtx_ctl_s cn63xx; 4940215976Sjmallett struct cvmx_agl_prtx_ctl_s cn63xxp1; 4941232812Sjmallett struct cvmx_agl_prtx_ctl_s cn66xx; 4942232812Sjmallett struct cvmx_agl_prtx_ctl_s cn68xx; 4943232812Sjmallett struct cvmx_agl_prtx_ctl_s cn68xxp1; 4944215976Sjmallett}; 4945215976Sjmalletttypedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t; 4946215976Sjmallett 4947215976Sjmallett#endif 4948