Searched refs:intel_de_wait_for_set (Results 1 - 17 of 17) sorted by relevance

/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_de.h75 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, function
H A Dhsw_ips.c55 if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
H A Dvlv_dsi.c96 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
356 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
378 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
417 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
425 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
H A Dintel_pch_display.c305 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
568 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
H A Dintel_display_power_well.c278 if (intel_de_wait_for_set(dev_priv, regs->driver,
338 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
1430 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1848 if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
H A Dintel_hdcp.c390 if (intel_de_wait_for_set(i915, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
669 if (intel_de_wait_for_set(i915, HDCP_REP_CTL,
817 if (intel_de_wait_for_set(i915,
912 if (intel_de_wait_for_set(i915,
1860 ret = intel_de_wait_for_set(i915,
H A Dvlv_dsi_pll.c561 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
H A Dintel_lvds.c327 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
H A Dintel_dpio_phy.c362 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
H A Dintel_cdclk.c1039 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1689 if (intel_de_wait_for_set(dev_priv,
1720 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1740 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
H A Dintel_dpll.c1943 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
2095 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
H A Dintel_dpll_mgr.c1361 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
3867 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
3879 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
H A Dintel_snps_phy.c1867 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
H A Dintel_display_power.c1350 if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
H A Dicl_dsi.c1015 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
H A Dintel_dp_mst.c911 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
H A Dintel_ddi.c2281 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
3682 if (intel_de_wait_for_set(dev_priv,

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