1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11#include <linux/component.h> 12#include <linux/i2c.h> 13#include <linux/random.h> 14 15#include <drm/display/drm_hdcp_helper.h> 16#include <drm/i915_component.h> 17 18#include "i915_drv.h" 19#include "i915_reg.h" 20#include "intel_connector.h" 21#include "intel_de.h" 22#include "intel_display_power.h" 23#include "intel_display_power_well.h" 24#include "intel_display_types.h" 25#include "intel_hdcp.h" 26#include "intel_hdcp_gsc.h" 27#include "intel_hdcp_regs.h" 28#include "intel_pcode.h" 29 30#define KEY_LOAD_TRIES 5 31#define HDCP2_LC_RETRY_CNT 3 32 33static int intel_conn_to_vcpi(struct intel_atomic_state *state, 34 struct intel_connector *connector) 35{ 36 struct drm_dp_mst_topology_mgr *mgr; 37 struct drm_dp_mst_atomic_payload *payload; 38 struct drm_dp_mst_topology_state *mst_state; 39 int vcpi = 0; 40 41 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 42 if (!connector->port) 43 return 0; 44 mgr = connector->port->mgr; 45 46 drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); 47 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 48 payload = drm_atomic_get_mst_payload_state(mst_state, connector->port); 49 if (drm_WARN_ON(mgr->dev, !payload)) 50 goto out; 51 52 vcpi = payload->vcpi; 53 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 54 vcpi = 0; 55 goto out; 56 } 57out: 58 return vcpi; 59} 60 61/* 62 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 63 * content_type for all streams in DP MST topology because security f/w doesn't 64 * have any provision to mark content_type for each stream separately, it marks 65 * all available streams with the content_type proivided at the time of port 66 * authentication. This may prohibit the userspace to use type1 content on 67 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 68 * DP MST topology. Though it is not compulsory, security fw should change its 69 * policy to mark different content_types for different streams. 70 */ 71static int 72intel_hdcp_required_content_stream(struct intel_atomic_state *state, 73 struct intel_digital_port *dig_port) 74{ 75 struct drm_connector_list_iter conn_iter; 76 struct intel_digital_port *conn_dig_port; 77 struct intel_connector *connector; 78 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 79 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 80 bool enforce_type0 = false; 81 int k; 82 83 if (dig_port->hdcp_auth_status) 84 return 0; 85 86 data->k = 0; 87 88 if (!dig_port->hdcp_mst_type1_capable) 89 enforce_type0 = true; 90 91 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 92 for_each_intel_connector_iter(connector, &conn_iter) { 93 if (connector->base.status == connector_status_disconnected) 94 continue; 95 96 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 97 continue; 98 99 conn_dig_port = intel_attached_dig_port(connector); 100 if (conn_dig_port != dig_port) 101 continue; 102 103 data->streams[data->k].stream_id = 104 intel_conn_to_vcpi(state, connector); 105 data->k++; 106 107 /* if there is only one active stream */ 108 if (dig_port->dp.active_mst_links <= 1) 109 break; 110 } 111 drm_connector_list_iter_end(&conn_iter); 112 113 if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0)) 114 return -EINVAL; 115 116 /* 117 * Apply common protection level across all streams in DP MST Topology. 118 * Use highest supported content type for all streams in DP MST Topology. 119 */ 120 for (k = 0; k < data->k; k++) 121 data->streams[k].stream_type = 122 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 123 124 return 0; 125} 126 127static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 128 struct intel_connector *connector) 129{ 130 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 131 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 132 struct intel_hdcp *hdcp = &connector->hdcp; 133 134 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 135 return intel_hdcp_required_content_stream(state, dig_port); 136 137 data->k = 1; 138 data->streams[0].stream_id = 0; 139 data->streams[0].stream_type = hdcp->content_type; 140 141 return 0; 142} 143 144static 145bool intel_hdcp_is_ksv_valid(u8 *ksv) 146{ 147 int i, ones = 0; 148 /* KSV has 20 1's and 20 0's */ 149 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 150 ones += hweight8(ksv[i]); 151 if (ones != 20) 152 return false; 153 154 return true; 155} 156 157static 158int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 159 const struct intel_hdcp_shim *shim, u8 *bksv) 160{ 161 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 162 int ret, i, tries = 2; 163 164 /* HDCP spec states that we must retry the bksv if it is invalid */ 165 for (i = 0; i < tries; i++) { 166 ret = shim->read_bksv(dig_port, bksv); 167 if (ret) 168 return ret; 169 if (intel_hdcp_is_ksv_valid(bksv)) 170 break; 171 } 172 if (i == tries) { 173 drm_dbg_kms(&i915->drm, "Bksv is invalid\n"); 174 return -ENODEV; 175 } 176 177 return 0; 178} 179 180/* Is HDCP1.4 capable on Platform and Sink */ 181bool intel_hdcp_get_capability(struct intel_connector *connector) 182{ 183 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 184 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 185 bool capable = false; 186 u8 bksv[5]; 187 188 if (!shim) 189 return capable; 190 191 if (shim->hdcp_get_capability) { 192 shim->hdcp_get_capability(dig_port, &capable); 193 } else { 194 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 195 capable = true; 196 } 197 198 return capable; 199} 200 201/* 202 * Check if the source has all the building blocks ready to make 203 * HDCP 2.2 work 204 */ 205static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 206{ 207 struct drm_i915_private *i915 = to_i915(connector->base.dev); 208 struct intel_hdcp *hdcp = &connector->hdcp; 209 210 /* I915 support for HDCP2.2 */ 211 if (!hdcp->hdcp2_supported) 212 return false; 213 214 /* If MTL+ make sure gsc is loaded and proxy is setup */ 215 if (intel_hdcp_gsc_cs_required(i915)) { 216 if (!intel_hdcp_gsc_check_status(i915)) 217 return false; 218 } 219 220 /* MEI/GSC interface is solid depending on which is used */ 221 mutex_lock(&i915->display.hdcp.hdcp_mutex); 222 if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) { 223 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 224 return false; 225 } 226 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 227 228 return true; 229} 230 231/* Is HDCP2.2 capable on Platform and Sink */ 232bool intel_hdcp2_get_capability(struct intel_connector *connector) 233{ 234 struct intel_hdcp *hdcp = &connector->hdcp; 235 bool capable = false; 236 237 if (!intel_hdcp2_prerequisite(connector)) 238 return false; 239 240 /* Sink's capability for HDCP2.2 */ 241 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 242 243 return capable; 244} 245 246void intel_hdcp_get_remote_capability(struct intel_connector *connector, 247 bool *hdcp_capable, 248 bool *hdcp2_capable) 249{ 250 struct intel_hdcp *hdcp = &connector->hdcp; 251 252 if (!hdcp->shim->get_remote_hdcp_capability) 253 return; 254 255 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 256 hdcp2_capable); 257 258 if (!intel_hdcp2_prerequisite(connector)) 259 *hdcp2_capable = false; 260} 261 262static bool intel_hdcp_in_use(struct drm_i915_private *i915, 263 enum transcoder cpu_transcoder, enum port port) 264{ 265 return intel_de_read(i915, 266 HDCP_STATUS(i915, cpu_transcoder, port)) & 267 HDCP_STATUS_ENC; 268} 269 270static bool intel_hdcp2_in_use(struct drm_i915_private *i915, 271 enum transcoder cpu_transcoder, enum port port) 272{ 273 return intel_de_read(i915, 274 HDCP2_STATUS(i915, cpu_transcoder, port)) & 275 LINK_ENCRYPTION_STATUS; 276} 277 278static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 279 const struct intel_hdcp_shim *shim) 280{ 281 int ret, read_ret; 282 bool ksv_ready; 283 284 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 285 ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, 286 &ksv_ready), 287 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 288 100 * 1000); 289 if (ret) 290 return ret; 291 if (read_ret) 292 return read_ret; 293 if (!ksv_ready) 294 return -ETIMEDOUT; 295 296 return 0; 297} 298 299static bool hdcp_key_loadable(struct drm_i915_private *i915) 300{ 301 enum i915_power_well_id id; 302 intel_wakeref_t wakeref; 303 bool enabled = false; 304 305 /* 306 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 307 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 308 */ 309 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 310 id = HSW_DISP_PW_GLOBAL; 311 else 312 id = SKL_DISP_PW_1; 313 314 /* PG1 (power well #1) needs to be enabled */ 315 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 316 enabled = intel_display_power_well_is_enabled(i915, id); 317 318 /* 319 * Another req for hdcp key loadability is enabled state of pll for 320 * cdclk. Without active crtc we wont land here. So we are assuming that 321 * cdclk is already on. 322 */ 323 324 return enabled; 325} 326 327static void intel_hdcp_clear_keys(struct drm_i915_private *i915) 328{ 329 intel_de_write(i915, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 330 intel_de_write(i915, HDCP_KEY_STATUS, 331 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 332} 333 334static int intel_hdcp_load_keys(struct drm_i915_private *i915) 335{ 336 int ret; 337 u32 val; 338 339 val = intel_de_read(i915, HDCP_KEY_STATUS); 340 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 341 return 0; 342 343 /* 344 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 345 * out of reset. So if Key is not already loaded, its an error state. 346 */ 347 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 348 if (!(intel_de_read(i915, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 349 return -ENXIO; 350 351 /* 352 * Initiate loading the HDCP key from fuses. 353 * 354 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 355 * version 9 platforms (minus BXT) differ in the key load trigger 356 * process from other platforms. These platforms use the GT Driver 357 * Mailbox interface. 358 */ 359 if (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)) { 360 ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); 361 if (ret) { 362 drm_err(&i915->drm, 363 "Failed to initiate HDCP key load (%d)\n", 364 ret); 365 return ret; 366 } 367 } else { 368 intel_de_write(i915, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 369 } 370 371 /* Wait for the keys to load (500us) */ 372 ret = __intel_wait_for_register(&i915->uncore, HDCP_KEY_STATUS, 373 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 374 10, 1, &val); 375 if (ret) 376 return ret; 377 else if (!(val & HDCP_KEY_LOAD_STATUS)) 378 return -ENXIO; 379 380 /* Send Aksv over to PCH display for use in authentication */ 381 intel_de_write(i915, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 382 383 return 0; 384} 385 386/* Returns updated SHA-1 index */ 387static int intel_write_sha_text(struct drm_i915_private *i915, u32 sha_text) 388{ 389 intel_de_write(i915, HDCP_SHA_TEXT, sha_text); 390 if (intel_de_wait_for_set(i915, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 391 drm_err(&i915->drm, "Timed out waiting for SHA1 ready\n"); 392 return -ETIMEDOUT; 393 } 394 return 0; 395} 396 397static 398u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *i915, 399 enum transcoder cpu_transcoder, enum port port) 400{ 401 if (DISPLAY_VER(i915) >= 12) { 402 switch (cpu_transcoder) { 403 case TRANSCODER_A: 404 return HDCP_TRANSA_REP_PRESENT | 405 HDCP_TRANSA_SHA1_M0; 406 case TRANSCODER_B: 407 return HDCP_TRANSB_REP_PRESENT | 408 HDCP_TRANSB_SHA1_M0; 409 case TRANSCODER_C: 410 return HDCP_TRANSC_REP_PRESENT | 411 HDCP_TRANSC_SHA1_M0; 412 case TRANSCODER_D: 413 return HDCP_TRANSD_REP_PRESENT | 414 HDCP_TRANSD_SHA1_M0; 415 default: 416 drm_err(&i915->drm, "Unknown transcoder %d\n", 417 cpu_transcoder); 418 return 0; 419 } 420 } 421 422 switch (port) { 423 case PORT_A: 424 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 425 case PORT_B: 426 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 427 case PORT_C: 428 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 429 case PORT_D: 430 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 431 case PORT_E: 432 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 433 default: 434 drm_err(&i915->drm, "Unknown port %d\n", port); 435 return 0; 436 } 437} 438 439static 440int intel_hdcp_validate_v_prime(struct intel_connector *connector, 441 const struct intel_hdcp_shim *shim, 442 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 443{ 444 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 445 struct drm_i915_private *i915 = to_i915(connector->base.dev); 446 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 447 enum port port = dig_port->base.port; 448 u32 vprime, sha_text, sha_leftovers, rep_ctl; 449 int ret, i, j, sha_idx; 450 451 /* Process V' values from the receiver */ 452 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 453 ret = shim->read_v_prime_part(dig_port, i, &vprime); 454 if (ret) 455 return ret; 456 intel_de_write(i915, HDCP_SHA_V_PRIME(i), vprime); 457 } 458 459 /* 460 * We need to write the concatenation of all device KSVs, BINFO (DP) || 461 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 462 * stream is written via the HDCP_SHA_TEXT register in 32-bit 463 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 464 * index will keep track of our progress through the 64 bytes as well as 465 * helping us work the 40-bit KSVs through our 32-bit register. 466 * 467 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 468 */ 469 sha_idx = 0; 470 sha_text = 0; 471 sha_leftovers = 0; 472 rep_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port); 473 intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 474 for (i = 0; i < num_downstream; i++) { 475 unsigned int sha_empty; 476 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 477 478 /* Fill up the empty slots in sha_text and write it out */ 479 sha_empty = sizeof(sha_text) - sha_leftovers; 480 for (j = 0; j < sha_empty; j++) { 481 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 482 sha_text |= ksv[j] << off; 483 } 484 485 ret = intel_write_sha_text(i915, sha_text); 486 if (ret < 0) 487 return ret; 488 489 /* Programming guide writes this every 64 bytes */ 490 sha_idx += sizeof(sha_text); 491 if (!(sha_idx % 64)) 492 intel_de_write(i915, HDCP_REP_CTL, 493 rep_ctl | HDCP_SHA1_TEXT_32); 494 495 /* Store the leftover bytes from the ksv in sha_text */ 496 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 497 sha_text = 0; 498 for (j = 0; j < sha_leftovers; j++) 499 sha_text |= ksv[sha_empty + j] << 500 ((sizeof(sha_text) - j - 1) * 8); 501 502 /* 503 * If we still have room in sha_text for more data, continue. 504 * Otherwise, write it out immediately. 505 */ 506 if (sizeof(sha_text) > sha_leftovers) 507 continue; 508 509 ret = intel_write_sha_text(i915, sha_text); 510 if (ret < 0) 511 return ret; 512 sha_leftovers = 0; 513 sha_text = 0; 514 sha_idx += sizeof(sha_text); 515 } 516 517 /* 518 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 519 * bytes are leftover from the last ksv, we might be able to fit them 520 * all in sha_text (first 2 cases), or we might need to split them up 521 * into 2 writes (last 2 cases). 522 */ 523 if (sha_leftovers == 0) { 524 /* Write 16 bits of text, 16 bits of M0 */ 525 intel_de_write(i915, HDCP_REP_CTL, 526 rep_ctl | HDCP_SHA1_TEXT_16); 527 ret = intel_write_sha_text(i915, 528 bstatus[0] << 8 | bstatus[1]); 529 if (ret < 0) 530 return ret; 531 sha_idx += sizeof(sha_text); 532 533 /* Write 32 bits of M0 */ 534 intel_de_write(i915, HDCP_REP_CTL, 535 rep_ctl | HDCP_SHA1_TEXT_0); 536 ret = intel_write_sha_text(i915, 0); 537 if (ret < 0) 538 return ret; 539 sha_idx += sizeof(sha_text); 540 541 /* Write 16 bits of M0 */ 542 intel_de_write(i915, HDCP_REP_CTL, 543 rep_ctl | HDCP_SHA1_TEXT_16); 544 ret = intel_write_sha_text(i915, 0); 545 if (ret < 0) 546 return ret; 547 sha_idx += sizeof(sha_text); 548 549 } else if (sha_leftovers == 1) { 550 /* Write 24 bits of text, 8 bits of M0 */ 551 intel_de_write(i915, HDCP_REP_CTL, 552 rep_ctl | HDCP_SHA1_TEXT_24); 553 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 554 /* Only 24-bits of data, must be in the LSB */ 555 sha_text = (sha_text & 0xffffff00) >> 8; 556 ret = intel_write_sha_text(i915, sha_text); 557 if (ret < 0) 558 return ret; 559 sha_idx += sizeof(sha_text); 560 561 /* Write 32 bits of M0 */ 562 intel_de_write(i915, HDCP_REP_CTL, 563 rep_ctl | HDCP_SHA1_TEXT_0); 564 ret = intel_write_sha_text(i915, 0); 565 if (ret < 0) 566 return ret; 567 sha_idx += sizeof(sha_text); 568 569 /* Write 24 bits of M0 */ 570 intel_de_write(i915, HDCP_REP_CTL, 571 rep_ctl | HDCP_SHA1_TEXT_8); 572 ret = intel_write_sha_text(i915, 0); 573 if (ret < 0) 574 return ret; 575 sha_idx += sizeof(sha_text); 576 577 } else if (sha_leftovers == 2) { 578 /* Write 32 bits of text */ 579 intel_de_write(i915, HDCP_REP_CTL, 580 rep_ctl | HDCP_SHA1_TEXT_32); 581 sha_text |= bstatus[0] << 8 | bstatus[1]; 582 ret = intel_write_sha_text(i915, sha_text); 583 if (ret < 0) 584 return ret; 585 sha_idx += sizeof(sha_text); 586 587 /* Write 64 bits of M0 */ 588 intel_de_write(i915, HDCP_REP_CTL, 589 rep_ctl | HDCP_SHA1_TEXT_0); 590 for (i = 0; i < 2; i++) { 591 ret = intel_write_sha_text(i915, 0); 592 if (ret < 0) 593 return ret; 594 sha_idx += sizeof(sha_text); 595 } 596 597 /* 598 * Terminate the SHA-1 stream by hand. For the other leftover 599 * cases this is appended by the hardware. 600 */ 601 intel_de_write(i915, HDCP_REP_CTL, 602 rep_ctl | HDCP_SHA1_TEXT_32); 603 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 604 ret = intel_write_sha_text(i915, sha_text); 605 if (ret < 0) 606 return ret; 607 sha_idx += sizeof(sha_text); 608 } else if (sha_leftovers == 3) { 609 /* Write 32 bits of text (filled from LSB) */ 610 intel_de_write(i915, HDCP_REP_CTL, 611 rep_ctl | HDCP_SHA1_TEXT_32); 612 sha_text |= bstatus[0]; 613 ret = intel_write_sha_text(i915, sha_text); 614 if (ret < 0) 615 return ret; 616 sha_idx += sizeof(sha_text); 617 618 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 619 intel_de_write(i915, HDCP_REP_CTL, 620 rep_ctl | HDCP_SHA1_TEXT_8); 621 ret = intel_write_sha_text(i915, bstatus[1]); 622 if (ret < 0) 623 return ret; 624 sha_idx += sizeof(sha_text); 625 626 /* Write 32 bits of M0 */ 627 intel_de_write(i915, HDCP_REP_CTL, 628 rep_ctl | HDCP_SHA1_TEXT_0); 629 ret = intel_write_sha_text(i915, 0); 630 if (ret < 0) 631 return ret; 632 sha_idx += sizeof(sha_text); 633 634 /* Write 8 bits of M0 */ 635 intel_de_write(i915, HDCP_REP_CTL, 636 rep_ctl | HDCP_SHA1_TEXT_24); 637 ret = intel_write_sha_text(i915, 0); 638 if (ret < 0) 639 return ret; 640 sha_idx += sizeof(sha_text); 641 } else { 642 drm_dbg_kms(&i915->drm, "Invalid number of leftovers %d\n", 643 sha_leftovers); 644 return -EINVAL; 645 } 646 647 intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 648 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 649 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 650 ret = intel_write_sha_text(i915, 0); 651 if (ret < 0) 652 return ret; 653 sha_idx += sizeof(sha_text); 654 } 655 656 /* 657 * Last write gets the length of the concatenation in bits. That is: 658 * - 5 bytes per device 659 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 660 */ 661 sha_text = (num_downstream * 5 + 10) * 8; 662 ret = intel_write_sha_text(i915, sha_text); 663 if (ret < 0) 664 return ret; 665 666 /* Tell the HW we're done with the hash and wait for it to ACK */ 667 intel_de_write(i915, HDCP_REP_CTL, 668 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 669 if (intel_de_wait_for_set(i915, HDCP_REP_CTL, 670 HDCP_SHA1_COMPLETE, 1)) { 671 drm_err(&i915->drm, "Timed out waiting for SHA1 complete\n"); 672 return -ETIMEDOUT; 673 } 674 if (!(intel_de_read(i915, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 675 drm_dbg_kms(&i915->drm, "SHA-1 mismatch, HDCP failed\n"); 676 return -ENXIO; 677 } 678 679 return 0; 680} 681 682/* Implements Part 2 of the HDCP authorization procedure */ 683static 684int intel_hdcp_auth_downstream(struct intel_connector *connector) 685{ 686 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 687 struct drm_i915_private *i915 = to_i915(connector->base.dev); 688 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 689 u8 bstatus[2], num_downstream, *ksv_fifo; 690 int ret, i, tries = 3; 691 692 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 693 if (ret) { 694 drm_dbg_kms(&i915->drm, 695 "KSV list failed to become ready (%d)\n", ret); 696 return ret; 697 } 698 699 ret = shim->read_bstatus(dig_port, bstatus); 700 if (ret) 701 return ret; 702 703 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 704 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 705 drm_dbg_kms(&i915->drm, "Max Topology Limit Exceeded\n"); 706 return -EPERM; 707 } 708 709 /* 710 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 711 * the HDCP encryption. That implies that repeater can't have its own 712 * display. As there is no consumption of encrypted content in the 713 * repeater with 0 downstream devices, we are failing the 714 * authentication. 715 */ 716 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 717 if (num_downstream == 0) { 718 drm_dbg_kms(&i915->drm, 719 "Repeater with zero downstream devices\n"); 720 return -EINVAL; 721 } 722 723 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 724 if (!ksv_fifo) { 725 drm_dbg_kms(&i915->drm, "Out of mem: ksv_fifo\n"); 726 return -ENOMEM; 727 } 728 729 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 730 if (ret) 731 goto err; 732 733 if (drm_hdcp_check_ksvs_revoked(&i915->drm, ksv_fifo, 734 num_downstream) > 0) { 735 drm_err(&i915->drm, "Revoked Ksv(s) in ksv_fifo\n"); 736 ret = -EPERM; 737 goto err; 738 } 739 740 /* 741 * When V prime mismatches, DP Spec mandates re-read of 742 * V prime atleast twice. 743 */ 744 for (i = 0; i < tries; i++) { 745 ret = intel_hdcp_validate_v_prime(connector, shim, 746 ksv_fifo, num_downstream, 747 bstatus); 748 if (!ret) 749 break; 750 } 751 752 if (i == tries) { 753 drm_dbg_kms(&i915->drm, 754 "V Prime validation failed.(%d)\n", ret); 755 goto err; 756 } 757 758 drm_dbg_kms(&i915->drm, "HDCP is enabled (%d downstream devices)\n", 759 num_downstream); 760 ret = 0; 761err: 762 kfree(ksv_fifo); 763 return ret; 764} 765 766/* Implements Part 1 of the HDCP authorization procedure */ 767static int intel_hdcp_auth(struct intel_connector *connector) 768{ 769 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 770 struct drm_i915_private *i915 = to_i915(connector->base.dev); 771 struct intel_hdcp *hdcp = &connector->hdcp; 772 const struct intel_hdcp_shim *shim = hdcp->shim; 773 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 774 enum port port = dig_port->base.port; 775 unsigned long r0_prime_gen_start; 776 int ret, i, tries = 2; 777 union { 778 u32 reg[2]; 779 u8 shim[DRM_HDCP_AN_LEN]; 780 } an; 781 union { 782 u32 reg[2]; 783 u8 shim[DRM_HDCP_KSV_LEN]; 784 } bksv; 785 union { 786 u32 reg; 787 u8 shim[DRM_HDCP_RI_LEN]; 788 } ri; 789 bool repeater_present, hdcp_capable; 790 791 /* 792 * Detects whether the display is HDCP capable. Although we check for 793 * valid Bksv below, the HDCP over DP spec requires that we check 794 * whether the display supports HDCP before we write An. For HDMI 795 * displays, this is not necessary. 796 */ 797 if (shim->hdcp_get_capability) { 798 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 799 if (ret) 800 return ret; 801 if (!hdcp_capable) { 802 drm_dbg_kms(&i915->drm, 803 "Panel is not HDCP capable\n"); 804 return -EINVAL; 805 } 806 } 807 808 /* Initialize An with 2 random values and acquire it */ 809 for (i = 0; i < 2; i++) 810 intel_de_write(i915, 811 HDCP_ANINIT(i915, cpu_transcoder, port), 812 get_random_u32()); 813 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 814 HDCP_CONF_CAPTURE_AN); 815 816 /* Wait for An to be acquired */ 817 if (intel_de_wait_for_set(i915, 818 HDCP_STATUS(i915, cpu_transcoder, port), 819 HDCP_STATUS_AN_READY, 1)) { 820 drm_err(&i915->drm, "Timed out waiting for An\n"); 821 return -ETIMEDOUT; 822 } 823 824 an.reg[0] = intel_de_read(i915, 825 HDCP_ANLO(i915, cpu_transcoder, port)); 826 an.reg[1] = intel_de_read(i915, 827 HDCP_ANHI(i915, cpu_transcoder, port)); 828 ret = shim->write_an_aksv(dig_port, an.shim); 829 if (ret) 830 return ret; 831 832 r0_prime_gen_start = jiffies; 833 834 memset(&bksv, 0, sizeof(bksv)); 835 836 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 837 if (ret < 0) 838 return ret; 839 840 if (drm_hdcp_check_ksvs_revoked(&i915->drm, bksv.shim, 1) > 0) { 841 drm_err(&i915->drm, "BKSV is revoked\n"); 842 return -EPERM; 843 } 844 845 intel_de_write(i915, HDCP_BKSVLO(i915, cpu_transcoder, port), 846 bksv.reg[0]); 847 intel_de_write(i915, HDCP_BKSVHI(i915, cpu_transcoder, port), 848 bksv.reg[1]); 849 850 ret = shim->repeater_present(dig_port, &repeater_present); 851 if (ret) 852 return ret; 853 if (repeater_present) 854 intel_de_write(i915, HDCP_REP_CTL, 855 intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port)); 856 857 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 858 if (ret) 859 return ret; 860 861 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 862 HDCP_CONF_AUTH_AND_ENC); 863 864 /* Wait for R0 ready */ 865 if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 866 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 867 drm_err(&i915->drm, "Timed out waiting for R0 ready\n"); 868 return -ETIMEDOUT; 869 } 870 871 /* 872 * Wait for R0' to become available. The spec says 100ms from Aksv, but 873 * some monitors can take longer than this. We'll set the timeout at 874 * 300ms just to be sure. 875 * 876 * On DP, there's an R0_READY bit available but no such bit 877 * exists on HDMI. Since the upper-bound is the same, we'll just do 878 * the stupid thing instead of polling on one and not the other. 879 */ 880 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 881 882 tries = 3; 883 884 /* 885 * DP HDCP Spec mandates the two more reattempt to read R0, incase 886 * of R0 mismatch. 887 */ 888 for (i = 0; i < tries; i++) { 889 ri.reg = 0; 890 ret = shim->read_ri_prime(dig_port, ri.shim); 891 if (ret) 892 return ret; 893 intel_de_write(i915, 894 HDCP_RPRIME(i915, cpu_transcoder, port), 895 ri.reg); 896 897 /* Wait for Ri prime match */ 898 if (!wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 899 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 900 break; 901 } 902 903 if (i == tries) { 904 drm_dbg_kms(&i915->drm, 905 "Timed out waiting for Ri prime match (%x)\n", 906 intel_de_read(i915, 907 HDCP_STATUS(i915, cpu_transcoder, port))); 908 return -ETIMEDOUT; 909 } 910 911 /* Wait for encryption confirmation */ 912 if (intel_de_wait_for_set(i915, 913 HDCP_STATUS(i915, cpu_transcoder, port), 914 HDCP_STATUS_ENC, 915 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 916 drm_err(&i915->drm, "Timed out waiting for encryption\n"); 917 return -ETIMEDOUT; 918 } 919 920 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 921 if (shim->stream_encryption) { 922 ret = shim->stream_encryption(connector, true); 923 if (ret) { 924 drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 925 connector->base.base.id, connector->base.name); 926 return ret; 927 } 928 drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 929 transcoder_name(hdcp->stream_transcoder)); 930 } 931 932 if (repeater_present) 933 return intel_hdcp_auth_downstream(connector); 934 935 drm_dbg_kms(&i915->drm, "HDCP is enabled (no repeater present)\n"); 936 return 0; 937} 938 939static int _intel_hdcp_disable(struct intel_connector *connector) 940{ 941 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 942 struct drm_i915_private *i915 = to_i915(connector->base.dev); 943 struct intel_hdcp *hdcp = &connector->hdcp; 944 enum port port = dig_port->base.port; 945 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 946 u32 repeater_ctl; 947 int ret; 948 949 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 950 connector->base.base.id, connector->base.name); 951 952 if (hdcp->shim->stream_encryption) { 953 ret = hdcp->shim->stream_encryption(connector, false); 954 if (ret) { 955 drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 956 connector->base.base.id, connector->base.name); 957 return ret; 958 } 959 drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 960 transcoder_name(hdcp->stream_transcoder)); 961 /* 962 * If there are other connectors on this port using HDCP, 963 * don't disable it until it disabled HDCP encryption for 964 * all connectors in MST topology. 965 */ 966 if (dig_port->num_hdcp_streams > 0) 967 return 0; 968 } 969 970 hdcp->hdcp_encrypted = false; 971 intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 0); 972 if (intel_de_wait_for_clear(i915, 973 HDCP_STATUS(i915, cpu_transcoder, port), 974 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 975 drm_err(&i915->drm, 976 "Failed to disable HDCP, timeout clearing status\n"); 977 return -ETIMEDOUT; 978 } 979 980 repeater_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, 981 port); 982 intel_de_rmw(i915, HDCP_REP_CTL, repeater_ctl, 0); 983 984 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 985 if (ret) { 986 drm_err(&i915->drm, "Failed to disable HDCP signalling\n"); 987 return ret; 988 } 989 990 drm_dbg_kms(&i915->drm, "HDCP is disabled\n"); 991 return 0; 992} 993 994static int intel_hdcp1_enable(struct intel_connector *connector) 995{ 996 struct drm_i915_private *i915 = to_i915(connector->base.dev); 997 struct intel_hdcp *hdcp = &connector->hdcp; 998 int i, ret, tries = 3; 999 1000 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1001 connector->base.base.id, connector->base.name); 1002 1003 if (!hdcp_key_loadable(i915)) { 1004 drm_err(&i915->drm, "HDCP key Load is not possible\n"); 1005 return -ENXIO; 1006 } 1007 1008 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1009 ret = intel_hdcp_load_keys(i915); 1010 if (!ret) 1011 break; 1012 intel_hdcp_clear_keys(i915); 1013 } 1014 if (ret) { 1015 drm_err(&i915->drm, "Could not load HDCP keys, (%d)\n", 1016 ret); 1017 return ret; 1018 } 1019 1020 /* Incase of authentication failures, HDCP spec expects reauth. */ 1021 for (i = 0; i < tries; i++) { 1022 ret = intel_hdcp_auth(connector); 1023 if (!ret) { 1024 hdcp->hdcp_encrypted = true; 1025 return 0; 1026 } 1027 1028 drm_dbg_kms(&i915->drm, "HDCP Auth failure (%d)\n", ret); 1029 1030 /* Ensuring HDCP encryption and signalling are stopped. */ 1031 _intel_hdcp_disable(connector); 1032 } 1033 1034 drm_dbg_kms(&i915->drm, 1035 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1036 return ret; 1037} 1038 1039static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1040{ 1041 return container_of(hdcp, struct intel_connector, hdcp); 1042} 1043 1044static void intel_hdcp_update_value(struct intel_connector *connector, 1045 u64 value, bool update_property) 1046{ 1047 struct drm_device *dev = connector->base.dev; 1048 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1049 struct intel_hdcp *hdcp = &connector->hdcp; 1050 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1051 1052 drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex)); 1053 1054 if (hdcp->value == value) 1055 return; 1056 1057 drm_WARN_ON(dev, !mutex_is_locked(&dig_port->hdcp_mutex)); 1058 1059 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1060 if (!drm_WARN_ON(dev, dig_port->num_hdcp_streams == 0)) 1061 dig_port->num_hdcp_streams--; 1062 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1063 dig_port->num_hdcp_streams++; 1064 } 1065 1066 hdcp->value = value; 1067 if (update_property) { 1068 drm_connector_get(&connector->base); 1069 queue_work(i915->unordered_wq, &hdcp->prop_work); 1070 } 1071} 1072 1073/* Implements Part 3 of the HDCP authorization procedure */ 1074static int intel_hdcp_check_link(struct intel_connector *connector) 1075{ 1076 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1077 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1078 struct intel_hdcp *hdcp = &connector->hdcp; 1079 enum port port = dig_port->base.port; 1080 enum transcoder cpu_transcoder; 1081 int ret = 0; 1082 1083 mutex_lock(&hdcp->mutex); 1084 mutex_lock(&dig_port->hdcp_mutex); 1085 1086 cpu_transcoder = hdcp->cpu_transcoder; 1087 1088 /* Check_link valid only when HDCP1.4 is enabled */ 1089 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1090 !hdcp->hdcp_encrypted) { 1091 ret = -EINVAL; 1092 goto out; 1093 } 1094 1095 if (drm_WARN_ON(&i915->drm, 1096 !intel_hdcp_in_use(i915, cpu_transcoder, port))) { 1097 drm_err(&i915->drm, 1098 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1099 connector->base.base.id, connector->base.name, 1100 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); 1101 ret = -ENXIO; 1102 intel_hdcp_update_value(connector, 1103 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1104 true); 1105 goto out; 1106 } 1107 1108 if (hdcp->shim->check_link(dig_port, connector)) { 1109 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1110 intel_hdcp_update_value(connector, 1111 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1112 } 1113 goto out; 1114 } 1115 1116 drm_dbg_kms(&i915->drm, 1117 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1118 connector->base.base.id, connector->base.name); 1119 1120 ret = _intel_hdcp_disable(connector); 1121 if (ret) { 1122 drm_err(&i915->drm, "Failed to disable hdcp (%d)\n", ret); 1123 intel_hdcp_update_value(connector, 1124 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1125 true); 1126 goto out; 1127 } 1128 1129 intel_hdcp_update_value(connector, 1130 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1131 true); 1132out: 1133 mutex_unlock(&dig_port->hdcp_mutex); 1134 mutex_unlock(&hdcp->mutex); 1135 return ret; 1136} 1137 1138static void intel_hdcp_prop_work(struct work_struct *work) 1139{ 1140 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1141 prop_work); 1142 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1143 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1144 1145 drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); 1146 mutex_lock(&hdcp->mutex); 1147 1148 /* 1149 * This worker is only used to flip between ENABLED/DESIRED. Either of 1150 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1151 * we're running just after hdcp has been disabled, so just exit 1152 */ 1153 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1154 drm_hdcp_update_content_protection(&connector->base, 1155 hdcp->value); 1156 1157 mutex_unlock(&hdcp->mutex); 1158 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1159 1160 drm_connector_put(&connector->base); 1161} 1162 1163bool is_hdcp_supported(struct drm_i915_private *i915, enum port port) 1164{ 1165 return DISPLAY_RUNTIME_INFO(i915)->has_hdcp && 1166 (DISPLAY_VER(i915) >= 12 || port < PORT_E); 1167} 1168 1169static int 1170hdcp2_prepare_ake_init(struct intel_connector *connector, 1171 struct hdcp2_ake_init *ake_data) 1172{ 1173 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1174 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1175 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1176 struct i915_hdcp_arbiter *arbiter; 1177 int ret; 1178 1179 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1180 arbiter = i915->display.hdcp.arbiter; 1181 1182 if (!arbiter || !arbiter->ops) { 1183 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1184 return -EINVAL; 1185 } 1186 1187 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1188 if (ret) 1189 drm_dbg_kms(&i915->drm, "Prepare_ake_init failed. %d\n", 1190 ret); 1191 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1192 1193 return ret; 1194} 1195 1196static int 1197hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1198 struct hdcp2_ake_send_cert *rx_cert, 1199 bool *paired, 1200 struct hdcp2_ake_no_stored_km *ek_pub_km, 1201 size_t *msg_sz) 1202{ 1203 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1204 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1205 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1206 struct i915_hdcp_arbiter *arbiter; 1207 int ret; 1208 1209 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1210 arbiter = i915->display.hdcp.arbiter; 1211 1212 if (!arbiter || !arbiter->ops) { 1213 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1214 return -EINVAL; 1215 } 1216 1217 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1218 rx_cert, paired, 1219 ek_pub_km, msg_sz); 1220 if (ret < 0) 1221 drm_dbg_kms(&i915->drm, "Verify rx_cert failed. %d\n", 1222 ret); 1223 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1224 1225 return ret; 1226} 1227 1228static int hdcp2_verify_hprime(struct intel_connector *connector, 1229 struct hdcp2_ake_send_hprime *rx_hprime) 1230{ 1231 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1232 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1233 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1234 struct i915_hdcp_arbiter *arbiter; 1235 int ret; 1236 1237 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1238 arbiter = i915->display.hdcp.arbiter; 1239 1240 if (!arbiter || !arbiter->ops) { 1241 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1242 return -EINVAL; 1243 } 1244 1245 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1246 if (ret < 0) 1247 drm_dbg_kms(&i915->drm, "Verify hprime failed. %d\n", ret); 1248 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1249 1250 return ret; 1251} 1252 1253static int 1254hdcp2_store_pairing_info(struct intel_connector *connector, 1255 struct hdcp2_ake_send_pairing_info *pairing_info) 1256{ 1257 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1258 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1259 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1260 struct i915_hdcp_arbiter *arbiter; 1261 int ret; 1262 1263 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1264 arbiter = i915->display.hdcp.arbiter; 1265 1266 if (!arbiter || !arbiter->ops) { 1267 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1268 return -EINVAL; 1269 } 1270 1271 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1272 if (ret < 0) 1273 drm_dbg_kms(&i915->drm, "Store pairing info failed. %d\n", 1274 ret); 1275 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1276 1277 return ret; 1278} 1279 1280static int 1281hdcp2_prepare_lc_init(struct intel_connector *connector, 1282 struct hdcp2_lc_init *lc_init) 1283{ 1284 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1285 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1286 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1287 struct i915_hdcp_arbiter *arbiter; 1288 int ret; 1289 1290 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1291 arbiter = i915->display.hdcp.arbiter; 1292 1293 if (!arbiter || !arbiter->ops) { 1294 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1295 return -EINVAL; 1296 } 1297 1298 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1299 if (ret < 0) 1300 drm_dbg_kms(&i915->drm, "Prepare lc_init failed. %d\n", 1301 ret); 1302 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1303 1304 return ret; 1305} 1306 1307static int 1308hdcp2_verify_lprime(struct intel_connector *connector, 1309 struct hdcp2_lc_send_lprime *rx_lprime) 1310{ 1311 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1312 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1313 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1314 struct i915_hdcp_arbiter *arbiter; 1315 int ret; 1316 1317 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1318 arbiter = i915->display.hdcp.arbiter; 1319 1320 if (!arbiter || !arbiter->ops) { 1321 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1322 return -EINVAL; 1323 } 1324 1325 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1326 if (ret < 0) 1327 drm_dbg_kms(&i915->drm, "Verify L_Prime failed. %d\n", 1328 ret); 1329 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1330 1331 return ret; 1332} 1333 1334static int hdcp2_prepare_skey(struct intel_connector *connector, 1335 struct hdcp2_ske_send_eks *ske_data) 1336{ 1337 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1338 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1339 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1340 struct i915_hdcp_arbiter *arbiter; 1341 int ret; 1342 1343 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1344 arbiter = i915->display.hdcp.arbiter; 1345 1346 if (!arbiter || !arbiter->ops) { 1347 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1348 return -EINVAL; 1349 } 1350 1351 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1352 if (ret < 0) 1353 drm_dbg_kms(&i915->drm, "Get session key failed. %d\n", 1354 ret); 1355 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1356 1357 return ret; 1358} 1359 1360static int 1361hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1362 struct hdcp2_rep_send_receiverid_list 1363 *rep_topology, 1364 struct hdcp2_rep_send_ack *rep_send_ack) 1365{ 1366 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1367 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1368 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1369 struct i915_hdcp_arbiter *arbiter; 1370 int ret; 1371 1372 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1373 arbiter = i915->display.hdcp.arbiter; 1374 1375 if (!arbiter || !arbiter->ops) { 1376 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1377 return -EINVAL; 1378 } 1379 1380 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1381 data, 1382 rep_topology, 1383 rep_send_ack); 1384 if (ret < 0) 1385 drm_dbg_kms(&i915->drm, 1386 "Verify rep topology failed. %d\n", ret); 1387 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1388 1389 return ret; 1390} 1391 1392static int 1393hdcp2_verify_mprime(struct intel_connector *connector, 1394 struct hdcp2_rep_stream_ready *stream_ready) 1395{ 1396 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1397 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1398 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1399 struct i915_hdcp_arbiter *arbiter; 1400 int ret; 1401 1402 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1403 arbiter = i915->display.hdcp.arbiter; 1404 1405 if (!arbiter || !arbiter->ops) { 1406 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1407 return -EINVAL; 1408 } 1409 1410 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1411 if (ret < 0) 1412 drm_dbg_kms(&i915->drm, "Verify mprime failed. %d\n", ret); 1413 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1414 1415 return ret; 1416} 1417 1418static int hdcp2_authenticate_port(struct intel_connector *connector) 1419{ 1420 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1421 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1422 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1423 struct i915_hdcp_arbiter *arbiter; 1424 int ret; 1425 1426 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1427 arbiter = i915->display.hdcp.arbiter; 1428 1429 if (!arbiter || !arbiter->ops) { 1430 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1431 return -EINVAL; 1432 } 1433 1434 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1435 if (ret < 0) 1436 drm_dbg_kms(&i915->drm, "Enable hdcp auth failed. %d\n", 1437 ret); 1438 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1439 1440 return ret; 1441} 1442 1443static int hdcp2_close_session(struct intel_connector *connector) 1444{ 1445 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1446 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1447 struct i915_hdcp_arbiter *arbiter; 1448 int ret; 1449 1450 mutex_lock(&i915->display.hdcp.hdcp_mutex); 1451 arbiter = i915->display.hdcp.arbiter; 1452 1453 if (!arbiter || !arbiter->ops) { 1454 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1455 return -EINVAL; 1456 } 1457 1458 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1459 &dig_port->hdcp_port_data); 1460 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 1461 1462 return ret; 1463} 1464 1465static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1466{ 1467 return hdcp2_close_session(connector); 1468} 1469 1470/* Authentication flow starts from here */ 1471static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1472{ 1473 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1474 struct intel_hdcp *hdcp = &connector->hdcp; 1475 union { 1476 struct hdcp2_ake_init ake_init; 1477 struct hdcp2_ake_send_cert send_cert; 1478 struct hdcp2_ake_no_stored_km no_stored_km; 1479 struct hdcp2_ake_send_hprime send_hprime; 1480 struct hdcp2_ake_send_pairing_info pairing_info; 1481 } msgs; 1482 const struct intel_hdcp_shim *shim = hdcp->shim; 1483 size_t size; 1484 int ret; 1485 1486 /* Init for seq_num */ 1487 hdcp->seq_num_v = 0; 1488 hdcp->seq_num_m = 0; 1489 1490 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1491 if (ret < 0) 1492 return ret; 1493 1494 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1495 sizeof(msgs.ake_init)); 1496 if (ret < 0) 1497 return ret; 1498 1499 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1500 &msgs.send_cert, sizeof(msgs.send_cert)); 1501 if (ret < 0) 1502 return ret; 1503 1504 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1505 drm_dbg_kms(&i915->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1506 return -EINVAL; 1507 } 1508 1509 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1510 1511 if (drm_hdcp_check_ksvs_revoked(&i915->drm, 1512 msgs.send_cert.cert_rx.receiver_id, 1513 1) > 0) { 1514 drm_err(&i915->drm, "Receiver ID is revoked\n"); 1515 return -EPERM; 1516 } 1517 1518 /* 1519 * Here msgs.no_stored_km will hold msgs corresponding to the km 1520 * stored also. 1521 */ 1522 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1523 &hdcp->is_paired, 1524 &msgs.no_stored_km, &size); 1525 if (ret < 0) 1526 return ret; 1527 1528 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1529 if (ret < 0) 1530 return ret; 1531 1532 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1533 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1534 if (ret < 0) 1535 return ret; 1536 1537 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1538 if (ret < 0) 1539 return ret; 1540 1541 if (!hdcp->is_paired) { 1542 /* Pairing is required */ 1543 ret = shim->read_2_2_msg(connector, 1544 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1545 &msgs.pairing_info, 1546 sizeof(msgs.pairing_info)); 1547 if (ret < 0) 1548 return ret; 1549 1550 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1551 if (ret < 0) 1552 return ret; 1553 hdcp->is_paired = true; 1554 } 1555 1556 return 0; 1557} 1558 1559static int hdcp2_locality_check(struct intel_connector *connector) 1560{ 1561 struct intel_hdcp *hdcp = &connector->hdcp; 1562 union { 1563 struct hdcp2_lc_init lc_init; 1564 struct hdcp2_lc_send_lprime send_lprime; 1565 } msgs; 1566 const struct intel_hdcp_shim *shim = hdcp->shim; 1567 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1568 1569 for (i = 0; i < tries; i++) { 1570 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1571 if (ret < 0) 1572 continue; 1573 1574 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1575 sizeof(msgs.lc_init)); 1576 if (ret < 0) 1577 continue; 1578 1579 ret = shim->read_2_2_msg(connector, 1580 HDCP_2_2_LC_SEND_LPRIME, 1581 &msgs.send_lprime, 1582 sizeof(msgs.send_lprime)); 1583 if (ret < 0) 1584 continue; 1585 1586 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1587 if (!ret) 1588 break; 1589 } 1590 1591 return ret; 1592} 1593 1594static int hdcp2_session_key_exchange(struct intel_connector *connector) 1595{ 1596 struct intel_hdcp *hdcp = &connector->hdcp; 1597 struct hdcp2_ske_send_eks send_eks; 1598 int ret; 1599 1600 ret = hdcp2_prepare_skey(connector, &send_eks); 1601 if (ret < 0) 1602 return ret; 1603 1604 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1605 sizeof(send_eks)); 1606 if (ret < 0) 1607 return ret; 1608 1609 return 0; 1610} 1611 1612static 1613int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1614{ 1615 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1616 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1617 struct intel_hdcp *hdcp = &connector->hdcp; 1618 union { 1619 struct hdcp2_rep_stream_manage stream_manage; 1620 struct hdcp2_rep_stream_ready stream_ready; 1621 } msgs; 1622 const struct intel_hdcp_shim *shim = hdcp->shim; 1623 int ret, streams_size_delta, i; 1624 1625 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1626 return -ERANGE; 1627 1628 /* Prepare RepeaterAuth_Stream_Manage msg */ 1629 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1630 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1631 1632 msgs.stream_manage.k = cpu_to_be16(data->k); 1633 1634 for (i = 0; i < data->k; i++) { 1635 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1636 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1637 } 1638 1639 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1640 sizeof(struct hdcp2_streamid_type); 1641 /* Send it to Repeater */ 1642 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1643 sizeof(msgs.stream_manage) - streams_size_delta); 1644 if (ret < 0) 1645 goto out; 1646 1647 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1648 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1649 if (ret < 0) 1650 goto out; 1651 1652 data->seq_num_m = hdcp->seq_num_m; 1653 1654 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1655 1656out: 1657 hdcp->seq_num_m++; 1658 1659 return ret; 1660} 1661 1662static 1663int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1664{ 1665 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1666 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1667 struct intel_hdcp *hdcp = &connector->hdcp; 1668 union { 1669 struct hdcp2_rep_send_receiverid_list recvid_list; 1670 struct hdcp2_rep_send_ack rep_ack; 1671 } msgs; 1672 const struct intel_hdcp_shim *shim = hdcp->shim; 1673 u32 seq_num_v, device_cnt; 1674 u8 *rx_info; 1675 int ret; 1676 1677 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1678 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1679 if (ret < 0) 1680 return ret; 1681 1682 rx_info = msgs.recvid_list.rx_info; 1683 1684 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1685 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1686 drm_dbg_kms(&i915->drm, "Topology Max Size Exceeded\n"); 1687 return -EINVAL; 1688 } 1689 1690 /* 1691 * MST topology is not Type 1 capable if it contains a downstream 1692 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1693 */ 1694 dig_port->hdcp_mst_type1_capable = 1695 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1696 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1697 1698 if (!dig_port->hdcp_mst_type1_capable && hdcp->content_type) { 1699 drm_dbg_kms(&i915->drm, 1700 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1701 return -EINVAL; 1702 } 1703 1704 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1705 seq_num_v = 1706 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1707 1708 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1709 drm_dbg_kms(&i915->drm, 1710 "Non zero Seq_num_v at first RecvId_List msg\n"); 1711 return -EINVAL; 1712 } 1713 1714 if (seq_num_v < hdcp->seq_num_v) { 1715 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1716 drm_dbg_kms(&i915->drm, "Seq_num_v roll over.\n"); 1717 return -EINVAL; 1718 } 1719 1720 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1721 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1722 if (drm_hdcp_check_ksvs_revoked(&i915->drm, 1723 msgs.recvid_list.receiver_ids, 1724 device_cnt) > 0) { 1725 drm_err(&i915->drm, "Revoked receiver ID(s) is in list\n"); 1726 return -EPERM; 1727 } 1728 1729 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1730 &msgs.recvid_list, 1731 &msgs.rep_ack); 1732 if (ret < 0) 1733 return ret; 1734 1735 hdcp->seq_num_v = seq_num_v; 1736 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1737 sizeof(msgs.rep_ack)); 1738 if (ret < 0) 1739 return ret; 1740 1741 return 0; 1742} 1743 1744static int hdcp2_authenticate_sink(struct intel_connector *connector) 1745{ 1746 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1747 struct intel_hdcp *hdcp = &connector->hdcp; 1748 const struct intel_hdcp_shim *shim = hdcp->shim; 1749 int ret; 1750 1751 ret = hdcp2_authentication_key_exchange(connector); 1752 if (ret < 0) { 1753 drm_dbg_kms(&i915->drm, "AKE Failed. Err : %d\n", ret); 1754 return ret; 1755 } 1756 1757 ret = hdcp2_locality_check(connector); 1758 if (ret < 0) { 1759 drm_dbg_kms(&i915->drm, 1760 "Locality Check failed. Err : %d\n", ret); 1761 return ret; 1762 } 1763 1764 ret = hdcp2_session_key_exchange(connector); 1765 if (ret < 0) { 1766 drm_dbg_kms(&i915->drm, "SKE Failed. Err : %d\n", ret); 1767 return ret; 1768 } 1769 1770 if (shim->config_stream_type) { 1771 ret = shim->config_stream_type(connector, 1772 hdcp->is_repeater, 1773 hdcp->content_type); 1774 if (ret < 0) 1775 return ret; 1776 } 1777 1778 if (hdcp->is_repeater) { 1779 ret = hdcp2_authenticate_repeater_topology(connector); 1780 if (ret < 0) { 1781 drm_dbg_kms(&i915->drm, 1782 "Repeater Auth Failed. Err: %d\n", ret); 1783 return ret; 1784 } 1785 } 1786 1787 return ret; 1788} 1789 1790static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1791{ 1792 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1793 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1794 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1795 struct intel_hdcp *hdcp = &connector->hdcp; 1796 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1797 enum port port = dig_port->base.port; 1798 int ret = 0; 1799 1800 if (!(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1801 LINK_ENCRYPTION_STATUS)) { 1802 drm_err(&i915->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1803 connector->base.base.id, connector->base.name); 1804 ret = -EPERM; 1805 goto link_recover; 1806 } 1807 1808 if (hdcp->shim->stream_2_2_encryption) { 1809 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1810 if (ret) { 1811 drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1812 connector->base.base.id, connector->base.name); 1813 return ret; 1814 } 1815 drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1816 transcoder_name(hdcp->stream_transcoder)); 1817 } 1818 1819 return 0; 1820 1821link_recover: 1822 if (hdcp2_deauthenticate_port(connector) < 0) 1823 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1824 1825 dig_port->hdcp_auth_status = false; 1826 data->k = 0; 1827 1828 return ret; 1829} 1830 1831static int hdcp2_enable_encryption(struct intel_connector *connector) 1832{ 1833 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1834 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1835 struct intel_hdcp *hdcp = &connector->hdcp; 1836 enum port port = dig_port->base.port; 1837 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1838 int ret; 1839 1840 drm_WARN_ON(&i915->drm, 1841 intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1842 LINK_ENCRYPTION_STATUS); 1843 if (hdcp->shim->toggle_signalling) { 1844 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1845 true); 1846 if (ret) { 1847 drm_err(&i915->drm, 1848 "Failed to enable HDCP signalling. %d\n", 1849 ret); 1850 return ret; 1851 } 1852 } 1853 1854 if (intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1855 LINK_AUTH_STATUS) 1856 /* Link is Authenticated. Now set for Encryption */ 1857 intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), 1858 0, CTL_LINK_ENCRYPTION_REQ); 1859 1860 ret = intel_de_wait_for_set(i915, 1861 HDCP2_STATUS(i915, cpu_transcoder, 1862 port), 1863 LINK_ENCRYPTION_STATUS, 1864 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1865 dig_port->hdcp_auth_status = true; 1866 1867 return ret; 1868} 1869 1870static int hdcp2_disable_encryption(struct intel_connector *connector) 1871{ 1872 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1873 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1874 struct intel_hdcp *hdcp = &connector->hdcp; 1875 enum port port = dig_port->base.port; 1876 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1877 int ret; 1878 1879 drm_WARN_ON(&i915->drm, !(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & 1880 LINK_ENCRYPTION_STATUS)); 1881 1882 intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), 1883 CTL_LINK_ENCRYPTION_REQ, 0); 1884 1885 ret = intel_de_wait_for_clear(i915, 1886 HDCP2_STATUS(i915, cpu_transcoder, 1887 port), 1888 LINK_ENCRYPTION_STATUS, 1889 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1890 if (ret == -ETIMEDOUT) 1891 drm_dbg_kms(&i915->drm, "Disable Encryption Timedout"); 1892 1893 if (hdcp->shim->toggle_signalling) { 1894 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1895 false); 1896 if (ret) { 1897 drm_err(&i915->drm, 1898 "Failed to disable HDCP signalling. %d\n", 1899 ret); 1900 return ret; 1901 } 1902 } 1903 1904 return ret; 1905} 1906 1907static int 1908hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1909{ 1910 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1911 int i, tries = 3, ret; 1912 1913 if (!connector->hdcp.is_repeater) 1914 return 0; 1915 1916 for (i = 0; i < tries; i++) { 1917 ret = _hdcp2_propagate_stream_management_info(connector); 1918 if (!ret) 1919 break; 1920 1921 /* Lets restart the auth incase of seq_num_m roll over */ 1922 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 1923 drm_dbg_kms(&i915->drm, 1924 "seq_num_m roll over.(%d)\n", ret); 1925 break; 1926 } 1927 1928 drm_dbg_kms(&i915->drm, 1929 "HDCP2 stream management %d of %d Failed.(%d)\n", 1930 i + 1, tries, ret); 1931 } 1932 1933 return ret; 1934} 1935 1936static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 1937 struct intel_connector *connector) 1938{ 1939 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1940 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1941 int ret = 0, i, tries = 3; 1942 1943 for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { 1944 ret = hdcp2_authenticate_sink(connector); 1945 if (!ret) { 1946 ret = intel_hdcp_prepare_streams(state, connector); 1947 if (ret) { 1948 drm_dbg_kms(&i915->drm, 1949 "Prepare stream failed.(%d)\n", 1950 ret); 1951 break; 1952 } 1953 1954 ret = hdcp2_propagate_stream_management_info(connector); 1955 if (ret) { 1956 drm_dbg_kms(&i915->drm, 1957 "Stream management failed.(%d)\n", 1958 ret); 1959 break; 1960 } 1961 1962 ret = hdcp2_authenticate_port(connector); 1963 if (!ret) 1964 break; 1965 drm_dbg_kms(&i915->drm, "HDCP2 port auth failed.(%d)\n", 1966 ret); 1967 } 1968 1969 /* Clearing the mei hdcp session */ 1970 drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 1971 i + 1, tries, ret); 1972 if (hdcp2_deauthenticate_port(connector) < 0) 1973 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1974 } 1975 1976 if (!ret && !dig_port->hdcp_auth_status) { 1977 /* 1978 * Ensuring the required 200mSec min time interval between 1979 * Session Key Exchange and encryption. 1980 */ 1981 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 1982 ret = hdcp2_enable_encryption(connector); 1983 if (ret < 0) { 1984 drm_dbg_kms(&i915->drm, 1985 "Encryption Enable Failed.(%d)\n", ret); 1986 if (hdcp2_deauthenticate_port(connector) < 0) 1987 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 1988 } 1989 } 1990 1991 if (!ret) 1992 ret = hdcp2_enable_stream_encryption(connector); 1993 1994 return ret; 1995} 1996 1997static int _intel_hdcp2_enable(struct intel_atomic_state *state, 1998 struct intel_connector *connector) 1999{ 2000 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2001 struct intel_hdcp *hdcp = &connector->hdcp; 2002 int ret; 2003 2004 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2005 connector->base.base.id, connector->base.name, 2006 hdcp->content_type); 2007 2008 ret = hdcp2_authenticate_and_encrypt(state, connector); 2009 if (ret) { 2010 drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2011 hdcp->content_type, ret); 2012 return ret; 2013 } 2014 2015 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2016 connector->base.base.id, connector->base.name, 2017 hdcp->content_type); 2018 2019 hdcp->hdcp2_encrypted = true; 2020 return 0; 2021} 2022 2023static int 2024_intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2025{ 2026 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2027 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2028 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2029 struct intel_hdcp *hdcp = &connector->hdcp; 2030 int ret; 2031 2032 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2033 connector->base.base.id, connector->base.name); 2034 2035 if (hdcp->shim->stream_2_2_encryption) { 2036 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2037 if (ret) { 2038 drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2039 connector->base.base.id, connector->base.name); 2040 return ret; 2041 } 2042 drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2043 transcoder_name(hdcp->stream_transcoder)); 2044 2045 if (dig_port->num_hdcp_streams > 0 && !hdcp2_link_recovery) 2046 return 0; 2047 } 2048 2049 ret = hdcp2_disable_encryption(connector); 2050 2051 if (hdcp2_deauthenticate_port(connector) < 0) 2052 drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); 2053 2054 connector->hdcp.hdcp2_encrypted = false; 2055 dig_port->hdcp_auth_status = false; 2056 data->k = 0; 2057 2058 return ret; 2059} 2060 2061/* Implements the Link Integrity Check for HDCP2.2 */ 2062static int intel_hdcp2_check_link(struct intel_connector *connector) 2063{ 2064 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2065 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2066 struct intel_hdcp *hdcp = &connector->hdcp; 2067 enum port port = dig_port->base.port; 2068 enum transcoder cpu_transcoder; 2069 int ret = 0; 2070 2071 mutex_lock(&hdcp->mutex); 2072 mutex_lock(&dig_port->hdcp_mutex); 2073 cpu_transcoder = hdcp->cpu_transcoder; 2074 2075 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2076 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2077 !hdcp->hdcp2_encrypted) { 2078 ret = -EINVAL; 2079 goto out; 2080 } 2081 2082 if (drm_WARN_ON(&i915->drm, 2083 !intel_hdcp2_in_use(i915, cpu_transcoder, port))) { 2084 drm_err(&i915->drm, 2085 "HDCP2.2 link stopped the encryption, %x\n", 2086 intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port))); 2087 ret = -ENXIO; 2088 _intel_hdcp2_disable(connector, true); 2089 intel_hdcp_update_value(connector, 2090 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2091 true); 2092 goto out; 2093 } 2094 2095 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2096 if (ret == HDCP_LINK_PROTECTED) { 2097 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2098 intel_hdcp_update_value(connector, 2099 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2100 true); 2101 } 2102 goto out; 2103 } 2104 2105 if (ret == HDCP_TOPOLOGY_CHANGE) { 2106 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2107 goto out; 2108 2109 drm_dbg_kms(&i915->drm, 2110 "HDCP2.2 Downstream topology change\n"); 2111 } else { 2112 drm_dbg_kms(&i915->drm, 2113 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2114 connector->base.base.id, connector->base.name); 2115 } 2116 2117 ret = _intel_hdcp2_disable(connector, true); 2118 if (ret) { 2119 drm_err(&i915->drm, 2120 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2121 connector->base.base.id, connector->base.name, ret); 2122 intel_hdcp_update_value(connector, 2123 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2124 goto out; 2125 } 2126 2127 intel_hdcp_update_value(connector, 2128 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2129out: 2130 mutex_unlock(&dig_port->hdcp_mutex); 2131 mutex_unlock(&hdcp->mutex); 2132 return ret; 2133} 2134 2135static void intel_hdcp_check_work(struct work_struct *work) 2136{ 2137 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2138 struct intel_hdcp, 2139 check_work); 2140 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2141 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2142 2143 if (drm_connector_is_unregistered(&connector->base)) 2144 return; 2145 2146 if (!intel_hdcp2_check_link(connector)) 2147 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2148 DRM_HDCP2_CHECK_PERIOD_MS); 2149 else if (!intel_hdcp_check_link(connector)) 2150 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2151 DRM_HDCP_CHECK_PERIOD_MS); 2152} 2153 2154static int i915_hdcp_component_bind(struct device *i915_kdev, 2155 struct device *mei_kdev, void *data) 2156{ 2157 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 2158 2159 drm_dbg(&i915->drm, "I915 HDCP comp bind\n"); 2160 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2161 i915->display.hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2162 i915->display.hdcp.arbiter->hdcp_dev = mei_kdev; 2163 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2164 2165 return 0; 2166} 2167 2168static void i915_hdcp_component_unbind(struct device *i915_kdev, 2169 struct device *mei_kdev, void *data) 2170{ 2171 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 2172 2173 drm_dbg(&i915->drm, "I915 HDCP comp unbind\n"); 2174 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2175 i915->display.hdcp.arbiter = NULL; 2176 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2177} 2178 2179static const struct component_ops i915_hdcp_ops = { 2180 .bind = i915_hdcp_component_bind, 2181 .unbind = i915_hdcp_component_unbind, 2182}; 2183 2184static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2185{ 2186 switch (port) { 2187 case PORT_A: 2188 return HDCP_DDI_A; 2189 case PORT_B ... PORT_F: 2190 return (enum hdcp_ddi)port; 2191 default: 2192 return HDCP_DDI_INVALID_PORT; 2193 } 2194} 2195 2196static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2197{ 2198 switch (cpu_transcoder) { 2199 case TRANSCODER_A ... TRANSCODER_D: 2200 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2201 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2202 return HDCP_INVALID_TRANSCODER; 2203 } 2204} 2205 2206static int initialize_hdcp_port_data(struct intel_connector *connector, 2207 struct intel_digital_port *dig_port, 2208 const struct intel_hdcp_shim *shim) 2209{ 2210 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2211 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2212 enum port port = dig_port->base.port; 2213 2214 if (DISPLAY_VER(i915) < 12) 2215 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2216 else 2217 /* 2218 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2219 * with zero(INVALID PORT index). 2220 */ 2221 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2222 2223 /* 2224 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2225 * is initialized to zero (invalid transcoder index). This will be 2226 * retained for <Gen12 forever. 2227 */ 2228 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2229 2230 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2231 data->protocol = (u8)shim->protocol; 2232 2233 if (!data->streams) 2234 data->streams = kcalloc(INTEL_NUM_PIPES(i915), 2235 sizeof(struct hdcp2_streamid_type), 2236 GFP_KERNEL); 2237 if (!data->streams) { 2238 drm_err(&i915->drm, "Out of Memory\n"); 2239 return -ENOMEM; 2240 } 2241 2242 return 0; 2243} 2244 2245static bool is_hdcp2_supported(struct drm_i915_private *i915) 2246{ 2247 if (intel_hdcp_gsc_cs_required(i915)) 2248 return true; 2249 2250 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2251 return false; 2252 2253 return (DISPLAY_VER(i915) >= 10 || 2254 IS_KABYLAKE(i915) || 2255 IS_COFFEELAKE(i915) || 2256 IS_COMETLAKE(i915)); 2257} 2258 2259void intel_hdcp_component_init(struct drm_i915_private *i915) 2260{ 2261 int ret; 2262 2263 if (!is_hdcp2_supported(i915)) 2264 return; 2265 2266 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2267 drm_WARN_ON(&i915->drm, i915->display.hdcp.comp_added); 2268 2269 i915->display.hdcp.comp_added = true; 2270 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2271 if (intel_hdcp_gsc_cs_required(i915)) 2272 ret = intel_hdcp_gsc_init(i915); 2273 else 2274 ret = component_add_typed(i915->drm.dev, &i915_hdcp_ops, 2275 I915_COMPONENT_HDCP); 2276 2277 if (ret < 0) { 2278 drm_dbg_kms(&i915->drm, "Failed at fw component add(%d)\n", 2279 ret); 2280 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2281 i915->display.hdcp.comp_added = false; 2282 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2283 return; 2284 } 2285} 2286 2287static void intel_hdcp2_init(struct intel_connector *connector, 2288 struct intel_digital_port *dig_port, 2289 const struct intel_hdcp_shim *shim) 2290{ 2291 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2292 struct intel_hdcp *hdcp = &connector->hdcp; 2293 int ret; 2294 2295 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2296 if (ret) { 2297 drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); 2298 return; 2299 } 2300 2301 hdcp->hdcp2_supported = true; 2302} 2303 2304int intel_hdcp_init(struct intel_connector *connector, 2305 struct intel_digital_port *dig_port, 2306 const struct intel_hdcp_shim *shim) 2307{ 2308 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2309 struct intel_hdcp *hdcp = &connector->hdcp; 2310 int ret; 2311 2312 if (!shim) 2313 return -EINVAL; 2314 2315 if (is_hdcp2_supported(i915)) 2316 intel_hdcp2_init(connector, dig_port, shim); 2317 2318 ret = 2319 drm_connector_attach_content_protection_property(&connector->base, 2320 hdcp->hdcp2_supported); 2321 if (ret) { 2322 hdcp->hdcp2_supported = false; 2323 kfree(dig_port->hdcp_port_data.streams); 2324 return ret; 2325 } 2326 2327 hdcp->shim = shim; 2328 mutex_init(&hdcp->mutex); 2329 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2330 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2331 init_waitqueue_head(&hdcp->cp_irq_queue); 2332 2333 return 0; 2334} 2335 2336static int _intel_hdcp_enable(struct intel_atomic_state *state, 2337 struct intel_encoder *encoder, 2338 const struct intel_crtc_state *pipe_config, 2339 const struct drm_connector_state *conn_state) 2340{ 2341 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2342 struct intel_connector *connector = 2343 to_intel_connector(conn_state->connector); 2344 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2345 struct intel_hdcp *hdcp = &connector->hdcp; 2346 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2347 int ret = -EINVAL; 2348 2349 if (!hdcp->shim) 2350 return -ENOENT; 2351 2352 if (!connector->encoder) { 2353 drm_err(&i915->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n", 2354 connector->base.base.id, connector->base.name); 2355 return -ENODEV; 2356 } 2357 2358 mutex_lock(&hdcp->mutex); 2359 mutex_lock(&dig_port->hdcp_mutex); 2360 drm_WARN_ON(&i915->drm, 2361 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2362 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2363 2364 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2365 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2366 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2367 } else { 2368 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2369 hdcp->stream_transcoder = INVALID_TRANSCODER; 2370 } 2371 2372 if (DISPLAY_VER(i915) >= 12) 2373 dig_port->hdcp_port_data.hdcp_transcoder = 2374 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2375 2376 /* 2377 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2378 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2379 */ 2380 if (intel_hdcp2_get_capability(connector)) { 2381 ret = _intel_hdcp2_enable(state, connector); 2382 if (!ret) 2383 check_link_interval = 2384 DRM_HDCP2_CHECK_PERIOD_MS; 2385 } 2386 2387 /* 2388 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2389 * be attempted. 2390 */ 2391 if (ret && intel_hdcp_get_capability(connector) && 2392 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2393 ret = intel_hdcp1_enable(connector); 2394 } 2395 2396 if (!ret) { 2397 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2398 check_link_interval); 2399 intel_hdcp_update_value(connector, 2400 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2401 true); 2402 } 2403 2404 mutex_unlock(&dig_port->hdcp_mutex); 2405 mutex_unlock(&hdcp->mutex); 2406 return ret; 2407} 2408 2409void intel_hdcp_enable(struct intel_atomic_state *state, 2410 struct intel_encoder *encoder, 2411 const struct intel_crtc_state *crtc_state, 2412 const struct drm_connector_state *conn_state) 2413{ 2414 struct intel_connector *connector = 2415 to_intel_connector(conn_state->connector); 2416 struct intel_hdcp *hdcp = &connector->hdcp; 2417 2418 /* 2419 * Enable hdcp if it's desired or if userspace is enabled and 2420 * driver set its state to undesired 2421 */ 2422 if (conn_state->content_protection == 2423 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2424 (conn_state->content_protection == 2425 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2426 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2427 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2428} 2429 2430int intel_hdcp_disable(struct intel_connector *connector) 2431{ 2432 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2433 struct intel_hdcp *hdcp = &connector->hdcp; 2434 int ret = 0; 2435 2436 if (!hdcp->shim) 2437 return -ENOENT; 2438 2439 mutex_lock(&hdcp->mutex); 2440 mutex_lock(&dig_port->hdcp_mutex); 2441 2442 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2443 goto out; 2444 2445 intel_hdcp_update_value(connector, 2446 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2447 if (hdcp->hdcp2_encrypted) 2448 ret = _intel_hdcp2_disable(connector, false); 2449 else if (hdcp->hdcp_encrypted) 2450 ret = _intel_hdcp_disable(connector); 2451 2452out: 2453 mutex_unlock(&dig_port->hdcp_mutex); 2454 mutex_unlock(&hdcp->mutex); 2455 cancel_delayed_work_sync(&hdcp->check_work); 2456 return ret; 2457} 2458 2459void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2460 struct intel_encoder *encoder, 2461 const struct intel_crtc_state *crtc_state, 2462 const struct drm_connector_state *conn_state) 2463{ 2464 struct intel_connector *connector = 2465 to_intel_connector(conn_state->connector); 2466 struct intel_hdcp *hdcp = &connector->hdcp; 2467 bool content_protection_type_changed, desired_and_not_enabled = false; 2468 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2469 2470 if (!connector->hdcp.shim) 2471 return; 2472 2473 content_protection_type_changed = 2474 (conn_state->hdcp_content_type != hdcp->content_type && 2475 conn_state->content_protection != 2476 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2477 2478 /* 2479 * During the HDCP encryption session if Type change is requested, 2480 * disable the HDCP and reenable it with new TYPE value. 2481 */ 2482 if (conn_state->content_protection == 2483 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2484 content_protection_type_changed) 2485 intel_hdcp_disable(connector); 2486 2487 /* 2488 * Mark the hdcp state as DESIRED after the hdcp disable of type 2489 * change procedure. 2490 */ 2491 if (content_protection_type_changed) { 2492 mutex_lock(&hdcp->mutex); 2493 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2494 drm_connector_get(&connector->base); 2495 queue_work(i915->unordered_wq, &hdcp->prop_work); 2496 mutex_unlock(&hdcp->mutex); 2497 } 2498 2499 if (conn_state->content_protection == 2500 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2501 mutex_lock(&hdcp->mutex); 2502 /* Avoid enabling hdcp, if it already ENABLED */ 2503 desired_and_not_enabled = 2504 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2505 mutex_unlock(&hdcp->mutex); 2506 /* 2507 * If HDCP already ENABLED and CP property is DESIRED, schedule 2508 * prop_work to update correct CP property to user space. 2509 */ 2510 if (!desired_and_not_enabled && !content_protection_type_changed) { 2511 drm_connector_get(&connector->base); 2512 queue_work(i915->unordered_wq, &hdcp->prop_work); 2513 } 2514 } 2515 2516 if (desired_and_not_enabled || content_protection_type_changed) 2517 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2518} 2519 2520void intel_hdcp_component_fini(struct drm_i915_private *i915) 2521{ 2522 mutex_lock(&i915->display.hdcp.hdcp_mutex); 2523 if (!i915->display.hdcp.comp_added) { 2524 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2525 return; 2526 } 2527 2528 i915->display.hdcp.comp_added = false; 2529 mutex_unlock(&i915->display.hdcp.hdcp_mutex); 2530 2531 if (intel_hdcp_gsc_cs_required(i915)) 2532 intel_hdcp_gsc_fini(i915); 2533 else 2534 component_del(i915->drm.dev, &i915_hdcp_ops); 2535} 2536 2537void intel_hdcp_cleanup(struct intel_connector *connector) 2538{ 2539 struct intel_hdcp *hdcp = &connector->hdcp; 2540 2541 if (!hdcp->shim) 2542 return; 2543 2544 /* 2545 * If the connector is registered, it's possible userspace could kick 2546 * off another HDCP enable, which would re-spawn the workers. 2547 */ 2548 drm_WARN_ON(connector->base.dev, 2549 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2550 2551 /* 2552 * Now that the connector is not registered, check_work won't be run, 2553 * but cancel any outstanding instances of it 2554 */ 2555 cancel_delayed_work_sync(&hdcp->check_work); 2556 2557 /* 2558 * We don't cancel prop_work in the same way as check_work since it 2559 * requires connection_mutex which could be held while calling this 2560 * function. Instead, we rely on the connector references grabbed before 2561 * scheduling prop_work to ensure the connector is alive when prop_work 2562 * is run. So if we're in the destroy path (which is where this 2563 * function should be called), we're "guaranteed" that prop_work is not 2564 * active (tl;dr This Should Never Happen). 2565 */ 2566 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2567 2568 mutex_lock(&hdcp->mutex); 2569 hdcp->shim = NULL; 2570 mutex_unlock(&hdcp->mutex); 2571} 2572 2573void intel_hdcp_atomic_check(struct drm_connector *connector, 2574 struct drm_connector_state *old_state, 2575 struct drm_connector_state *new_state) 2576{ 2577 u64 old_cp = old_state->content_protection; 2578 u64 new_cp = new_state->content_protection; 2579 struct drm_crtc_state *crtc_state; 2580 2581 if (!new_state->crtc) { 2582 /* 2583 * If the connector is being disabled with CP enabled, mark it 2584 * desired so it's re-enabled when the connector is brought back 2585 */ 2586 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2587 new_state->content_protection = 2588 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2589 return; 2590 } 2591 2592 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2593 new_state->crtc); 2594 /* 2595 * Fix the HDCP uapi content protection state in case of modeset. 2596 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2597 * need to be sent if there is transition from ENABLED->DESIRED. 2598 */ 2599 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2600 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2601 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2602 new_state->content_protection = 2603 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2604 2605 /* 2606 * Nothing to do if the state didn't change, or HDCP was activated since 2607 * the last commit. And also no change in hdcp content type. 2608 */ 2609 if (old_cp == new_cp || 2610 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2611 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2612 if (old_state->hdcp_content_type == 2613 new_state->hdcp_content_type) 2614 return; 2615 } 2616 2617 crtc_state->mode_changed = true; 2618} 2619 2620/* Handles the CP_IRQ raised from the DP HDCP sink */ 2621void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2622{ 2623 struct intel_hdcp *hdcp = &connector->hdcp; 2624 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2625 2626 if (!hdcp->shim) 2627 return; 2628 2629 atomic_inc(&connector->hdcp.cp_irq_count); 2630 wake_up_all(&connector->hdcp.cp_irq_queue); 2631 2632 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); 2633} 2634