Searched refs:high_part (Results 1 - 25 of 31) sorted by relevance

12

/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubp.c118 address->grph.meta_addr.high_part);
127 address->grph.addr.high_part);
147 address->video_progressive.chroma_meta_addr.high_part);
155 address->video_progressive.luma_meta_addr.high_part);
164 address->video_progressive.chroma_addr.high_part);
172 address->video_progressive.luma_addr.high_part);
198 address->grph_stereo.right_alpha_meta_addr.high_part);
206 address->grph_stereo.right_meta_addr.high_part);
216 address->grph_stereo.left_alpha_meta_addr.high_part);
224 address->grph_stereo.left_meta_addr.high_part);
[all...]
H A Ddcn30_mmhubbub.c83 REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
138 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
153 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
164 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
171 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
181 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
188 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
197 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
H A Ddmub_dcn20.c170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
179 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
207 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
222 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
234 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
241 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
251 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
258 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
267 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
H A Ddmub_dcn31.c166 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
175 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
198 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
207 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
216 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
223 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
232 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
H A Ddmub_dcn35.c184 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
193 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
212 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
219 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
240 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
249 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
258 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
265 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
274 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
283 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
[all...]
H A Ddmub_dcn32.c165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
174 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
195 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
204 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
227 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
236 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
245 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
252 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
261 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcompressor.h43 int32_t high_part; member in struct:fbc_physical_address::__anon2486
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c398 address->grph.meta_addr.high_part);
407 address->grph.addr.high_part);
427 address->video_progressive.chroma_meta_addr.high_part);
435 address->video_progressive.luma_meta_addr.high_part);
444 address->video_progressive.chroma_addr.high_part);
452 address->video_progressive.luma_addr.high_part);
478 address->grph_stereo.right_meta_addr.high_part);
488 address->grph_stereo.left_meta_addr.high_part);
497 address->grph_stereo.right_addr.high_part);
505 address->grph_stereo.left_addr.high_part);
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c718 address->grph.meta_addr.high_part;
724 address->grph.addr.high_part;
735 address->video_progressive.luma_meta_addr.high_part;
740 address->video_progressive.chroma_meta_addr.high_part;
746 address->video_progressive.luma_addr.high_part;
752 address->video_progressive.chroma_addr.high_part;
767 address->grph_stereo.right_meta_addr.high_part;
774 address->grph_stereo.left_meta_addr.high_part;
780 address->grph_stereo.left_addr.high_part;
785 address->grph_stereo.right_addr.high_part;
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubp.c65 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
603 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
623 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;
664 DMDATA_ADDRESS_HIGH, attr->address.high_part);
752 address->grph.meta_addr.high_part);
761 address->grph.addr.high_part);
781 address->video_progressive.chroma_meta_addr.high_part);
789 address->video_progressive.luma_meta_addr.high_part);
798 address->video_progressive.chroma_addr.high_part);
806 address->video_progressive.luma_addr.high_part);
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubp.c125 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
H A Ddcn32_mmhubbub.c83 REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h48 int32_t high_part; member in struct:large_integer::__anon211
53 int32_t high_part; member in struct:large_integer::__anon212
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_ipp.c128 CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part);
H A Ddce_mem_input.c803 address.high_part);
817 address.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c415 clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
435 smu_dpm_clks->mc_address.high_part);
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c347 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
793 address->grph.addr.high_part = upper_32_bits(addr);
817 address->video_progressive.luma_addr.high_part =
821 address->video_progressive.chroma_addr.high_part =
1268 attributes.address.high_part = upper_32_bits(address);
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c317 compressor->compr_surface_address.addr.high_part);
H A Ddce110_mem_input_v.c67 temp = address.high_part &
103 temp = address.high_part &
/linux-master/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c351 pipe_ctx->plane_state->address.grph.addr.high_part,
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c493 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
513 smu_dpm_clks->mc_address.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c445 clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
465 smu_dpm_clks->mc_address.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c558 clk_mgr_dcn314->smu_wm_set.mc_address.high_part);
578 smu_dpm_clks->mc_address.high_part);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c459 clk_mgr_vgh->smu_wm_set.mc_address.high_part);
654 smu_dpm_clks->mc_address.high_part);

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