1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "../dmub_srv.h" 27#include "dmub_reg.h" 28#include "dmub_dcn32.h" 29#include "dc/dc_types.h" 30#include "dc_hw_types.h" 31 32#include "dcn/dcn_3_2_0_offset.h" 33#include "dcn/dcn_3_2_0_sh_mask.h" 34 35#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 36#define CTX dmub 37#define REGS dmub->regs_dcn32 38#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 39 40void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) 41{ 42 struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32; 43 44#define REG_STRUCT regs 45 46#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); 47 DMUB_DCN32_REGS() 48 DMCUB_INTERNAL_REGS() 49#undef DMUB_SR 50 51#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); 52 DMUB_DCN32_FIELDS() 53#undef DMUB_SF 54 55#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); 56 DMUB_DCN32_FIELDS() 57#undef DMUB_SF 58 59#undef REG_STRUCT 60} 61 62static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub, 63 uint64_t *fb_base, 64 uint64_t *fb_offset) 65{ 66 uint32_t tmp; 67 68 if (dmub->fb_base || dmub->fb_offset) { 69 *fb_base = dmub->fb_base; 70 *fb_offset = dmub->fb_offset; 71 return; 72 } 73 74 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 75 *fb_base = (uint64_t)tmp << 24; 76 77 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 78 *fb_offset = (uint64_t)tmp << 24; 79} 80 81static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in, 82 uint64_t fb_base, 83 uint64_t fb_offset, 84 union dmub_addr *addr_out) 85{ 86 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 87} 88 89void dmub_dcn32_reset(struct dmub_srv *dmub) 90{ 91 union dmub_gpint_data_register cmd; 92 const uint32_t timeout = 30; 93 uint32_t in_reset, scratch, i; 94 95 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 96 97 if (in_reset == 0) { 98 cmd.bits.status = 1; 99 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 100 cmd.bits.param = 0; 101 102 dmub->hw_funcs.set_gpint(dmub, cmd); 103 104 /** 105 * Timeout covers both the ACK and the wait 106 * for remaining work to finish. 107 * 108 * This is mostly bound by the PHY disable sequence. 109 * Each register check will be greater than 1us, so 110 * don't bother using udelay. 111 */ 112 113 for (i = 0; i < timeout; ++i) { 114 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 115 break; 116 } 117 118 for (i = 0; i < timeout; ++i) { 119 scratch = dmub->hw_funcs.get_gpint_response(dmub); 120 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 121 break; 122 } 123 124 /* Force reset in case we timed out, DMCUB is likely hung. */ 125 } 126 127 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 128 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 129 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 130 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 131 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 132 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 133 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 134 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 135 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 136 REG_WRITE(DMCUB_SCRATCH0, 0); 137 138 /* Clear the GPINT command manually so we don't reset again. */ 139 cmd.all = 0; 140 dmub->hw_funcs.set_gpint(dmub, cmd); 141} 142 143void dmub_dcn32_reset_release(struct dmub_srv *dmub) 144{ 145 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 146 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 147 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 148 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 149} 150 151void dmub_dcn32_backdoor_load(struct dmub_srv *dmub, 152 const struct dmub_window *cw0, 153 const struct dmub_window *cw1) 154{ 155 union dmub_addr offset; 156 uint64_t fb_base, fb_offset; 157 158 dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); 159 160 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 161 162 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 163 164 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 166 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 167 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 168 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 169 DMCUB_REGION3_CW0_ENABLE, 1); 170 171 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 172 173 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 174 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 175 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 176 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 177 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 178 DMCUB_REGION3_CW1_ENABLE, 1); 179 180 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 181 0x20); 182} 183 184void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, 185 const struct dmub_window *cw0, 186 const struct dmub_window *cw1) 187{ 188 union dmub_addr offset; 189 190 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 191 192 offset = cw0->offset; 193 194 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 195 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 196 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 197 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 198 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 199 DMCUB_REGION3_CW0_ENABLE, 1); 200 201 offset = cw1->offset; 202 203 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 204 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 205 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 206 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 207 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 208 DMCUB_REGION3_CW1_ENABLE, 1); 209 210 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 211 0x20); 212} 213 214void dmub_dcn32_setup_windows(struct dmub_srv *dmub, 215 const struct dmub_window *cw2, 216 const struct dmub_window *cw3, 217 const struct dmub_window *cw4, 218 const struct dmub_window *cw5, 219 const struct dmub_window *cw6, 220 const struct dmub_window *region6) 221{ 222 union dmub_addr offset; 223 224 offset = cw3->offset; 225 226 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 227 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 228 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 229 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 230 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 231 DMCUB_REGION3_CW3_ENABLE, 1); 232 233 offset = cw4->offset; 234 235 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 236 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 237 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 238 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 239 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 240 DMCUB_REGION3_CW4_ENABLE, 1); 241 242 offset = cw5->offset; 243 244 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 245 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 246 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 247 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 248 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 249 DMCUB_REGION3_CW5_ENABLE, 1); 250 251 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 252 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 253 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 254 DMCUB_REGION5_TOP_ADDRESS, 255 cw5->region.top - cw5->region.base - 1, 256 DMCUB_REGION5_ENABLE, 1); 257 258 offset = cw6->offset; 259 260 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 261 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 262 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 263 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 264 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 265 DMCUB_REGION3_CW6_ENABLE, 1); 266} 267 268void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, 269 const struct dmub_region *inbox1) 270{ 271 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 272 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 273} 274 275uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub) 276{ 277 return REG_READ(DMCUB_INBOX1_WPTR); 278} 279 280uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub) 281{ 282 return REG_READ(DMCUB_INBOX1_RPTR); 283} 284 285void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 286{ 287 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 288} 289 290void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub, 291 const struct dmub_region *outbox1) 292{ 293 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 294 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 295} 296 297uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub) 298{ 299 /** 300 * outbox1 wptr register is accessed without locks (dal & dc) 301 * and to be called only by dmub_srv_stat_get_notification() 302 */ 303 return REG_READ(DMCUB_OUTBOX1_WPTR); 304} 305 306void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 307{ 308 /** 309 * outbox1 rptr register is accessed without locks (dal & dc) 310 * and to be called only by dmub_srv_stat_get_notification() 311 */ 312 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 313} 314 315bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub) 316{ 317 union dmub_fw_boot_status status; 318 uint32_t is_hw_init; 319 320 status.all = REG_READ(DMCUB_SCRATCH0); 321 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); 322 323 return is_hw_init != 0 && status.bits.dal_fw; 324} 325 326bool dmub_dcn32_is_supported(struct dmub_srv *dmub) 327{ 328 uint32_t supported = 0; 329 330 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 331 332 return supported; 333} 334 335void dmub_dcn32_set_gpint(struct dmub_srv *dmub, 336 union dmub_gpint_data_register reg) 337{ 338 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 339} 340 341bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub, 342 union dmub_gpint_data_register reg) 343{ 344 union dmub_gpint_data_register test; 345 346 reg.bits.status = 0; 347 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 348 349 return test.all == reg.all; 350} 351 352uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub) 353{ 354 return REG_READ(DMCUB_SCRATCH7); 355} 356 357uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub) 358{ 359 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 360 361 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 362 363 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 364 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 365 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 366 367 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 368 369 return dataout; 370} 371 372union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub) 373{ 374 union dmub_fw_boot_status status; 375 376 status.all = REG_READ(DMCUB_SCRATCH0); 377 return status; 378} 379 380void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 381{ 382 union dmub_fw_boot_options boot_options = {0}; 383 384 boot_options.bits.z10_disable = params->disable_z10; 385 386 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 387} 388 389void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 390{ 391 union dmub_fw_boot_options boot_options; 392 boot_options.all = REG_READ(DMCUB_SCRATCH14); 393 boot_options.bits.skip_phy_init_panel_sequence = skip; 394 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 395} 396 397void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub, 398 const struct dmub_region *outbox0) 399{ 400 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 401 402 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 403} 404 405uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub) 406{ 407 return REG_READ(DMCUB_OUTBOX0_WPTR); 408} 409 410void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 411{ 412 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 413} 414 415uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub) 416{ 417 return REG_READ(DMCUB_TIMER_CURRENT); 418} 419 420void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 421{ 422 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 423 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 424 425 if (!dmub || !diag_data) 426 return; 427 428 memset(diag_data, 0, sizeof(*diag_data)); 429 430 diag_data->dmcub_version = dmub->fw_version; 431 432 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 433 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 434 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 435 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 436 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 437 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 438 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 439 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 440 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 441 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 442 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 443 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 444 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 445 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 446 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 447 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 448 diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16); 449 450 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 451 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 452 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 453 454 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 455 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 456 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 457 458 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 459 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 460 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 461 462 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 463 diag_data->is_dmcub_enabled = is_dmub_enabled; 464 465 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 466 diag_data->is_dmcub_soft_reset = is_soft_reset; 467 468 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 469 diag_data->is_dmcub_secure_reset = is_sec_reset; 470 471 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 472 diag_data->is_traceport_en = is_traceport_enabled; 473 474 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 475 diag_data->is_cw0_enabled = is_cw0_enabled; 476 477 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 478 diag_data->is_cw6_enabled = is_cw6_enabled; 479 480 diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 481} 482void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub) 483{ 484 /* DMCUB_REGION3_TMR_AXI_SPACE values: 485 * 0b011 (0x3) - FB physical address 486 * 0b100 (0x4) - GPU virtual address 487 * 488 * Default value is 0x3 (FB Physical address for TMR). When programming 489 * DMUB to be in system memory, change to 0x4. The system memory allocated 490 * is accessible by both GPU and CPU, so we use GPU virtual address. 491 */ 492 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); 493} 494 495void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) 496{ 497 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); 498} 499 500void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub) 501{ 502 REG_WRITE(DMCUB_SCRATCH17, 0); 503} 504 505uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub) 506{ 507 return REG_READ(DMCUB_SCRATCH17); 508} 509 510void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 511{ 512 uint32_t index = 0; 513 514 if (subvp_index == 0) { 515 index = REG_READ(DMCUB_SCRATCH15); 516 if (index) { 517 REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part); 518 REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part); 519 } else { 520 REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part); 521 REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part); 522 } 523 REG_WRITE(DMCUB_SCRATCH15, !index); 524 } else if (subvp_index == 1) { 525 index = REG_READ(DMCUB_SCRATCH23); 526 if (index) { 527 REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part); 528 REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part); 529 } else { 530 REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part); 531 REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part); 532 } 533 REG_WRITE(DMCUB_SCRATCH23, !index); 534 } else { 535 return; 536 } 537} 538