Searched refs:event_base (Results 1 - 25 of 32) sorted by relevance

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/linux-master/drivers/clocksource/
H A Dtimer-qcom.c34 static void __iomem *event_base; variable
42 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
44 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
56 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
58 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
73 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
75 writel_relaxed(ctrl, event_base
[all...]
/linux-master/arch/x86/events/
H A Dmsr.c223 event->hw.event_base = msr[cfg].msr;
233 if (event->hw.event_base)
234 rdmsrl(event->hw.event_base, now);
253 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
256 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
H A Drapl.c156 rdmsrl(event->hw.event_base, raw);
184 rdmsrl(event->hw.event_base, new_raw_count);
364 event->hw.event_base = rapl_msrs[bit].msr;
H A Dcore.c122 if (unlikely(!hwc->event_base))
1228 hwc->event_base = 0;
1237 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1245 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1372 if (unlikely(!hwc->event_base))
1410 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
/linux-master/arch/s390/include/asm/
H A Dpai.h84 #define PAI_SAVE_AREA(x) ((x)->hw.event_base)
H A Dperf_event.h70 #define SAMPL_RATE(hwc) ((hwc)->event_base)
/linux-master/drivers/perf/
H A Dthunderx2_pmu.c334 hwc->event_base = (unsigned long)tx2_pmu->base
350 hwc->event_base = (unsigned long)tx2_pmu->base
364 hwc->event_base = (unsigned long)tx2_pmu->base;
380 reg_writel(0, hwc->event_base);
410 reg_writel(0, hwc->event_base);
451 hwc->event_base + CCPI2_PERF_CTL);
460 reg_writel(0, hwc->event_base + CCPI2_PERF_CTL);
480 hwc->event_base + CCPI2_COUNTER_SEL);
481 new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H);
483 reg_readl(hwc->event_base
[all...]
H A Driscv_pmu_sbi.c394 cmask, cflags, hwc->event_base, hwc->config,
398 cmask, cflags, hwc->event_base, hwc->config, 0);
402 hwc->event_base, hwc->config);
H A Darm-ccn.c902 dt_cfg = hw->event_base;
956 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
999 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1022 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
H A Driscv_pmu.c336 hwc->event_base = mapped_event;
H A Dcxl_pmu.c661 hwc->event_base);
754 hwc->event_base = event_idx;
/linux-master/arch/alpha/kernel/
H A Dperf_event.c351 evtype[n] = group->hw.event_base;
359 evtype[n] = pe->hw.event_base;
459 cpuc->evtype[n0] = event->hw.event_base;
634 * We place the event type in event_base here and leave calculation
642 hwc->event_base = ev;
656 evtypes[n] = hwc->event_base;
/linux-master/arch/x86/events/intel/
H A Dcstate.c338 event->hw.event_base = core_msr[cfg].msr;
350 event->hw.event_base = pkg_msr[cfg].msr;
359 event->hw.event_base = module_msr[cfg].msr;
379 rdmsrl(event->hw.event_base, val);
H A Duncore.c152 rdmsrl(event->hw.event_base, count);
169 if (!uncore_mmio_is_valid_offset(box, event->hw.event_base))
172 return readq(box->io_addr + event->hw.event_base);
261 hwc->event_base = uncore_fixed_ctr(box);
267 hwc->event_base = uncore_perf_ctr(box, hwc->idx);
794 event->hw.event_base = uncore_freerunning_counter(box, event);
H A Duncore_discovery.c459 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
460 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
H A Dp4.c874 rdmsrl(hwc->event_base, v);
1017 if (hwc->event_base) {
1026 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
/linux-master/arch/loongarch/kernel/
H A Dperf_event.c274 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base) |
558 event->hw.event_base = 0xffffffff;
782 hwc->event_base = loongarch_pmu_perf_event_encode(pev);
/linux-master/drivers/fpga/
H A Ddfl-fme-perf.c788 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base);
826 hwc->event_base = evtype;
844 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base);
858 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base);
/linux-master/arch/x86/events/amd/
H A Duncore.c109 rdmsrl(hwc->event_base, new);
124 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
176 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx);
876 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
/linux-master/drivers/perf/hisilicon/
H A Dhisi_pcie_pmu.c374 hwc->event_base = HISI_PCIE_EXT_CNT;
376 hwc->event_base = HISI_PCIE_CNT;
398 return hisi_pcie_pmu_readq(pcie_pmu, event->hw.event_base, idx);
520 hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt);
/linux-master/arch/mips/kernel/
H A Dperf_event_mipsxx.c325 cntr_mask = (hwc->event_base >> 10) & 0xffff;
327 cntr_mask = (hwc->event_base >> 8) & 0xffff;
352 unsigned int range = evt->event_base >> 24;
357 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) |
362 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
440 M_PERFCTL_EVENT(hwc->event_base & 0x3ff));
1506 hwc->event_base = mipspmu_perf_event_encode(pev);
/linux-master/arch/sparc/kernel/
H A Dperf_event.c1356 events[n] = group->hw.event_base;
1365 events[n] = event->hw.event_base;
1385 cpuc->events[n0] = event->hw.event_base;
1455 hwc->event_base = perf_event_encode(pmap);
1461 hwc->event_base = attr->config;
1481 events[n] = hwc->event_base;
/linux-master/drivers/dma/idxd/
H A Dperfmon.c131 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx));
219 event->hw.event_base = ioread64(PERFMON_TABLE_OFFSET(idxd));
/linux-master/arch/powerpc/perf/
H A Dimc-pmu.c562 event->hw.event_base = (u64)pcni->vbase + l_config;
894 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
1043 return (__be64 *)event->hw.event_base;
H A Dcore-book3s.c1604 flags[n] = group->hw.event_base;
1613 flags[n] = event->hw.event_base;
1646 cpuhw->flags[n0] = event->hw.event_base;
2166 event->hw.event_base = cflags[n];

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