Searched refs:dppclk (Results 1 - 10 of 10) sorted by relevance
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | clk_mgr.h | 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 58 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 68 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 78 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 87 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 94 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass 179 uint32_t dppclk; member in struct:clk_state_registers_and_bypass 202 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk 209 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calc_auto.c | 320 /*maximum dispclk/dppclk support check*/ 1179 /*dispclk and dppclk calculation*/ 1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; 1300 v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; 1312 v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; 1423 v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); 1426 v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); 1643 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; 1654 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); 1655 v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk [all...] |
H A D | dcn_calcs.c | 145 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/ 146 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/ 147 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/ 148 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/ 496 input->clks_cfg.dppclk_mhz = v->dppclk; 1061 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */ 1651 "max_dchub_topscl_throughput: %d pixels/dppclk\n" 1652 "max_pscl_tolb_throughput: %d pixels/dppclk\n" 1653 "max_lb_tovscl_throughput: %d pixels/dppclk\n" 1654 "max_vscl_tohscl_throughput: %d pixels/dppclk\ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | dcn_calcs.h | 436 float dppclk; member in struct:dcn_bw_internal_vars 604 int max_dchub_topscl_throughput; /*pixels/dppclk*/ 605 int max_pscl_tolb_throughput; /*pixels/dppclk*/ 606 int max_lb_tovscl_throughput; /*pixels/dppclk*/ 607 int max_vscl_tohscl_throughput; /*pixels/dppclk*/
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H A D | core_types.h | 370 uint32_t dppclk : 1; member in struct:pipe_update_flags::__anon231
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 153 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 172 // increase per DPP DTO before lowering global dppclk 252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 338 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 185 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 186 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result 214 // increase per DPP DTO before lowering global dppclk with requested dppclk 320 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 406 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 590 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - " 768 * SMU uses discrete dppclk presets. We applied 771 * contract, we should use the preset dppclk 807 * SMU uses discrete dppclk presets. We applied 810 * contract, we should use the preset dppclk 821 * compare the current and new dppclk before calling this function. 904 //Get dppclk in khz 905 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.c | 1513 new_pipe->update_flags.bits.dppclk = 1; 1591 /* Detect dppclk change */ 1593 new_pipe->update_flags.bits.dppclk = 1; 1679 if (pipe_ctx->update_flags.bits.dppclk)
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
H A D | dcn32_hwseq.c | 1374 phantom_pipe->update_flags.bits.dppclk = 1;
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