1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26/** 27 * Bandwidth and Watermark calculations interface. 28 * (Refer to "DCEx_mode_support.xlsm" from Perforce.) 29 */ 30#ifndef __DCN_CALCS_H__ 31#define __DCN_CALCS_H__ 32 33#include "bw_fixed.h" 34#include "../dml/display_mode_lib.h" 35 36 37struct dc; 38struct dc_state; 39 40/******************************************************************************* 41 * DCN data structures. 42 ******************************************************************************/ 43 44#define number_of_planes 6 45#define number_of_planes_minus_one 5 46#define number_of_states 4 47#define number_of_states_plus_one 5 48 49#define ddr4_dram_width 64 50#define ddr4_dram_factor_single_Channel 16 51enum dcn_bw_defs { 52 dcn_bw_v_min0p65, 53 dcn_bw_v_mid0p72, 54 dcn_bw_v_nom0p8, 55 dcn_bw_v_max0p9, 56 dcn_bw_v_max0p91, 57 dcn_bw_no_support = 5, 58 dcn_bw_yes, 59 dcn_bw_hor, 60 dcn_bw_vert, 61 dcn_bw_override, 62 dcn_bw_rgb_sub_64, 63 dcn_bw_rgb_sub_32, 64 dcn_bw_rgb_sub_16, 65 dcn_bw_no, 66 dcn_bw_sw_linear, 67 dcn_bw_sw_4_kb_d, 68 dcn_bw_sw_4_kb_d_x, 69 dcn_bw_sw_64_kb_d, 70 dcn_bw_sw_64_kb_d_t, 71 dcn_bw_sw_64_kb_d_x, 72 dcn_bw_sw_var_d, 73 dcn_bw_sw_var_d_x, 74 dcn_bw_yuv420_sub_8, 75 dcn_bw_sw_4_kb_s, 76 dcn_bw_sw_4_kb_s_x, 77 dcn_bw_sw_64_kb_s, 78 dcn_bw_sw_64_kb_s_t, 79 dcn_bw_sw_64_kb_s_x, 80 dcn_bw_writeback, 81 dcn_bw_444, 82 dcn_bw_dp, 83 dcn_bw_420, 84 dcn_bw_hdmi, 85 dcn_bw_sw_var_s, 86 dcn_bw_sw_var_s_x, 87 dcn_bw_yuv420_sub_10, 88 dcn_bw_supported_in_v_active, 89 dcn_bw_supported_in_v_blank, 90 dcn_bw_not_supported, 91 dcn_bw_na, 92 dcn_bw_encoder_8bpc, 93 dcn_bw_encoder_10bpc, 94 dcn_bw_encoder_12bpc, 95 dcn_bw_encoder_16bpc, 96}; 97 98/*bounding box parameters*/ 99/*mode parameters*/ 100/*system configuration*/ 101/* display configuration*/ 102struct dcn_bw_internal_vars { 103 float voltage[number_of_states_plus_one + 1]; 104 float max_dispclk[number_of_states_plus_one + 1]; 105 float max_dppclk[number_of_states_plus_one + 1]; 106 float dcfclk_per_state[number_of_states_plus_one + 1]; 107 float phyclk_per_state[number_of_states_plus_one + 1]; 108 float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1]; 109 float sr_exit_time; 110 float sr_enter_plus_exit_time; 111 float dram_clock_change_latency; 112 float urgent_latency; 113 float write_back_latency; 114 float percent_of_ideal_drambw_received_after_urg_latency; 115 float dcfclkv_max0p9; 116 float dcfclkv_nom0p8; 117 float dcfclkv_mid0p72; 118 float dcfclkv_min0p65; 119 float max_dispclk_vmax0p9; 120 float max_dppclk_vmax0p9; 121 float max_dispclk_vnom0p8; 122 float max_dppclk_vnom0p8; 123 float max_dispclk_vmid0p72; 124 float max_dppclk_vmid0p72; 125 float max_dispclk_vmin0p65; 126 float max_dppclk_vmin0p65; 127 float socclk; 128 float fabric_and_dram_bandwidth_vmax0p9; 129 float fabric_and_dram_bandwidth_vnom0p8; 130 float fabric_and_dram_bandwidth_vmid0p72; 131 float fabric_and_dram_bandwidth_vmin0p65; 132 float round_trip_ping_latency_cycles; 133 float urgent_out_of_order_return_per_channel; 134 float number_of_channels; 135 float vmm_page_size; 136 float return_bus_width; 137 float rob_buffer_size_in_kbyte; 138 float det_buffer_size_in_kbyte; 139 float dpp_output_buffer_pixels; 140 float opp_output_buffer_lines; 141 float pixel_chunk_size_in_kbyte; 142 float pte_chunk_size; 143 float meta_chunk_size; 144 float writeback_chunk_size; 145 enum dcn_bw_defs odm_capability; 146 enum dcn_bw_defs dsc_capability; 147 float line_buffer_size; 148 enum dcn_bw_defs is_line_buffer_bpp_fixed; 149 float line_buffer_fixed_bpp; 150 float max_line_buffer_lines; 151 float writeback_luma_buffer_size; 152 float writeback_chroma_buffer_size; 153 float max_num_dpp; 154 float max_num_writeback; 155 float max_dchub_topscl_throughput; 156 float max_pscl_tolb_throughput; 157 float max_lb_tovscl_throughput; 158 float max_vscl_tohscl_throughput; 159 float max_hscl_ratio; 160 float max_vscl_ratio; 161 float max_hscl_taps; 162 float max_vscl_taps; 163 float under_scan_factor; 164 float phyclkv_max0p9; 165 float phyclkv_nom0p8; 166 float phyclkv_mid0p72; 167 float phyclkv_min0p65; 168 float pte_buffer_size_in_requests; 169 float dispclk_ramping_margin; 170 float downspreading; 171 float max_inter_dcn_tile_repeaters; 172 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 173 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 174 int mode; 175 float viewport_width[number_of_planes_minus_one + 1]; 176 float htotal[number_of_planes_minus_one + 1]; 177 float vtotal[number_of_planes_minus_one + 1]; 178 float v_sync_plus_back_porch[number_of_planes_minus_one + 1]; 179 float vactive[number_of_planes_minus_one + 1]; 180 float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/ 181 float viewport_height[number_of_planes_minus_one + 1]; 182 enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1]; 183 float dcc_rate[number_of_planes_minus_one + 1]; 184 enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1]; 185 float lb_bit_per_pixel[number_of_planes_minus_one + 1]; 186 enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1]; 187 enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1]; 188 enum dcn_bw_defs output_format[number_of_planes_minus_one + 1]; 189 enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1]; 190 enum dcn_bw_defs output[number_of_planes_minus_one + 1]; 191 float scaler_rec_out_width[number_of_planes_minus_one + 1]; 192 float scaler_recout_height[number_of_planes_minus_one + 1]; 193 float underscan_output[number_of_planes_minus_one + 1]; 194 float interlace_output[number_of_planes_minus_one + 1]; 195 float override_hta_ps[number_of_planes_minus_one + 1]; 196 float override_vta_ps[number_of_planes_minus_one + 1]; 197 float override_hta_pschroma[number_of_planes_minus_one + 1]; 198 float override_vta_pschroma[number_of_planes_minus_one + 1]; 199 float urgent_latency_support_us[number_of_planes_minus_one + 1]; 200 float h_ratio[number_of_planes_minus_one + 1]; 201 float v_ratio[number_of_planes_minus_one + 1]; 202 float htaps[number_of_planes_minus_one + 1]; 203 float vtaps[number_of_planes_minus_one + 1]; 204 float hta_pschroma[number_of_planes_minus_one + 1]; 205 float vta_pschroma[number_of_planes_minus_one + 1]; 206 enum dcn_bw_defs pte_enable; 207 enum dcn_bw_defs synchronized_vblank; 208 enum dcn_bw_defs ta_pscalculation; 209 int voltage_override_level; 210 int number_of_active_planes; 211 int voltage_level; 212 enum dcn_bw_defs immediate_flip_supported; 213 float dcfclk; 214 float max_phyclk; 215 float fabric_and_dram_bandwidth; 216 float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1]; 217 enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1]; 218 float required_dispclk_per_ratio[1 + 1]; 219 enum dcn_bw_defs error_message[1 + 1]; 220 int dispclk_dppclk_ratio; 221 float dpp_per_plane[number_of_planes_minus_one + 1]; 222 float det_buffer_size_y[number_of_planes_minus_one + 1]; 223 float det_buffer_size_c[number_of_planes_minus_one + 1]; 224 float swath_height_y[number_of_planes_minus_one + 1]; 225 float swath_height_c[number_of_planes_minus_one + 1]; 226 enum dcn_bw_defs final_error_message; 227 float frequency; 228 float header_line; 229 float header; 230 enum dcn_bw_defs voltage_override; 231 enum dcn_bw_defs allow_different_hratio_vratio; 232 float acceptable_quality_hta_ps; 233 float acceptable_quality_vta_ps; 234 float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 235 float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 236 float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 237 float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 238 float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 239 float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 240 float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 241 float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 242 float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 243 float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 244 float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 245 enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 246 enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 247 enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 248 enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 249 float required_dispclk[number_of_states_plus_one + 1][1 + 1]; 250 enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1]; 251 enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1]; 252 float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1]; 253 float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1]; 254 enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1]; 255 enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 256 enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 257 float return_bw_per_state[number_of_states_plus_one + 1]; 258 enum dcn_bw_defs dio_support[number_of_states_plus_one + 1]; 259 float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1]; 260 enum dcn_bw_defs rob_support[number_of_states_plus_one + 1]; 261 enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1]; 262 float prefetch_bw[number_of_planes_minus_one + 1]; 263 float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1]; 264 float meta_row_bytes[number_of_planes_minus_one + 1]; 265 float dpte_bytes_per_row[number_of_planes_minus_one + 1]; 266 float prefetch_lines_y[number_of_planes_minus_one + 1]; 267 float prefetch_lines_c[number_of_planes_minus_one + 1]; 268 float max_num_sw_y[number_of_planes_minus_one + 1]; 269 float max_num_sw_c[number_of_planes_minus_one + 1]; 270 float line_times_for_prefetch[number_of_planes_minus_one + 1]; 271 float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1]; 272 float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1]; 273 float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1]; 274 float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1]; 275 float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1]; 276 float swath_width_ysingle_dpp[number_of_planes_minus_one + 1]; 277 float byte_per_pixel_in_dety[number_of_planes_minus_one + 1]; 278 float byte_per_pixel_in_detc[number_of_planes_minus_one + 1]; 279 float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1]; 280 float required_phyclk[number_of_planes_minus_one + 1]; 281 float read256_block_height_y[number_of_planes_minus_one + 1]; 282 float read256_block_width_y[number_of_planes_minus_one + 1]; 283 float read256_block_height_c[number_of_planes_minus_one + 1]; 284 float read256_block_width_c[number_of_planes_minus_one + 1]; 285 float max_swath_height_y[number_of_planes_minus_one + 1]; 286 float max_swath_height_c[number_of_planes_minus_one + 1]; 287 float min_swath_height_y[number_of_planes_minus_one + 1]; 288 float min_swath_height_c[number_of_planes_minus_one + 1]; 289 float read_bandwidth[number_of_planes_minus_one + 1]; 290 float write_bandwidth[number_of_planes_minus_one + 1]; 291 float pscl_factor[number_of_planes_minus_one + 1]; 292 float pscl_factor_chroma[number_of_planes_minus_one + 1]; 293 enum dcn_bw_defs scale_ratio_support; 294 enum dcn_bw_defs source_format_pixel_and_scan_support; 295 float total_read_bandwidth_consumed_gbyte_per_second; 296 float total_write_bandwidth_consumed_gbyte_per_second; 297 float total_bandwidth_consumed_gbyte_per_second; 298 enum dcn_bw_defs dcc_enabled_in_any_plane; 299 float return_bw_todcn_per_state; 300 float critical_point; 301 enum dcn_bw_defs writeback_latency_support; 302 float required_output_bw; 303 float total_number_of_active_writeback; 304 enum dcn_bw_defs total_available_writeback_support; 305 float maximum_swath_width; 306 float number_of_dpp_required_for_det_size; 307 float number_of_dpp_required_for_lb_size; 308 float min_dispclk_using_single_dpp; 309 float min_dispclk_using_dual_dpp; 310 enum dcn_bw_defs viewport_size_support; 311 float swath_width_granularity_y; 312 float rounded_up_max_swath_size_bytes_y; 313 float swath_width_granularity_c; 314 float rounded_up_max_swath_size_bytes_c; 315 float lines_in_det_luma; 316 float lines_in_det_chroma; 317 float effective_lb_latency_hiding_source_lines_luma; 318 float effective_lb_latency_hiding_source_lines_chroma; 319 float effective_detlb_lines_luma; 320 float effective_detlb_lines_chroma; 321 float projected_dcfclk_deep_sleep; 322 float meta_req_height_y; 323 float meta_req_width_y; 324 float meta_surface_width_y; 325 float meta_surface_height_y; 326 float meta_pte_bytes_per_frame_y; 327 float meta_row_bytes_y; 328 float macro_tile_block_size_bytes_y; 329 float macro_tile_block_height_y; 330 float data_pte_req_height_y; 331 float data_pte_req_width_y; 332 float dpte_bytes_per_row_y; 333 float meta_req_height_c; 334 float meta_req_width_c; 335 float meta_surface_width_c; 336 float meta_surface_height_c; 337 float meta_pte_bytes_per_frame_c; 338 float meta_row_bytes_c; 339 float macro_tile_block_size_bytes_c; 340 float macro_tile_block_height_c; 341 float macro_tile_block_width_c; 342 float data_pte_req_height_c; 343 float data_pte_req_width_c; 344 float dpte_bytes_per_row_c; 345 float v_init_y; 346 float max_partial_sw_y; 347 float v_init_c; 348 float max_partial_sw_c; 349 float dst_x_after_scaler; 350 float dst_y_after_scaler; 351 float time_calc; 352 float v_update_offset[number_of_planes_minus_one + 1][2]; 353 float total_repeater_delay; 354 float v_update_width[number_of_planes_minus_one + 1][2]; 355 float v_ready_offset[number_of_planes_minus_one + 1][2]; 356 float time_setup; 357 float extra_latency; 358 float maximum_vstartup; 359 float bw_available_for_immediate_flip; 360 float total_immediate_flip_bytes[number_of_planes_minus_one + 1]; 361 float time_for_meta_pte_with_immediate_flip; 362 float time_for_meta_pte_without_immediate_flip; 363 float time_for_meta_and_dpte_row_with_immediate_flip; 364 float time_for_meta_and_dpte_row_without_immediate_flip; 365 float line_times_to_request_prefetch_pixel_data_with_immediate_flip; 366 float line_times_to_request_prefetch_pixel_data_without_immediate_flip; 367 float maximum_read_bandwidth_with_prefetch_with_immediate_flip; 368 float maximum_read_bandwidth_with_prefetch_without_immediate_flip; 369 float voltage_level_with_immediate_flip; 370 float voltage_level_without_immediate_flip; 371 float total_number_of_active_dpp_per_ratio[1 + 1]; 372 float byte_per_pix_dety; 373 float byte_per_pix_detc; 374 float read256_bytes_block_height_y; 375 float read256_bytes_block_width_y; 376 float read256_bytes_block_height_c; 377 float read256_bytes_block_width_c; 378 float maximum_swath_height_y; 379 float maximum_swath_height_c; 380 float minimum_swath_height_y; 381 float minimum_swath_height_c; 382 float swath_width; 383 float prefetch_bandwidth[number_of_planes_minus_one + 1]; 384 float v_init_pre_fill_y[number_of_planes_minus_one + 1]; 385 float v_init_pre_fill_c[number_of_planes_minus_one + 1]; 386 float max_num_swath_y[number_of_planes_minus_one + 1]; 387 float max_num_swath_c[number_of_planes_minus_one + 1]; 388 float prefill_y[number_of_planes_minus_one + 1]; 389 float prefill_c[number_of_planes_minus_one + 1]; 390 float v_startup[number_of_planes_minus_one + 1]; 391 enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1]; 392 float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1]; 393 float v_ratio_prefetch_y[number_of_planes_minus_one + 1]; 394 float v_ratio_prefetch_c[number_of_planes_minus_one + 1]; 395 float destination_lines_for_prefetch[number_of_planes_minus_one + 1]; 396 float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1]; 397 float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1]; 398 float min_ttuv_blank[number_of_planes_minus_one + 1]; 399 float byte_per_pixel_dety[number_of_planes_minus_one + 1]; 400 float byte_per_pixel_detc[number_of_planes_minus_one + 1]; 401 float swath_width_y[number_of_planes_minus_one + 1]; 402 float lines_in_dety[number_of_planes_minus_one + 1]; 403 float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1]; 404 float lines_in_detc[number_of_planes_minus_one + 1]; 405 float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1]; 406 float full_det_buffering_time_y[number_of_planes_minus_one + 1]; 407 float full_det_buffering_time_c[number_of_planes_minus_one + 1]; 408 float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 409 float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 410 float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1]; 411 float read_bandwidth_plane_luma[number_of_planes_minus_one + 1]; 412 float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1]; 413 float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1]; 414 float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1]; 415 float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1]; 416 float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1]; 417 float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1]; 418 float meta_pte_bytes_frame[number_of_planes_minus_one + 1]; 419 float meta_row_byte[number_of_planes_minus_one + 1]; 420 float prefetch_source_lines_y[number_of_planes_minus_one + 1]; 421 float prefetch_source_lines_c[number_of_planes_minus_one + 1]; 422 float pscl_throughput[number_of_planes_minus_one + 1]; 423 float pscl_throughput_chroma[number_of_planes_minus_one + 1]; 424 float output_bpphdmi[number_of_planes_minus_one + 1]; 425 float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1]; 426 float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1]; 427 float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1]; 428 float max_vstartup_lines[number_of_planes_minus_one + 1]; 429 float dispclk_with_ramping; 430 float dispclk_without_ramping; 431 float dppclk_using_single_dpp_luma; 432 float dppclk_using_single_dpp; 433 float dppclk_using_single_dpp_chroma; 434 enum dcn_bw_defs odm_capable; 435 float dispclk; 436 float dppclk; 437 float return_bandwidth_to_dcn; 438 enum dcn_bw_defs dcc_enabled_any_plane; 439 float return_bw; 440 float critical_compression; 441 float total_data_read_bandwidth; 442 float total_active_dpp; 443 float total_dcc_active_dpp; 444 float urgent_round_trip_and_out_of_order_latency; 445 float last_pixel_of_line_extra_watermark; 446 float data_fabric_line_delivery_time_luma; 447 float data_fabric_line_delivery_time_chroma; 448 float urgent_extra_latency; 449 float urgent_watermark; 450 float ptemeta_urgent_watermark; 451 float dram_clock_change_watermark; 452 float total_active_writeback; 453 float writeback_dram_clock_change_watermark; 454 float min_full_det_buffering_time; 455 float frame_time_for_min_full_det_buffering_time; 456 float average_read_bandwidth_gbyte_per_second; 457 float part_of_burst_that_fits_in_rob; 458 float stutter_burst_time; 459 float stutter_efficiency_not_including_vblank; 460 float smallest_vblank; 461 float v_blank_time; 462 float stutter_efficiency; 463 float dcf_clk_deep_sleep; 464 float stutter_exit_watermark; 465 float stutter_enter_plus_exit_watermark; 466 float effective_det_plus_lb_lines_luma; 467 float urgent_latency_support_us_luma; 468 float effective_det_plus_lb_lines_chroma; 469 float urgent_latency_support_us_chroma; 470 float min_urgent_latency_support_us; 471 float non_urgent_latency_tolerance; 472 float block_height256_bytes_y; 473 float block_height256_bytes_c; 474 float meta_request_width_y; 475 float meta_surf_width_y; 476 float meta_surf_height_y; 477 float meta_pte_bytes_frame_y; 478 float meta_row_byte_y; 479 float macro_tile_size_byte_y; 480 float macro_tile_height_y; 481 float pixel_pte_req_height_y; 482 float pixel_pte_req_width_y; 483 float pixel_pte_bytes_per_row_y; 484 float meta_request_width_c; 485 float meta_surf_width_c; 486 float meta_surf_height_c; 487 float meta_pte_bytes_frame_c; 488 float meta_row_byte_c; 489 float macro_tile_size_bytes_c; 490 float macro_tile_height_c; 491 float pixel_pte_req_height_c; 492 float pixel_pte_req_width_c; 493 float pixel_pte_bytes_per_row_c; 494 float max_partial_swath_y; 495 float max_partial_swath_c; 496 float t_calc; 497 float next_prefetch_mode; 498 float v_startup_lines; 499 enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw; 500 enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4; 501 enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2; 502 enum dcn_bw_defs v_ratio_prefetch_more_than4; 503 enum dcn_bw_defs destination_line_times_for_prefetch_less_than2; 504 float prefetch_mode; 505 float dstx_after_scaler; 506 float dsty_after_scaler; 507 float v_update_offset_pix[number_of_planes_minus_one + 1]; 508 float total_repeater_delay_time; 509 float v_update_width_pix[number_of_planes_minus_one + 1]; 510 float v_ready_offset_pix[number_of_planes_minus_one + 1]; 511 float t_setup; 512 float t_wait; 513 float bandwidth_available_for_immediate_flip; 514 float tot_immediate_flip_bytes; 515 float max_rd_bandwidth; 516 float time_for_fetching_meta_pte; 517 float time_for_fetching_row_in_vblank; 518 float lines_to_request_prefetch_pixel_data; 519 float required_prefetch_pix_data_bw; 520 enum dcn_bw_defs prefetch_mode_supported; 521 float active_dp_ps; 522 float lb_latency_hiding_source_lines_y; 523 float lb_latency_hiding_source_lines_c; 524 float effective_lb_latency_hiding_y; 525 float effective_lb_latency_hiding_c; 526 float dpp_output_buffer_lines_y; 527 float dpp_output_buffer_lines_c; 528 float dppopp_buffering_y; 529 float max_det_buffering_time_y; 530 float active_dram_clock_change_latency_margin_y; 531 float dppopp_buffering_c; 532 float max_det_buffering_time_c; 533 float active_dram_clock_change_latency_margin_c; 534 float writeback_dram_clock_change_latency_margin; 535 float min_active_dram_clock_change_margin; 536 float v_blank_of_min_active_dram_clock_change_margin; 537 float second_min_active_dram_clock_change_margin; 538 float min_vblank_dram_clock_change_margin; 539 float dram_clock_change_margin; 540 float dram_clock_change_support; 541 float wr_bandwidth; 542 float max_used_bw; 543}; 544 545struct dcn_soc_bounding_box { 546 float sr_exit_time; /*us*/ 547 float sr_enter_plus_exit_time; /*us*/ 548 float urgent_latency; /*us*/ 549 float write_back_latency; /*us*/ 550 float percent_of_ideal_drambw_received_after_urg_latency; /*%*/ 551 int max_request_size; /*bytes*/ 552 float dcfclkv_max0p9; /*MHz*/ 553 float dcfclkv_nom0p8; /*MHz*/ 554 float dcfclkv_mid0p72; /*MHz*/ 555 float dcfclkv_min0p65; /*MHz*/ 556 float max_dispclk_vmax0p9; /*MHz*/ 557 float max_dispclk_vmid0p72; /*MHz*/ 558 float max_dispclk_vnom0p8; /*MHz*/ 559 float max_dispclk_vmin0p65; /*MHz*/ 560 float max_dppclk_vmax0p9; /*MHz*/ 561 float max_dppclk_vnom0p8; /*MHz*/ 562 float max_dppclk_vmid0p72; /*MHz*/ 563 float max_dppclk_vmin0p65; /*MHz*/ 564 float socclk; /*MHz*/ 565 float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/ 566 float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/ 567 float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/ 568 float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/ 569 float phyclkv_max0p9; /*MHz*/ 570 float phyclkv_nom0p8; /*MHz*/ 571 float phyclkv_mid0p72; /*MHz*/ 572 float phyclkv_min0p65; /*MHz*/ 573 float downspreading; /*%*/ 574 int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/ 575 int urgent_out_of_order_return_per_channel; /*bytes*/ 576 int number_of_channels; 577 int vmm_page_size; /*bytes*/ 578 float dram_clock_change_latency; /*us*/ 579 int return_bus_width; /*bytes*/ 580 float percent_disp_bw_limit; /*%*/ 581}; 582extern const struct dcn_soc_bounding_box dcn10_soc_defaults; 583 584struct dcn_ip_params { 585 float rob_buffer_size_in_kbyte; 586 float det_buffer_size_in_kbyte; 587 float dpp_output_buffer_pixels; 588 float opp_output_buffer_lines; 589 float pixel_chunk_size_in_kbyte; 590 enum dcn_bw_defs pte_enable; 591 int pte_chunk_size; /*kbytes*/ 592 int meta_chunk_size; /*kbytes*/ 593 int writeback_chunk_size; /*kbytes*/ 594 enum dcn_bw_defs odm_capability; 595 enum dcn_bw_defs dsc_capability; 596 int line_buffer_size; /*bit*/ 597 int max_line_buffer_lines; 598 enum dcn_bw_defs is_line_buffer_bpp_fixed; 599 int line_buffer_fixed_bpp; 600 int writeback_luma_buffer_size; /*kbytes*/ 601 int writeback_chroma_buffer_size; /*kbytes*/ 602 int max_num_dpp; 603 int max_num_writeback; 604 int max_dchub_topscl_throughput; /*pixels/dppclk*/ 605 int max_pscl_tolb_throughput; /*pixels/dppclk*/ 606 int max_lb_tovscl_throughput; /*pixels/dppclk*/ 607 int max_vscl_tohscl_throughput; /*pixels/dppclk*/ 608 float max_hscl_ratio; 609 float max_vscl_ratio; 610 int max_hscl_taps; 611 int max_vscl_taps; 612 int pte_buffer_size_in_requests; 613 float dispclk_ramping_margin; /*%*/ 614 float under_scan_factor; 615 int max_inter_dcn_tile_repeaters; 616 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 617 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 618 int dcfclk_cstate_latency; 619}; 620extern const struct dcn_ip_params dcn10_ip_defaults; 621 622bool dcn_validate_bandwidth( 623 struct dc *dc, 624 struct dc_state *context, 625 bool fast_validate); 626 627unsigned int dcn_find_dcfclk_suits_all( 628 const struct dc *dc, 629 struct dc_clocks *clocks); 630 631void dcn_get_soc_clks( 632 struct dc *dc, 633 int *min_fclk_khz, 634 int *min_dcfclk_khz, 635 int *socclk_khz); 636 637void dcn_bw_update_from_pplib_fclks( 638 struct dc *dc, 639 struct dm_pp_clock_levels_with_voltage *fclks); 640void dcn_bw_update_from_pplib_dcfclks( 641 struct dc *dc, 642 struct dm_pp_clock_levels_with_voltage *dcfclks); 643void dcn_bw_notify_pplib_of_wm_ranges( 644 struct dc *dc, 645 int min_fclk_khz, 646 int min_dcfclk_khz, 647 int socclk_khz); 648void dcn_bw_sync_calcs_and_dml(struct dc *dc); 649 650enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode); 651 652#endif /* __DCN_CALCS_H__ */ 653 654