drm/amd/display: Fix mutex lock in dcn10

Removal of DC_FP_* wrappers from dml (9696679bf7ac) provokes a mutex
lock [2] on the amdgpu driver. Re-arrange the dcn10 code to avoid
locking the mutex by placing the DC_FP_* wrappers around the proper
functions.

This fixes the following WARN/stacktrace:

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:283
in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 227, name: systemd-udevd
preempt_count: 1, expected: 0
CPU: 4 PID: 227 Comm: systemd-udevd Not tainted 6.0.0-rc6-qtec-standard #2
Hardware name: Qtechnology A/S QT5222/QT5221, BIOS v1.0.1 06/07/2021
Call Trace:
<TASK>
dump_stack_lvl+0x33/0x42
__might_resched.cold.172+0xa5/0xb3
mutex_lock+0x1a/0x40
amdgpu_dpm_get_clock_by_type_with_voltage+0x38/0x70 [amdgpu]
dm_pp_get_clock_levels_by_type_with_voltage+0x64/0xa0 [amdgpu]
dcn_bw_update_from_pplib+0x70/0x340 [amdgpu]
dcn10_create_resource_pool+0x8c8/0xd20 [amdgpu]
? __kmalloc+0x1c7/0x4a0
dc_create_resource_pool+0xe7/0x190 [amdgpu]
dc_create+0x212/0x5d0 [amdgpu]
amdgpu_dm_init+0x246/0x370 [amdgpu]
? schedule_hrtimeout_range_clock+0x93/0x120
? phm_wait_for_register_unequal.part.1+0x4a/0x80 [amdgpu]
dm_hw_init+0xe/0x20 [amdgpu]
amdgpu_device_init.cold.56+0x1324/0x1653 [amdgpu]
? pci_bus_read_config_word+0x43/0x80
amdgpu_driver_load_kms+0x15/0x120 [amdgpu]
amdgpu_pci_probe+0x116/0x320 [amdgpu]
pci_device_probe+0x97/0x110
really_probe+0xdd/0x340
__driver_probe_device+0x80/0x170
driver_probe_device+0x1f/0x90
__driver_attach+0xdc/0x180
? __device_attach_driver+0x100/0x100
? __device_attach_driver+0x100/0x100
bus_for_each_dev+0x74/0xc0
bus_add_driver+0x19e/0x210
? kset_find_obj+0x30/0xa0
? 0xffffffffa0a5b000
driver_register+0x6b/0xc0
? 0xffffffffa0a5b000
do_one_initcall+0x4a/0x1f0
? __vunmap+0x28e/0x2f0
? __cond_resched+0x15/0x30
? kmem_cache_alloc_trace+0x3d/0x440
do_init_module+0x4a/0x1e0
load_module+0x1cba/0x1e10
? __do_sys_finit_module+0xb7/0x120
__do_sys_finit_module+0xb7/0x120
do_syscall_64+0x3c/0x80
entry_SYSCALL_64_after_hwframe+0x63/0xcd
RIP: 0033:0x7ff2b5f5422d
Code: 5d c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48
89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48>
3d 01 f0 ff ff 73 01 c3 48 8b 0d c3 ab 0e 00 f7 d8 64 89 01 48
RSP: 002b:00007ffc44ab28e8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
RAX: ffffffffffffffda RBX: 0000555c566a9240 RCX: 00007ff2b5f5422d
RDX: 0000000000000000 RSI: 00007ff2b60bb353 RDI: 0000000000000019
RBP: 00007ff2b60bb353 R08: 0000000000000000 R09: 0000555c566a9240
R10: 0000000000000019 R11: 0000000000000246 R12: 0000000000000000
R13: 0000000000020000 R14: 0000000000000000 R15: 0000000000000000
</TASK>

Fixes: 9696679bf7ac ("drm/amd/display: remove DC_FP_* wrapper from dml folder")
Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Daniel Gomez <daniel@qtec.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: detach fpu operations from dcn10_validate_bandwidth in calcs

dcn10_validate_bandwidth is only used on dcn10 files, but is declared in
dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper
inside DML folder and create an specific dcn10_validate_bandwidth in
dcn10_resources that calls dcn_validate_bandwidth and properly wraps that
FPU function with DC_FP_* macro.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: Rename dcn_validate_bandwidth to dcn10_validate_bandwidth

[Why]
Rename function name so it aligns with other resource
function names being used by dcn10.

[How]
Rename function name for consistency.

Reviewed-by: Ahmad Othman <Ahmad.Othman@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: make clk mgr soc specific

[Why]
First step of refactoring clk mgr to better handle different
ways of handling clock operations. Clock operation policies are
soc specific and not just DCN vesion specific. It is not a hw resource,
should not be in the resource pool.

[How]
Change clock manager creation to be based on HW internal ID, rename
clock manager members to be more clear. Move clock manager out of
resource.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: Add fast_validate parameter

Add a fast_validate parameter in dc_validate_global_state for future use

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: Populate macro_tile_size field for dml

Create a functions to return swizzle types for dml

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: rename dccg to clk_mgr

In preparation for adding the actual dccg block since the
current implementation of dccg is mor eof a clock manager
than a hw block

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: split dccg clock manager into asic folders

Currently dccg contains code related to every dcn revision in
a single file.

This change splits out the dcn parts of code into correct folders

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: program v_update and v_ready with proper field

[WHY]
There are two different variables used to calculate v_update and v_ready,
one for validation and the other for performance parameter calculation.
Before the variable for validation was used which caused underflow on
1080edp with vsr enabled

[HOW]
program v_update and v_ready with the variables for performance parameter
calculation

Signed-off-by: Su Sung Chung <su.chung@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: replace clocks_value struct with dc_clocks

This will avoid structs with duplicate information. Also
removes pixel clock voltage request. This has no effect since
pixel clock does not affect dcn voltage and this function only
matters for dcn.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: fix global sync param retrieval when not pipe splitting

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: Rename dc validate_context and current_context

Rename all the dc validate_context to dc_state and
dc current_context to current_state.

Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: Flattening core_dc to dc

-Flattening core_dc to dc

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: fix PHYCLK in formula.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/display: block modes that require read bw greater than 30%

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/display: Add calcs code for DCN

Bandwidth and scaling calculations for DCN.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>