Searched refs:dpm_level_enable_mask (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dci_dpm.c2600 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3261 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3315 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3779 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3782 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3789 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3792 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3799 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3802 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3899 pi->dpm_level_enable_mask
[all...]
H A Dci_dpm.h236 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member in struct:ci_power_info
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.h306 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:smu7_hwmgr
H A Dsmu7_hwmgr.c3038 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3040 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3052 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3054 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3067 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3069 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3093 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3096 data->dpm_level_enable_mask.sclk_dpm_enable_mask,
3101 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3104 data->dpm_level_enable_mask
[all...]
H A Dvega10_hwmgr.h369 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega10_hwmgr
H A Dvega12_hwmgr.h371 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega12_hwmgr
H A Dvega20_hwmgr.h494 struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega20_hwmgr
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c594 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
910 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1068 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1073 (hw_data->dpm_level_enable_mask
[all...]
H A Dfiji_smumgr.c849 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1043 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1055 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1056 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1060 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1061 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1066 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1258 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
H A Dpolaris10_smumgr.c840 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1099 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1104 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
1115 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1116 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1120 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1121 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1126 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1238 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1243 (hw_data->dpm_level_enable_mask
[all...]
H A Diceland_smumgr.c789 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1383 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
H A Dtonga_smumgr.c532 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
732 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
745 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
748 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
749 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
754 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
755 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
761 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1131 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
H A Dci_smumgr.c502 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1017 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1340 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2879 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
2883 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
2888 data->dpm_level_enable_mask.uvd_dpm_enable_mask,
2911 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
2915 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
2920 data->dpm_level_enable_mask.vce_dpm_enable_mask,

Completed in 236 milliseconds