Searched refs:clk_rate (Results 1 - 25 of 155) sorted by relevance

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/linux-master/arch/m68k/include/asm/
H A Dmcfclk.h32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
35 .rate = clk_rate, \
42 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
44 .rate = clk_rate, \
/linux-master/include/linux/platform_data/
H A Dkeypad-ep93xx.h26 unsigned int clk_rate; member in struct:ep93xx_keypad_platform_data
/linux-master/drivers/ufs/host/
H A Dufs-mediatek-trace.h32 TP_PROTO(const char *name, bool scale_up, unsigned long clk_rate),
33 TP_ARGS(name, scale_up, clk_rate),
38 __field(unsigned long, clk_rate)
44 __entry->clk_rate = clk_rate;
50 __entry->clk_rate)
H A Dti-j721e-ufs.c21 unsigned long clk_rate; local
43 clk_rate = clk_get_rate(clk);
44 if (clk_rate == 26000000)
/linux-master/include/linux/platform_data/x86/
H A Dpwm-lpss.h14 unsigned long clk_rate; member in struct:pwm_lpss_boardinfo
/linux-master/drivers/watchdog/
H A Dloongson1_wdt.c29 unsigned long clk_rate; member in struct:ls1x_wdt_drvdata
51 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat);
106 unsigned long clk_rate; local
121 clk_rate = clk_get_rate(drvdata->clk);
122 if (!clk_rate)
124 drvdata->clk_rate = clk_rate;
131 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000;
H A Dimgpdc_wdt.c116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
183 unsigned long clk_rate; local
207 clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
208 if (clk_rate == 0) {
213 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
218 if (order_base_2(clk_rate) == 0)
227 do_div(div, clk_rate);
H A Dlpc18xx_wdt.c55 unsigned long clk_rate; member in struct:lpc18xx_wdt_dev
107 val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
129 return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
226 lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
227 if (lpc18xx_wdt->clk_rate == 0) {
236 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
239 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
H A Dlantiq_wdt.c65 unsigned long clk_rate; member in struct:ltq_wdt_priv
104 timeout = wdt->timeout * priv->clk_rate;
132 timeout = wdt->timeout * priv->clk_rate;
148 return do_div(timeout, priv->clk_rate);
220 priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
221 if (!priv->clk_rate) {
231 wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
H A Drenesas_wdt.c32 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
52 unsigned long clk_rate; member in struct:rwdt_priv
80 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
143 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
155 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
237 priv->clk_rate = clk_get_rate(priv->clk);
242 if (!priv->clk_rate) {
248 clks_per_sec = priv->clk_rate / clk_div
[all...]
/linux-master/drivers/mfd/
H A Dintel-lpss-acpi.c37 .clk_rate = 120000000,
51 .clk_rate = 120000000,
67 .clk_rate = 120000000,
82 .clk_rate = 100000000,
98 .clk_rate = 133000000,
114 .clk_rate = 133000000,
128 .clk_rate = 120000000,
133 .clk_rate = 216000000,
H A Dintel-lpss.h36 unsigned long clk_rate; member in struct:intel_lpss_platform_info
/linux-master/drivers/memory/
H A Dti-aemif.c115 * @clk_rate: clock's rate in kHz
123 unsigned long clk_rate; member in struct:aemif_device
179 unsigned long clk_rate = aemif->clk_rate; local
185 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
186 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
187 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
188 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
189 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
190 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MA
217 aemif_cycles_to_nsec(int val, unsigned long clk_rate) argument
235 unsigned long clk_rate = aemif->clk_rate; local
[all...]
/linux-master/drivers/char/hw_random/
H A Dks-sa-rng.c92 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) argument
95 cycles, clk_rate);
98 static unsigned int startup_delay_ns(unsigned long clk_rate) argument
101 return cycles_to_ns(clk_rate, BIT(24));
102 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_STARTUP_CYCLES);
105 static unsigned int refill_delay_ns(unsigned long clk_rate) argument
108 return cycles_to_ns(clk_rate, BIT(24));
109 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_MAX_REFILL_CYCLES);
116 unsigned long clk_rate = clk_get_rate(ks_sa_rng->clk); local
145 ks_sa_rng->refill_delay_ns = refill_delay_ns(clk_rate);
[all...]
/linux-master/drivers/pwm/
H A Dpwm-omap-dmtimer.c75 * @clk_rate: pwm timer clock rate
80 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) argument
82 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
153 unsigned long clk_rate; local
169 clk_rate = clk_get_rate(fclk);
170 if (!clk_rate) {
175 dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate); local
193 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
194 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
199 period_ns, clk_rate); local
206 duty_ns, clk_rate); local
212 duty_ns, period_ns, clk_rate); local
[all...]
H A Dpwm-sunplus.c60 u64 clk_rate; local
77 clk_rate = clk_get_rate(priv->clk);
84 if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC)
88 * With clk_rate limited above we have dd_freq <= state->period,
91 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
114 * duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow.
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
132 u64 clk_rate; local
137 clk_rate = clk_get_rate(priv->clk);
146 * NSEC_PER_SEC, clk_rate);
[all...]
H A Dpwm-keembay.c96 unsigned long clk_rate; local
99 clk_rate = clk_get_rate(priv->clk);
112 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
113 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
125 unsigned long clk_rate; local
153 clk_rate = clk_get_rate(priv->clk);
154 div = clk_rate * state->duty_cycle;
160 div = clk_rate * state->period;
H A Dpwm-sun4i.c114 u64 clk_rate, tmp; local
118 clk_rate = clk_get_rate(sun4ichip->clk);
119 if (!clk_rate)
131 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
174 u64 clk_rate, div = 0; local
177 clk_rate = clk_get_rate(sun4ichip->clk);
181 (state->period * clk_rate >= NSEC_PER_SEC) &&
182 (state->period * clk_rate <
[all...]
H A Dpwm-lpss.c37 .clk_rate = 25000000,
45 .clk_rate = 19200000,
54 .clk_rate = 19200000,
63 .clk_rate = 19200000,
128 unsigned long c = lpwm->info->clk_rate, base_unit_range;
224 freq = base_unit * lpwm->info->clk_rate;
268 c = lpwm->info->clk_rate;
H A Dpwm-microchip-core.c133 static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate, argument
141 * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
145 duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);
184 static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate, argument
195 * clk_rate
206 * It's therefore not possible to set a period lower than 1/clk_rate, so
211 tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
248 * period * clk_rate
253 * period * clk_rate
261 * period * clk_rate
278 unsigned long clk_rate; local
[all...]
/linux-master/include/linux/mtd/
H A Dspear_smi.h54 * clk_rate: clk rate at which SMI must operate
59 unsigned long clk_rate; member in struct:spear_smi_plat_data
/linux-master/drivers/clocksource/
H A Dtimer-microchip-pit64b.c239 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, argument
245 tmp = clk_rate / (*pres + 1);
348 u32 clk_rate)
374 ret = clocksource_register_hz(&cs->clksrc, clk_rate);
385 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
388 mchp_pit64b_dt.freq = clk_rate;
395 u32 clk_rate, u32 irq)
404 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
428 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
437 unsigned long clk_rate; local
347 mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, u32 clk_rate) argument
394 mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, u32 clk_rate, u32 irq) argument
[all...]
H A Dtimer-vf-pit.c153 unsigned long clk_rate; local
182 clk_rate = clk_get_rate(pit_clk);
183 cycle_per_jiffy = clk_rate / (HZ);
188 ret = pit_clocksource_init(clk_rate);
192 return pit_clockevent_init(clk_rate, irq);
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.c138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
282 u64 clk_rate; local
292 clk_rate = 0;
296 clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
297 clk_rate);
301 return clk_rate;
309 u64 clk_rate = 0; local
380 clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
382 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
384 trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate);
[all...]
/linux-master/drivers/i2c/busses/
H A Di2c-pasemi-platform.c27 unsigned long clk_rate = clk_get_rate(data->clk_ref); local
29 if (!clk_rate)
32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency);

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