Lines Matching refs:clk_rate
60 u64 clk_rate;
77 clk_rate = clk_get_rate(priv->clk);
84 if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC)
88 * With clk_rate limited above we have dd_freq <= state->period,
91 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
114 * duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow.
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
132 u64 clk_rate;
137 clk_rate = clk_get_rate(priv->clk);
146 * NSEC_PER_SEC, clk_rate);
151 clk_rate);