Lines Matching refs:clk_rate
75 * @clk_rate: pwm timer clock rate
80 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
82 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
153 unsigned long clk_rate;
169 clk_rate = clk_get_rate(fclk);
170 if (!clk_rate) {
175 dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate);
193 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
194 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
199 period_ns, clk_rate);
206 duty_ns, clk_rate);
212 duty_ns, period_ns, clk_rate);
219 clk_rate),
221 clk_rate));