Searched refs:bw_params (Results 1 - 25 of 52) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.h32 void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn321_fpu.c344 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, argument
365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
371 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
372 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
373 if (bw_params
610 dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.h30 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn302_fpu.c195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
220 if (bw_params->clk_table.entries[0].memclk_mhz) {
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
231 max_phyclk_mhz = bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.h29 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
H A Ddcn303_fpu.c191 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
216 if (bw_params->clk_table.entries[0].memclk_mhz) {
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
227 max_phyclk_mhz = bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.h35 void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.h36 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.h36 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.h10 struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.h46 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
47 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c486 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) argument
494 if (!bw_params->wm_table.entries[i].valid)
497 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
498 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
509 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
512 bw_params->clk_table.entries[i].dcfclk_mhz;
555 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table);
621 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
622 struct clk_limit_table_entry def_max = bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c373 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table) argument
381 if (!bw_params->wm_table.entries[i].valid)
384 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
396 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
399 bw_params->clk_table.entries[i].dcfclk_mhz;
442 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
477 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
479 struct clk_limit_table_entry def_max = bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.h29 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.h35 struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c568 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table) argument
576 if (!bw_params->wm_table.entries[i].valid)
579 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
580 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
591 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
594 bw_params->clk_table.entries[i].dcfclk_mhz;
637 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
710 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
711 struct clk_limit_table_entry def_max = bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
413 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
432 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
437 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
438 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
439 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
459 if (dc->clk_mgr->bw_params
639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
118 if (!clk_mgr_base->bw_params)
133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
150 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
160 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
253 if ((new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) !=
254 (clk_mgr_base->clks.dramclk_khz <= dc->clk_mgr->bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c343 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) argument
351 if (!bw_params->wm_table.entries[i].valid)
354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
369 bw_params->clk_table.entries[i].dcfclk_mhz;
412 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
483 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
505 bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
166 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
176 if (!clk_mgr_base->bw_params)
190 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
192 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
196 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
198 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
203 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
205 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
211 &clk_mgr_base->bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c191 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
192 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
200 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
202 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
204 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
205 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
208 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
209 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
210 clk_mgr->base.bw_params
2624 dcn32_patch_dpm_table(struct clk_bw_params *bw_params) argument
2756 build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) argument
3005 dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) argument
[all...]
H A Ddcn32_fpu.h59 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
67 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.h81 void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
83 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c421 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) argument
429 if (!bw_params->wm_table.entries[i].valid)
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
447 bw_params->clk_table.entries[i].dcfclk_mhz;
490 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
560 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
582 bw_params
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c386 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) argument
394 if (!bw_params->wm_table.entries[i].valid)
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
412 bw_params->clk_table.entries[i].dcfclk_mhz;
456 vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
565 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; local
586 bw_params
[all...]

Completed in 219 milliseconds

123