dml/dcn302/dcn302_fpu.c

195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
220 	if (bw_params->clk_table.entries[0].memclk_mhz) {
224 			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
225 				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
226 			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
227 				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
228 			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
229 				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
230 			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
231 				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
258 		num_uclk_states = bw_params->clk_table.num_entries;
262 			dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
264 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
265 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
273 							bw_params->clk_table.entries[j].memclk_mhz * 16;
289 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
304 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
318 			/* Populate from bw_params for DTBCLK, SOCCLK */
319 			if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
322 				dcn3_02_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
323 			if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
326 				dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
327 			/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */