clk_mgr/dcn32/dcn32_clk_mgr.c

151 		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
166 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
176 	if (!clk_mgr_base->bw_params)
190 			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
192 	clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
196 					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
198 	clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
203 				&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
205 		clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
211 			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
214 	clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
216 	if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
217 		clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
221 			&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
224 	clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DPPCLK);
226 	if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950)
227 		clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950;
236 			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
238 				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
242 		if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
243 			clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
247 			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
249 				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
254 		if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950)
255 			clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950;
539     num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
542 	    dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
545 	    fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
716 						dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
717 						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
720 								dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
722 					dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
756 						max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
796 		new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
982 		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
984 			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
1005 					clk_mgr_base->bw_params->max_memclk_mhz);
1008 				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
1020 	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
1027 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1035 			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1037 	clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1038 	clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1044 			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1046 	clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1053 	clk_mgr_base->bw_params->max_memclk_mhz =
1054 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1055 	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1061 		dcn32_patch_dpm_table(clk_mgr_base->bw_params);
1066 			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1210 	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1220 	kfree(clk_mgr->base.bw_params);