clk_mgr/dcn314/dcn314_clk_mgr.c

486 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
494 		if (!bw_params->wm_table.entries[i].valid)
497 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
498 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
509 						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
512 					bw_params->clk_table.entries[i].dcfclk_mhz;
555 	dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table);
621 	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
622 	struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
663 		for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
664 			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
667 		bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
668 		bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
669 		bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
672 		bw_params->clk_table.entries[i].fclk_mhz = min_fclk;
673 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
674 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
675 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
676 		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
677 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
678 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
679 		bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
688 		bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
689 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
690 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
691 		bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
692 		bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
693 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
694 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
695 		bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
699 	bw_params->clk_table.num_entries = i--;
702 	bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
703 	bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
704 	bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
706 	bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
707 	bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
708 	bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
714 	for (i = 0; i < bw_params->clk_table.num_entries; i++) {
715 		if (!bw_params->clk_table.entries[i].fclk_mhz) {
716 			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
717 			bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
718 			bw_params->clk_table.entries[i].voltage = def_max.voltage;
720 		if (!bw_params->clk_table.entries[i].dcfclk_mhz)
721 			bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
722 		if (!bw_params->clk_table.entries[i].socclk_mhz)
723 			bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
724 		if (!bw_params->clk_table.entries[i].dispclk_mhz)
725 			bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
726 		if (!bw_params->clk_table.entries[i].dppclk_mhz)
727 			bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
728 		if (!bw_params->clk_table.entries[i].phyclk_mhz)
729 			bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
730 		if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
731 			bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
732 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
733 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
735 	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
736 	bw_params->vram_type = bios_info->memory_type;
738 	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
739 	bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
742 		bw_params->wm_table.entries[i].wm_inst = i;
744 		if (i >= bw_params->clk_table.num_entries) {
745 			bw_params->wm_table.entries[i].valid = false;
749 		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
750 		bw_params->wm_table.entries[i].valid = true;
853 	clk_mgr->base.base.bw_params = &dcn314_bw_params;