Searched refs:UVD_VCPU_CNTL__CLK_EN_MASK (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c638 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
661 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
741 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); local
945 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v4_0_5.c855 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
902 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
986 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); local
1214 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v4_0_3.c747 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
796 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1069 UVD_VCPU_CNTL__CLK_EN_MASK, local
1070 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1305 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v2_0.c817 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
955 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1171 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v3_0.c968 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1029 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1128 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); local
1575 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v4_0.c941 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
988 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1075 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); local
1552 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v2_5.c845 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
908 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1003 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); local
1432 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
H A Dvcn_v1_0.c854 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
985 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1143 ~UVD_VCPU_CNTL__CLK_EN_MASK);
H A Duvd_v7_0.c905 UVD_VCPU_CNTL__CLK_EN_MASK); local
1036 UVD_VCPU_CNTL__CLK_EN_MASK);
H A Duvd_v6_0.c794 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_5_0_sh_mask.h579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_6_0_sh_mask.h581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_4_0_sh_mask.h768 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Duvd_3_1_sh_mask.h543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
H A Duvd_7_0_sh_mask.h665 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1187 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_2_0_0_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_2_6_0_sh_mask.h112 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_2_5_sh_mask.h2759 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_3_0_0_sh_mask.h3818 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_5_0_0_sh_mask.h3767 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_4_0_3_sh_mask.h4104 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
[all...]
H A Dvcn_4_0_0_sh_mask.h4066 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
H A Dvcn_4_0_5_sh_mask.h3933 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro

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