1/* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22#ifndef _vcn_2_5_SH_MASK_HEADER 23#define _vcn_2_5_SH_MASK_HEADER 24 25// addressBlock: uvd0_mmsch_dec 26//MMSCH_UCODE_ADDR 27#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 28#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 29#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 30#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 31//MMSCH_UCODE_DATA 32#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 33#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 34//MMSCH_SRAM_ADDR 35#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 36#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 37#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 38#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 39//MMSCH_SRAM_DATA 40#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 41#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 42//MMSCH_VF_SRAM_OFFSET 43#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 44#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 45#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 46#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 47//MMSCH_DB_SRAM_OFFSET 48#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 49#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 50#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 51#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 52#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 53#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 54//MMSCH_CTX_SRAM_OFFSET 55#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 56#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 57#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 58#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 59//MMSCH_CTL 60#define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 61#define MMSCH_CTL__P_RESET__SHIFT 0x1 62#define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 63#define MMSCH_CTL__P_LOCK__SHIFT 0x1f 64#define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 65#define MMSCH_CTL__P_RESET_MASK 0x00000002L 66#define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 67#define MMSCH_CTL__P_LOCK_MASK 0x80000000L 68//MMSCH_INTR 69#define MMSCH_INTR__INTR__SHIFT 0x0 70#define MMSCH_INTR__INTR_MASK 0x00001FFFL 71//MMSCH_INTR_ACK 72#define MMSCH_INTR_ACK__INTR__SHIFT 0x0 73#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 74//MMSCH_INTR_STATUS 75#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 76#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 77//MMSCH_VF_VMID 78#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 79#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 80#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 81#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 82//MMSCH_VF_CTX_ADDR_LO 83#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 84#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 85//MMSCH_VF_CTX_ADDR_HI 86#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 87#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 88//MMSCH_VF_CTX_SIZE 89#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 90#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 91//MMSCH_VF_GPCOM_ADDR_LO 92#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 93#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 94//MMSCH_VF_GPCOM_ADDR_HI 95#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 96#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 97//MMSCH_VF_GPCOM_SIZE 98#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 99#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 100//MMSCH_VF_MAILBOX_HOST 101#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 102#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 103//MMSCH_VF_MAILBOX_RESP 104#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 105#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 106//MMSCH_VF_MAILBOX_0 107#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 108#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 109//MMSCH_VF_MAILBOX_0_RESP 110#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 111#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 112//MMSCH_VF_MAILBOX_1 113#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 114#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 115//MMSCH_VF_MAILBOX_1_RESP 116#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 117#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 118//MMSCH_CNTL 119#define MMSCH_CNTL__CLK_EN__SHIFT 0x0 120#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 121#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 122#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 123#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 124#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 125#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 126#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 127#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 128#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 129#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 130#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 131#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 132#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 133//MMSCH_NONCACHE_OFFSET0 134#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 135#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 136//MMSCH_NONCACHE_SIZE0 137#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 138#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 139//MMSCH_NONCACHE_OFFSET1 140#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 141#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 142//MMSCH_NONCACHE_SIZE1 143#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 144#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 145//MMSCH_PROC_STATE1 146#define MMSCH_PROC_STATE1__PC__SHIFT 0x0 147#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 148//MMSCH_LAST_MC_ADDR 149#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 150#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 151#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 152#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 153//MMSCH_LAST_MEM_ACCESS_HI 154#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 155#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 156#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 157#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 158#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 159#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 160//MMSCH_LAST_MEM_ACCESS_LO 161#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 162#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 163//MMSCH_IOV_ACTIVE_FCN_ID 164#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 165#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 166#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 167#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 168//MMSCH_SCRATCH_0 169#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 170#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 171//MMSCH_SCRATCH_1 172#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 173#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 174//MMSCH_GPUIOV_SCH_BLOCK_0 175#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 176#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 177#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 178#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 179#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 180#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 181//MMSCH_GPUIOV_CMD_CONTROL_0 182#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 183#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 184#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 185#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 186#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 187#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 188#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 189#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 190#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 191#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 192#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 193#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 194//MMSCH_GPUIOV_CMD_STATUS_0 195#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 196#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 197//MMSCH_GPUIOV_VM_BUSY_STATUS_0 198#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 199#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 200//MMSCH_GPUIOV_ACTIVE_FCNS_0 201#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 202#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 203//MMSCH_GPUIOV_ACTIVE_FCN_ID_0 204#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 205#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 206#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 207#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 208//MMSCH_GPUIOV_DW6_0 209#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 210#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 211//MMSCH_GPUIOV_DW7_0 212#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 213#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 214//MMSCH_GPUIOV_DW8_0 215#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 216#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 217//MMSCH_GPUIOV_SCH_BLOCK_1 218#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 219#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 220#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 221#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 222#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 223#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 224//MMSCH_GPUIOV_CMD_CONTROL_1 225#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 226#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 227#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 228#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 229#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 230#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 231#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 232#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 233#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 234#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 235#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 236#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 237//MMSCH_GPUIOV_CMD_STATUS_1 238#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 239#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 240//MMSCH_GPUIOV_VM_BUSY_STATUS_1 241#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 242#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 243//MMSCH_GPUIOV_ACTIVE_FCNS_1 244#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 245#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 246//MMSCH_GPUIOV_ACTIVE_FCN_ID_1 247#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 248#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 249#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 250#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 251//MMSCH_GPUIOV_DW6_1 252#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 253#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 254//MMSCH_GPUIOV_DW7_1 255#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 256#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 257//MMSCH_GPUIOV_DW8_1 258#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 259#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 260//MMSCH_GPUIOV_CNTXT 261#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 262#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 263#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 264#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 265#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 266#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 267//MMSCH_SCRATCH_2 268#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 269#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 270//MMSCH_SCRATCH_3 271#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 272#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 273//MMSCH_SCRATCH_4 274#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 275#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 276//MMSCH_SCRATCH_5 277#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 278#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 279//MMSCH_SCRATCH_6 280#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 281#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 282//MMSCH_SCRATCH_7 283#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 284#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 285//MMSCH_VFID_FIFO_HEAD_0 286#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 287#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 288//MMSCH_VFID_FIFO_TAIL_0 289#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 290#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 291//MMSCH_VFID_FIFO_HEAD_1 292#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 293#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 294//MMSCH_VFID_FIFO_TAIL_1 295#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 296#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 297//MMSCH_NACK_STATUS 298#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 299#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 300#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 301#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 302//MMSCH_VF_MAILBOX0_DATA 303#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 304#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 305//MMSCH_VF_MAILBOX1_DATA 306#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 307#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 308//MMSCH_GPUIOV_SCH_BLOCK_IP_0 309#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 310#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 311#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 312#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 313#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 314#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 315//MMSCH_GPUIOV_CMD_STATUS_IP_0 316#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 317#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 318//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 319#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 320#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 321#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 322#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 323//MMSCH_GPUIOV_SCH_BLOCK_IP_1 324#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 325#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 326#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 327#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 328#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 329#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 330//MMSCH_GPUIOV_CMD_STATUS_IP_1 331#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 332#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 333//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 334#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 335#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 336#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 337#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 338//MMSCH_GPUIOV_CNTXT_IP 339#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 340#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 341#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 342#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 343//MMSCH_GPUIOV_SCH_BLOCK_2 344#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 345#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 346#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 347#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 348#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 349#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 350//MMSCH_GPUIOV_CMD_CONTROL_2 351#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 352#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 353#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 354#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 355#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 356#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 357#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 358#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 359#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 360#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 361#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 362#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 363//MMSCH_GPUIOV_CMD_STATUS_2 364#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 365#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 366//MMSCH_GPUIOV_VM_BUSY_STATUS_2 367#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 368#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 369//MMSCH_GPUIOV_ACTIVE_FCNS_2 370#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 371#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 372//MMSCH_GPUIOV_ACTIVE_FCN_ID_2 373#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 374#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 375#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 376#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 377//MMSCH_GPUIOV_DW6_2 378#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 379#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 380//MMSCH_GPUIOV_DW7_2 381#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 382#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 383//MMSCH_GPUIOV_DW8_2 384#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 385#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 386//MMSCH_GPUIOV_SCH_BLOCK_IP_2 387#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 388#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 389#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 390#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 391#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 392#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 393//MMSCH_GPUIOV_CMD_STATUS_IP_2 394#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 395#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 396//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 397#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 398#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 399#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 400#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 401//MMSCH_VFID_FIFO_HEAD_2 402#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 403#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 404//MMSCH_VFID_FIFO_TAIL_2 405#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 406#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 407//MMSCH_VM_BUSY_STATUS_0 408#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 409#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 410//MMSCH_VM_BUSY_STATUS_1 411#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 412#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 413//MMSCH_VM_BUSY_STATUS_2 414#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 415#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 416 417 418// addressBlock: uvd0_jpegnpdec 419//UVD_JPEG_CNTL 420#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 421#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 422#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 423#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 424#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 425#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 426#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 427#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 428#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 429#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L 430//UVD_JPEG_RB_BASE 431#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 432#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 433#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 434#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 435//UVD_JPEG_RB_WPTR 436#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 437#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 438//UVD_JPEG_RB_RPTR 439#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 440#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 441//UVD_JPEG_RB_SIZE 442#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 443#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 444//UVD_JPEG_DEC_SCRATCH0 445#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 446#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 447//UVD_JPEG_INT_EN 448#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 449#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 450#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 451#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 452#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 453#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 454#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 455#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 456#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 457#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 458#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 459#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 460#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 461#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 462#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 463#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 464#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 465#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 466#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 467#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 468#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 469#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 470#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 471#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 472#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 473#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 474//UVD_JPEG_INT_STAT 475#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 476#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 477#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 478#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 479#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 480#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 481#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 482#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 483#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 484#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 485#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 486#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 487#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 488#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 489#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 490#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 491#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 492#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 493#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 494#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 495#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 496#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 497#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 498#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 499#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 500#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 501//UVD_JPEG_PITCH 502#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 503#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 504//UVD_JPEG_UV_PITCH 505#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 506#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 507//JPEG_DEC_Y_GFX8_TILING_SURFACE 508#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 509#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 510#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 511#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 512#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 513#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 514#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 515#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 516#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 517#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 518#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 519#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 520#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 521#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 522//JPEG_DEC_UV_GFX8_TILING_SURFACE 523#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 524#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 525#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 526#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 527#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 528#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 529#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 530#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 531#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 532#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 533#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 534#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 535#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 536#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 537//JPEG_DEC_GFX8_ADDR_CONFIG 538#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 539#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 540//JPEG_DEC_Y_GFX10_TILING_SURFACE 541#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 542#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 543//JPEG_DEC_UV_GFX10_TILING_SURFACE 544#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 545#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 546//JPEG_DEC_GFX10_ADDR_CONFIG 547#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 548#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 549#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 550#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 551#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 552#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 553#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 554#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 555//JPEG_DEC_ADDR_MODE 556#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 557#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 558#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 559#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 560#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 561#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 562//UVD_JPEG_OUTPUT_XY 563//UVD_JPEG_GPCOM_CMD 564#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 565#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 566//UVD_JPEG_GPCOM_DATA0 567#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 568#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 569//UVD_JPEG_GPCOM_DATA1 570#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 571#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 572//UVD_JPEG_SCRATCH1 573#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 574#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 575//UVD_JPEG_DEC_SOFT_RST 576#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 577#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 578#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 579#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 580 581 582// addressBlock: uvd0_uvd_jpeg_enc_dec 583//UVD_JPEG_ENC_INT_EN 584#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 585#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 586#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 587#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 588#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 589#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 590#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 591#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 592#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 593#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 594#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 595#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 596#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 597#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 598//UVD_JPEG_ENC_INT_STATUS 599#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 600#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 601#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 602#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 603#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 604#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 605#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 606#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 607#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 608#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 609#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 610#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 611#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 612#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 613//UVD_JPEG_ENC_ENGINE_CNTL 614#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 615#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 616#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 617#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 618#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 619#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 620#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 621#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 622#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 623#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 624#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 625#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 626//UVD_JPEG_ENC_SCRATCH1 627#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 628#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 629 630 631// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 632//UVD_JPEG_ENC_STATUS 633#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 634#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 635#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 636#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 637#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 638#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 639#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 640#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 641//UVD_JPEG_ENC_PITCH 642#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 643#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 644#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 645#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 646//UVD_JPEG_ENC_LUMA_BASE 647#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 648#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 649//UVD_JPEG_ENC_CHROMAU_BASE 650#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 651#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 652//UVD_JPEG_ENC_CHROMAV_BASE 653#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 654#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 655//JPEG_ENC_Y_GFX10_TILING_SURFACE 656#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 657#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 658//JPEG_ENC_UV_GFX10_TILING_SURFACE 659#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 660#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 661//JPEG_ENC_GFX10_ADDR_CONFIG 662#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 663#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 664#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 665#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 666#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 667#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 668#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 669#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 670//JPEG_ENC_ADDR_MODE 671#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 672#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 673#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 674#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 675#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 676#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 677//UVD_JPEG_ENC_GPCOM_CMD 678#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 679#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 680//UVD_JPEG_ENC_GPCOM_DATA0 681#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 682#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 683//UVD_JPEG_ENC_GPCOM_DATA1 684#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 685#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 686//UVD_JPEG_ENC_CGC_CNTL 687#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 688#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 689//UVD_JPEG_ENC_SCRATCH0 690#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 691#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 692//UVD_JPEG_ENC_SOFT_RST 693#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 694#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 695#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 696#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 697 698 699// addressBlock: uvd0_uvd_jrbc_dec 700//UVD_JRBC_RB_WPTR 701#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 702#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 703//UVD_JRBC_RB_CNTL 704#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 705#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 706#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 707#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 708#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 709#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 710//UVD_JRBC_IB_SIZE 711#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 712#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 713//UVD_JRBC_URGENT_CNTL 714#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 715#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 716//UVD_JRBC_RB_REF_DATA 717#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 718#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 719//UVD_JRBC_RB_COND_RD_TIMER 720#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 721#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 722#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 723#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 724#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 725#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 726#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 727#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 728//UVD_JRBC_SOFT_RESET 729#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 730#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 731#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 732#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 733//UVD_JRBC_STATUS 734#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 735#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 736#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 737#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 738#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 739#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 740#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 741#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 742#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 743#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 744#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 745#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 746#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 747#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 748#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 749#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 750#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 751#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 752#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 753#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 754#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 755#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 756#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 757#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 758#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 759#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 760#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 761#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 762#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 763#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 764//UVD_JRBC_RB_RPTR 765#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 766#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 767//UVD_JRBC_RB_BUF_STATUS 768#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 769#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 770#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 771#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 772#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 773#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 774//UVD_JRBC_IB_BUF_STATUS 775#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 776#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 777#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 778#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 779#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 780#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 781//UVD_JRBC_IB_SIZE_UPDATE 782#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 783#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 784//UVD_JRBC_IB_COND_RD_TIMER 785#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 786#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 787#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 788#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 789#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 790#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 791#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 792#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 793//UVD_JRBC_IB_REF_DATA 794#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 795#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 796//UVD_JPEG_PREEMPT_CMD 797#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 798#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 799#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 800#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 801#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 802#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 803//UVD_JPEG_PREEMPT_FENCE_DATA0 804#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 805#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 806//UVD_JPEG_PREEMPT_FENCE_DATA1 807#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 808#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 809//UVD_JRBC_RB_SIZE 810#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 811#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 812//UVD_JRBC_SCRATCH0 813#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 814#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 815 816 817// addressBlock: uvd0_uvd_jrbc_enc_dec 818//UVD_JRBC_ENC_RB_WPTR 819#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 820#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 821//UVD_JRBC_ENC_RB_CNTL 822#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 823#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 824#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 825#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 826#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 827#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 828//UVD_JRBC_ENC_IB_SIZE 829#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 830#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 831//UVD_JRBC_ENC_URGENT_CNTL 832#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 833#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 834//UVD_JRBC_ENC_RB_REF_DATA 835#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 836#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 837//UVD_JRBC_ENC_RB_COND_RD_TIMER 838#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 839#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 840#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 841#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 842#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 843#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 844#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 845#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 846//UVD_JRBC_ENC_SOFT_RESET 847#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 848#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 849#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 850#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 851//UVD_JRBC_ENC_STATUS 852#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 853#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 854#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 855#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 856#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 857#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 858#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 859#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 860#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 861#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 862#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 863#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 864#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 865#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 866#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 867#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 868#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 869#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 870#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 871#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 872#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 873#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 874#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 875#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 876#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 877#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 878#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 879#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 880#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 881#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 882//UVD_JRBC_ENC_RB_RPTR 883#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 884#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 885//UVD_JRBC_ENC_RB_BUF_STATUS 886#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 887#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 888#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 889#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 890#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 891#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 892//UVD_JRBC_ENC_IB_BUF_STATUS 893#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 894#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 895#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 896#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 897#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 898#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 899//UVD_JRBC_ENC_IB_SIZE_UPDATE 900#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 901#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 902//UVD_JRBC_ENC_IB_COND_RD_TIMER 903#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 904#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 905#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 906#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 907#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 908#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 909#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 910#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 911//UVD_JRBC_ENC_IB_REF_DATA 912#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 913#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 914//UVD_JPEG_ENC_PREEMPT_CMD 915#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 916#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 917#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 918#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 919#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 920#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 921//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 922#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 923#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 924//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 925#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 926#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 927//UVD_JRBC_ENC_RB_SIZE 928#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 929#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 930//UVD_JRBC_ENC_SCRATCH0 931#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 932#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 933 934 935// addressBlock: uvd0_uvd_jmi_dec 936//UVD_JMI_CTRL 937#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 938#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 939#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 940#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 941#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 942#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 943#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 944#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 945#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 946#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 947#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 948#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 949#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 950#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 951//UVD_LMI_JRBC_CTRL 952#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 953#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 954#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 955#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 956#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 957#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 958#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 959#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 960#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 961#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 962#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 963#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 964//UVD_LMI_JPEG_CTRL 965#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 966#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 967#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 968#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 969#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 970#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 971#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 972#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 973#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 974#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 975#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 976#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 977//UVD_JMI_EJRBC_CTRL 978#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 979#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 980#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 981#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 982#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 983#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 984#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 985#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 986#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 987#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 988#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 989#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 990//UVD_LMI_EJPEG_CTRL 991#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 992#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 993#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 994#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 995#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 996#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 997#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 998#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 999#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1000#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1001#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1002#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1003//UVD_LMI_JRBC_IB_VMID 1004#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1005#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1006#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1007#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1008#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1009#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1010//UVD_LMI_JRBC_RB_VMID 1011#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1012#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1013#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1014#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1015#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1016#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1017//UVD_LMI_JPEG_VMID 1018#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1019#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1020#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1021#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1022#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1023#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1024//UVD_JMI_ENC_JRBC_IB_VMID 1025#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1026#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1027#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1028#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1029#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1030#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1031//UVD_JMI_ENC_JRBC_RB_VMID 1032#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1033#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1034#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1035#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1036#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1037#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1038//UVD_JMI_ENC_JPEG_VMID 1039#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1040#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1041#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1042#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1043#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1044#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1045#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1046#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1047#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1048#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1049#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1050#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1051//UVD_JMI_PERFMON_CTRL 1052#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1053#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1054#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1055#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1056//UVD_JMI_PERFMON_COUNT_LO 1057#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1058#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1059//UVD_JMI_PERFMON_COUNT_HI 1060#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1061#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1062//UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1063#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1064#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1065//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1066#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1067#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1068//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1069#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1070#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1071//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1072#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1073#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1074//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1075#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1076#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1077//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1078#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1079#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1080//UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1081#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1082#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1083//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1084#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1085#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1086//UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1087#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1088#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1089//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1090#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1091#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1092//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1093#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1094#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1095//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1096#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1097#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1098//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1099#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1100#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1101//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1102#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1103#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1104//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1105#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1106#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1107//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1108#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1109#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1110//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1111#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1112#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1113//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1114#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1115#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1116//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1117#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1118#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1119//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1120#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1121#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1122//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1123#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1124#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1125//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1126#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1127#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1128//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1129#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1130#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1131//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1132#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1133#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1134//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1135#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1136#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1137//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1138#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1139#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1140//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1141#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1142#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1143//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1144#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1145#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1146//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1147#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1148#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1149//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1150#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1151#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1152//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1153#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1154#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1155//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1156#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1157#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1158//UVD_LMI_JPEG_PREEMPT_VMID 1159#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1160#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1161//UVD_LMI_ENC_JPEG_PREEMPT_VMID 1162#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1163#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1164//UVD_LMI_JPEG2_VMID 1165#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1166#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1167#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1168#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1169//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1170#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1171#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1172//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1173#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1174#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1175//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1176#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1177#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1178//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1179#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1180#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1181//UVD_LMI_JPEG_CTRL2 1182#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1183#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1184#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1185#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1186#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1187#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1188#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1189#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1190#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1191#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1192#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1193#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1194//UVD_JMI_DEC_SWAP_CNTL 1195#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1196#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1197#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1198#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1199#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1200#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1201#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1202#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1203#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1204#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1205#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1206#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1207#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1208#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1209#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1210#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1211#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1212#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1213//UVD_JMI_ENC_SWAP_CNTL 1214#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1215#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1216#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1217#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1218#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1219#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1220#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1221#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1222#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1223#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1224#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1225#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1226#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1227#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1228#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1229#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1230#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1231#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1232#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1233#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1234#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1235#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1236#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1237#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1238//UVD_JMI_CNTL 1239#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1240#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1241#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1242#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1243//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1244#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1245#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1246//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1247#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1248#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1249//UVD_JMI_DEC_SWAP_CNTL2 1250#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1251#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1252#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1253#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1254 1255 1256// addressBlock: uvd0_uvd_jpeg_common_dec 1257//JPEG_SOFT_RESET_STATUS 1258#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1259#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1260#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1261#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1262#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1263#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1264#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1265#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1266#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1267#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1268#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1269#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1270//JPEG_SYS_INT_EN 1271#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1272#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1273#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1274#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1275#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1276#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1277#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1278#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1279#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1280#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1281#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1282#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1283#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1284#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1285//JPEG_SYS_INT_STATUS 1286#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1287#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1288#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1289#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1290#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1291#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1292#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1293#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1294#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1295#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1296#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1297#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1298#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1299#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1300//JPEG_SYS_INT_ACK 1301#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1302#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1303#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1304#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1305#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1306#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1307#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1308#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1309#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1310#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1311#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1312#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1313#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1314#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1315//JPEG_MASTINT_EN 1316#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1317#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1318#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1319#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1320//JPEG_IH_CTRL 1321#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1322#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1323#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1324#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1325#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1326#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1327#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1328#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1329#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1330#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1331#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1332#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1333//JRBBM_ARB_CTRL 1334#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1335#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1336#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1337#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1338#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1339#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1340 1341 1342// addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1343//JPEG_CGC_GATE 1344#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1345#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1346#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1347#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1348#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1349#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1350#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1351#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1352#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1353#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1354//JPEG_CGC_CTRL 1355#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1356#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1357#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1358#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1359#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1360#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1361#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1362#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1363#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1364#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1365#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1366#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1367#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1368#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1369#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1370#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1371#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1372#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1373#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1374#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1375#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1376#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1377//JPEG_CGC_STATUS 1378#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1379#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1380#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1381#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1382#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1383#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1384#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1385#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1386#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1387#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1388#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1389#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1390#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1391#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1392#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1393#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1394#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1395#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1396//JPEG_COMN_CGC_MEM_CTRL 1397#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1398#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1399#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1400#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1401#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1402#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1403#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1404#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1405#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1406#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1407//JPEG_DEC_CGC_MEM_CTRL 1408#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1409#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1410#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1411#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1412#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1413#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1414//JPEG2_DEC_CGC_MEM_CTRL 1415#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1416#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1417#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1418#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1419#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1420#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1421//JPEG_ENC_CGC_MEM_CTRL 1422#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1423#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1424#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1425#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1426#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1427#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1428//JPEG_SOFT_RESET2 1429#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1430#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1431//JPEG_PERF_BANK_CONF 1432#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1433#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1434#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1435#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1436#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1437#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1438//JPEG_PERF_BANK_EVENT_SEL 1439#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1440#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1441#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1442#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1443#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1444#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1445#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1446#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1447//JPEG_PERF_BANK_COUNT0 1448#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1449#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1450//JPEG_PERF_BANK_COUNT1 1451#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1452#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1453//JPEG_PERF_BANK_COUNT2 1454#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1455#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1456//JPEG_PERF_BANK_COUNT3 1457#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1458#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1459 1460 1461// addressBlock: uvd0_uvd_pg_dec 1462//UVD_PGFSM_CONFIG 1463#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1464#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1465#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1466#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1467#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1468#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 1469#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 1470#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1471#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1472#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1473#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 1474#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1475#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 1476#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 1477#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 1478#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 1479#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 1480#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 1481#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 1482#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 1483#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 1484#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 1485#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 1486#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 1487//UVD_PGFSM_STATUS 1488#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 1489#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 1490#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 1491#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 1492#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 1493#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 1494#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 1495#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 1496#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 1497#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 1498#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 1499#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 1500#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 1501#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 1502#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 1503#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 1504#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 1505#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 1506#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 1507#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 1508#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 1509#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 1510#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 1511#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 1512//UVD_POWER_STATUS 1513#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 1514#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 1515#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 1516#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 1517#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 1518#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 1519#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 1520#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 1521#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 1522#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 1523#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 1524#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 1525#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 1526#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 1527//UVD_PG_IND_INDEX 1528#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 1529#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 1530//UVD_PG_IND_DATA 1531#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 1532#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 1533//CC_UVD_HARVESTING 1534#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 1535#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 1536#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 1537#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 1538//UVD_JPEG_POWER_STATUS 1539#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 1540#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 1541#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 1542#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 1543#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 1544#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 1545#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 1546#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 1547#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 1548#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 1549//UVD_DPG_LMA_CTL 1550#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 1551#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 1552#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 1553#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 1554#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 1555#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 1556#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 1557#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 1558#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 1559#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 1560//UVD_DPG_LMA_DATA 1561#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 1562#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 1563//UVD_DPG_LMA_MASK 1564#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 1565#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 1566//UVD_DPG_PAUSE 1567#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 1568#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 1569#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 1570#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 1571#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 1572#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 1573#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 1574#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 1575//UVD_SCRATCH1 1576#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 1577#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 1578//UVD_SCRATCH2 1579#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 1580#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 1581//UVD_SCRATCH3 1582#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 1583#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 1584//UVD_SCRATCH4 1585#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 1586#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 1587//UVD_SCRATCH5 1588#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 1589#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 1590//UVD_SCRATCH6 1591#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 1592#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 1593//UVD_SCRATCH7 1594#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 1595#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 1596//UVD_SCRATCH8 1597#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 1598#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 1599//UVD_SCRATCH9 1600#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 1601#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 1602//UVD_SCRATCH10 1603#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 1604#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 1605//UVD_SCRATCH11 1606#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 1607#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 1608//UVD_SCRATCH12 1609#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 1610#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 1611//UVD_SCRATCH13 1612#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 1613#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 1614//UVD_SCRATCH14 1615#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 1616#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 1617//UVD_FREE_COUNTER_REG 1618#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 1619#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 1620//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 1621#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1622#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1623//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 1624#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1625#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1626//UVD_DPG_VCPU_CACHE_OFFSET0 1627#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 1628#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 1629//UVD_DPG_LMI_VCPU_CACHE_VMID 1630#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 1631#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 1632//UVD_PF_STATUS 1633#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 1634#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 1635#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 1636#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 1637#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 1638#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 1639#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 1640#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 1641#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 1642#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 1643#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 1644#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 1645#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 1646#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 1647#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 1648#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 1649#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 1650#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 1651#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 1652#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 1653#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 1654#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 1655#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 1656#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 1657#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 1658#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 1659#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 1660#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 1661#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 1662#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 1663#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 1664#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 1665#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 1666#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 1667#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 1668#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 1669#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 1670#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 1671//UVD_DPG_CLK_EN_VCPU_REPORT 1672#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 1673#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 1674#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 1675#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 1676//UVD_GFX8_ADDR_CONFIG 1677#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1678#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 1679//UVD_GFX10_ADDR_CONFIG 1680#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1681#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1682#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 1683#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1684#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1685#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1686#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 1687#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1688//UVD_GPCNT2_CNTL 1689#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 1690#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 1691#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 1692#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 1693#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 1694#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 1695//UVD_GPCNT2_TARGET_LOWER 1696#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 1697#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1698//UVD_GPCNT2_STATUS_LOWER 1699#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 1700#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1701//UVD_GPCNT2_TARGET_UPPER 1702#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 1703#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1704//UVD_GPCNT2_STATUS_UPPER 1705#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 1706#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1707//UVD_GPCNT3_CNTL 1708#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 1709#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 1710#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 1711#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 1712#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 1713#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 1714#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 1715#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 1716#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 1717#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 1718//UVD_GPCNT3_TARGET_LOWER 1719#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 1720#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1721//UVD_GPCNT3_STATUS_LOWER 1722#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 1723#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1724//UVD_GPCNT3_TARGET_UPPER 1725#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 1726#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1727//UVD_GPCNT3_STATUS_UPPER 1728#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 1729#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1730 1731 1732// addressBlock: uvd0_uvddec 1733//UVD_STATUS 1734#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 1735#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 1736#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 1737#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 1738#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 1739#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 1740#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 1741#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 1742//UVD_ENC_PIPE_BUSY 1743#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 1744#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 1745#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 1746#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 1747#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 1748#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 1749#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 1750#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 1751#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 1752#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 1753#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 1754#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 1755#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 1756#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 1757#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 1758#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 1759#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 1760#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 1761#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 1762#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 1763#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 1764#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 1765#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 1766#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 1767#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 1768#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 1769#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 1770#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 1771#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 1772#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 1773#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 1774#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 1775#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 1776#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 1777#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 1778#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 1779#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 1780#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 1781#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 1782#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 1783#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 1784#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 1785#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 1786#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 1787#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 1788#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 1789#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 1790#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 1791#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 1792#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 1793#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 1794#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 1795#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 1796#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 1797//UVD_SOFT_RESET 1798#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 1799#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 1800#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 1801#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 1802#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 1803#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 1804#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 1805#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 1806#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 1807#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 1808#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 1809#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 1810#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 1811#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 1812#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 1813#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 1814#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 1815#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 1816#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 1817#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 1818#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 1819#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 1820#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 1821#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 1822#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 1823#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 1824#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 1825#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 1826#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 1827#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 1828#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 1829#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 1830#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 1831#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 1832#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 1833#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 1834#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 1835#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 1836#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 1837#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 1838#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 1839#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 1840#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 1841#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 1842#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 1843#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 1844#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 1845#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 1846#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 1847#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 1848#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 1849#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 1850#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 1851#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 1852#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 1853#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 1854#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 1855#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 1856#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 1857#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 1858#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 1859#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 1860//UVD_SOFT_RESET2 1861#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1862#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 1863#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 1864#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1865#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 1866#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 1867//UVD_MMSCH_SOFT_RESET 1868#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 1869#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 1870#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 1871#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 1872#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 1873#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 1874//UVD_CGC_GATE 1875#define UVD_CGC_GATE__SYS__SHIFT 0x0 1876#define UVD_CGC_GATE__UDEC__SHIFT 0x1 1877#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1878#define UVD_CGC_GATE__REGS__SHIFT 0x3 1879#define UVD_CGC_GATE__RBC__SHIFT 0x4 1880#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1881#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1882#define UVD_CGC_GATE__IDCT__SHIFT 0x7 1883#define UVD_CGC_GATE__MPRD__SHIFT 0x8 1884#define UVD_CGC_GATE__MPC__SHIFT 0x9 1885#define UVD_CGC_GATE__LBSI__SHIFT 0xa 1886#define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1887#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1888#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1889#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1890#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1891#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1892#define UVD_CGC_GATE__WCB__SHIFT 0x11 1893#define UVD_CGC_GATE__VCPU__SHIFT 0x12 1894#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 1895#define UVD_CGC_GATE__SYS_MASK 0x00000001L 1896#define UVD_CGC_GATE__UDEC_MASK 0x00000002L 1897#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 1898#define UVD_CGC_GATE__REGS_MASK 0x00000008L 1899#define UVD_CGC_GATE__RBC_MASK 0x00000010L 1900#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 1901#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 1902#define UVD_CGC_GATE__IDCT_MASK 0x00000080L 1903#define UVD_CGC_GATE__MPRD_MASK 0x00000100L 1904#define UVD_CGC_GATE__MPC_MASK 0x00000200L 1905#define UVD_CGC_GATE__LBSI_MASK 0x00000400L 1906#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 1907#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 1908#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 1909#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 1910#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 1911#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 1912#define UVD_CGC_GATE__WCB_MASK 0x00020000L 1913#define UVD_CGC_GATE__VCPU_MASK 0x00040000L 1914#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 1915//UVD_CGC_STATUS 1916#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1917#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1918#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1919#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1920#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1921#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1922#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1923#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1924#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1925#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 1926#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 1927#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 1928#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 1929#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 1930#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 1931#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 1932#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 1933#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 1934#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 1935#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 1936#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 1937#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 1938#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 1939#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 1940#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 1941#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 1942#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 1943#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 1944#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 1945#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 1946#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 1947#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 1948#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 1949#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 1950#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 1951#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 1952#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 1953#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 1954#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 1955#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 1956#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 1957#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 1958#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 1959#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 1960#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 1961#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 1962#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 1963#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 1964#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 1965#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 1966#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 1967#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 1968#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 1969#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 1970#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 1971#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 1972#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 1973#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 1974#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 1975#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 1976#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 1977#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 1978//UVD_CGC_CTRL 1979#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1980#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 1981#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 1982#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 1983#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 1984#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 1985#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 1986#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 1987#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 1988#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 1989#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 1990#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 1991#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 1992#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 1993#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 1994#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 1995#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 1996#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 1997#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 1998#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 1999#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2000#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2001#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 2002#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2003#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 2004#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 2005#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 2006#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 2007#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 2008#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 2009#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 2010#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 2011#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 2012#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 2013#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 2014#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 2015#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 2016#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 2017#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 2018#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 2019#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 2020#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 2021#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 2022#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 2023#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 2024#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 2025//UVD_CGC_UDEC_STATUS 2026#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2027#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2028#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2029#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 2030#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 2031#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 2032#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 2033#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 2034#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 2035#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 2036#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 2037#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 2038#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 2039#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 2040#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 2041#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 2042#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 2043#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 2044#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 2045#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 2046#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 2047#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2048#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2049#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2050#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2051#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2052#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2053#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2054#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2055#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2056//UVD_SUVD_CGC_GATE 2057#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 2058#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 2059#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 2060#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 2061#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 2062#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 2063#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 2064#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 2065#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 2066#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 2067#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 2068#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 2069#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 2070#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 2071#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 2072#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 2073#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 2074#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 2075#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 2076#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 2077#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 2078#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 2079#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 2080#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 2081#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 2082#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 2083#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 2084#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 2085#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 2086#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 2087#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 2088#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 2089#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 2090#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 2091#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 2092#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 2093#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 2094#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 2095#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 2096#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 2097#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 2098#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 2099#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 2100#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 2101#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 2102#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 2103#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 2104#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 2105#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 2106#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 2107#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 2108#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 2109//UVD_SUVD_CGC_STATUS 2110#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 2111#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 2112#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 2113#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 2114#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 2115#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 2116#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 2117#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 2118#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 2119#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 2120#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 2121#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 2122#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 2123#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 2124#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 2125#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 2126#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 2127#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 2128#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 2129#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 2130#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 2131#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 2132#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 2133#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 2134#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 2135#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 2136#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 2137#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 2138#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 2139#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 2140#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 2141#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 2142#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 2143#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 2144#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 2145#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 2146#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 2147#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 2148#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 2149#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 2150#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 2151#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 2152#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 2153#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 2154#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 2155#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 2156#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 2157#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 2158#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 2159#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 2160#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 2161#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 2162#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 2163#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 2164#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 2165#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 2166#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 2167#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 2168//UVD_SUVD_CGC_CTRL 2169#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2170#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2171#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2172#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2173#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2174#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2175#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2176#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2177#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2178#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2179#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2180#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2181#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2182#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2183#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2184#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2185#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2186#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2187#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2188#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2189#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2190#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2191//UVD_GPCOM_VCPU_CMD 2192#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 2193#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 2194#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 2195#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 2196#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 2197#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 2198//UVD_GPCOM_VCPU_DATA0 2199#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2200#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2201//UVD_GPCOM_VCPU_DATA1 2202#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2203#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2204//UVD_GPCOM_SYS_CMD 2205#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2206#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2207#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2208#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2209#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2210#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2211//UVD_GPCOM_SYS_DATA0 2212#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2213#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2214//UVD_GPCOM_SYS_DATA1 2215#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2216#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2217//UVD_VCPU_INT_EN 2218#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2219#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2220#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2221#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2222#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2223#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2224#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2225#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2226#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2227#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2228#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2229#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2230#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2231#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2232#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2233#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2234#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2235#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2236#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2237#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2238#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2239#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2240#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2241#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2242#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2243#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2244#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2245#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2246#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2247#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2248#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2249#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2250#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2251#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2252#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2253#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2254#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2255#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2256#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2257#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2258#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2259#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2260#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2261#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2262#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2263#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2264#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2265#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2266//UVD_VCPU_INT_ACK 2267#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2268#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2269#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2270#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 2271#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 2272#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 2273#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2274#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 2275#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 2276#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 2277#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 2278#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 2279#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 2280#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 2281#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 2282#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2283#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 2284#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 2285#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 2286#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2287#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2288#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2289#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 2290#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 2291#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2292#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2293#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2294#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 2295#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 2296#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 2297#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2298#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 2299#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 2300#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 2301#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 2302#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 2303#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 2304#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 2305#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 2306#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2307#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 2308#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 2309#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 2310#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2311#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2312#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2313#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 2314#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 2315//UVD_VCPU_INT_ROUTE 2316#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 2317#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 2318#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 2319#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 2320#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 2321#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 2322//UVD_ENC_VCPU_INT_EN 2323#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 2324#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 2325#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 2326#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 2327#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 2328#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 2329//UVD_ENC_VCPU_INT_ACK 2330#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 2331#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 2332#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 2333#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 2334#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 2335#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 2336//UVD_MASTINT_EN 2337#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2338#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 2339#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 2340#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2341#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2342#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 2343#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 2344#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2345//UVD_SYS_INT_EN 2346#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2347#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2348#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2349#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 2350#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2351#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 2352#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 2353#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 2354#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2355#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 2356#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 2357#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2358#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2359#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2360#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 2361#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2362#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2363#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2364#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 2365#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2366#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 2367#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 2368#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 2369#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2370#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 2371#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 2372#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2373#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2374#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2375#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 2376//UVD_SYS_INT_STATUS 2377#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2378#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2379#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2380#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 2381#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2382#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 2383#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 2384#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 2385#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 2386#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2387#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 2388#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 2389#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2390#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2391#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2392#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 2393#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2394#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2395#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2396#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 2397#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2398#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 2399#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 2400#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 2401#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 2402#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2403#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 2404#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 2405#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2406#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2407#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2408#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 2409//UVD_SYS_INT_ACK 2410#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2411#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2412#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2413#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 2414#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2415#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 2416#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 2417#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 2418#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2419#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 2420#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 2421#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2422#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2423#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2424#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 2425#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2426#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2427#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2428#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 2429#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2430#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 2431#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 2432#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 2433#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2434#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 2435#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 2436#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2437#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2438#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2439#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 2440//UVD_JOB_DONE 2441#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 2442#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 2443//UVD_CBUF_ID 2444#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 2445#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 2446//UVD_CONTEXT_ID 2447#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 2448#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 2449//UVD_CONTEXT_ID2 2450#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 2451#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 2452//UVD_NO_OP 2453#define UVD_NO_OP__NO_OP__SHIFT 0x0 2454#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 2455//UVD_RB_BASE_LO 2456#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2457#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2458//UVD_RB_BASE_HI 2459#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2460#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2461//UVD_RB_SIZE 2462#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 2463#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2464//UVD_RB_RPTR 2465#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 2466#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2467//UVD_RB_WPTR 2468#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 2469#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2470//UVD_RB_BASE_LO2 2471#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 2472#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 2473//UVD_RB_BASE_HI2 2474#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 2475#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 2476//UVD_RB_SIZE2 2477#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 2478#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 2479//UVD_RB_RPTR2 2480#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 2481#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 2482//UVD_RB_WPTR2 2483#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 2484#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 2485//UVD_RB_BASE_LO3 2486#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 2487#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 2488//UVD_RB_BASE_HI3 2489#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 2490#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 2491//UVD_RB_SIZE3 2492#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 2493#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 2494//UVD_RB_RPTR3 2495#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 2496#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 2497//UVD_RB_WPTR3 2498#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 2499#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 2500//UVD_RB_BASE_LO4 2501#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 2502#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 2503//UVD_RB_BASE_HI4 2504#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 2505#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 2506//UVD_RB_SIZE4 2507#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 2508#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 2509//UVD_RB_RPTR4 2510#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 2511#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 2512//UVD_RB_WPTR4 2513#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 2514#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 2515//UVD_OUT_RB_BASE_LO 2516#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2517#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2518//UVD_OUT_RB_BASE_HI 2519#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2520#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2521//UVD_OUT_RB_SIZE 2522#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 2523#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2524//UVD_OUT_RB_RPTR 2525#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 2526#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2527//UVD_OUT_RB_WPTR 2528#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 2529#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2530//UVD_RB_ARB_CTRL 2531#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 2532#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 2533#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 2534#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 2535#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 2536#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 2537#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 2538#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 2539#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 2540#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 2541#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 2542#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 2543#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 2544#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 2545#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 2546#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 2547#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 2548#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 2549//UVD_CTX_INDEX 2550#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 2551#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 2552//UVD_CTX_DATA 2553#define UVD_CTX_DATA__DATA__SHIFT 0x0 2554#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 2555//UVD_CXW_WR 2556#define UVD_CXW_WR__DAT__SHIFT 0x0 2557#define UVD_CXW_WR__STAT__SHIFT 0x1f 2558#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 2559#define UVD_CXW_WR__STAT_MASK 0x80000000L 2560//UVD_CXW_WR_INT_ID 2561#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 2562#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 2563//UVD_CXW_WR_INT_CTX_ID 2564#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 2565#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 2566//UVD_CXW_INT_ID 2567#define UVD_CXW_INT_ID__ID__SHIFT 0x0 2568#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 2569//UVD_TOP_CTRL 2570#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 2571#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 2572#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 2573#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 2574//UVD_YBASE 2575#define UVD_YBASE__DUM__SHIFT 0x0 2576#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 2577//UVD_UVBASE 2578#define UVD_UVBASE__DUM__SHIFT 0x0 2579#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 2580//UVD_PITCH 2581#define UVD_PITCH__DUM__SHIFT 0x0 2582#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 2583//UVD_WIDTH 2584#define UVD_WIDTH__DUM__SHIFT 0x0 2585#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 2586//UVD_HEIGHT 2587#define UVD_HEIGHT__DUM__SHIFT 0x0 2588#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 2589//UVD_PICCOUNT 2590#define UVD_PICCOUNT__DUM__SHIFT 0x0 2591#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 2592//UVD_SCRATCH_NP 2593#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 2594#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 2595//UVD_VERSION 2596#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 2597#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 2598#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 2599#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 2600//UVD_GP_SCRATCH0 2601#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 2602#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 2603//UVD_GP_SCRATCH1 2604#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 2605#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 2606//UVD_GP_SCRATCH2 2607#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 2608#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 2609//UVD_GP_SCRATCH3 2610#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 2611#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 2612//UVD_GP_SCRATCH4 2613#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 2614#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 2615//UVD_GP_SCRATCH5 2616#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 2617#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 2618//UVD_GP_SCRATCH6 2619#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 2620#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 2621//UVD_GP_SCRATCH7 2622#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 2623#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 2624//UVD_GP_SCRATCH8 2625#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 2626#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 2627//UVD_GP_SCRATCH9 2628#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 2629#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 2630//UVD_GP_SCRATCH10 2631#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 2632#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 2633//UVD_GP_SCRATCH11 2634#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 2635#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 2636//UVD_GP_SCRATCH12 2637#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 2638#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 2639//UVD_GP_SCRATCH13 2640#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 2641#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 2642//UVD_GP_SCRATCH14 2643#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 2644#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 2645//UVD_GP_SCRATCH15 2646#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 2647#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 2648//UVD_GP_SCRATCH16 2649#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 2650#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 2651//UVD_GP_SCRATCH17 2652#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 2653#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 2654//UVD_GP_SCRATCH18 2655#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 2656#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 2657//UVD_GP_SCRATCH19 2658#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 2659#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 2660//UVD_GP_SCRATCH20 2661#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 2662#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 2663//UVD_GP_SCRATCH21 2664#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 2665#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 2666//UVD_GP_SCRATCH22 2667#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 2668#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 2669//UVD_GP_SCRATCH23 2670#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 2671#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 2672 2673 2674// addressBlock: uvd0_ecpudec 2675//UVD_VCPU_CACHE_OFFSET0 2676#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2677#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 2678//UVD_VCPU_CACHE_SIZE0 2679#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 2680#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 2681//UVD_VCPU_CACHE_OFFSET1 2682#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 2683#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 2684//UVD_VCPU_CACHE_SIZE1 2685#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 2686#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 2687//UVD_VCPU_CACHE_OFFSET2 2688#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 2689#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 2690//UVD_VCPU_CACHE_SIZE2 2691#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 2692#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 2693//UVD_VCPU_CACHE_OFFSET3 2694#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 2695#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 2696//UVD_VCPU_CACHE_SIZE3 2697#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 2698#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 2699//UVD_VCPU_CACHE_OFFSET4 2700#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 2701#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 2702//UVD_VCPU_CACHE_SIZE4 2703#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 2704#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 2705//UVD_VCPU_CACHE_OFFSET5 2706#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 2707#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 2708//UVD_VCPU_CACHE_SIZE5 2709#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 2710#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 2711//UVD_VCPU_CACHE_OFFSET6 2712#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 2713#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 2714//UVD_VCPU_CACHE_SIZE6 2715#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 2716#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 2717//UVD_VCPU_CACHE_OFFSET7 2718#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 2719#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 2720//UVD_VCPU_CACHE_SIZE7 2721#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 2722#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 2723//UVD_VCPU_CACHE_OFFSET8 2724#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 2725#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 2726//UVD_VCPU_CACHE_SIZE8 2727#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 2728#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 2729//UVD_VCPU_NONCACHE_OFFSET0 2730#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 2731#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 2732//UVD_VCPU_NONCACHE_SIZE0 2733#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 2734#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 2735//UVD_VCPU_NONCACHE_OFFSET1 2736#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 2737#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 2738//UVD_VCPU_NONCACHE_SIZE1 2739#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 2740#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 2741//UVD_VCPU_CNTL 2742#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 2743#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 2744#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 2745#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 2746#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 2747#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 2748#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 2749#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 2750#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 2751#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 2752#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 2753#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 2754#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 2755#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 2756#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 2757#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 2758#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 2759#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 2760#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 2761#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 2762#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 2763#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 2764#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 2765#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 2766//UVD_VCPU_PRID 2767#define UVD_VCPU_PRID__PRID__SHIFT 0x0 2768#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 2769//UVD_VCPU_TRCE 2770#define UVD_VCPU_TRCE__PC__SHIFT 0x0 2771#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 2772//UVD_VCPU_TRCE_RD 2773#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 2774#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 2775 2776 2777// addressBlock: uvd0_uvd_mpcdec 2778//UVD_MP_SWAP_CNTL 2779#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2780#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2781#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2782#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2783#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2784#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2785#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2786#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2787#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2788#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2789#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2790#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2791#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2792#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2793#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2794#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2795#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2796#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2797#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2798#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2799#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2800#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2801#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2802#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2803#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2804#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2805#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2806#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2807#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2808#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2809#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2810#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2811//UVD_MPC_LUMA_SRCH 2812#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2813#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2814//UVD_MPC_LUMA_HIT 2815#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2816#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2817//UVD_MPC_LUMA_HITPEND 2818#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2819#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2820//UVD_MPC_CHROMA_SRCH 2821#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2822#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2823//UVD_MPC_CHROMA_HIT 2824#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2825#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2826//UVD_MPC_CHROMA_HITPEND 2827#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2828#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2829//UVD_MPC_CNTL 2830#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2831#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2832#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2833#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2834#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2835#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2836#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2837#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2838#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2839#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2840#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2841#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2842//UVD_MPC_PITCH 2843#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2844#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2845//UVD_MPC_SET_MUXA0 2846#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2847#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2848#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2849#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2850#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2851#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2852#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2853#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2854#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2855#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2856//UVD_MPC_SET_MUXA1 2857#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2858#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2859#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2860#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2861#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2862#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2863//UVD_MPC_SET_MUXB0 2864#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2865#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2866#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2867#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2868#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2869#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2870#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2871#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2872#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2873#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2874//UVD_MPC_SET_MUXB1 2875#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2876#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2877#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2878#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2879#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2880#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2881//UVD_MPC_SET_MUX 2882#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2883#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2884#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2885#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2886#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2887#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2888//UVD_MPC_SET_ALU 2889#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2890#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2891#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2892#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2893//UVD_MPC_PERF0 2894#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2895#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2896//UVD_MPC_PERF1 2897#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2898#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2899 2900 2901// addressBlock: uvd0_uvd_rbcdec 2902//UVD_RBC_IB_SIZE 2903#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2904#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2905//UVD_RBC_IB_SIZE_UPDATE 2906#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2907#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2908//UVD_RBC_RB_CNTL 2909#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 2910#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 2911#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 2912#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 2913#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 2914#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 2915#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 2916#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 2917#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 2918#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 2919#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 2920#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 2921//UVD_RBC_RB_RPTR_ADDR 2922#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 2923#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 2924//UVD_RBC_RB_RPTR 2925#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2926#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2927//UVD_RBC_RB_WPTR 2928#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2929#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2930//UVD_RBC_VCPU_ACCESS 2931#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 2932#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 2933//UVD_RBC_READ_REQ_URGENT_CNTL 2934#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2935#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2936//UVD_RBC_RB_WPTR_CNTL 2937#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 2938#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 2939//UVD_RBC_WPTR_STATUS 2940#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 2941#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 2942//UVD_RBC_WPTR_POLL_CNTL 2943#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 2944#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2945#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 2946#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2947//UVD_RBC_WPTR_POLL_ADDR 2948#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 2949#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 2950//UVD_SEMA_CMD 2951#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 2952#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 2953#define UVD_SEMA_CMD__MODE__SHIFT 0x6 2954#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 2955#define UVD_SEMA_CMD__VMID__SHIFT 0x8 2956#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 2957#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 2958#define UVD_SEMA_CMD__MODE_MASK 0x00000040L 2959#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 2960#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 2961//UVD_SEMA_ADDR_LOW 2962#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 2963#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 2964//UVD_SEMA_ADDR_HIGH 2965#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 2966#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 2967//UVD_ENGINE_CNTL 2968#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 2969#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 2970#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 2971#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 2972#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 2973#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 2974//UVD_SEMA_TIMEOUT_STATUS 2975#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 2976#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 2977#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 2978#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 2979#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 2980#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 2981#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 2982#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 2983//UVD_SEMA_CNTL 2984#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 2985#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 2986#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 2987#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 2988//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 2989#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 2990#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 2991#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2992#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 2993#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2994#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2995//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 2996#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 2997#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 2998#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2999#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 3000#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 3001#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3002//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 3003#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 3004#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 3005#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3006#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 3007#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3008#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3009//UVD_JOB_START 3010#define UVD_JOB_START__JOB_START__SHIFT 0x0 3011#define UVD_JOB_START__JOB_START_MASK 0x00000001L 3012//UVD_RBC_BUF_STATUS 3013#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3014#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3015#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3016#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3017#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3018#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3019#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3020#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3021#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3022#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3023#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3024#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3025 3026 3027// addressBlock: uvd0_uvdgendec 3028//UVD_LCM_CGC_CNTRL 3029#define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12 3030#define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13 3031#define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14 3032#define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c 3033#define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L 3034#define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L 3035#define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L 3036#define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L 3037 3038 3039// addressBlock: uvd0_lmi_adpdec 3040//UVD_LMI_RBC_RB_64BIT_BAR_LOW 3041#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3042#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3043//UVD_LMI_RBC_RB_64BIT_BAR_HIGH 3044#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3045#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3046//UVD_LMI_RBC_IB_64BIT_BAR_LOW 3047#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3048#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3049//UVD_LMI_RBC_IB_64BIT_BAR_HIGH 3050#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3051#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3052//UVD_LMI_LBSI_64BIT_BAR_LOW 3053#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3054#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3055//UVD_LMI_LBSI_64BIT_BAR_HIGH 3056#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3057#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3058//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 3059#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3060#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3061//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 3062#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3063#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3064//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 3065#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3066#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3067//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 3068#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3069#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3070//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 3071#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3072#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3073//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3074#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3075#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3076//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 3077#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3078#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3079//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 3080#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3081#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3082//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 3083#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3084#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3085//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 3086#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3087#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3088//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 3089#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3090#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3091//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 3092#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3093#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3094//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 3095#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3096#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3097//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 3098#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3099#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3100//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 3101#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3102#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3103//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 3104#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3105#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3106//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 3107#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3108#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3109//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 3110#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3111#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3112//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 3113#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3114#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3115//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 3116#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3117#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3118//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 3119#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3120#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3121//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 3122#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3123#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3124//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 3125#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3126#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3127//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 3128#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3129#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3130//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 3131#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3132#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3133//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 3134#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3135#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3136//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 3137#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3138#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3139//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 3140#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3141#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3142//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 3143#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3144#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3145//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 3146#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3147#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3148//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 3149#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3150#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3151//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 3152#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3153#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3154//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 3155#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3156#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3157//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 3158#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3159#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3160//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 3161#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3162#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3163//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 3164#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3165#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3166//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 3167#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3168#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3169//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 3170#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3171#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3172//UVD_LMI_MMSCH_NC_VMID 3173#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 3174#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 3175#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 3176#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 3177#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 3178#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 3179#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 3180#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 3181#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 3182#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 3183#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 3184#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 3185#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 3186#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 3187#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 3188#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 3189//UVD_LMI_MMSCH_CTRL 3190#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 3191#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 3192#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 3193#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 3194#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 3195#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 3196#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 3197#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 3198#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 3199#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 3200#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 3201#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 3202#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 3203#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 3204#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 3205#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 3206//UVD_LMI_ARB_CTRL2 3207#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 3208#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 3209#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 3210#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 3211#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 3212#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 3213#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 3214#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 3215#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 3216#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 3217#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 3218#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 3219//UVD_LMI_VCPU_CACHE_VMIDS_MULTI 3220#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 3221#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 3222#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 3223#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 3224#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 3225#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 3226#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 3227#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 3228#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 3229#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 3230#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 3231#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 3232#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 3233#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 3234#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 3235#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 3236//UVD_LMI_VCPU_NC_VMIDS_MULTI 3237#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 3238#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 3239#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 3240#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 3241#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 3242#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 3243#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 3244#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 3245#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 3246#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 3247#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 3248#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 3249//UVD_LMI_LAT_CTRL 3250#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 3251#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 3252#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 3253#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 3254#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 3255#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 3256#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 3257#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 3258#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 3259#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 3260#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 3261#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 3262//UVD_LMI_LAT_CNTR 3263#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 3264#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 3265#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 3266#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 3267//UVD_LMI_AVG_LAT_CNTR 3268#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 3269#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 3270#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 3271#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 3272#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 3273#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 3274//UVD_LMI_SPH 3275#define UVD_LMI_SPH__ADDR__SHIFT 0x0 3276#define UVD_LMI_SPH__STS__SHIFT 0x1c 3277#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 3278#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 3279#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 3280#define UVD_LMI_SPH__STS_MASK 0x30000000L 3281#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 3282#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 3283//UVD_LMI_VCPU_CACHE_VMID 3284#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 3285#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 3286//UVD_LMI_CTRL2 3287#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 3288#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 3289#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 3290#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 3291#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 3292#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 3293#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 3294#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 3295#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 3296#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 3297#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 3298#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 3299#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 3300#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 3301#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 3302#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 3303#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 3304#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 3305#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 3306#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 3307#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 3308#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 3309#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 3310#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 3311#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 3312#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 3313#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 3314#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 3315#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 3316#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 3317#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 3318#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 3319#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 3320#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 3321//UVD_LMI_URGENT_CTRL 3322#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 3323#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 3324#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 3325#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 3326#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 3327#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 3328#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 3329#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 3330#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 3331#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 3332#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 3333#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 3334#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 3335#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 3336#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 3337#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 3338#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 3339#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 3340#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 3341#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 3342#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 3343#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 3344#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 3345#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 3346//UVD_LMI_CTRL 3347#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 3348#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 3349#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 3350#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 3351#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 3352#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 3353#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 3354#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 3355#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 3356#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 3357#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 3358#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 3359#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 3360#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 3361#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 3362#define UVD_LMI_CTRL__RFU__SHIFT 0x1e 3363#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 3364#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 3365#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 3366#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 3367#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 3368#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 3369#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 3370#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 3371#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 3372#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 3373#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 3374#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 3375#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 3376#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 3377#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 3378#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 3379//UVD_LMI_STATUS 3380#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 3381#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 3382#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 3383#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 3384#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 3385#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 3386#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 3387#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 3388#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 3389#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 3390#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 3391#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 3392#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 3393#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 3394#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 3395#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 3396#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 3397#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 3398#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 3399#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 3400#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 3401#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 3402#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 3403#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 3404#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 3405#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 3406#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 3407#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 3408#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 3409#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 3410#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 3411#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 3412#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 3413#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 3414#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 3415#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 3416#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 3417#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 3418//UVD_LMI_PERFMON_CTRL 3419#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 3420#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 3421#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 3422#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 3423//UVD_LMI_PERFMON_COUNT_LO 3424#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 3425#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 3426//UVD_LMI_PERFMON_COUNT_HI 3427#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 3428#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 3429//UVD_LMI_RBC_RB_VMID 3430#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 3431#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 3432//UVD_LMI_RBC_IB_VMID 3433#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 3434#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 3435//UVD_LMI_MC_CREDITS 3436#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 3437#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 3438#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 3439#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 3440#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 3441#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 3442#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 3443#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 3444 3445 3446// addressBlock: uvd0_uvdnpdec 3447//MDM_DMA_CMD 3448#define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0 3449#define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL 3450//MDM_DMA_STATUS 3451#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0 3452#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1 3453#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2 3454#define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3 3455#define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4 3456#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5 3457#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6 3458#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L 3459#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L 3460#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L 3461#define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L 3462#define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L 3463#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L 3464#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L 3465//MDM_DMA_CTL 3466#define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0 3467#define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1 3468#define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2 3469#define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3 3470#define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f 3471#define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L 3472#define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L 3473#define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L 3474#define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L 3475#define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L 3476//MDM_ENC_PIPE_BUSY 3477#define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3478#define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3479#define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3480#define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3481#define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3482#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3483#define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3484#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3485#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3486#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3487#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3488#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3489#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc 3490#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd 3491#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3492#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3493#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3494#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3495#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3496#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3497#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3498#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3499#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3500#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3501#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3502#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3503#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3504#define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3505#define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3506#define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3507#define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3508#define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3509#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3510#define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3511#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3512#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3513#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3514#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3515#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3516#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L 3517#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L 3518#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3519#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3520#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3521#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3522#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3523#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3524#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3525#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3526#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3527#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3528#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3529#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3530#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3531//MDM_WIG_PIPE_BUSY 3532#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0 3533#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1 3534#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2 3535#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3 3536#define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4 3537#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5 3538#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6 3539#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7 3540#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8 3541#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9 3542#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa 3543#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb 3544#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc 3545#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd 3546#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe 3547#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf 3548#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10 3549#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11 3550#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12 3551#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13 3552#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14 3553#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15 3554#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16 3555#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17 3556#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18 3557#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19 3558#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a 3559#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b 3560#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c 3561#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d 3562#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L 3563#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L 3564#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L 3565#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L 3566#define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L 3567#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L 3568#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L 3569#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L 3570#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L 3571#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L 3572#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L 3573#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L 3574#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L 3575#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L 3576#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L 3577#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L 3578#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L 3579#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L 3580#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L 3581#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L 3582#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L 3583#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L 3584#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L 3585#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L 3586#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L 3587#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L 3588#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L 3589#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L 3590#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L 3591#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L 3592 3593 3594// addressBlock: lmi_adp_indirect 3595//UVD_LMI_CRC0 3596#define UVD_LMI_CRC0__CRC32__SHIFT 0x0 3597#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 3598//UVD_LMI_CRC1 3599#define UVD_LMI_CRC1__CRC32__SHIFT 0x0 3600#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 3601//UVD_LMI_CRC2 3602#define UVD_LMI_CRC2__CRC32__SHIFT 0x0 3603#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 3604//UVD_LMI_CRC3 3605#define UVD_LMI_CRC3__CRC32__SHIFT 0x0 3606#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 3607 3608 3609/* VCN 2_6_0 UVD_RAS_VCPU_VCODEC_STATUS */ 3610#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 3611#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f 3612#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3613#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L 3614 3615/* VCN 2_6_0 UVD_RAS_MMSCH_FATAL_ERROR */ 3616#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 3617#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f 3618#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL 3619#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L 3620 3621//VCN 2_6_0 VCN_RAS_CNTL 3622#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 3623#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 3624#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 3625#define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5 3626#define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 3627#define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9 3628#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc 3629#define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 3630#define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11 3631#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L 3632#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L 3633#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L 3634#define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L 3635#define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L 3636#define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L 3637#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L 3638#define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L 3639#define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L 3640 3641//VCN 2_6_0 UVD_VCPU_INT_EN 3642#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16 3643#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L 3644 3645//VCN 2_6_0 UVD_SYS_INT_EN 3646#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L 3647 3648/* JPEG 2_6_0 UVD_RAS_JPEG0_STATUS */ 3649#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 3650#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f 3651#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3652#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L 3653 3654/* JPEG 2_6_0 UVD_RAS_JPEG1_STATUS */ 3655#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 3656#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f 3657#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 3658#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L 3659 3660#endif 3661