#
037b98a2 |
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08-Nov-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move UVD and VCE sched entity init after sched init We need kernel scheduling entities to deal with handle clean up if apps are not cleaned up properly. With commit 56e449603f0ac5 ("drm/sched: Convert the GPU scheduler to variable number of run-queues") the scheduler entities have to be created after scheduler init, so change the ordering to fix this. v2: Leave logic in UVD and VCE code Fixes: 56e449603f0a ("drm/sched: Convert the GPU scheduler to variable number of run-queues") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <ltuikov89@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: ltuikov89@gmail.com
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#
db998890 |
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06-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Split up UVD suspend into prepare and suspend steps amdgpu_uvd_suspend() allocates memory and copies objects into that allocated memory. This fails under memory pressure. Instead move majority of this code into a prepare step when swap can still be allocated. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a788b54f |
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02-Aug-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amdgpu: Clean up errors in uvd_v7_0.c Fix the following errors reported by checkpatch: ERROR: spaces required around that ':' (ctx:VxE) that open brace { should be on the previous line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f4caf584 |
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14-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3) v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0530553b |
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19-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4) It looks better to place this field in ring structure. Also drop the repeated ring funcs definitions if there's no difference except for vmhub field. v2: rename the field to vm_hub like others (Le) v3: apply the changes to new ip blocks (Hawking) v4: fix vcn sw ring (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f7d66fb2 |
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28-Sep-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup scheduler job initialization v2 Init the DRM scheduler base class while allocating the job. This makes the whole handling much more cleaner. v2: fix coding style Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221014084641.128280-7-christian.koenig@amd.com
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#
3748424b |
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19-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: use ring structure to access rptr/wptr v2 Use ring structure to access the cpu/gpu address of rptr/wptr. v2: merge gfx10/sdma5/sdma5.2 patches Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cdc7893f |
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01-Mar-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use job and ib structures directly in CS parsers Instead of providing the ib index provide the job and ib pointers directly to the patch and parse functions for UVD and VCE. Also move the set/get functions for IB values to the IB declerations. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a190f8dc |
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21-Feb-2022 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: header cleanup No function change, just move a bunch of definitions from amdgpu.h into separate header files. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d82e2c24 |
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15-Sep-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix crash on device remove/driver unload Crash: BUG: unable to handle page fault for address: 00000000000010e1 RIP: 0010:vega10_power_gate_vce+0x26/0x50 [amdgpu] Call Trace: pp_set_powergating_by_smu+0x16a/0x2b0 [amdgpu] amdgpu_dpm_set_powergating_by_smu+0x92/0xf0 [amdgpu] amdgpu_dpm_enable_vce+0x2e/0xc0 [amdgpu] vce_v4_0_hw_fini+0x95/0xa0 [amdgpu] amdgpu_device_fini_hw+0x232/0x30d [amdgpu] amdgpu_driver_unload_kms+0x5c/0x80 [amdgpu] amdgpu_pci_remove+0x27/0x40 [amdgpu] pci_device_remove+0x3e/0xb0 device_release_driver_internal+0x103/0x1d0 device_release_driver+0x12/0x20 pci_stop_bus_device+0x79/0xa0 pci_stop_and_remove_bus_device_locked+0x1b/0x30 remove_store+0x7b/0x90 dev_attr_store+0x17/0x30 sysfs_kf_write+0x4b/0x60 kernfs_fop_write_iter+0x151/0x1e0 Why: VCE/UVD had dependency on SMC block for their suspend but SMC block is the first to do HW fini due to some constraints How: Since the original patch was dealing with suspend issues move the SMC block dependency back into suspend hooks as was done in V1 of the original patches. Keep flushing idle work both in suspend and HW fini seuqnces since it's essential in both cases. Fixes: 859e4659273f1d ("drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend") Fixes: bf756fb833cbe8 ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend") Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
68331d7c |
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09-Sep-2021 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: UVD avoid memory allocation during IB test move BO allocation in sw_init. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
859e4659 |
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18-Aug-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend This is a supplement for commit below: "drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend". Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f40801d |
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14-Apr-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: make sure we unpin the UVD BO Releasing pinned BOs is illegal now. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210415084730.2057-1-christian.koenig@amd.com
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#
c107171b |
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02-Feb-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add the sched_score to amdgpu_ring_init Allow separate ring to share the same scheduler score. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9ca0674a |
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28-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: remove redundant logic related HDP Remove hdp_flush function from amdgpu_nbio struct as it have been unified into hdp struct. Remove the include about hdp register which was not used. V2: Remove hdp golden setting which is unnecessary. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9307d1b0 |
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24-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/amdgpu/uvd_v7_0: Fix a bunch of kernel-doc function documentation issues Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:219: warning: Function parameter or member 'bo' not described in 'uvd_v7_0_enc_get_create_msg' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:219: warning: Excess function parameter 'adev' description in 'uvd_v7_0_enc_get_create_msg' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:282: warning: Function parameter or member 'bo' not described in 'uvd_v7_0_enc_get_destroy_msg' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:282: warning: Excess function parameter 'adev' description in 'uvd_v7_0_enc_get_destroy_msg' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:339: warning: Function parameter or member 'timeout' not described in 'uvd_v7_0_enc_ring_test_ib' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:527: warning: Function parameter or member 'handle' not described in 'uvd_v7_0_hw_init' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:527: warning: Excess function parameter 'adev' description in 'uvd_v7_0_hw_init' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:605: warning: Function parameter or member 'handle' not described in 'uvd_v7_0_hw_fini' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:605: warning: Excess function parameter 'adev' description in 'uvd_v7_0_hw_fini' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1156: warning: Function parameter or member 'addr' not described in 'uvd_v7_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1156: warning: Function parameter or member 'seq' not described in 'uvd_v7_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1156: warning: Function parameter or member 'flags' not described in 'uvd_v7_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1156: warning: Excess function parameter 'fence' description in 'uvd_v7_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1195: warning: Function parameter or member 'addr' not described in 'uvd_v7_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1195: warning: Function parameter or member 'seq' not described in 'uvd_v7_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1195: warning: Function parameter or member 'flags' not described in 'uvd_v7_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1195: warning: Excess function parameter 'fence' description in 'uvd_v7_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1293: warning: Function parameter or member 'job' not described in 'uvd_v7_0_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1293: warning: Function parameter or member 'flags' not described in 'uvd_v7_0_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1324: warning: Function parameter or member 'job' not described in 'uvd_v7_0_enc_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c:1324: warning: Function parameter or member 'flags' not described in 'uvd_v7_0_enc_ring_emit_ib' Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f349f772 |
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22-Sep-2020 |
Bernard Zhao <bernard@vivo.com> |
drm/amd: fix typoes in comments Change the comment typo: "programm" -> "program". Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2fcaca94 |
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01-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use register distance member instead of hardcode in UVD7/VCE4 This patch updates to use register distance member instead of hardcode in UVD7/VCE4. They are for the same ASIC. Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: AnZhong Huang <anzhong.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c6d567b |
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01-Apr-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: rework sched_list generation Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1675c3a2 |
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21-Feb-2020 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop disable the scheduler during HW fini When we stop the HW for example for GPU reset we should not stop the front-end scheduler. Otherwise we run into intermediate failures during command submission. The scheduler should only be stopped in very few cases: 1. We can't get the hardware working in ring or IB test after a GPU reset. 2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset. 3. In amdgpu_ring_fini() when the driver unloads. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Test-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8e42d57 |
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25-Mar-2020 |
xinhui pan <xinhui.pan@amd.com> |
drm/amdgpu: implement more ib pools (v2) We have three ib pools, they are normal, VM, direct pools. Any jobs which schedule IBs without dependence on gpu scheduler should use DIRECT pool. Any jobs schedule direct VM update IBs should use VM pool. Any other jobs use NORMAL pool. v2: squash in coding style fix Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
955df04e |
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24-Mar-2020 |
Chen Zhou <chenzhou10@huawei.com> |
drm/amdgpu/uvd7: remove unnecessary conversion to bool The conversion to bool is not needed, remove it. Signed-off-by: Chen Zhou <chenzhou10@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5d230bc9 |
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15-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd7: fix allocation size in enc ring test (v2) We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
b24c459f |
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15-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd7: fix allocation size in enc ring test (v2) We need to allocate a large enough buffer for the session info, otherwise the IB test can overwrite other memory. v2: - session info is 128K according to mesa - use the same session info for create and destroy Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2d15ed7 |
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16-Jul-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
517b91f4 |
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04-Jun-2019 |
Shirish S <shirish.s@amd.com> |
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc [What] readptr read always returns zero, since most likely these blocks are either power or clock gated. [How] fetch rptr after amdgpu_ring_alloc() which informs the power management code that the block is about to be used and hence the gating is turned off. Signed-off-by: Louis Li <Ching-shih.Li@amd.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
e038b901 |
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04-Jun-2019 |
Shirish S <shirish.s@amd.com> |
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc [What] readptr read always returns zero, since most likely these blocks are either power or clock gated. [How] fetch rptr after amdgpu_ring_alloc() which informs the power management code that the block is about to be used and hence the gating is turned off. Signed-off-by: Louis Li <Ching-shih.Li@amd.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47b757fb |
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09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in remaining files With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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#
c366be54 |
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09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop dependencies on drm_os_linux.h Fix so no files in drm/amd/ depends on the deprecated drm_os_linux.h header file. It was done manually: - remove drm_os_linux.h from drmP.h - fix all build errros Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-3-sam@ravnborg.org
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#
7ee250b1 |
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08-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/UVD: set no_user_fence flag to true There is no user fence support for UVD Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
992fbe8c |
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25-Feb-2019 |
Trigger Huang <Trigger.Huang@amd.com> |
drm/amdgpu: Use FW addr returned by PSP for VF MM One Vega10 SR-IOV VF, the FW address returned by PSP should be set into the init table, while not the original BO mc address. otherwise, UVD and VCE IB test will fail under Vega10 SR-IOV reference: commit bfcea5204287 ("drm/amdgpu:change VEGA booting with firmware loaded by PSP") commit aa5873dca463 ("drm/amdgpu: Change VCE booting with firmware loaded by PSP") Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4c905ec |
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18-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add flags to emit_ib interface v2 Replace the last bool type parameter with a general flags parameter, to make the last parameter be able to contain more information. v2: drop setting need_ctx_switch = false Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2bf55d2e |
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18-Dec-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/uvd:Change uvd ring name convention Since umr tool can't handle bracket, change uvd ring name convention. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b34c14f |
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16-Nov-2018 |
Chris Wilson <chris@chris-wilson.co.uk> |
drm/amdgpu: Reorder uvd ring init before uvd resume As amd_uvd_resume() accesses the uvd ring, it must be initialised first or else we trigger errors like: [ 5.595963] [drm] Found UVD firmware Version: 1.87 Family ID: 17 [ 5.595969] [drm] PSP loading UVD firmware [ 5.596266] ------------[ cut here ]------------ [ 5.596268] ODEBUG: assert_init not available (active state 0) object type: timer_list hint: (null) [ 5.596285] WARNING: CPU: 0 PID: 507 at lib/debugobjects.c:329 debug_print_object+0x6a/0x80 [ 5.596286] Modules linked in: amdgpu(+) hid_logitech_hidpp(+) chash gpu_sched amd_iommu_v2 ttm drm_kms_helper crc32c_intel drm hid_sony ff_memless igb hid_logitech_dj nvme dca i2c_algo_bit nvme_core wmi pinctrl_amd uas usb_storage [ 5.596299] CPU: 0 PID: 507 Comm: systemd-udevd Tainted: G W 4.20.0-0.rc1.git4.1.fc30.x86_64 #1 [ 5.596301] Hardware name: System manufacturer System Product Name/ROG STRIX X470-I GAMING, BIOS 0901 07/23/2018 [ 5.596303] RIP: 0010:debug_print_object+0x6a/0x80 [ 5.596305] Code: 8b 43 10 83 c2 01 8b 4b 14 4c 89 e6 89 15 e6 82 b0 02 4c 8b 45 00 48 c7 c7 60 fd 34 a6 48 8b 14 c5 a0 da 08 a6 e8 6a 6a b8 ff <0f> 0b 5b 83 05 d0 45 3e 01 01 5d 41 5c c3 83 05 c5 45 3e 01 01 c3 [ 5.596306] RSP: 0018:ffffa02ac863f8c0 EFLAGS: 00010282 [ 5.596307] RAX: 0000000000000000 RBX: ffffa02ac863f8e0 RCX: 0000000000000006 [ 5.596308] RDX: 0000000000000007 RSI: ffff9160e9a7bfe8 RDI: ffff9160f91d6c60 [ 5.596310] RBP: ffffffffa6742740 R08: 0000000000000002 R09: 0000000000000000 [ 5.596311] R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffa634ff69 [ 5.596312] R13: 00000000000b79d0 R14: ffffffffa80f76d8 R15: 0000000000266000 [ 5.596313] FS: 00007f762abf7940(0000) GS:ffff9160f9000000(0000) knlGS:0000000000000000 [ 5.596314] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 5.596315] CR2: 000055fdc593f000 CR3: 00000007e999c000 CR4: 00000000003406f0 [ 5.596317] Call Trace: [ 5.596321] debug_object_assert_init+0x14a/0x180 [ 5.596327] del_timer+0x2e/0x90 [ 5.596383] amdgpu_fence_process+0x47/0x100 [amdgpu] [ 5.596430] amdgpu_uvd_resume+0xf6/0x120 [amdgpu] [ 5.596475] uvd_v7_0_sw_init+0xe0/0x280 [amdgpu] [ 5.596523] amdgpu_device_init.cold.30+0xf97/0x14b6 [amdgpu] [ 5.596563] ? amdgpu_driver_load_kms+0x53/0x330 [amdgpu] [ 5.596604] amdgpu_driver_load_kms+0x86/0x330 [amdgpu] [ 5.596614] drm_dev_register+0x115/0x150 [drm] [ 5.596654] amdgpu_pci_probe+0xbd/0x120 [amdgpu] [ 5.596658] local_pci_probe+0x41/0x90 [ 5.596661] pci_device_probe+0x188/0x1a0 [ 5.596666] really_probe+0xf8/0x3b0 [ 5.596669] driver_probe_device+0xb3/0xf0 [ 5.596672] __driver_attach+0xe1/0x110 [ 5.596674] ? driver_probe_device+0xf0/0xf0 [ 5.596676] bus_for_each_dev+0x79/0xc0 [ 5.596679] bus_add_driver+0x155/0x230 [ 5.596681] ? 0xffffffffc07d9000 [ 5.596683] driver_register+0x6b/0xb0 [ 5.596685] ? 0xffffffffc07d9000 [ 5.596688] do_one_initcall+0x5d/0x2be [ 5.596691] ? rcu_read_lock_sched_held+0x79/0x80 [ 5.596693] ? kmem_cache_alloc_trace+0x264/0x290 [ 5.596695] ? do_init_module+0x22/0x210 [ 5.596698] do_init_module+0x5a/0x210 [ 5.596701] load_module+0x2137/0x2430 [ 5.596703] ? lockdep_hardirqs_on+0xed/0x180 [ 5.596714] ? __do_sys_init_module+0x150/0x1a0 [ 5.596715] __do_sys_init_module+0x150/0x1a0 [ 5.596722] do_syscall_64+0x60/0x1f0 [ 5.596725] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 5.596726] RIP: 0033:0x7f762b877dee [ 5.596728] Code: 48 8b 0d 9d 20 0c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 6a 20 0c 00 f7 d8 64 89 01 48 [ 5.596729] RSP: 002b:00007ffc777b8558 EFLAGS: 00000246 ORIG_RAX: 00000000000000af [ 5.596730] RAX: ffffffffffffffda RBX: 000055fdc48da320 RCX: 00007f762b877dee [ 5.596731] RDX: 00007f762b9f284d RSI: 00000000006c5fc6 RDI: 000055fdc527a060 [ 5.596732] RBP: 00007f762b9f284d R08: 0000000000000003 R09: 0000000000000002 [ 5.596733] R10: 000055fdc48ad010 R11: 0000000000000246 R12: 000055fdc527a060 [ 5.596734] R13: 000055fdc48dca20 R14: 0000000000020000 R15: 0000000000000000 [ 5.596740] irq event stamp: 134618 [ 5.596743] hardirqs last enabled at (134617): [<ffffffffa513d52e>] console_unlock+0x45e/0x610 [ 5.596744] hardirqs last disabled at (134618): [<ffffffffa50037e8>] trace_hardirqs_off_thunk+0x1a/0x1c [ 5.596746] softirqs last enabled at (133146): [<ffffffffa5e00365>] __do_softirq+0x365/0x47c [ 5.596748] softirqs last disabled at (133139): [<ffffffffa50c64f9>] irq_exit+0x119/0x120 [ 5.596749] ---[ end trace eaee508abfebccdc ]--- Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108709 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9564f192 |
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19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Use asic specific doorbell index instead of macro definition ASIC specific doorbell layout is used instead of enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
34955e03 |
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23-Oct-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Modify the argument of emit_ib interface use the point of struct amdgpu_job as the function argument instand of vmid, so the other members of struct amdgpu_job can be visit in emit_ib function. v2: add a wrapper for getting the VMID add the job before the ib on the parameter list. v3: refine the wrapper name Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
98079389 |
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29-Oct-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove messages from IB tests We already print an error message that an IB test failed in the common code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dc9eeff8 |
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29-Oct-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: further ring test cleanups Move all error messages from IP specific code into the common helper. This way we now uses the ring name in the messages instead of the index and note which device is affected as well. Also cleanup error handling in the IP specific code and consequently use ETIMEDOUT when the ring test timed out. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c66ed765 |
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19-Oct-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Retire amdgpu_ring.ready flag v4 Start using drm_gpu_scheduler.ready isntead. v3: Add helper function to run ring test and set sched.ready flag status accordingly, clean explicit sched.ready sets from the IP specific files. v4: Add kerneldoc and rebase. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ec442fd3 |
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28-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msg 1. make uvd_v7_0_enc_get_destroy_msg static 2. drop a function variable that always true Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bfcea520 |
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14-Aug-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:change VEGA booting with firmware loaded by PSP With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d4e83843 |
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14-Aug-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: added support 2nd UVD instance Added psp fw loading support for vega20 2nd UVD instance. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0d346a14 |
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19-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use entity instead of ring for CS Further demangle ring from entity handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
33d5bd07 |
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13-Aug-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu/uvd: UVD entity initialization relys on ring initialization Entity init should after ring init, as the entity's sched_rq's initialization is in ring init. SWDEV-161495 Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1e582eb |
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25-Jul-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: implement harvesting support for UVD 7.2 (v3) Properly handle cases where one or more instance of the IP block may be harvested. v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c v3: rebase on Christian's UVD changes, drop unused var Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
66c28d6d |
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18-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: patch the IBs for the second UVD instance v2 Patch the IBs for the second UVD instance so that userspace don't need to care about the instance they submit to. v2: use direct IB patching Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
58c24b7c |
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18-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove superflous UVD encode entity Not sure what that was every used for, but now it is completely unused. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee913fd9 |
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13-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add amdgpu_job_submit_direct helper Make sure that we properly initialize at least the sched member. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0e28b10f |
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13-Jul-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove ring parameter from amdgpu_job_submit We know the ring through the entity anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aa16b6c6 |
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13-Jul-2018 |
Nayan Deshmukh <nayan26deshmukh@gmail.com> |
drm/scheduler: modify args of drm_sched_entity_init replace run queue by a list of run queues and remove the sched arg as that is part of run queue itself Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
44a99b65 |
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25-May-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amd: Use newly added interrupt source defs for SOC15. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
180fc134 |
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04-Jun-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/scheduler: Rename cleanup functions v2. Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() This patch also effect the amdgpu and etnaviv drivers which use those functions. v2: Also pplay the change to vd3. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cbb7a239 |
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17-May-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: fix insert nop for UVD7 ring NO_OP register should be writen to 0 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b53a6ebc |
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23-Apr-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2 For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9181dba6 |
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11-May-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vg20:Enable the 2nd instance for uvd For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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10dd74ea |
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15-May-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2bb795f5 |
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15-May-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vg20:Restruct uvd to support multiple uvds Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8344c53f |
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29-Mar-2018 |
Nayan Deshmukh <nayan26deshmukh@gmail.com> |
drm/scheduler: remove unused parameter this patch also effect the amdgpu and etnaviv drivers which use the function drm_sched_entity_init Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Suggested-by: Christian König <christian.koenig@amd.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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996cab95 |
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07-May-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add HDP flush dummy for UVD 6/7 The UVD firmware doesn't seem to like the HDP flush here. This worked for years without HDP flush, so just skip it. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f3336254 |
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26-Apr-2018 |
Xiaojie Yuan <Xiaojie.Yuan@amd.com> |
drm/amdgpu/uvd7: add emit_reg_write_reg_wait ring callback Fix the NULL pointer dereference while running amdgpu_test: [ 54.972246] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [ 54.972265] IP: (null) [ 54.972273] PGD 0 P4D 0 [ 54.972280] Oops: 0010 [#1] SMP PTI [ 54.972288] Modules linked in: amdkfd amd_iommu_v2 amdgpu(OE) chash gpu_sched ttm drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep intel_rapl snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel snd_seq snd_seq_device kvm irqbypass snd_timer crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc snd soundcore joydev input_leds aesni_intel aes_x86_64 crypto_simd glue_helper cryptd idma64 virt_dma mei_me intel_lpss_pci serio_raw intel_cstate intel_rapl_perf shpchp intel_pch_thermal mei mac_hid intel_lpss acpi_pad parport_pc ppdev nfsd lp auth_rpcgss nfs_acl lockd grace sunrpc parport autofs4 hid_generic [ 54.972434] usbhid mxm_wmi e1000e psmouse ahci hid libahci wmi pinctrl_sunrisepoint video pinctrl_intel [ 54.972457] CPU: 6 PID: 1393 Comm: uvd Tainted: G OE 4.16.0-rc7-27fb84fda777 #1 [ 54.972473] Hardware name: MSI MS-7984/Z170 KRAIT GAMING (MS-7984), BIOS B.80 05/11/2016 [ 54.972489] RIP: 0010: (null) [ 54.972497] RSP: 0018:ffffaea002c8bcc0 EFLAGS: 00010202 [ 54.972508] RAX: 0000000000000000 RBX: ffff9d30d3c56f60 RCX: 00000000007c0002 [ 54.972522] RDX: 000000000001a6fb RSI: 000000000001a6e9 RDI: ffff9d30d3c56f60 [ 54.972536] RBP: ffffaea002c8bd10 R08: 0000000000000002 R09: ffffffffc06977d0 [ 54.972550] R10: 0000000000000040 R11: 0000000000000000 R12: 0000000000000002 [ 54.972564] R13: ffff9d30d3c5001c R14: ffff9d30d3c50000 R15: 0000000000000006 [ 54.972579] FS: 0000000000000000(0000) GS:ffff9d30eed80000(0000) knlGS:0000000000000000 [ 54.972594] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 54.972606] CR2: 0000000000000000 CR3: 00000002dbc0a001 CR4: 00000000003606e0 [ 54.972620] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 54.972634] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 54.972648] Call Trace: [ 54.972685] ? gmc_v9_0_emit_flush_gpu_tlb+0x111/0x140 [amdgpu] [ 54.972721] uvd_v7_0_ring_emit_vm_flush+0x31/0x70 [amdgpu] [ 54.972751] amdgpu_vm_flush+0x5dc/0x6c0 [amdgpu] [ 54.972787] ? pp_dpm_powergate_uvd+0x50/0x80 [amdgpu] [ 54.972816] amdgpu_ib_schedule+0x120/0x4e0 [amdgpu] [ 54.972850] amdgpu_job_run+0x17b/0x1c0 [amdgpu] [ 54.972861] drm_sched_main+0x2cc/0x490 [gpu_sched] [ 54.972873] ? wait_woken+0x80/0x80 [ 54.972882] kthread+0x121/0x140 [ 54.972891] ? drm_sched_job_finish+0xf0/0xf0 [gpu_sched] [ 54.972902] ? kthread_create_worker_on_cpu+0x70/0x70 [ 54.972914] ret_from_fork+0x35/0x40 [ 54.972922] Code: Bad RIP value. [ 54.972932] RIP: (null) RSP: ffffaea002c8bcc0 [ 54.972943] CR2: 0000000000000000 [ 54.972951] ---[ end trace 5feb349263bbf633 ]--- Signed-off-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ab0c9a7 |
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27-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd7: add emit_reg_write_reg_wait ring callback This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3760f76c |
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08-Mar-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Move IH clientid defs to separate file This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c633c00b |
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04-Feb-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: separate PASID mapping from VM flush v2 Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f732b6b3 |
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26-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
38d32a75 |
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26-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2 Add emit_reg_wait implementation for UVD v7. v2: call new function directly from the existing code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ee150cd |
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19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove now superflous *_hdp operation All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9096d6e5 |
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12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlb Unify tlb flushing for gmc v9. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6cb3b5c |
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12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: wire up emit_wreg for UVD v7 Needed for vm_flush unification. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5a4633c4 |
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08-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: forward pasid to backend flush implementations rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
132f34e4 |
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12-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move struct gart_funcs into amdgpu_gmc.h And rename it to struct gmc_funcs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4f46f22 |
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18-Dec-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename vm_id to vmid sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3de676d8 |
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29-Nov-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: allow get_vm_pde to change flags as well And also provide the level for which we need a PDE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4fd09a19 |
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29-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/admgpu: Reduce the usage of soc15ip.h Remove the header where it's not used. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cd29253f |
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29-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
946a4d5b |
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28-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b1f42d8 |
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06-Dec-2017 |
Lucas Stach <l.stach@pengutronix.de> |
drm: move amd_gpu_scheduler into common location This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fb960bd2 |
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23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 header files. Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
daad67b5 |
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23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 nbif header files. Cleanup asic_reg/vega10/NBIF folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
65417d9f |
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22-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 mmhub header files. Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
18297a21 |
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22-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 vce header files. Cleanup asic_reg/vega10/VCE folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5d735f83 |
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22-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 uvd header files. Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
75199b8c |
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15-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 hdp header files. Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1fe75c9 |
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10-Nov-2017 |
Piotr Redlewski <predlewski@gmail.com> |
drm/amd/amdgpu: fix UVD mc offsets When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Piotr Redlewski <predlewski@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9953b72f |
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25-Oct-2017 |
pding <Pixel.Ding@amd.com> |
drm/amdgpu: change redundant init logs to debug level When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: pding <Pixel.Ding@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b3eebe3d |
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22-Oct-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amd/scheduler:introduce guilty pointer member this member will be used later, it will points to the real var inside of context and CS_SUBMIT & gpu schdduler can decide if skip a job depends on context->guilty or *entity->guilty Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a0144bf |
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23-Oct-2017 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Remove workaround for suspend/resume in uvd7 The workaround is not required anymor and would result in hangs during suspend/resume cycles if the uvd block were busy. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6e2e216f |
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04-Jul-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:use formal register to trigger hdp invalidate Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
81fe3f35 |
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12-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV 1.Since in sriov there is no need of decoding, so skip the related code; 2.Vcpu boot up and umc enable need to take at the end of the init sequence; Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ed11d79 |
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11-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: According hardware design revert vce and uvd doorbell assignment Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a1b9022a |
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11-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: Skip uvd and vce ring test for SRIOV Since rptr would not be accessed on later secure asics in sriov, remove the ring test. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
257deb8c |
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15-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset Add uvd and vce re-init after gpu reset. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ab2b2e4f |
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11-Jun-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: Clear vce&uvd ring wptr for SRIOV MMSCH FW need to get the wptr from 0 after it get the mailbox request from driver, since every time kick the mailbox, mmsch thinks that it is the first time engine start to initialize. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ad5751a6 |
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12-Jun-2017 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
b1166325 |
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12-May-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup adjust_mc_addr handling v4 Rename adjust_mc_addr to get_vm_pde and check the address bits in one place. v2: handle vcn as well, keep setting the valid bit manually, add a BUG_ON() for GMC v6, v7 and v8 as well. v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well. v4: fix the BUG_ON mask for GFX6-8 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9a94f5a5 |
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12-May-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move adjust adjust_mc_addr into the GFX9 vm_flush functions That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b48622b0 |
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02-May-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: clean doorbell after sending init table to mmsch According to HW design, need to clean doorbell after setup MMSCH table. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5dd696ae |
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26-Apr-2017 |
Trigger Huang <trigger.huang@amd.com> |
drm/amdgpu: Bypass GMC/UVD/VCE hw_fini in SR-IOV On vega10, some hw finish operations should not be applied in SR-IOV case. This works as workaround to fix multi-VFs reboot/shutdown issues. Signed-off-by: Trigger Huang <trigger.huang@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6fa336a7 |
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16-Apr-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/uvd7: add UVD hw init sequences for sriov Add UVD hw init. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
beb2ced5 |
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16-Apr-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/uvd7: add uvd doorbell initialization for sriov Add UVD doorbell for SRIOV. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
247ac951 |
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16-Apr-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/uvd7: add sriov uvd initialization sequences Add UVD initialization for SRIOV. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4789c463 |
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31-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: assign VM invalidation engine manually v2 For Vega10 we have 18 VM invalidation engines for each VMHUB. Start to assign them manually to the rings. v2: add a BUG_ON if we use to many engines Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2e819849 |
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30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: invalidate only the currently needed VMHUB v2 Drop invalidating both hubs from each engine. v2: don't use hardcoded values Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0eeb68b3 |
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30-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add VMHUB to ring association Add the info which ring belonging to which VMHUB. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
03f89feb |
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04-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: cleanup get_invalidate_req v2 The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50237287 |
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30-Mar-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: various cleanups for uvd/vce. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
09bfb891 |
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03-Mar-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add initial uvd 7.0 support for vega10 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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