1/* 2 * UVD_3_1 Register documentation 3 * 4 * Copyright (C) 2020 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef UVD_3_1_SH_MASK_H 25#define UVD_3_1_SH_MASK_H 26 27#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35#define UVD_SEMA_CMD__MODE_MASK 0x40 36#define UVD_SEMA_CMD__MODE__SHIFT 0x6 37#define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39#define UVD_SEMA_CMD__VMID_MASK 0xf00 40#define UVD_SEMA_CMD__VMID__SHIFT 0x8 41#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 110#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 111#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 112#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 113#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 114#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 115#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 116#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 117#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 118#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 119#define UVD_CTX_INDEX__INDEX_MASK 0x1ff 120#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 121#define UVD_CTX_DATA__DATA_MASK 0xffffffff 122#define UVD_CTX_DATA__DATA__SHIFT 0x0 123#define UVD_CGC_GATE__SYS_MASK 0x1 124#define UVD_CGC_GATE__SYS__SHIFT 0x0 125#define UVD_CGC_GATE__UDEC_MASK 0x2 126#define UVD_CGC_GATE__UDEC__SHIFT 0x1 127#define UVD_CGC_GATE__MPEG2_MASK 0x4 128#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 129#define UVD_CGC_GATE__REGS_MASK 0x8 130#define UVD_CGC_GATE__REGS__SHIFT 0x3 131#define UVD_CGC_GATE__RBC_MASK 0x10 132#define UVD_CGC_GATE__RBC__SHIFT 0x4 133#define UVD_CGC_GATE__LMI_MC_MASK 0x20 134#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 135#define UVD_CGC_GATE__LMI_UMC_MASK 0x40 136#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 137#define UVD_CGC_GATE__IDCT_MASK 0x80 138#define UVD_CGC_GATE__IDCT__SHIFT 0x7 139#define UVD_CGC_GATE__MPRD_MASK 0x100 140#define UVD_CGC_GATE__MPRD__SHIFT 0x8 141#define UVD_CGC_GATE__MPC_MASK 0x200 142#define UVD_CGC_GATE__MPC__SHIFT 0x9 143#define UVD_CGC_GATE__LBSI_MASK 0x400 144#define UVD_CGC_GATE__LBSI__SHIFT 0xa 145#define UVD_CGC_GATE__LRBBM_MASK 0x800 146#define UVD_CGC_GATE__LRBBM__SHIFT 0xb 147#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 148#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 149#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 150#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 151#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 152#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 153#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 154#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 155#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 156#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 157#define UVD_CGC_GATE__WCB_MASK 0x20000 158#define UVD_CGC_GATE__WCB__SHIFT 0x11 159#define UVD_CGC_GATE__VCPU_MASK 0x40000 160#define UVD_CGC_GATE__VCPU__SHIFT 0x12 161#define UVD_CGC_GATE__SCPU_MASK 0x80000 162#define UVD_CGC_GATE__SCPU__SHIFT 0x13 163#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 164#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 165#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 166#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 167#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 168#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 169#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 170#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 171#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 172#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 173#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 174#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 175#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 176#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 177#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 178#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 179#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 180#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 181#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 182#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 183#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 184#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 185#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 186#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 187#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 188#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 189#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 190#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 191#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 192#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 193#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 194#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 195#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 196#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 197#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 198#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 199#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 200#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 201#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 202#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 203#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 204#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 205#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 206#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 207#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 208#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 209#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 210#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 211#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 212#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 213#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 214#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 215#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 216#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 217#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 218#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 219#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 220#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 221#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 222#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 223#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 224#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 225#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 226#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 227#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 228#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 229#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 230#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 231#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 232#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 233#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 234#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 235#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 236#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 237#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 238#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 239#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 240#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 241#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 242#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 243#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 244#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 245#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 246#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 247#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 248#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 249#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 250#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 251#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 252#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 253#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 254#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 255#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 256#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 257#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 258#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 259#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 260#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 261#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 262#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 263#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 264#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 265#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 266#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 267#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 268#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 269#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 270#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 271#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 272#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 273#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 274#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 275#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 276#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 277#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 278#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 279#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 280#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 281#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 282#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 283#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 284#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 285#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 286#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 287#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 288#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 289#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 290#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 291#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 292#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 293#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 294#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 295#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 296#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 297#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 298#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 299#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 300#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 301#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 302#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 303#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 304#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 305#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 306#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 307#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 308#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 309#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 310#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 311#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 312#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 313#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 314#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 315#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 316#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 317#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 318#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 319#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 320#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 321#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 322#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 323#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 324#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 325#define UVD_MASTINT_EN__SYS_EN_MASK 0x4 326#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 327#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 328#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 329#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 330#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 331#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 332#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 333#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 334#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 335#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 336#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 337#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 338#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 339#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 340#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 341#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 342#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 343#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 344#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 345#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 346#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 347#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 348#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 349#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 350#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 351#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 352#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 353#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 354#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 355#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 356#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 357#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 358#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 359#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 360#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 361#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 362#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 363#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 364#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 365#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 366#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 367#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 368#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 369#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 370#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 371#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 372#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 373#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 374#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 375#define UVD_LMI_CTRL__RFU_MASK 0xf8000000 376#define UVD_LMI_CTRL__RFU__SHIFT 0x1b 377#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 378#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 379#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 380#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 381#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 382#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 383#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 384#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 385#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 386#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 387#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 388#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 389#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 390#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 391#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 392#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 393#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 394#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 395#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 396#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 397#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 398#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 399#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 400#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 401#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 402#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 403#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 404#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 405#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 406#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 407#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 408#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 409#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 410#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 411#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 412#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 413#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 414#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 415#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 416#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 417#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 418#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 419#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 420#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 421#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 422#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 423#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 424#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 425#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 426#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 427#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 428#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 429#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 430#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 431#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 432#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 433#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 434#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 435#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 436#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 437#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 438#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 439#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 440#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 441#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 442#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 443#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 444#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 445#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 446#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 447#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 448#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 449#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 450#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 451#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 452#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 453#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 454#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 455#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 456#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 457#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 458#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 459#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 460#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 461#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 462#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 463#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 464#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 465#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 466#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 467#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 468#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 469#define UVD_MPC_CNTL__PERF_RST_MASK 0x40 470#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 471#define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 472#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 473#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 474#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 475#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 476#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 477#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 478#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 479#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 480#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 481#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 482#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 483#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 484#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 485#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 486#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 487#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 488#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 489#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 490#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 491#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 492#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 493#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 494#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 495#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 496#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 497#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 498#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 499#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 500#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 501#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 502#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 503#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 504#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 505#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 506#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 507#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 508#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 509#define UVD_MPC_SET_MUX__SET_0_MASK 0x7 510#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 511#define UVD_MPC_SET_MUX__SET_1_MASK 0x38 512#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 513#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 514#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 515#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 516#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 517#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 518#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 519#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 520#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 521#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 522#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 523#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 524#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 525#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 526#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 527#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 528#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 529#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 530#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 531#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 532#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 533#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 534#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 535#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 536#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 537#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 538#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 539#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 540#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 541#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 542#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 543#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 544#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 545#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 546#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 547#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 548#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 549#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 550#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 551#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 552#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 553#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 554#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 555#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 556#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 557#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 558#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 559#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 560#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 561#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 562#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d 563#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 564#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 565#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 566#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 567#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 568#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 569#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 570#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 571#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 572#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 573#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 574#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 575#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 576#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 577#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 578#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 579#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 580#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 581#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 582#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 583#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 584#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 585#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 586#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 587#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 588#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 589#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 590#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 591#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 592#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 593#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 594#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 595#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 596#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 597#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 598#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 599#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 600#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 601#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 602#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 603#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 604#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 605#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 606#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 607#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 608#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 609#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 610#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 611#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 612#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 613#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 614#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 615#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 616#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 617#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 618#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 619#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 620#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 621#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 622#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 623#define UVD_STATUS__RBC_BUSY_MASK 0x1 624#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 625#define UVD_STATUS__VCPU_REPORT_MASK 0xfe 626#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 627#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 628#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 629#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 630#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 631#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 632#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 633#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 634#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 635#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 636#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 637#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 638#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 639#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 640#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 641#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 642#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 643#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 644#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 645#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 646#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 647#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 648#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 649#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 650#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 651#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 652#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 653#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 654#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 655#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 656#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 657#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 658#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 659#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 660#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 661#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 662#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 663#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 664#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 665#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 666#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 667#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 668#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 669#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 670#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 671#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 672#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 673#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 674#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 675#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 676#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 677#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 678#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 679#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 680#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 681#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 682#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 683#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 684#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 685#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 686#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 687#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 688#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 689#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 690#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 691#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 692#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 693#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 694#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 695#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 696#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 697#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 698#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 699#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 700#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 701#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 702#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 703#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 704#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 705#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 706#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 707#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 708#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 709#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 710#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 711#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 712#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 713#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 714#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 715#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 716#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 717#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 718#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 719#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 720#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 721#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 722#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 723#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 724#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 725#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 726#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 727#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 728#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 729#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 730#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 731#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 732#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 733#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 734#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 735#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 736#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 737#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 738#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 739#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 740#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 741#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 742#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 743#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 744#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 745#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 746#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 747#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 748#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 749#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 750#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 751#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 752#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 753#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 754#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 755#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 756#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 757#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 758#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 759#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 760#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 761#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 762#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 763#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 764#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 765#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 766#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 767#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 768#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 769#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 770#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 771#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 772#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 773#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 774#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 775#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 776#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 777#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 778#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 779#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 780#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 781#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 782#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 783#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 784#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 785#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 786#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 787#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 788#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 789#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 790#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 791#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 792#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 793// UVD_FW_STATUS 794#define UVD_FW_STATUS__BUSY_MASK 0x00000001L 795#define UVD_FW_STATUS__ACTIVE_MASK 0x00000002L 796#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK 0x00000004L 797#define UVD_FW_STATUS__DONE_MASK 0x00000100L 798#define UVD_FW_STATUS__PASS_MASK 0x00010000L 799#define UVD_FW_STATUS__FAIL_MASK 0x00020000L 800#define UVD_FW_STATUS__INVALID_LEN_MASK 0x00040000L 801#define UVD_FW_STATUS__INVALID_0_PADDING_MASK 0x00080000L 802#define UVD_FW_STATUS__INVALID_NONCE_MASK 0x00100000L 803 804#endif /* UVD_3_1_SH_MASK_H */ 805