1/* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef _vcn_4_0_5_SH_MASK_HEADER 25#define _vcn_4_0_5_SH_MASK_HEADER 26 27 28// addressBlock: uvd_uvddec 29//UVD_CGC_GATE 30#define UVD_CGC_GATE__SYS__SHIFT 0x0 31#define UVD_CGC_GATE__UDEC__SHIFT 0x1 32#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 33#define UVD_CGC_GATE__REGS__SHIFT 0x3 34#define UVD_CGC_GATE__RBC__SHIFT 0x4 35#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 36#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 37#define UVD_CGC_GATE__IDCT__SHIFT 0x7 38#define UVD_CGC_GATE__MPRD__SHIFT 0x8 39#define UVD_CGC_GATE__MPC__SHIFT 0x9 40#define UVD_CGC_GATE__LBSI__SHIFT 0xa 41#define UVD_CGC_GATE__LRBBM__SHIFT 0xb 42#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 43#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 44#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 45#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 46#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 47#define UVD_CGC_GATE__WCB__SHIFT 0x11 48#define UVD_CGC_GATE__VCPU__SHIFT 0x12 49#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 50#define UVD_CGC_GATE__LCM0__SHIFT 0x15 51#define UVD_CGC_GATE__LCM1__SHIFT 0x16 52#define UVD_CGC_GATE__MIF__SHIFT 0x17 53#define UVD_CGC_GATE__VREG__SHIFT 0x18 54#define UVD_CGC_GATE__PE__SHIFT 0x19 55#define UVD_CGC_GATE__PPU__SHIFT 0x1a 56#define UVD_CGC_GATE__SYS_MASK 0x00000001L 57#define UVD_CGC_GATE__UDEC_MASK 0x00000002L 58#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 59#define UVD_CGC_GATE__REGS_MASK 0x00000008L 60#define UVD_CGC_GATE__RBC_MASK 0x00000010L 61#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 62#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 63#define UVD_CGC_GATE__IDCT_MASK 0x00000080L 64#define UVD_CGC_GATE__MPRD_MASK 0x00000100L 65#define UVD_CGC_GATE__MPC_MASK 0x00000200L 66#define UVD_CGC_GATE__LBSI_MASK 0x00000400L 67#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 68#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 69#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 70#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 71#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 72#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 73#define UVD_CGC_GATE__WCB_MASK 0x00020000L 74#define UVD_CGC_GATE__VCPU_MASK 0x00040000L 75#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 76#define UVD_CGC_GATE__LCM0_MASK 0x00200000L 77#define UVD_CGC_GATE__LCM1_MASK 0x00400000L 78#define UVD_CGC_GATE__MIF_MASK 0x00800000L 79#define UVD_CGC_GATE__VREG_MASK 0x01000000L 80#define UVD_CGC_GATE__PE_MASK 0x02000000L 81#define UVD_CGC_GATE__PPU_MASK 0x04000000L 82//UVD_CGC_CTRL 83#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 84#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 85#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 86#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 87#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 88#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 89#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 90#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 91#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 92#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 93#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 94#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 95#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 96#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 97#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 98#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 99#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 100#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 101#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 102#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 103#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 104#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 105#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 106#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 107#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 108#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 109#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 110#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 111#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 112#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 113#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 114#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 115#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 116#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 117#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 118#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 119#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 120#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 121#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 122#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 123#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 124#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 125#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 126#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 127#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 128#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 129//AVM_SUVD_CGC_GATE 130#define AVM_SUVD_CGC_GATE__SRE__SHIFT 0x0 131#define AVM_SUVD_CGC_GATE__SIT__SHIFT 0x1 132#define AVM_SUVD_CGC_GATE__SMP__SHIFT 0x2 133#define AVM_SUVD_CGC_GATE__SCM__SHIFT 0x3 134#define AVM_SUVD_CGC_GATE__SDB__SHIFT 0x4 135#define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 136#define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 137#define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 138#define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 139#define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 140#define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 141#define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 142#define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 143#define AVM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 144#define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 145#define AVM_SUVD_CGC_GATE__ENT__SHIFT 0xf 146#define AVM_SUVD_CGC_GATE__IME__SHIFT 0x10 147#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 148#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 149#define AVM_SUVD_CGC_GATE__SITE__SHIFT 0x13 150#define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 151#define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 152#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 153#define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 154#define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 155#define AVM_SUVD_CGC_GATE__EFC__SHIFT 0x19 156#define AVM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 157#define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 158#define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 159#define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 160#define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 161#define AVM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 162#define AVM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 163#define AVM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 164#define AVM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 165#define AVM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 166#define AVM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 167#define AVM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 168#define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 169#define AVM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 170#define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 171#define AVM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 172#define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 173#define AVM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 174#define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 175#define AVM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 176#define AVM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 177#define AVM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 178#define AVM_SUVD_CGC_GATE__IME_MASK 0x00010000L 179#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 180#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 181#define AVM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 182#define AVM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 183#define AVM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 184#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 185#define AVM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 186#define AVM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 187#define AVM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 188#define AVM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 189#define AVM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 190#define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 191#define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 192#define AVM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 193#define AVM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 194//CDEFE_SUVD_CGC_GATE 195#define CDEFE_SUVD_CGC_GATE__SRE__SHIFT 0x0 196#define CDEFE_SUVD_CGC_GATE__SIT__SHIFT 0x1 197#define CDEFE_SUVD_CGC_GATE__SMP__SHIFT 0x2 198#define CDEFE_SUVD_CGC_GATE__SCM__SHIFT 0x3 199#define CDEFE_SUVD_CGC_GATE__SDB__SHIFT 0x4 200#define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 201#define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 202#define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 203#define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 204#define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 205#define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 206#define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 207#define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 208#define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 209#define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 210#define CDEFE_SUVD_CGC_GATE__ENT__SHIFT 0xf 211#define CDEFE_SUVD_CGC_GATE__IME__SHIFT 0x10 212#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 213#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 214#define CDEFE_SUVD_CGC_GATE__SITE__SHIFT 0x13 215#define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 216#define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 217#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 218#define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 219#define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 220#define CDEFE_SUVD_CGC_GATE__EFC__SHIFT 0x19 221#define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 222#define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 223#define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 224#define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 225#define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 226#define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 227#define CDEFE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 228#define CDEFE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 229#define CDEFE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 230#define CDEFE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 231#define CDEFE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 232#define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 233#define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 234#define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 235#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 236#define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 237#define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 238#define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 239#define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 240#define CDEFE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 241#define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 242#define CDEFE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 243#define CDEFE_SUVD_CGC_GATE__IME_MASK 0x00010000L 244#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 245#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 246#define CDEFE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 247#define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 248#define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 249#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 250#define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 251#define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 252#define CDEFE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 253#define CDEFE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 254#define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 255#define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 256#define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 257#define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 258#define CDEFE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 259//EFC_SUVD_CGC_GATE 260#define EFC_SUVD_CGC_GATE__SRE__SHIFT 0x0 261#define EFC_SUVD_CGC_GATE__SIT__SHIFT 0x1 262#define EFC_SUVD_CGC_GATE__SMP__SHIFT 0x2 263#define EFC_SUVD_CGC_GATE__SCM__SHIFT 0x3 264#define EFC_SUVD_CGC_GATE__SDB__SHIFT 0x4 265#define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 266#define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 267#define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 268#define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 269#define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 270#define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 271#define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 272#define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 273#define EFC_SUVD_CGC_GATE__SCLR__SHIFT 0xd 274#define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 275#define EFC_SUVD_CGC_GATE__ENT__SHIFT 0xf 276#define EFC_SUVD_CGC_GATE__IME__SHIFT 0x10 277#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 278#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 279#define EFC_SUVD_CGC_GATE__SITE__SHIFT 0x13 280#define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 281#define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 282#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 283#define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 284#define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 285#define EFC_SUVD_CGC_GATE__EFC__SHIFT 0x19 286#define EFC_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 287#define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 288#define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 289#define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 290#define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 291#define EFC_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 292#define EFC_SUVD_CGC_GATE__SRE_MASK 0x00000001L 293#define EFC_SUVD_CGC_GATE__SIT_MASK 0x00000002L 294#define EFC_SUVD_CGC_GATE__SMP_MASK 0x00000004L 295#define EFC_SUVD_CGC_GATE__SCM_MASK 0x00000008L 296#define EFC_SUVD_CGC_GATE__SDB_MASK 0x00000010L 297#define EFC_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 298#define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 299#define EFC_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 300#define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 301#define EFC_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 302#define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 303#define EFC_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 304#define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 305#define EFC_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 306#define EFC_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 307#define EFC_SUVD_CGC_GATE__ENT_MASK 0x00008000L 308#define EFC_SUVD_CGC_GATE__IME_MASK 0x00010000L 309#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 310#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 311#define EFC_SUVD_CGC_GATE__SITE_MASK 0x00080000L 312#define EFC_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 313#define EFC_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 314#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 315#define EFC_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 316#define EFC_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 317#define EFC_SUVD_CGC_GATE__EFC_MASK 0x02000000L 318#define EFC_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 319#define EFC_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 320#define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 321#define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 322#define EFC_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 323#define EFC_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 324//ENT_SUVD_CGC_GATE 325#define ENT_SUVD_CGC_GATE__SRE__SHIFT 0x0 326#define ENT_SUVD_CGC_GATE__SIT__SHIFT 0x1 327#define ENT_SUVD_CGC_GATE__SMP__SHIFT 0x2 328#define ENT_SUVD_CGC_GATE__SCM__SHIFT 0x3 329#define ENT_SUVD_CGC_GATE__SDB__SHIFT 0x4 330#define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 331#define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 332#define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 333#define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 334#define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 335#define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 336#define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 337#define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 338#define ENT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 339#define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 340#define ENT_SUVD_CGC_GATE__ENT__SHIFT 0xf 341#define ENT_SUVD_CGC_GATE__IME__SHIFT 0x10 342#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 343#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 344#define ENT_SUVD_CGC_GATE__SITE__SHIFT 0x13 345#define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 346#define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 347#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 348#define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 349#define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 350#define ENT_SUVD_CGC_GATE__EFC__SHIFT 0x19 351#define ENT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 352#define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 353#define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 354#define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 355#define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 356#define ENT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 357#define ENT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 358#define ENT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 359#define ENT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 360#define ENT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 361#define ENT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 362#define ENT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 363#define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 364#define ENT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 365#define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 366#define ENT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 367#define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 368#define ENT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 369#define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 370#define ENT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 371#define ENT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 372#define ENT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 373#define ENT_SUVD_CGC_GATE__IME_MASK 0x00010000L 374#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 375#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 376#define ENT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 377#define ENT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 378#define ENT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 379#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 380#define ENT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 381#define ENT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 382#define ENT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 383#define ENT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 384#define ENT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 385#define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 386#define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 387#define ENT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 388#define ENT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 389//IME_SUVD_CGC_GATE 390#define IME_SUVD_CGC_GATE__SRE__SHIFT 0x0 391#define IME_SUVD_CGC_GATE__SIT__SHIFT 0x1 392#define IME_SUVD_CGC_GATE__SMP__SHIFT 0x2 393#define IME_SUVD_CGC_GATE__SCM__SHIFT 0x3 394#define IME_SUVD_CGC_GATE__SDB__SHIFT 0x4 395#define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 396#define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 397#define IME_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 398#define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 399#define IME_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 400#define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 401#define IME_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 402#define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 403#define IME_SUVD_CGC_GATE__SCLR__SHIFT 0xd 404#define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 405#define IME_SUVD_CGC_GATE__ENT__SHIFT 0xf 406#define IME_SUVD_CGC_GATE__IME__SHIFT 0x10 407#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 408#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 409#define IME_SUVD_CGC_GATE__SITE__SHIFT 0x13 410#define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 411#define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 412#define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 413#define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 414#define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 415#define IME_SUVD_CGC_GATE__EFC__SHIFT 0x19 416#define IME_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 417#define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 418#define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 419#define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 420#define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 421#define IME_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 422#define IME_SUVD_CGC_GATE__SRE_MASK 0x00000001L 423#define IME_SUVD_CGC_GATE__SIT_MASK 0x00000002L 424#define IME_SUVD_CGC_GATE__SMP_MASK 0x00000004L 425#define IME_SUVD_CGC_GATE__SCM_MASK 0x00000008L 426#define IME_SUVD_CGC_GATE__SDB_MASK 0x00000010L 427#define IME_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 428#define IME_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 429#define IME_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 430#define IME_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 431#define IME_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 432#define IME_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 433#define IME_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 434#define IME_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 435#define IME_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 436#define IME_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 437#define IME_SUVD_CGC_GATE__ENT_MASK 0x00008000L 438#define IME_SUVD_CGC_GATE__IME_MASK 0x00010000L 439#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 440#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 441#define IME_SUVD_CGC_GATE__SITE_MASK 0x00080000L 442#define IME_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 443#define IME_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 444#define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 445#define IME_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 446#define IME_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 447#define IME_SUVD_CGC_GATE__EFC_MASK 0x02000000L 448#define IME_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 449#define IME_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 450#define IME_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 451#define IME_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 452#define IME_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 453#define IME_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 454//PPU_SUVD_CGC_GATE 455#define PPU_SUVD_CGC_GATE__SRE__SHIFT 0x0 456#define PPU_SUVD_CGC_GATE__SIT__SHIFT 0x1 457#define PPU_SUVD_CGC_GATE__SMP__SHIFT 0x2 458#define PPU_SUVD_CGC_GATE__SCM__SHIFT 0x3 459#define PPU_SUVD_CGC_GATE__SDB__SHIFT 0x4 460#define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 461#define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 462#define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 463#define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 464#define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 465#define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 466#define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 467#define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 468#define PPU_SUVD_CGC_GATE__SCLR__SHIFT 0xd 469#define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 470#define PPU_SUVD_CGC_GATE__ENT__SHIFT 0xf 471#define PPU_SUVD_CGC_GATE__IME__SHIFT 0x10 472#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 473#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 474#define PPU_SUVD_CGC_GATE__SITE__SHIFT 0x13 475#define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 476#define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 477#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 478#define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 479#define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 480#define PPU_SUVD_CGC_GATE__EFC__SHIFT 0x19 481#define PPU_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 482#define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 483#define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 484#define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 485#define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 486#define PPU_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 487#define PPU_SUVD_CGC_GATE__SRE_MASK 0x00000001L 488#define PPU_SUVD_CGC_GATE__SIT_MASK 0x00000002L 489#define PPU_SUVD_CGC_GATE__SMP_MASK 0x00000004L 490#define PPU_SUVD_CGC_GATE__SCM_MASK 0x00000008L 491#define PPU_SUVD_CGC_GATE__SDB_MASK 0x00000010L 492#define PPU_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 493#define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 494#define PPU_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 495#define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 496#define PPU_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 497#define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 498#define PPU_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 499#define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 500#define PPU_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 501#define PPU_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 502#define PPU_SUVD_CGC_GATE__ENT_MASK 0x00008000L 503#define PPU_SUVD_CGC_GATE__IME_MASK 0x00010000L 504#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 505#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 506#define PPU_SUVD_CGC_GATE__SITE_MASK 0x00080000L 507#define PPU_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 508#define PPU_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 509#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 510#define PPU_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 511#define PPU_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 512#define PPU_SUVD_CGC_GATE__EFC_MASK 0x02000000L 513#define PPU_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 514#define PPU_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 515#define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 516#define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 517#define PPU_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 518#define PPU_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 519//SAOE_SUVD_CGC_GATE 520#define SAOE_SUVD_CGC_GATE__SRE__SHIFT 0x0 521#define SAOE_SUVD_CGC_GATE__SIT__SHIFT 0x1 522#define SAOE_SUVD_CGC_GATE__SMP__SHIFT 0x2 523#define SAOE_SUVD_CGC_GATE__SCM__SHIFT 0x3 524#define SAOE_SUVD_CGC_GATE__SDB__SHIFT 0x4 525#define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 526#define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 527#define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 528#define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 529#define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 530#define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 531#define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 532#define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 533#define SAOE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 534#define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 535#define SAOE_SUVD_CGC_GATE__ENT__SHIFT 0xf 536#define SAOE_SUVD_CGC_GATE__IME__SHIFT 0x10 537#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 538#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 539#define SAOE_SUVD_CGC_GATE__SITE__SHIFT 0x13 540#define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 541#define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 542#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 543#define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 544#define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 545#define SAOE_SUVD_CGC_GATE__EFC__SHIFT 0x19 546#define SAOE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 547#define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 548#define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 549#define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 550#define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 551#define SAOE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 552#define SAOE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 553#define SAOE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 554#define SAOE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 555#define SAOE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 556#define SAOE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 557#define SAOE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 558#define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 559#define SAOE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 560#define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 561#define SAOE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 562#define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 563#define SAOE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 564#define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 565#define SAOE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 566#define SAOE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 567#define SAOE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 568#define SAOE_SUVD_CGC_GATE__IME_MASK 0x00010000L 569#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 570#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 571#define SAOE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 572#define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 573#define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 574#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 575#define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 576#define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 577#define SAOE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 578#define SAOE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 579#define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 580#define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 581#define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 582#define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 583#define SAOE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 584//SCM_SUVD_CGC_GATE 585#define SCM_SUVD_CGC_GATE__SRE__SHIFT 0x0 586#define SCM_SUVD_CGC_GATE__SIT__SHIFT 0x1 587#define SCM_SUVD_CGC_GATE__SMP__SHIFT 0x2 588#define SCM_SUVD_CGC_GATE__SCM__SHIFT 0x3 589#define SCM_SUVD_CGC_GATE__SDB__SHIFT 0x4 590#define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 591#define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 592#define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 593#define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 594#define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 595#define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 596#define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 597#define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 598#define SCM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 599#define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 600#define SCM_SUVD_CGC_GATE__ENT__SHIFT 0xf 601#define SCM_SUVD_CGC_GATE__IME__SHIFT 0x10 602#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 603#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 604#define SCM_SUVD_CGC_GATE__SITE__SHIFT 0x13 605#define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 606#define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 607#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 608#define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 609#define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 610#define SCM_SUVD_CGC_GATE__EFC__SHIFT 0x19 611#define SCM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 612#define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 613#define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 614#define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 615#define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 616#define SCM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 617#define SCM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 618#define SCM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 619#define SCM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 620#define SCM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 621#define SCM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 622#define SCM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 623#define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 624#define SCM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 625#define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 626#define SCM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 627#define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 628#define SCM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 629#define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 630#define SCM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 631#define SCM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 632#define SCM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 633#define SCM_SUVD_CGC_GATE__IME_MASK 0x00010000L 634#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 635#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 636#define SCM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 637#define SCM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 638#define SCM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 639#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 640#define SCM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 641#define SCM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 642#define SCM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 643#define SCM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 644#define SCM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 645#define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 646#define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 647#define SCM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 648#define SCM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 649//SDB_SUVD_CGC_GATE 650#define SDB_SUVD_CGC_GATE__SRE__SHIFT 0x0 651#define SDB_SUVD_CGC_GATE__SIT__SHIFT 0x1 652#define SDB_SUVD_CGC_GATE__SMP__SHIFT 0x2 653#define SDB_SUVD_CGC_GATE__SCM__SHIFT 0x3 654#define SDB_SUVD_CGC_GATE__SDB__SHIFT 0x4 655#define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 656#define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 657#define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 658#define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 659#define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 660#define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 661#define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 662#define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 663#define SDB_SUVD_CGC_GATE__SCLR__SHIFT 0xd 664#define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 665#define SDB_SUVD_CGC_GATE__ENT__SHIFT 0xf 666#define SDB_SUVD_CGC_GATE__IME__SHIFT 0x10 667#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 668#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 669#define SDB_SUVD_CGC_GATE__SITE__SHIFT 0x13 670#define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 671#define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 672#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 673#define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 674#define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 675#define SDB_SUVD_CGC_GATE__EFC__SHIFT 0x19 676#define SDB_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 677#define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 678#define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 679#define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 680#define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 681#define SDB_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 682#define SDB_SUVD_CGC_GATE__SRE_MASK 0x00000001L 683#define SDB_SUVD_CGC_GATE__SIT_MASK 0x00000002L 684#define SDB_SUVD_CGC_GATE__SMP_MASK 0x00000004L 685#define SDB_SUVD_CGC_GATE__SCM_MASK 0x00000008L 686#define SDB_SUVD_CGC_GATE__SDB_MASK 0x00000010L 687#define SDB_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 688#define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 689#define SDB_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 690#define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 691#define SDB_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 692#define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 693#define SDB_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 694#define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 695#define SDB_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 696#define SDB_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 697#define SDB_SUVD_CGC_GATE__ENT_MASK 0x00008000L 698#define SDB_SUVD_CGC_GATE__IME_MASK 0x00010000L 699#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 700#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 701#define SDB_SUVD_CGC_GATE__SITE_MASK 0x00080000L 702#define SDB_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 703#define SDB_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 704#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 705#define SDB_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 706#define SDB_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 707#define SDB_SUVD_CGC_GATE__EFC_MASK 0x02000000L 708#define SDB_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 709#define SDB_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 710#define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 711#define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 712#define SDB_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 713#define SDB_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 714//SIT0_NXT_SUVD_CGC_GATE 715#define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 716#define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 717#define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 718#define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 719#define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 720#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 721#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 722#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 723#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 724#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 725#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 726#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 727#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 728#define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 729#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 730#define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 731#define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 732#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 733#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 734#define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 735#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 736#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 737#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 738#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 739#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 740#define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 741#define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 742#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 743#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 744#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 745#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 746#define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 747#define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 748#define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 749#define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 750#define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 751#define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 752#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 753#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 754#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 755#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 756#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 757#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 758#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 759#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 760#define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 761#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 762#define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 763#define SIT0_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 764#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 765#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 766#define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 767#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 768#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 769#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 770#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 771#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 772#define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 773#define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 774#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 775#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 776#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 777#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 778#define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 779//SIT1_NXT_SUVD_CGC_GATE 780#define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 781#define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 782#define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 783#define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 784#define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 785#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 786#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 787#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 788#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 789#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 790#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 791#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 792#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 793#define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 794#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 795#define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 796#define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 797#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 798#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 799#define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 800#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 801#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 802#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 803#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 804#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 805#define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 806#define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 807#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 808#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 809#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 810#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 811#define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 812#define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 813#define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 814#define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 815#define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 816#define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 817#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 818#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 819#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 820#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 821#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 822#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 823#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 824#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 825#define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 826#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 827#define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 828#define SIT1_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 829#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 830#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 831#define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 832#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 833#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 834#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 835#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 836#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 837#define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 838#define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 839#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 840#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 841#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 842#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 843#define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 844//SIT2_NXT_SUVD_CGC_GATE 845#define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 846#define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 847#define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 848#define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 849#define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 850#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 851#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 852#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 853#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 854#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 855#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 856#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 857#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 858#define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 859#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 860#define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 861#define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 862#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 863#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 864#define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 865#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 866#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 867#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 868#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 869#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 870#define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 871#define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 872#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 873#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 874#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 875#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 876#define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 877#define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 878#define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 879#define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 880#define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 881#define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 882#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 883#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 884#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 885#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 886#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 887#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 888#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 889#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 890#define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 891#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 892#define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 893#define SIT2_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 894#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 895#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 896#define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 897#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 898#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 899#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 900#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 901#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 902#define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 903#define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 904#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 905#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 906#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 907#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 908#define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 909//SIT_SUVD_CGC_GATE 910#define SIT_SUVD_CGC_GATE__SRE__SHIFT 0x0 911#define SIT_SUVD_CGC_GATE__SIT__SHIFT 0x1 912#define SIT_SUVD_CGC_GATE__SMP__SHIFT 0x2 913#define SIT_SUVD_CGC_GATE__SCM__SHIFT 0x3 914#define SIT_SUVD_CGC_GATE__SDB__SHIFT 0x4 915#define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 916#define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 917#define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 918#define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 919#define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 920#define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 921#define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 922#define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 923#define SIT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 924#define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 925#define SIT_SUVD_CGC_GATE__ENT__SHIFT 0xf 926#define SIT_SUVD_CGC_GATE__IME__SHIFT 0x10 927#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 928#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 929#define SIT_SUVD_CGC_GATE__SITE__SHIFT 0x13 930#define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 931#define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 932#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 933#define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 934#define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 935#define SIT_SUVD_CGC_GATE__EFC__SHIFT 0x19 936#define SIT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 937#define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 938#define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 939#define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 940#define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 941#define SIT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 942#define SIT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 943#define SIT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 944#define SIT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 945#define SIT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 946#define SIT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 947#define SIT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 948#define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 949#define SIT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 950#define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 951#define SIT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 952#define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 953#define SIT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 954#define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 955#define SIT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 956#define SIT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 957#define SIT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 958#define SIT_SUVD_CGC_GATE__IME_MASK 0x00010000L 959#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 960#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 961#define SIT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 962#define SIT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 963#define SIT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 964#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 965#define SIT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 966#define SIT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 967#define SIT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 968#define SIT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 969#define SIT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 970#define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 971#define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 972#define SIT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 973#define SIT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 974//SMPA_SUVD_CGC_GATE 975#define SMPA_SUVD_CGC_GATE__SRE__SHIFT 0x0 976#define SMPA_SUVD_CGC_GATE__SIT__SHIFT 0x1 977#define SMPA_SUVD_CGC_GATE__SMP__SHIFT 0x2 978#define SMPA_SUVD_CGC_GATE__SCM__SHIFT 0x3 979#define SMPA_SUVD_CGC_GATE__SDB__SHIFT 0x4 980#define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 981#define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 982#define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 983#define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 984#define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 985#define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 986#define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 987#define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 988#define SMPA_SUVD_CGC_GATE__SCLR__SHIFT 0xd 989#define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 990#define SMPA_SUVD_CGC_GATE__ENT__SHIFT 0xf 991#define SMPA_SUVD_CGC_GATE__IME__SHIFT 0x10 992#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 993#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 994#define SMPA_SUVD_CGC_GATE__SITE__SHIFT 0x13 995#define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 996#define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 997#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 998#define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 999#define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1000#define SMPA_SUVD_CGC_GATE__EFC__SHIFT 0x19 1001#define SMPA_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1002#define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1003#define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1004#define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1005#define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1006#define SMPA_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1007#define SMPA_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1008#define SMPA_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1009#define SMPA_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1010#define SMPA_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1011#define SMPA_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1012#define SMPA_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1013#define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1014#define SMPA_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1015#define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1016#define SMPA_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1017#define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1018#define SMPA_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1019#define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1020#define SMPA_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1021#define SMPA_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1022#define SMPA_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1023#define SMPA_SUVD_CGC_GATE__IME_MASK 0x00010000L 1024#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1025#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1026#define SMPA_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1027#define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1028#define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1029#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1030#define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1031#define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1032#define SMPA_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1033#define SMPA_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1034#define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1035#define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1036#define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1037#define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1038#define SMPA_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1039//SMP_SUVD_CGC_GATE 1040#define SMP_SUVD_CGC_GATE__SRE__SHIFT 0x0 1041#define SMP_SUVD_CGC_GATE__SIT__SHIFT 0x1 1042#define SMP_SUVD_CGC_GATE__SMP__SHIFT 0x2 1043#define SMP_SUVD_CGC_GATE__SCM__SHIFT 0x3 1044#define SMP_SUVD_CGC_GATE__SDB__SHIFT 0x4 1045#define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1046#define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1047#define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1048#define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1049#define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1050#define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1051#define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1052#define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1053#define SMP_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1054#define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1055#define SMP_SUVD_CGC_GATE__ENT__SHIFT 0xf 1056#define SMP_SUVD_CGC_GATE__IME__SHIFT 0x10 1057#define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1058#define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1059#define SMP_SUVD_CGC_GATE__SITE__SHIFT 0x13 1060#define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1061#define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1062#define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1063#define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1064#define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1065#define SMP_SUVD_CGC_GATE__EFC__SHIFT 0x19 1066#define SMP_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1067#define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1068#define SMP_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1069#define SMP_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1070#define SMP_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1071#define SMP_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1072#define SMP_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1073#define SMP_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1074#define SMP_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1075#define SMP_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1076#define SMP_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1077#define SMP_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1078#define SMP_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1079#define SMP_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1080#define SMP_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1081#define SMP_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1082#define SMP_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1083#define SMP_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1084#define SMP_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1085#define SMP_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1086#define SMP_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1087#define SMP_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1088#define SMP_SUVD_CGC_GATE__IME_MASK 0x00010000L 1089#define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1090#define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1091#define SMP_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1092#define SMP_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1093#define SMP_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1094#define SMP_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1095#define SMP_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1096#define SMP_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1097#define SMP_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1098#define SMP_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1099#define SMP_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1100#define SMP_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1101#define SMP_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1102#define SMP_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1103#define SMP_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1104//SRE_SUVD_CGC_GATE 1105#define SRE_SUVD_CGC_GATE__SRE__SHIFT 0x0 1106#define SRE_SUVD_CGC_GATE__SIT__SHIFT 0x1 1107#define SRE_SUVD_CGC_GATE__SMP__SHIFT 0x2 1108#define SRE_SUVD_CGC_GATE__SCM__SHIFT 0x3 1109#define SRE_SUVD_CGC_GATE__SDB__SHIFT 0x4 1110#define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1111#define SRE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1112#define SRE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1113#define SRE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1114#define SRE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1115#define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1116#define SRE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1117#define SRE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1118#define SRE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1119#define SRE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1120#define SRE_SUVD_CGC_GATE__ENT__SHIFT 0xf 1121#define SRE_SUVD_CGC_GATE__IME__SHIFT 0x10 1122#define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1123#define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1124#define SRE_SUVD_CGC_GATE__SITE__SHIFT 0x13 1125#define SRE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1126#define SRE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1127#define SRE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1128#define SRE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1129#define SRE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1130#define SRE_SUVD_CGC_GATE__EFC__SHIFT 0x19 1131#define SRE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1132#define SRE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1133#define SRE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1134#define SRE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1135#define SRE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1136#define SRE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1137#define SRE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1138#define SRE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1139#define SRE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1140#define SRE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1141#define SRE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1142#define SRE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1143#define SRE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1144#define SRE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1145#define SRE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1146#define SRE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1147#define SRE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1148#define SRE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1149#define SRE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1150#define SRE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1151#define SRE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1152#define SRE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1153#define SRE_SUVD_CGC_GATE__IME_MASK 0x00010000L 1154#define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1155#define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1156#define SRE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1157#define SRE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1158#define SRE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1159#define SRE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1160#define SRE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1161#define SRE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1162#define SRE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1163#define SRE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1164#define SRE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1165#define SRE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1166#define SRE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1167#define SRE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1168#define SRE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1169//UVD_MPBE0_SUVD_CGC_GATE 1170#define UVD_MPBE0_SUVD_CGC_GATE__SRE__SHIFT 0x0 1171#define UVD_MPBE0_SUVD_CGC_GATE__SIT__SHIFT 0x1 1172#define UVD_MPBE0_SUVD_CGC_GATE__SMP__SHIFT 0x2 1173#define UVD_MPBE0_SUVD_CGC_GATE__SCM__SHIFT 0x3 1174#define UVD_MPBE0_SUVD_CGC_GATE__SDB__SHIFT 0x4 1175#define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1176#define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1177#define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1178#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1179#define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1180#define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1181#define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1182#define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1183#define UVD_MPBE0_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1184#define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1185#define UVD_MPBE0_SUVD_CGC_GATE__ENT__SHIFT 0xf 1186#define UVD_MPBE0_SUVD_CGC_GATE__IME__SHIFT 0x10 1187#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1188#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1189#define UVD_MPBE0_SUVD_CGC_GATE__SITE__SHIFT 0x13 1190#define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1191#define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1192#define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1193#define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1194#define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1195#define UVD_MPBE0_SUVD_CGC_GATE__EFC__SHIFT 0x19 1196#define UVD_MPBE0_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1197#define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1198#define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1199#define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1200#define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1201#define UVD_MPBE0_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1202#define UVD_MPBE0_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1203#define UVD_MPBE0_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1204#define UVD_MPBE0_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1205#define UVD_MPBE0_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1206#define UVD_MPBE0_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1207#define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1208#define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1209#define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1210#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1211#define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1212#define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1213#define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1214#define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1215#define UVD_MPBE0_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1216#define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1217#define UVD_MPBE0_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1218#define UVD_MPBE0_SUVD_CGC_GATE__IME_MASK 0x00010000L 1219#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1220#define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1221#define UVD_MPBE0_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1222#define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1223#define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1224#define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1225#define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1226#define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1227#define UVD_MPBE0_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1228#define UVD_MPBE0_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1229#define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1230#define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1231#define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1232#define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1233#define UVD_MPBE0_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1234//UVD_MPBE1_SUVD_CGC_GATE 1235#define UVD_MPBE1_SUVD_CGC_GATE__SRE__SHIFT 0x0 1236#define UVD_MPBE1_SUVD_CGC_GATE__SIT__SHIFT 0x1 1237#define UVD_MPBE1_SUVD_CGC_GATE__SMP__SHIFT 0x2 1238#define UVD_MPBE1_SUVD_CGC_GATE__SCM__SHIFT 0x3 1239#define UVD_MPBE1_SUVD_CGC_GATE__SDB__SHIFT 0x4 1240#define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1241#define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1242#define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1243#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1244#define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1245#define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1246#define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1247#define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1248#define UVD_MPBE1_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1249#define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1250#define UVD_MPBE1_SUVD_CGC_GATE__ENT__SHIFT 0xf 1251#define UVD_MPBE1_SUVD_CGC_GATE__IME__SHIFT 0x10 1252#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1253#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1254#define UVD_MPBE1_SUVD_CGC_GATE__SITE__SHIFT 0x13 1255#define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1256#define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1257#define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1258#define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1259#define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1260#define UVD_MPBE1_SUVD_CGC_GATE__EFC__SHIFT 0x19 1261#define UVD_MPBE1_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1262#define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1263#define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1264#define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1265#define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1266#define UVD_MPBE1_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1267#define UVD_MPBE1_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1268#define UVD_MPBE1_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1269#define UVD_MPBE1_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1270#define UVD_MPBE1_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1271#define UVD_MPBE1_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1272#define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1273#define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1274#define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1275#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1276#define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1277#define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1278#define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1279#define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1280#define UVD_MPBE1_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1281#define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1282#define UVD_MPBE1_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1283#define UVD_MPBE1_SUVD_CGC_GATE__IME_MASK 0x00010000L 1284#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1285#define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1286#define UVD_MPBE1_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1287#define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1288#define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1289#define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1290#define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1291#define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1292#define UVD_MPBE1_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1293#define UVD_MPBE1_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1294#define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1295#define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1296#define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1297#define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1298#define UVD_MPBE1_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1299//UVD_SUVD_CGC_GATE 1300#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 1301#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 1302#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 1303#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 1304#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 1305#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1306#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1307#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1308#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1309#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1310#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1311#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1312#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1313#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1314#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1315#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 1316#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 1317#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1318#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1319#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 1320#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1321#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1322#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1323#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1324#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1325#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 1326#define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1327#define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1328#define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1329#define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1330#define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1331#define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1332#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1333#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1334#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1335#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1336#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1337#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1338#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1339#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1340#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1341#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1342#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1343#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1344#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1345#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1346#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1347#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1348#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 1349#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1350#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1351#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1352#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1353#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1354#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1355#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1356#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1357#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1358#define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1359#define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1360#define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1361#define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1362#define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1363#define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1364//AVM_SUVD_CGC_GATE2 1365#define AVM_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1366#define AVM_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1367#define AVM_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1368#define AVM_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1369#define AVM_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1370#define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1371#define AVM_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1372#define AVM_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1373#define AVM_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1374#define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1375#define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1376#define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1377#define AVM_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1378#define AVM_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1379#define AVM_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1380#define AVM_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1381#define AVM_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1382#define AVM_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1383#define AVM_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1384#define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1385#define AVM_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1386#define AVM_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1387#define AVM_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1388#define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1389#define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1390#define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1391//CDEFE_SUVD_CGC_GATE2 1392#define CDEFE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1393#define CDEFE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1394#define CDEFE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1395#define CDEFE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1396#define CDEFE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1397#define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1398#define CDEFE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1399#define CDEFE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1400#define CDEFE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1401#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1402#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1403#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1404#define CDEFE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1405#define CDEFE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1406#define CDEFE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1407#define CDEFE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1408#define CDEFE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1409#define CDEFE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1410#define CDEFE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1411#define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1412#define CDEFE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1413#define CDEFE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1414#define CDEFE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1415#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1416#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1417#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1418//DBR_SUVD_CGC_GATE2 1419#define DBR_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1420#define DBR_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1421#define DBR_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1422#define DBR_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1423#define DBR_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1424#define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1425#define DBR_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1426#define DBR_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1427#define DBR_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1428#define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1429#define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1430#define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1431#define DBR_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1432#define DBR_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1433#define DBR_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1434#define DBR_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1435#define DBR_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1436#define DBR_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1437#define DBR_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1438#define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1439#define DBR_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1440#define DBR_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1441#define DBR_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1442#define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1443#define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1444#define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1445//ENT_SUVD_CGC_GATE2 1446#define ENT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1447#define ENT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1448#define ENT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1449#define ENT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1450#define ENT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1451#define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1452#define ENT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1453#define ENT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1454#define ENT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1455#define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1456#define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1457#define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1458#define ENT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1459#define ENT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1460#define ENT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1461#define ENT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1462#define ENT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1463#define ENT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1464#define ENT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1465#define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1466#define ENT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1467#define ENT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1468#define ENT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1469#define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1470#define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1471#define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1472//IME_SUVD_CGC_GATE2 1473#define IME_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1474#define IME_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1475#define IME_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1476#define IME_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1477#define IME_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1478#define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1479#define IME_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1480#define IME_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1481#define IME_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1482#define IME_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1483#define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1484#define IME_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1485#define IME_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1486#define IME_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1487#define IME_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1488#define IME_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1489#define IME_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1490#define IME_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1491#define IME_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1492#define IME_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1493#define IME_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1494#define IME_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1495#define IME_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1496#define IME_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1497#define IME_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1498#define IME_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1499//MPC1_SUVD_CGC_GATE2 1500#define MPC1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1501#define MPC1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1502#define MPC1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1503#define MPC1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1504#define MPC1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1505#define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1506#define MPC1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1507#define MPC1_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1508#define MPC1_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1509#define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1510#define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1511#define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1512#define MPC1_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1513#define MPC1_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1514#define MPC1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1515#define MPC1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1516#define MPC1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1517#define MPC1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1518#define MPC1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1519#define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1520#define MPC1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1521#define MPC1_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1522#define MPC1_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1523#define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1524#define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1525#define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1526//SAOE_SUVD_CGC_GATE2 1527#define SAOE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1528#define SAOE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1529#define SAOE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1530#define SAOE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1531#define SAOE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1532#define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1533#define SAOE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1534#define SAOE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1535#define SAOE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1536#define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1537#define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1538#define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1539#define SAOE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1540#define SAOE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1541#define SAOE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1542#define SAOE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1543#define SAOE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1544#define SAOE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1545#define SAOE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1546#define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1547#define SAOE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1548#define SAOE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1549#define SAOE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1550#define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1551#define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1552#define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1553//SDB_SUVD_CGC_GATE2 1554#define SDB_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1555#define SDB_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1556#define SDB_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1557#define SDB_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1558#define SDB_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1559#define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1560#define SDB_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1561#define SDB_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1562#define SDB_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1563#define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1564#define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1565#define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1566#define SDB_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1567#define SDB_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1568#define SDB_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1569#define SDB_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1570#define SDB_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1571#define SDB_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1572#define SDB_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1573#define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1574#define SDB_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1575#define SDB_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1576#define SDB_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1577#define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1578#define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1579#define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1580//SIT0_NXT_SUVD_CGC_GATE2 1581#define SIT0_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1582#define SIT0_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1583#define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1584#define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1585#define SIT0_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1586#define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1587#define SIT0_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1588#define SIT0_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1589#define SIT0_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1590#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1591#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1592#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1593#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1594#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1595#define SIT0_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1596#define SIT0_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1597#define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1598#define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1599#define SIT0_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1600#define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1601#define SIT0_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1602#define SIT0_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1603#define SIT0_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1604#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1605#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1606#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1607//SIT1_NXT_SUVD_CGC_GATE2 1608#define SIT1_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1609#define SIT1_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1610#define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1611#define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1612#define SIT1_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1613#define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1614#define SIT1_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1615#define SIT1_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1616#define SIT1_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1617#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1618#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1619#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1620#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1621#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1622#define SIT1_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1623#define SIT1_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1624#define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1625#define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1626#define SIT1_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1627#define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1628#define SIT1_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1629#define SIT1_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1630#define SIT1_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1631#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1632#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1633#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1634//SIT2_NXT_SUVD_CGC_GATE2 1635#define SIT2_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1636#define SIT2_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1637#define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1638#define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1639#define SIT2_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1640#define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1641#define SIT2_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1642#define SIT2_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1643#define SIT2_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1644#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1645#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1646#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1647#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1648#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1649#define SIT2_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1650#define SIT2_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1651#define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1652#define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1653#define SIT2_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1654#define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1655#define SIT2_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1656#define SIT2_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1657#define SIT2_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1658#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1659#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1660#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1661//SIT_SUVD_CGC_GATE2 1662#define SIT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1663#define SIT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1664#define SIT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1665#define SIT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1666#define SIT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1667#define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1668#define SIT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1669#define SIT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1670#define SIT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1671#define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1672#define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1673#define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1674#define SIT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1675#define SIT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1676#define SIT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1677#define SIT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1678#define SIT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1679#define SIT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1680#define SIT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1681#define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1682#define SIT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1683#define SIT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1684#define SIT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1685#define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1686#define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1687#define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1688//SMPA_SUVD_CGC_GATE2 1689#define SMPA_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1690#define SMPA_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1691#define SMPA_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1692#define SMPA_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1693#define SMPA_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1694#define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1695#define SMPA_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1696#define SMPA_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1697#define SMPA_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1698#define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1699#define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1700#define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1701#define SMPA_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1702#define SMPA_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1703#define SMPA_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1704#define SMPA_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1705#define SMPA_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1706#define SMPA_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1707#define SMPA_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1708#define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1709#define SMPA_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1710#define SMPA_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1711#define SMPA_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1712#define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1713#define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1714#define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1715//SMP_SUVD_CGC_GATE2 1716#define SMP_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1717#define SMP_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1718#define SMP_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1719#define SMP_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1720#define SMP_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1721#define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1722#define SMP_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1723#define SMP_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1724#define SMP_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1725#define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1726#define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1727#define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1728#define SMP_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1729#define SMP_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1730#define SMP_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1731#define SMP_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1732#define SMP_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1733#define SMP_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1734#define SMP_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1735#define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1736#define SMP_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1737#define SMP_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1738#define SMP_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1739#define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1740#define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1741#define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1742//SRE_SUVD_CGC_GATE2 1743#define SRE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1744#define SRE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1745#define SRE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1746#define SRE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1747#define SRE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1748#define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1749#define SRE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1750#define SRE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1751#define SRE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1752#define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1753#define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1754#define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1755#define SRE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1756#define SRE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1757#define SRE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1758#define SRE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1759#define SRE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1760#define SRE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1761#define SRE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1762#define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1763#define SRE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1764#define SRE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1765#define SRE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1766#define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1767#define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1768#define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1769//UVD_MPBE0_SUVD_CGC_GATE2 1770#define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1771#define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1772#define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1773#define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1774#define UVD_MPBE0_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1775#define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1776#define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1777#define UVD_MPBE0_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1778#define UVD_MPBE0_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1779#define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1780#define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1781#define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1782#define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1783#define UVD_MPBE0_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1784#define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1785#define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1786//UVD_MPBE1_SUVD_CGC_GATE2 1787#define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1788#define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1789#define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1790#define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1791#define UVD_MPBE1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1792#define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1793#define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1794#define UVD_MPBE1_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1795#define UVD_MPBE1_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1796#define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1797#define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1798#define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1799#define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1800#define UVD_MPBE1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1801#define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1802#define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1803//UVD_SUVD_CGC_GATE2 1804#define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1805#define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1806#define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1807#define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1808#define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1809#define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1810#define UVD_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1811#define UVD_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1812#define UVD_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1813#define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1814#define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1815#define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1816#define UVD_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc 1817#define UVD_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd 1818#define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1819#define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1820#define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1821#define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1822#define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1823#define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1824#define UVD_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1825#define UVD_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1826#define UVD_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1827#define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1828#define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1829#define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1830//AVM_SUVD_CGC_CTRL 1831#define AVM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1832#define AVM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1833#define AVM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1834#define AVM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1835#define AVM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1836#define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1837#define AVM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1838#define AVM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1839#define AVM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1840#define AVM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1841#define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1842#define AVM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1843#define AVM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1844#define AVM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1845#define AVM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1846#define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1847#define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1848#define AVM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1849#define AVM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1850#define AVM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1851#define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1852#define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1853#define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1854#define AVM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1855#define AVM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1856#define AVM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1857#define AVM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1858#define AVM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1859#define AVM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1860#define AVM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1861#define AVM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1862#define AVM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1863#define AVM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1864#define AVM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1865#define AVM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1866#define AVM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1867#define AVM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1868#define AVM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1869#define AVM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1870#define AVM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1871#define AVM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1872#define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1873#define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1874#define AVM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1875#define AVM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1876#define AVM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1877#define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1878#define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1879#define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1880#define AVM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1881#define AVM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1882#define AVM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1883//CDEFE_SUVD_CGC_CTRL 1884#define CDEFE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1885#define CDEFE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1886#define CDEFE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1887#define CDEFE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1888#define CDEFE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1889#define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1890#define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1891#define CDEFE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1892#define CDEFE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1893#define CDEFE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1894#define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1895#define CDEFE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1896#define CDEFE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1897#define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1898#define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1899#define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1900#define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1901#define CDEFE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1902#define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1903#define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1904#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1905#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1906#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1907#define CDEFE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1908#define CDEFE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1909#define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1910#define CDEFE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1911#define CDEFE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1912#define CDEFE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1913#define CDEFE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1914#define CDEFE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1915#define CDEFE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1916#define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1917#define CDEFE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1918#define CDEFE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1919#define CDEFE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1920#define CDEFE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1921#define CDEFE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1922#define CDEFE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1923#define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1924#define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1925#define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1926#define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1927#define CDEFE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1928#define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1929#define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1930#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1931#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1932#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1933#define CDEFE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1934#define CDEFE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1935#define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1936//DBR_SUVD_CGC_CTRL 1937#define DBR_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1938#define DBR_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1939#define DBR_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1940#define DBR_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1941#define DBR_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1942#define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1943#define DBR_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1944#define DBR_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1945#define DBR_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1946#define DBR_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1947#define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1948#define DBR_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1949#define DBR_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1950#define DBR_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1951#define DBR_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1952#define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1953#define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1954#define DBR_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1955#define DBR_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1956#define DBR_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1957#define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1958#define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1959#define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1960#define DBR_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1961#define DBR_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1962#define DBR_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1963#define DBR_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1964#define DBR_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1965#define DBR_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1966#define DBR_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1967#define DBR_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1968#define DBR_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1969#define DBR_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1970#define DBR_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1971#define DBR_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1972#define DBR_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1973#define DBR_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1974#define DBR_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1975#define DBR_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1976#define DBR_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1977#define DBR_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1978#define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1979#define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1980#define DBR_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1981#define DBR_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1982#define DBR_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1983#define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1984#define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1985#define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1986#define DBR_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1987#define DBR_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1988#define DBR_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1989//EFC_SUVD_CGC_CTRL 1990#define EFC_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1991#define EFC_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1992#define EFC_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1993#define EFC_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1994#define EFC_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1995#define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1996#define EFC_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1997#define EFC_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1998#define EFC_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1999#define EFC_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2000#define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2001#define EFC_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2002#define EFC_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2003#define EFC_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2004#define EFC_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2005#define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2006#define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2007#define EFC_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2008#define EFC_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2009#define EFC_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2010#define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2011#define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2012#define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2013#define EFC_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2014#define EFC_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2015#define EFC_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2016#define EFC_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2017#define EFC_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2018#define EFC_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2019#define EFC_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2020#define EFC_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2021#define EFC_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2022#define EFC_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2023#define EFC_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2024#define EFC_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2025#define EFC_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2026#define EFC_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2027#define EFC_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2028#define EFC_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2029#define EFC_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2030#define EFC_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2031#define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2032#define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2033#define EFC_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2034#define EFC_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2035#define EFC_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2036#define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2037#define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2038#define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2039#define EFC_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2040#define EFC_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2041#define EFC_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2042//ENT_SUVD_CGC_CTRL 2043#define ENT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2044#define ENT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2045#define ENT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2046#define ENT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2047#define ENT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2048#define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2049#define ENT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2050#define ENT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2051#define ENT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2052#define ENT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2053#define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2054#define ENT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2055#define ENT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2056#define ENT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2057#define ENT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2058#define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2059#define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2060#define ENT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2061#define ENT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2062#define ENT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2063#define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2064#define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2065#define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2066#define ENT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2067#define ENT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2068#define ENT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2069#define ENT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2070#define ENT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2071#define ENT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2072#define ENT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2073#define ENT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2074#define ENT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2075#define ENT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2076#define ENT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2077#define ENT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2078#define ENT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2079#define ENT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2080#define ENT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2081#define ENT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2082#define ENT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2083#define ENT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2084#define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2085#define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2086#define ENT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2087#define ENT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2088#define ENT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2089#define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2090#define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2091#define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2092#define ENT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2093#define ENT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2094#define ENT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2095//IME_SUVD_CGC_CTRL 2096#define IME_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2097#define IME_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2098#define IME_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2099#define IME_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2100#define IME_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2101#define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2102#define IME_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2103#define IME_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2104#define IME_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2105#define IME_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2106#define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2107#define IME_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2108#define IME_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2109#define IME_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2110#define IME_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2111#define IME_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2112#define IME_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2113#define IME_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2114#define IME_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2115#define IME_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2116#define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2117#define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2118#define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2119#define IME_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2120#define IME_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2121#define IME_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2122#define IME_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2123#define IME_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2124#define IME_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2125#define IME_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2126#define IME_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2127#define IME_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2128#define IME_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2129#define IME_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2130#define IME_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2131#define IME_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2132#define IME_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2133#define IME_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2134#define IME_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2135#define IME_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2136#define IME_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2137#define IME_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2138#define IME_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2139#define IME_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2140#define IME_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2141#define IME_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2142#define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2143#define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2144#define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2145#define IME_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2146#define IME_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2147#define IME_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2148//MPC1_SUVD_CGC_CTRL 2149#define MPC1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2150#define MPC1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2151#define MPC1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2152#define MPC1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2153#define MPC1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2154#define MPC1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2155#define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2156#define MPC1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2157#define MPC1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2158#define MPC1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2159#define MPC1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2160#define MPC1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2161#define MPC1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2162#define MPC1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2163#define MPC1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2164#define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2165#define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2166#define MPC1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2167#define MPC1_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2168#define MPC1_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2169#define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2170#define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2171#define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2172#define MPC1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2173#define MPC1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2174#define MPC1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2175#define MPC1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2176#define MPC1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2177#define MPC1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2178#define MPC1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2179#define MPC1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2180#define MPC1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2181#define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2182#define MPC1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2183#define MPC1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2184#define MPC1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2185#define MPC1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2186#define MPC1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2187#define MPC1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2188#define MPC1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2189#define MPC1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2190#define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2191#define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2192#define MPC1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2193#define MPC1_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2194#define MPC1_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2195#define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2196#define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2197#define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2198#define MPC1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2199#define MPC1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2200#define MPC1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2201//PPU_SUVD_CGC_CTRL 2202#define PPU_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2203#define PPU_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2204#define PPU_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2205#define PPU_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2206#define PPU_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2207#define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2208#define PPU_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2209#define PPU_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2210#define PPU_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2211#define PPU_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2212#define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2213#define PPU_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2214#define PPU_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2215#define PPU_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2216#define PPU_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2217#define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2218#define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2219#define PPU_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2220#define PPU_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2221#define PPU_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2222#define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2223#define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2224#define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2225#define PPU_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2226#define PPU_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2227#define PPU_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2228#define PPU_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2229#define PPU_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2230#define PPU_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2231#define PPU_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2232#define PPU_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2233#define PPU_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2234#define PPU_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2235#define PPU_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2236#define PPU_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2237#define PPU_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2238#define PPU_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2239#define PPU_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2240#define PPU_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2241#define PPU_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2242#define PPU_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2243#define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2244#define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2245#define PPU_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2246#define PPU_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2247#define PPU_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2248#define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2249#define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2250#define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2251#define PPU_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2252#define PPU_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2253#define PPU_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2254//SAOE_SUVD_CGC_CTRL 2255#define SAOE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2256#define SAOE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2257#define SAOE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2258#define SAOE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2259#define SAOE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2260#define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2261#define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2262#define SAOE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2263#define SAOE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2264#define SAOE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2265#define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2266#define SAOE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2267#define SAOE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2268#define SAOE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2269#define SAOE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2270#define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2271#define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2272#define SAOE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2273#define SAOE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2274#define SAOE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2275#define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2276#define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2277#define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2278#define SAOE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2279#define SAOE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2280#define SAOE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2281#define SAOE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2282#define SAOE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2283#define SAOE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2284#define SAOE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2285#define SAOE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2286#define SAOE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2287#define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2288#define SAOE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2289#define SAOE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2290#define SAOE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2291#define SAOE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2292#define SAOE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2293#define SAOE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2294#define SAOE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2295#define SAOE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2296#define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2297#define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2298#define SAOE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2299#define SAOE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2300#define SAOE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2301#define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2302#define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2303#define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2304#define SAOE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2305#define SAOE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2306#define SAOE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2307//SCM_SUVD_CGC_CTRL 2308#define SCM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2309#define SCM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2310#define SCM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2311#define SCM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2312#define SCM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2313#define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2314#define SCM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2315#define SCM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2316#define SCM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2317#define SCM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2318#define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2319#define SCM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2320#define SCM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2321#define SCM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2322#define SCM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2323#define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2324#define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2325#define SCM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2326#define SCM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2327#define SCM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2328#define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2329#define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2330#define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2331#define SCM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2332#define SCM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2333#define SCM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2334#define SCM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2335#define SCM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2336#define SCM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2337#define SCM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2338#define SCM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2339#define SCM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2340#define SCM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2341#define SCM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2342#define SCM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2343#define SCM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2344#define SCM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2345#define SCM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2346#define SCM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2347#define SCM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2348#define SCM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2349#define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2350#define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2351#define SCM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2352#define SCM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2353#define SCM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2354#define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2355#define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2356#define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2357#define SCM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2358#define SCM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2359#define SCM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2360//SDB_SUVD_CGC_CTRL 2361#define SDB_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2362#define SDB_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2363#define SDB_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2364#define SDB_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2365#define SDB_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2366#define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2367#define SDB_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2368#define SDB_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2369#define SDB_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2370#define SDB_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2371#define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2372#define SDB_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2373#define SDB_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2374#define SDB_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2375#define SDB_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2376#define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2377#define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2378#define SDB_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2379#define SDB_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2380#define SDB_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2381#define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2382#define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2383#define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2384#define SDB_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2385#define SDB_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2386#define SDB_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2387#define SDB_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2388#define SDB_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2389#define SDB_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2390#define SDB_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2391#define SDB_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2392#define SDB_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2393#define SDB_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2394#define SDB_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2395#define SDB_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2396#define SDB_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2397#define SDB_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2398#define SDB_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2399#define SDB_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2400#define SDB_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2401#define SDB_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2402#define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2403#define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2404#define SDB_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2405#define SDB_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2406#define SDB_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2407#define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2408#define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2409#define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2410#define SDB_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2411#define SDB_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2412#define SDB_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2413//SIT0_NXT_SUVD_CGC_CTRL 2414#define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2415#define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2416#define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2417#define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2418#define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2419#define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2420#define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2421#define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2422#define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2423#define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2424#define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2425#define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2426#define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2427#define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2428#define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2429#define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2430#define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2431#define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2432#define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2433#define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2434#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2435#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2436#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2437#define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2438#define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2439#define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2440#define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2441#define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2442#define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2443#define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2444#define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2445#define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2446#define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2447#define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2448#define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2449#define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2450#define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2451#define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2452#define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2453#define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2454#define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2455#define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2456#define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2457#define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2458#define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2459#define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2460#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2461#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2462#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2463#define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2464#define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2465#define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2466//SIT1_NXT_SUVD_CGC_CTRL 2467#define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2468#define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2469#define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2470#define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2471#define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2472#define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2473#define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2474#define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2475#define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2476#define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2477#define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2478#define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2479#define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2480#define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2481#define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2482#define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2483#define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2484#define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2485#define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2486#define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2487#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2488#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2489#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2490#define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2491#define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2492#define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2493#define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2494#define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2495#define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2496#define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2497#define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2498#define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2499#define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2500#define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2501#define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2502#define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2503#define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2504#define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2505#define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2506#define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2507#define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2508#define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2509#define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2510#define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2511#define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2512#define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2513#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2514#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2515#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2516#define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2517#define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2518#define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2519//SIT2_NXT_SUVD_CGC_CTRL 2520#define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2521#define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2522#define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2523#define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2524#define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2525#define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2526#define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2527#define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2528#define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2529#define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2530#define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2531#define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2532#define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2533#define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2534#define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2535#define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2536#define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2537#define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2538#define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2539#define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2540#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2541#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2542#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2543#define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2544#define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2545#define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2546#define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2547#define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2548#define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2549#define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2550#define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2551#define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2552#define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2553#define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2554#define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2555#define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2556#define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2557#define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2558#define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2559#define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2560#define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2561#define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2562#define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2563#define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2564#define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2565#define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2566#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2567#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2568#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2569#define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2570#define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2571#define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2572//SIT_SUVD_CGC_CTRL 2573#define SIT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2574#define SIT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2575#define SIT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2576#define SIT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2577#define SIT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2578#define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2579#define SIT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2580#define SIT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2581#define SIT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2582#define SIT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2583#define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2584#define SIT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2585#define SIT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2586#define SIT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2587#define SIT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2588#define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2589#define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2590#define SIT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2591#define SIT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2592#define SIT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2593#define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2594#define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2595#define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2596#define SIT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2597#define SIT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2598#define SIT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2599#define SIT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2600#define SIT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2601#define SIT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2602#define SIT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2603#define SIT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2604#define SIT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2605#define SIT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2606#define SIT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2607#define SIT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2608#define SIT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2609#define SIT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2610#define SIT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2611#define SIT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2612#define SIT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2613#define SIT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2614#define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2615#define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2616#define SIT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2617#define SIT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2618#define SIT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2619#define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2620#define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2621#define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2622#define SIT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2623#define SIT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2624#define SIT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2625//SMPA_SUVD_CGC_CTRL 2626#define SMPA_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2627#define SMPA_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2628#define SMPA_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2629#define SMPA_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2630#define SMPA_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2631#define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2632#define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2633#define SMPA_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2634#define SMPA_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2635#define SMPA_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2636#define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2637#define SMPA_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2638#define SMPA_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2639#define SMPA_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2640#define SMPA_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2641#define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2642#define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2643#define SMPA_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2644#define SMPA_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2645#define SMPA_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2646#define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2647#define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2648#define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2649#define SMPA_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2650#define SMPA_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2651#define SMPA_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2652#define SMPA_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2653#define SMPA_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2654#define SMPA_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2655#define SMPA_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2656#define SMPA_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2657#define SMPA_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2658#define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2659#define SMPA_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2660#define SMPA_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2661#define SMPA_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2662#define SMPA_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2663#define SMPA_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2664#define SMPA_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2665#define SMPA_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2666#define SMPA_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2667#define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2668#define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2669#define SMPA_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2670#define SMPA_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2671#define SMPA_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2672#define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2673#define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2674#define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2675#define SMPA_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2676#define SMPA_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2677#define SMPA_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2678//SMP_SUVD_CGC_CTRL 2679#define SMP_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2680#define SMP_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2681#define SMP_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2682#define SMP_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2683#define SMP_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2684#define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2685#define SMP_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2686#define SMP_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2687#define SMP_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2688#define SMP_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2689#define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2690#define SMP_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2691#define SMP_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2692#define SMP_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2693#define SMP_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2694#define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2695#define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2696#define SMP_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2697#define SMP_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2698#define SMP_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2699#define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2700#define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2701#define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2702#define SMP_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2703#define SMP_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2704#define SMP_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2705#define SMP_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2706#define SMP_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2707#define SMP_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2708#define SMP_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2709#define SMP_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2710#define SMP_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2711#define SMP_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2712#define SMP_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2713#define SMP_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2714#define SMP_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2715#define SMP_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2716#define SMP_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2717#define SMP_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2718#define SMP_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2719#define SMP_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2720#define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2721#define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2722#define SMP_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2723#define SMP_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2724#define SMP_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2725#define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2726#define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2727#define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2728#define SMP_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2729#define SMP_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2730#define SMP_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2731//SRE_SUVD_CGC_CTRL 2732#define SRE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2733#define SRE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2734#define SRE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2735#define SRE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2736#define SRE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2737#define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2738#define SRE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2739#define SRE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2740#define SRE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2741#define SRE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2742#define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2743#define SRE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2744#define SRE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2745#define SRE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2746#define SRE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2747#define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2748#define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2749#define SRE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2750#define SRE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2751#define SRE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2752#define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2753#define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2754#define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2755#define SRE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2756#define SRE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2757#define SRE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2758#define SRE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2759#define SRE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2760#define SRE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2761#define SRE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2762#define SRE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2763#define SRE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2764#define SRE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2765#define SRE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2766#define SRE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2767#define SRE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2768#define SRE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2769#define SRE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2770#define SRE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2771#define SRE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2772#define SRE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2773#define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2774#define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2775#define SRE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2776#define SRE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2777#define SRE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2778#define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2779#define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2780#define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2781#define SRE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2782#define SRE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2783#define SRE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2784//UVD_MPBE0_SUVD_CGC_CTRL 2785#define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2786#define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2787#define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2788#define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2789#define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2790#define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2791#define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2792#define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2793#define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2794#define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2795#define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2796#define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2797#define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2798#define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2799#define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2800#define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2801#define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2802#define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2803#define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2804#define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2805#define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2806#define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2807#define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2808#define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2809#define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2810#define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2811#define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2812#define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2813#define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2814#define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2815#define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2816#define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2817#define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2818#define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2819#define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2820#define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2821#define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2822#define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2823#define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2824#define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2825#define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2826#define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2827//UVD_MPBE1_SUVD_CGC_CTRL 2828#define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2829#define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2830#define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2831#define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2832#define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2833#define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2834#define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2835#define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2836#define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2837#define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2838#define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2839#define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2840#define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2841#define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2842#define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2843#define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2844#define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2845#define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2846#define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2847#define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2848#define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2849#define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2850#define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2851#define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2852#define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2853#define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2854#define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2855#define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2856#define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2857#define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2858#define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2859#define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2860#define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2861#define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2862#define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2863#define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2864#define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2865#define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2866#define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2867#define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2868#define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2869#define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2870//UVD_SUVD_CGC_CTRL 2871#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2872#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2873#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2874#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2875#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2876#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2877#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2878#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2879#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2880#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2881#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2882#define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2883#define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2884#define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2885#define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2886#define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2887#define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2888#define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2889#define UVD_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2890#define UVD_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2891#define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2892#define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2893#define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2894#define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2895#define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2896#define UVD_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2897#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2898#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2899#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2900#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2901#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2902#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2903#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2904#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2905#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2906#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2907#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2908#define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2909#define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2910#define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2911#define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2912#define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2913#define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2914#define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2915#define UVD_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2916#define UVD_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2917#define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2918#define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2919#define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2920#define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2921#define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2922#define UVD_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2923//UVD_CGC_CTRL3 2924#define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY__SHIFT 0x0 2925#define UVD_CGC_CTRL3__LCM0_MODE__SHIFT 0xb 2926#define UVD_CGC_CTRL3__LCM1_MODE__SHIFT 0xc 2927#define UVD_CGC_CTRL3__MIF_MODE__SHIFT 0xd 2928#define UVD_CGC_CTRL3__VREG_MODE__SHIFT 0xe 2929#define UVD_CGC_CTRL3__PE_MODE__SHIFT 0xf 2930#define UVD_CGC_CTRL3__PPU_MODE__SHIFT 0x10 2931#define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY_MASK 0x000000FFL 2932#define UVD_CGC_CTRL3__LCM0_MODE_MASK 0x00000800L 2933#define UVD_CGC_CTRL3__LCM1_MODE_MASK 0x00001000L 2934#define UVD_CGC_CTRL3__MIF_MODE_MASK 0x00002000L 2935#define UVD_CGC_CTRL3__VREG_MODE_MASK 0x00004000L 2936#define UVD_CGC_CTRL3__PE_MODE_MASK 0x00008000L 2937#define UVD_CGC_CTRL3__PPU_MODE_MASK 0x00010000L 2938//UVD_GPCOM_VCPU_DATA0 2939#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2940#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2941//UVD_GPCOM_VCPU_DATA1 2942#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2943#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2944//UVD_GPCOM_SYS_CMD 2945#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2946#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2947#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2948#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2949#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2950#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2951//UVD_GPCOM_SYS_DATA0 2952#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2953#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2954//UVD_GPCOM_SYS_DATA1 2955#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2956#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2957//UVD_VCPU_INT_EN 2958#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2959#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2960#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2961#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2962#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2963#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2964#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2965#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2966#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2967#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2968#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2969#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2970#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 2971#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 2972#define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 2973#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2974#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2975#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2976#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2977#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2978#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2979#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2980#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2981#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2982#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2983#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2984#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2985#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2986#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2987#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2988#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2989#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2990#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2991#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2992#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2993#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2994#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2995#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2996#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2997#define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 2998#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2999#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 3000#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 3001#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3002#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 3003#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 3004#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 3005#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3006#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3007#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3008#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 3009#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 3010//UVD_VCPU_INT_ACK 3011#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3012#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3013#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3014#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 3015#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 3016#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 3017#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3018#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 3019#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 3020#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 3021#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 3022#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 3023#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 3024#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 3025#define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 3026#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 3027#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 3028#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 3029#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3030#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 3031#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 3032#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 3033#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3034#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3035#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3036#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 3037#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 3038#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3039#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3040#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3041#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 3042#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 3043#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 3044#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3045#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 3046#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 3047#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 3048#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 3049#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 3050#define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 3051#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 3052#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 3053#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 3054#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3055#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 3056#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 3057#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 3058#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3059#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3060#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3061#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 3062#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 3063//UVD_VCPU_INT_ROUTE 3064#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 3065#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 3066#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 3067#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 3068#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 3069#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 3070//UVD_SUVD_INT_EN 3071#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 3072#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 3073#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 3074#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 3075#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 3076#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 3077#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 3078#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 3079#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 3080#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 3081#define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e 3082#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 3083#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 3084#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 3085#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 3086#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 3087#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 3088#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 3089#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 3090#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 3091#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 3092#define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L 3093//UVD_SUVD_INT_STATUS 3094#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 3095#define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 3096#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 3097#define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 3098#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 3099#define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 3100#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 3101#define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 3102#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 3103#define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 3104#define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e 3105#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 3106#define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 3107#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 3108#define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 3109#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 3110#define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 3111#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 3112#define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 3113#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 3114#define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 3115#define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L 3116//UVD_SUVD_INT_ACK 3117#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 3118#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 3119#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 3120#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 3121#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 3122#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 3123#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 3124#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 3125#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 3126#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 3127#define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e 3128#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 3129#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 3130#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 3131#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 3132#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 3133#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 3134#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 3135#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 3136#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 3137#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 3138#define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L 3139//UVD_MASTINT_EN 3140#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3141#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3142#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3143#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3144#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 3145#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 3146#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 3147#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 3148//UVD_SYS_INT_EN 3149#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3150#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3151#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3152#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 3153#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3154#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 3155#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 3156#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 3157#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 3158#define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 3159#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 3160#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3161#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 3162#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 3163#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3164#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3165#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3166#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 3167#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3168#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3169#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3170#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 3171#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3172#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 3173#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 3174#define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 3175#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 3176#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3177#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 3178#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 3179#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3180#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3181#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3182#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 3183//UVD_SYS_INT_STATUS 3184#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3185#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3186#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3187#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 3188#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3189#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 3190#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 3191#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd 3192#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe 3193#define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 3194#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 3195#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 3196#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3197#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 3198#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 3199#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3200#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3201#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3202#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 3203#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3204#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3205#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3206#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 3207#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3208#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 3209#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 3210#define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 3211#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 3212#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 3213#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3214#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 3215#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 3216#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3217#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3218#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3219#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 3220//UVD_SYS_INT_ACK 3221#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3222#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3223#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3224#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 3225#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3226#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 3227#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 3228#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 3229#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 3230#define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 3231#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 3232#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3233#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 3234#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 3235#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3236#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3237#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3238#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 3239#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3240#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3241#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3242#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 3243#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3244#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 3245#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 3246#define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 3247#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 3248#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3249#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 3250#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 3251#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3252#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3253#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3254#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 3255//UVD_JOB_DONE 3256#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 3257#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 3258//UVD_CBUF_ID 3259#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 3260#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 3261//UVD_CONTEXT_ID 3262#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 3263#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 3264//UVD_CONTEXT_ID2 3265#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 3266#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 3267//UVD_NO_OP 3268#define UVD_NO_OP__NO_OP__SHIFT 0x0 3269#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3270//UVD_RB_BASE_LO 3271#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3272#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3273//UVD_RB_BASE_HI 3274#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3275#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3276//UVD_RB_SIZE 3277#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3278#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3279//UVD_RB_BASE_LO2 3280#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3281#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3282//UVD_RB_BASE_HI2 3283#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3284#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3285//UVD_RB_SIZE2 3286#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3287#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3288//UVD_RB_BASE_LO3 3289#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 3290#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 3291//UVD_RB_BASE_HI3 3292#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 3293#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 3294//UVD_RB_SIZE3 3295#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 3296#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 3297//UVD_RB_BASE_LO4 3298#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3299#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3300//UVD_RB_BASE_HI4 3301#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3302#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3303//UVD_RB_SIZE4 3304#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3305#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3306//UVD_OUT_RB_BASE_LO 3307#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3308#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3309//UVD_OUT_RB_BASE_HI 3310#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3311#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3312//UVD_OUT_RB_SIZE 3313#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3314#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3315//UVD_IOV_ACTIVE_FCN_ID 3316#define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 3317#define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 3318#define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 3319#define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 3320//UVD_IOV_MAILBOX 3321#define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 3322#define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 3323//UVD_IOV_MAILBOX_RESP 3324#define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 3325#define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 3326//UVD_RB_ARB_CTRL 3327#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 3328#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 3329#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 3330#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 3331#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 3332#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 3333#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 3334#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 3335#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 3336#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 3337#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 3338#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 3339#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 3340#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 3341#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 3342#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 3343#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 3344#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 3345//UVD_CTX_INDEX 3346#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 3347#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 3348//UVD_CTX_DATA 3349#define UVD_CTX_DATA__DATA__SHIFT 0x0 3350#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 3351//UVD_CXW_WR 3352#define UVD_CXW_WR__DAT__SHIFT 0x0 3353#define UVD_CXW_WR__STAT__SHIFT 0x1f 3354#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 3355#define UVD_CXW_WR__STAT_MASK 0x80000000L 3356//UVD_CXW_WR_INT_ID 3357#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 3358#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 3359//UVD_CXW_WR_INT_CTX_ID 3360#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 3361#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 3362//UVD_CXW_INT_ID 3363#define UVD_CXW_INT_ID__ID__SHIFT 0x0 3364#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3365//UVD_MPEG2_ERROR 3366#define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 3367#define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 3368//UVD_YBASE 3369#define UVD_YBASE__DUM__SHIFT 0x0 3370#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3371//UVD_UVBASE 3372#define UVD_UVBASE__DUM__SHIFT 0x0 3373#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3374//UVD_PITCH 3375#define UVD_PITCH__DUM__SHIFT 0x0 3376#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3377//UVD_WIDTH 3378#define UVD_WIDTH__DUM__SHIFT 0x0 3379#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3380//UVD_HEIGHT 3381#define UVD_HEIGHT__DUM__SHIFT 0x0 3382#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3383//UVD_PICCOUNT 3384#define UVD_PICCOUNT__DUM__SHIFT 0x0 3385#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3386//UVD_MPRD_INITIAL_XY 3387#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 3388#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 3389#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 3390#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 3391//UVD_MPEG2_CTRL 3392#define UVD_MPEG2_CTRL__EN__SHIFT 0x0 3393#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 3394#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 3395#define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 3396#define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 3397#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 3398//UVD_MB_CTL_BUF_BASE 3399#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 3400#define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3401//UVD_PIC_CTL_BUF_BASE 3402#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 3403#define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3404//UVD_DXVA_BUF_SIZE 3405#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 3406#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 3407#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 3408#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 3409//UVD_SCRATCH_NP 3410#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3411#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3412//UVD_CLK_SWT_HANDSHAKE 3413#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 3414#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 3415#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 3416#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 3417//UVD_GP_SCRATCH0 3418#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 3419#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 3420//UVD_GP_SCRATCH1 3421#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 3422#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 3423//UVD_GP_SCRATCH2 3424#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 3425#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 3426//UVD_GP_SCRATCH3 3427#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 3428#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 3429//UVD_GP_SCRATCH4 3430#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 3431#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 3432//UVD_GP_SCRATCH5 3433#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 3434#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 3435//UVD_GP_SCRATCH6 3436#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 3437#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 3438//UVD_GP_SCRATCH7 3439#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 3440#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 3441//UVD_GP_SCRATCH8 3442#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3443#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3444//UVD_GP_SCRATCH9 3445#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3446#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3447//UVD_GP_SCRATCH10 3448#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3449#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3450//UVD_GP_SCRATCH11 3451#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3452#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3453//UVD_GP_SCRATCH12 3454#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3455#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3456//UVD_GP_SCRATCH13 3457#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3458#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3459//UVD_GP_SCRATCH14 3460#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3461#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3462//UVD_GP_SCRATCH15 3463#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3464#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3465//UVD_GP_SCRATCH16 3466#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3467#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3468//UVD_GP_SCRATCH17 3469#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3470#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3471//UVD_GP_SCRATCH18 3472#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3473#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3474//UVD_GP_SCRATCH19 3475#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3476#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3477//UVD_GP_SCRATCH20 3478#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3479#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3480//UVD_GP_SCRATCH21 3481#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3482#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3483//UVD_GP_SCRATCH22 3484#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3485#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3486//UVD_GP_SCRATCH23 3487#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3488#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3489//UVD_AUDIO_RB_BASE_LO 3490#define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3491#define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3492//UVD_AUDIO_RB_BASE_HI 3493#define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3494#define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3495//UVD_AUDIO_RB_SIZE 3496#define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 3497#define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3498//UVD_VCPU_INT_ACK2 3499#define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 3500#define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L 3501//UVD_VCPU_INT_EN2 3502#define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 3503#define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L 3504//UVD_SUVD_CGC_STATUS2 3505#define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 3506#define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 3507#define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 3508#define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 3509#define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 3510#define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 3511#define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 3512#define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 3513#define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK__SHIFT 0x9 3514#define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa 3515#define UVD_SUVD_CGC_STATUS2__SIT0_DCLK__SHIFT 0xb 3516#define UVD_SUVD_CGC_STATUS2__SIT1_DCLK__SHIFT 0xc 3517#define UVD_SUVD_CGC_STATUS2__SIT2_DCLK__SHIFT 0xd 3518#define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c 3519#define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d 3520#define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L 3521#define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L 3522#define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L 3523#define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L 3524#define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L 3525#define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L 3526#define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L 3527#define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L 3528#define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK_MASK 0x00000200L 3529#define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK_MASK 0x00000400L 3530#define UVD_SUVD_CGC_STATUS2__SIT0_DCLK_MASK 0x00000800L 3531#define UVD_SUVD_CGC_STATUS2__SIT1_DCLK_MASK 0x00001000L 3532#define UVD_SUVD_CGC_STATUS2__SIT2_DCLK_MASK 0x00002000L 3533#define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L 3534#define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L 3535//UVD_SUVD_INT_STATUS2 3536#define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 3537#define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 3538#define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 3539#define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb 3540#define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL 3541#define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L 3542#define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L 3543#define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L 3544//UVD_SUVD_INT_EN2 3545#define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 3546#define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 3547#define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 3548#define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb 3549#define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL 3550#define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L 3551#define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L 3552#define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L 3553//UVD_SUVD_INT_ACK2 3554#define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 3555#define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 3556#define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 3557#define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb 3558#define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL 3559#define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L 3560#define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L 3561#define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L 3562//UVD_STATUS 3563#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 3564#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 3565#define UVD_STATUS__FILL_0__SHIFT 0x8 3566#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 3567#define UVD_STATUS__FILL_1__SHIFT 0x12 3568#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 3569#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 3570#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 3571#define UVD_STATUS__FILL_0_MASK 0x0000FF00L 3572#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 3573#define UVD_STATUS__FILL_1_MASK 0x7FFC0000L 3574#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 3575//UVD_CNTL 3576#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 3577#define UVD_CNTL__SUVD_EN__SHIFT 0x13 3578#define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 3579#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 3580#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 3581#define UVD_CNTL__SUVD_EN_MASK 0x00080000L 3582#define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 3583#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 3584//UVD_SOFT_RESET 3585#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 3586#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 3587#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 3588#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 3589#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 3590#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 3591#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 3592#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 3593#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 3594#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 3595#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 3596#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 3597#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 3598#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 3599#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 3600#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 3601#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 3602#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 3603#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 3604#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 3605#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 3606#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 3607#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 3608#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 3609#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 3610#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 3611#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 3612#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 3613#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 3614#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 3615#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 3616#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 3617#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 3618#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 3619#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 3620#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 3621#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 3622#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 3623#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 3624#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 3625#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 3626#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 3627#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 3628#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 3629#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 3630#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 3631#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 3632#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 3633#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 3634#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 3635#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 3636#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 3637#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 3638#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 3639#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 3640#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 3641#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 3642#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 3643#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 3644#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 3645#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 3646#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 3647//UVD_SOFT_RESET2 3648#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 3649#define UVD_SOFT_RESET2__PPU_SOFT_RESET__SHIFT 0x1 3650#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 3651#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 3652#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 3653#define UVD_SOFT_RESET2__PPU_SOFT_RESET_MASK 0x00000002L 3654#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 3655#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 3656//UVD_MMSCH_SOFT_RESET 3657#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3658#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3659#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3660#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3661#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3662#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3663//UVD_WIG_CTRL 3664#define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 3665#define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 3666#define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 3667#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 3668#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 3669#define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 3670#define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 3671#define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 3672#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 3673#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 3674//UVD_CGC_STATUS 3675#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 3676#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 3677#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 3678#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 3679#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 3680#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 3681#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 3682#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 3683#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 3684#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 3685#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 3686#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 3687#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 3688#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 3689#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 3690#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 3691#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 3692#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 3693#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 3694#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 3695#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 3696#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 3697#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 3698#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 3699#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 3700#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 3701#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 3702#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 3703#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 3704#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 3705#define UVD_CGC_STATUS__LRBBM_DCLK__SHIFT 0x1e 3706#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 3707#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 3708#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 3709#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 3710#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 3711#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 3712#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 3713#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 3714#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 3715#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 3716#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 3717#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 3718#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 3719#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 3720#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 3721#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 3722#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 3723#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 3724#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 3725#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 3726#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 3727#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 3728#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 3729#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 3730#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 3731#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 3732#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 3733#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 3734#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 3735#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 3736#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 3737#define UVD_CGC_STATUS__LRBBM_DCLK_MASK 0x40000000L 3738#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 3739//UVD_CGC_UDEC_STATUS 3740#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 3741#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 3742#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 3743#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3744#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3745#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3746#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3747#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3748#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3749#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3750#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3751#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3752#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3753#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3754#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3755#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 3756#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 3757#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 3758#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 3759#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 3760#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 3761#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 3762#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 3763#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 3764#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 3765#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 3766#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 3767#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 3768#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 3769#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 3770//UVD_SUVD_CGC_STATUS 3771#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3772#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3773#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3774#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3775#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3776#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3777#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3778#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3779#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3780#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3781#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3782#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3783#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3784#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3785#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3786#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3787#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3788#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3789#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3790#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3791#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3792#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3793#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3794#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3795#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3796#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3797#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3798#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3799#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3800#define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d 3801#define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e 3802#define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f 3803#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3804#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3805#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3806#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3807#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3808#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3809#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3810#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3811#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3812#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3813#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3814#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3815#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3816#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3817#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3818#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3819#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3820#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3821#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3822#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3823#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3824#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3825#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3826#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3827#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3828#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3829#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3830#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3831#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3832#define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L 3833#define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L 3834#define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L 3835//UVD_GPCOM_VCPU_CMD 3836#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3837#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3838#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3839#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3840#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3841#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3842 3843 3844// addressBlock: uvd_ecpudec 3845//UVD_VCPU_CACHE_OFFSET0 3846#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 3847#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 3848//UVD_VCPU_CACHE_SIZE0 3849#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 3850#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 3851//UVD_VCPU_CACHE_OFFSET1 3852#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 3853#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 3854//UVD_VCPU_CACHE_SIZE1 3855#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 3856#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 3857//UVD_VCPU_CACHE_OFFSET2 3858#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 3859#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 3860//UVD_VCPU_CACHE_SIZE2 3861#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 3862#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 3863//UVD_VCPU_CACHE_OFFSET3 3864#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 3865#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 3866//UVD_VCPU_CACHE_SIZE3 3867#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 3868#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 3869//UVD_VCPU_CACHE_OFFSET4 3870#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 3871#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 3872//UVD_VCPU_CACHE_SIZE4 3873#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 3874#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 3875//UVD_VCPU_CACHE_OFFSET5 3876#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 3877#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 3878//UVD_VCPU_CACHE_SIZE5 3879#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 3880#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 3881//UVD_VCPU_CACHE_OFFSET6 3882#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 3883#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 3884//UVD_VCPU_CACHE_SIZE6 3885#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 3886#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 3887//UVD_VCPU_CACHE_OFFSET7 3888#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 3889#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 3890//UVD_VCPU_CACHE_SIZE7 3891#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 3892#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 3893//UVD_VCPU_CACHE_OFFSET8 3894#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 3895#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 3896//UVD_VCPU_CACHE_SIZE8 3897#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 3898#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 3899//UVD_VCPU_NONCACHE_OFFSET0 3900#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 3901#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 3902//UVD_VCPU_NONCACHE_SIZE0 3903#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 3904#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 3905//UVD_VCPU_NONCACHE_OFFSET1 3906#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 3907#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 3908//UVD_VCPU_NONCACHE_SIZE1 3909#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 3910#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 3911//UVD_VCPU_CNTL 3912#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 3913#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 3914#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 3915#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 3916#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 3917#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 3918#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 3919#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 3920#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 3921#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 3922#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 3923#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 3924#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 3925#define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d 3926#define UVD_VCPU_CNTL__SRE_CMDIF_DRST__SHIFT 0x1e 3927#define UVD_VCPU_CNTL__SRE_CMDIF_VRST__SHIFT 0x1f 3928#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 3929#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 3930#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 3931#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 3932#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 3933#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 3934#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 3935#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 3936#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 3937#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 3938#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 3939#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 3940#define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L 3941#define UVD_VCPU_CNTL__SRE_CMDIF_DRST_MASK 0x40000000L 3942#define UVD_VCPU_CNTL__SRE_CMDIF_VRST_MASK 0x80000000L 3943//UVD_VCPU_PRID 3944#define UVD_VCPU_PRID__PRID__SHIFT 0x0 3945#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 3946//UVD_VCPU_TRCE 3947#define UVD_VCPU_TRCE__PC__SHIFT 0x0 3948#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 3949//UVD_VCPU_TRCE_RD 3950#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 3951#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 3952//UVD_VCPU_IND_INDEX 3953#define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 3954#define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 3955//UVD_VCPU_IND_DATA 3956#define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 3957#define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 3958 3959 3960// addressBlock: uvd_uvd_mpcdec 3961//UVD_MP_SWAP_CNTL 3962#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 3963#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 3964#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 3965#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 3966#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 3967#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 3968#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 3969#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 3970#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 3971#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 3972#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 3973#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 3974#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 3975#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 3976#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 3977#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 3978#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 3979#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 3980#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 3981#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 3982#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 3983#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 3984#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 3985#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 3986#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 3987#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 3988#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 3989#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 3990#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 3991#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 3992#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 3993#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 3994//UVD_MP_SWAP_CNTL2 3995#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 3996#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 3997//UVD_MPC_LUMA_SRCH 3998#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 3999#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 4000//UVD_MPC_LUMA_HIT 4001#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 4002#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 4003//UVD_MPC_LUMA_HITPEND 4004#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 4005#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 4006//UVD_MPC_CHROMA_SRCH 4007#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 4008#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 4009//UVD_MPC_CHROMA_HIT 4010#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 4011#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 4012//UVD_MPC_CHROMA_HITPEND 4013#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 4014#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 4015//UVD_MPC_CNTL 4016#define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 4017#define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT__SHIFT 0x1 4018#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 4019#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 4020#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 4021#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 4022#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 4023#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 4024#define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 4025#define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT_MASK 0x00000002L 4026#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 4027#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 4028#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 4029#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 4030#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 4031#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00300000L 4032//UVD_MPC_PITCH 4033#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 4034#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 4035//UVD_MPC_SET_MUXA0 4036#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 4037#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 4038#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 4039#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 4040#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 4041#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 4042#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 4043#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 4044#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 4045#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 4046//UVD_MPC_SET_MUXA1 4047#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 4048#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 4049#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 4050#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 4051#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 4052#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 4053//UVD_MPC_SET_MUXB0 4054#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 4055#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 4056#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 4057#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 4058#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 4059#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 4060#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 4061#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 4062#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 4063#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 4064//UVD_MPC_SET_MUXB1 4065#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 4066#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 4067#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 4068#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 4069#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 4070#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 4071//UVD_MPC_SET_MUX 4072#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 4073#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 4074#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 4075#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 4076#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 4077#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 4078//UVD_MPC_SET_ALU 4079#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 4080#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 4081#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 4082#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 4083//UVD_MPC_PERF0 4084#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 4085#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 4086//UVD_MPC_PERF1 4087#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 4088#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 4089//UVD_MPC_IND_INDEX 4090#define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 4091#define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 4092//UVD_MPC_IND_DATA 4093#define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 4094#define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 4095 4096 4097// addressBlock: uvd_uvd_rbcdec 4098//UVD_RBC_IB_SIZE 4099#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 4100#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 4101//UVD_RBC_IB_SIZE_UPDATE 4102#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 4103#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 4104//UVD_RBC_RB_CNTL 4105#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 4106#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 4107#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 4108#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 4109#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 4110#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 4111#define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 4112#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 4113#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 4114#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 4115#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 4116#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 4117#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 4118#define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 4119//UVD_RBC_RB_RPTR_ADDR 4120#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 4121#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 4122//UVD_RBC_VCPU_ACCESS 4123#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 4124#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 4125//UVD_RBC_READ_REQ_URGENT_CNTL 4126#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 4127#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 4128//UVD_RBC_RB_WPTR_CNTL 4129#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 4130#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 4131//UVD_RBC_WPTR_STATUS 4132#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 4133#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 4134//UVD_RBC_WPTR_POLL_CNTL 4135#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 4136#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4137#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 4138#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4139//UVD_RBC_WPTR_POLL_ADDR 4140#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 4141#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 4142//UVD_SEMA_CMD 4143#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 4144#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 4145#define UVD_SEMA_CMD__MODE__SHIFT 0x6 4146#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 4147#define UVD_SEMA_CMD__VMID__SHIFT 0x8 4148#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 4149#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 4150#define UVD_SEMA_CMD__MODE_MASK 0x00000040L 4151#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 4152#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 4153//UVD_SEMA_ADDR_LOW 4154#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 4155#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 4156//UVD_SEMA_ADDR_HIGH 4157#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 4158#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 4159//UVD_ENGINE_CNTL 4160#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 4161#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 4162#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 4163#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 4164#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 4165#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 4166//UVD_SEMA_TIMEOUT_STATUS 4167#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 4168#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 4169#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 4170#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 4171#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 4172#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 4173#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 4174#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 4175//UVD_SEMA_CNTL 4176#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 4177#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 4178#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 4179#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 4180//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 4181#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 4182#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 4183#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4184#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 4185#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4186#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4187//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 4188#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 4189#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 4190#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4191#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 4192#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 4193#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4194//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 4195#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 4196#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 4197#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4198#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 4199#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4200#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4201//UVD_JOB_START 4202#define UVD_JOB_START__JOB_START__SHIFT 0x0 4203#define UVD_JOB_START__JOB_START_MASK 0x00000001L 4204//UVD_RBC_BUF_STATUS 4205#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 4206#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 4207#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 4208#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 4209#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 4210#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 4211#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 4212#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 4213#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 4214#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 4215#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 4216#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 4217//UVD_RBC_SWAP_CNTL 4218#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4219#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4220#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4221#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4222#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 4223#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 4224#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 4225#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 4226 4227 4228// addressBlock: uvd_lmi_adpdec 4229//UVD_LMI_RE_64BIT_BAR_LOW 4230#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4231#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4232//UVD_LMI_RE_64BIT_BAR_HIGH 4233#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4234#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4235//UVD_LMI_IT_64BIT_BAR_LOW 4236#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4237#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4238//UVD_LMI_IT_64BIT_BAR_HIGH 4239#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4240#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4241//UVD_LMI_MP_64BIT_BAR_LOW 4242#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4243#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4244//UVD_LMI_MP_64BIT_BAR_HIGH 4245#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4246#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4247//UVD_LMI_CM_64BIT_BAR_LOW 4248#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4249#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4250//UVD_LMI_CM_64BIT_BAR_HIGH 4251#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4252#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4253//UVD_LMI_DB_64BIT_BAR_LOW 4254#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4255#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4256//UVD_LMI_DB_64BIT_BAR_HIGH 4257#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4258#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4259//UVD_LMI_DBW_64BIT_BAR_LOW 4260#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4261#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4262//UVD_LMI_DBW_64BIT_BAR_HIGH 4263#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4264#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4265//UVD_LMI_IDCT_64BIT_BAR_LOW 4266#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4267#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4268//UVD_LMI_IDCT_64BIT_BAR_HIGH 4269#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4270#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4271//UVD_LMI_MPRD_S0_64BIT_BAR_LOW 4272#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4273#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4274//UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 4275#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4276#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4277//UVD_LMI_MPRD_S1_64BIT_BAR_LOW 4278#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4279#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4280//UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 4281#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4282#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4283//UVD_LMI_MPC_64BIT_BAR_LOW 4284#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4285#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4286//UVD_LMI_MPC_64BIT_BAR_HIGH 4287#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4288#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4289//UVD_LMI_RBC_RB_64BIT_BAR_LOW 4290#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4291#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4292//UVD_LMI_RBC_RB_64BIT_BAR_HIGH 4293#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4294#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4295//UVD_LMI_RBC_IB_64BIT_BAR_LOW 4296#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4297#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4298//UVD_LMI_RBC_IB_64BIT_BAR_HIGH 4299#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4300#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4301//UVD_LMI_LBSI_64BIT_BAR_LOW 4302#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4303#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4304//UVD_LMI_LBSI_64BIT_BAR_HIGH 4305#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4306#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4307//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 4308#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4309#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4310//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 4311#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4312#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4313//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 4314#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4315#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4316//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 4317#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4318#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4319//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 4320#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4321#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4322//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 4323#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4324#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4325//UVD_LMI_CENC_64BIT_BAR_LOW 4326#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4327#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4328//UVD_LMI_CENC_64BIT_BAR_HIGH 4329#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4330#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4331//UVD_LMI_SRE_64BIT_BAR_LOW 4332#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4333#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4334//UVD_LMI_SRE_64BIT_BAR_HIGH 4335#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4336#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4337//UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 4338#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4339#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4340//UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 4341#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4342#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4343//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 4344#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4345#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4346//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 4347#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4348#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4349//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 4350#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4351#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4352//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 4353#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4354#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4355//UVD_LMI_MIF_REF_64BIT_BAR_LOW 4356#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4357#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4358//UVD_LMI_MIF_REF_64BIT_BAR_HIGH 4359#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4360#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4361//UVD_LMI_MIF_DBW_64BIT_BAR_LOW 4362#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4363#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4364//UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 4365#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4366#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4367//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 4368#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4369#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4370//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 4371#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4372#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4373//UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 4374#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4375#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4376//UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 4377#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4378#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4379//UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 4380#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4381#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4382//UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 4383#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4384#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4385//UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 4386#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4387#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4388//UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 4389#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4390#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4391//UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 4392#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4393#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4394//UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 4395#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4396#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4397//UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 4398#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4399#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4400//UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 4401#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4402#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4403//UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 4404#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4405#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4406//UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 4407#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4408#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4409//UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 4410#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4411#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4412//UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 4413#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4414#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4415//UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 4416#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4417#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4418//UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 4419#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4420#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4421//UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 4422#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4423#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4424//UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 4425#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4426#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4427//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 4428#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4429#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4430//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 4431#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4432#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4433//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 4434#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4435#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4436//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 4437#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4438#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4439//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 4440#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4441#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4442//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 4443#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4444#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4445//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 4446#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4447#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4448//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 4449#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4450#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4451//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 4452#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4453#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4454//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 4455#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4456#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4457//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 4458#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4459#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4460//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 4461#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4462#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4463//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 4464#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4465#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4466//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 4467#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4468#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4469//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 4470#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4471#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4472//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 4473#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4474#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4475//UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 4476#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4477#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4478//UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 4479#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4480#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4481//UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 4482#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4483#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4484//UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 4485#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4486#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4487//UVD_LMI_SPH_64BIT_BAR_HIGH 4488#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4489#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4490//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 4491#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4492#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4493//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 4494#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4495#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4496//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 4497#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4498#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4499//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 4500#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4501#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4502//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 4503#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4504#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4505//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 4506#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4507#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4508//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 4509#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4510#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4511//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 4512#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4513#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4514//UVD_LMI_ARB_CTRL2 4515#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 4516#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 4517#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 4518#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 4519#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 4520#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 4521#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 4522#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 4523#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 4524#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 4525#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 4526#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 4527//UVD_LMI_VCPU_CACHE_VMIDS_MULTI 4528#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 4529#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 4530#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 4531#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 4532#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 4533#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 4534#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 4535#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 4536#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 4537#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 4538#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 4539#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 4540#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 4541#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 4542#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 4543#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 4544//UVD_LMI_VCPU_NC_VMIDS_MULTI 4545#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 4546#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 4547#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 4548#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 4549#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 4550#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 4551#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 4552#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 4553#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 4554#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 4555#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 4556#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 4557//UVD_LMI_LAT_CTRL 4558#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 4559#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 4560#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 4561#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 4562#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4563#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 4564#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4565#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4566#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4567#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4568#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4569#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4570//UVD_LMI_LAT_CNTR 4571#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4572#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4573#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4574#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4575//UVD_LMI_AVG_LAT_CNTR 4576#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4577#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4578#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4579#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4580#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4581#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4582//UVD_LMI_SPH 4583#define UVD_LMI_SPH__ADDR__SHIFT 0x0 4584#define UVD_LMI_SPH__STS__SHIFT 0x1c 4585#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 4586#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 4587#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 4588#define UVD_LMI_SPH__STS_MASK 0x30000000L 4589#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 4590#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 4591//UVD_LMI_VCPU_CACHE_VMID 4592#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 4593#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 4594//UVD_LMI_CTRL2 4595#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 4596#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 4597#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 4598#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 4599#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 4600#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 4601#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 4602#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 4603#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 4604#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 4605#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 4606#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 4607#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 4608#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 4609#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 4610#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 4611#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 4612#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 4613#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 4614#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 4615#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 4616#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 4617#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 4618#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 4619#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 4620#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 4621#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 4622#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 4623#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 4624#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 4625#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 4626#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 4627#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 4628#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 4629//UVD_LMI_URGENT_CTRL 4630#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4631#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 4632#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 4633#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 4634#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 4635#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 4636#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 4637#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 4638#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 4639#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 4640#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 4641#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 4642#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4643#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 4644#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 4645#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 4646#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 4647#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 4648#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 4649#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 4650#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 4651#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 4652#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 4653#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 4654//UVD_LMI_CTRL 4655#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 4656#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 4657#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 4658#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 4659#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 4660#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 4661#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 4662#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 4663#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4664#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4665#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4666#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4667#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4668#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4669#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 4670#define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 4671#define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 4672#define UVD_LMI_CTRL__RFU__SHIFT 0x1e 4673#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 4674#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 4675#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 4676#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 4677#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 4678#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 4679#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 4680#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 4681#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 4682#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 4683#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 4684#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 4685#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 4686#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 4687#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 4688#define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 4689#define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 4690#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 4691//UVD_LMI_STATUS 4692#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4693#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4694#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4695#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4696#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4697#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4698#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4699#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4700#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4701#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4702#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4703#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4704#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4705#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4706#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 4707#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 4708#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 4709#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 4710#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 4711#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 4712#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 4713#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 4714#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 4715#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 4716#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 4717#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 4718#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 4719#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 4720#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 4721#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 4722#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 4723#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 4724#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 4725#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 4726#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 4727#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 4728#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 4729#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 4730//UVD_LMI_PERFMON_CTRL 4731#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4732#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4733#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4734#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4735//UVD_LMI_PERFMON_COUNT_LO 4736#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4737#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4738//UVD_LMI_PERFMON_COUNT_HI 4739#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4740#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4741//UVD_LMI_ADP_SWAP_CNTL 4742#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4743#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4744#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4745#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4746#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4747#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4748#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4749#define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 4750#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4751#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4752#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4753#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 4754#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 4755#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 4756#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 4757#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 4758#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 4759#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 4760#define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L 4761#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 4762#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 4763#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 4764//UVD_LMI_RBC_RB_VMID 4765#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 4766#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 4767//UVD_LMI_RBC_IB_VMID 4768#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 4769#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 4770//UVD_LMI_MC_CREDITS 4771#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 4772#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 4773#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 4774#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 4775#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 4776#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 4777#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 4778#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 4779//UVD_LMI_ADP_IND_INDEX 4780#define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 4781#define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 4782//UVD_LMI_ADP_IND_DATA 4783#define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 4784#define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 4785//UVD_LMI_ADP_PF_EN 4786#define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 4787#define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 4788#define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 4789#define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L 4790#define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L 4791#define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L 4792//UVD_LMI_PREF_CTRL 4793#define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 4794#define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 4795#define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 4796#define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 4797#define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 4798#define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 4799#define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L 4800#define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L 4801#define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L 4802#define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L 4803#define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L 4804#define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L 4805//UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 4806#define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4807#define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4808//UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 4809#define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4810#define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4811 4812 4813// addressBlock: uvd_jpegnpdec 4814//UVD_JPEG_CNTL 4815#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 4816#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 4817#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 4818#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 4819//UVD_JPEG_RB_BASE 4820#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 4821#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 4822#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 4823#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 4824//UVD_JPEG_RB_WPTR 4825#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 4826#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 4827//UVD_JPEG_RB_RPTR 4828#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 4829#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 4830//UVD_JPEG_RB_SIZE 4831#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 4832#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 4833//UVD_JPEG_SPS_INFO 4834#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 4835#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 4836#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 4837#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 4838//UVD_JPEG_SPS1_INFO 4839#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 4840#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 4841#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 4842#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 4843#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 4844#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 4845//UVD_JPEG_RE_TIMER 4846#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 4847#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 4848#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 4849#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 4850//UVD_JPEG_INT_EN 4851#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 4852#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 4853#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 4854#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 4855#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 4856#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 4857#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 4858#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 4859#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 4860#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 4861#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 4862#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 4863#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 4864#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 4865#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 4866#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 4867#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 4868#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 4869#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 4870#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 4871#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 4872#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 4873#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 4874#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 4875#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 4876#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 4877//UVD_JPEG_INT_STAT 4878#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 4879#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 4880#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 4881#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 4882#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 4883#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 4884#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 4885#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 4886#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 4887#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 4888#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 4889#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 4890#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 4891#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 4892#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 4893#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 4894#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 4895#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 4896#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 4897#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 4898#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 4899#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 4900#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 4901#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 4902#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 4903#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 4904//UVD_JPEG_TIER_CNTL0 4905#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 4906#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 4907#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 4908#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 4909#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 4910#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 4911#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 4912#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 4913#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 4914#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 4915#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 4916#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 4917#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 4918#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 4919#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 4920#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 4921#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 4922#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 4923#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 4924#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 4925#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 4926#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 4927#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 4928#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 4929#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 4930#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 4931//UVD_JPEG_TIER_CNTL1 4932#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 4933#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 4934#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 4935#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 4936//UVD_JPEG_TIER_CNTL2 4937#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 4938#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 4939#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 4940#define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 4941#define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 4942#define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 4943#define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 4944#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 4945#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 4946#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 4947#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 4948#define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 4949#define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 4950#define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 4951#define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 4952#define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 4953#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 4954#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 4955//UVD_JPEG_TIER_STATUS 4956#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 4957#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 4958#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 4959#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 4960//UVD_JPEG_OUTBUF_CNTL 4961#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 4962#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 4963#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 4964#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 4965#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 4966#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 4967#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 4968#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 4969#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 4970#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 4971//UVD_JPEG_OUTBUF_WPTR 4972#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 4973#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 4974//UVD_JPEG_OUTBUF_RPTR 4975#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 4976#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 4977//UVD_JPEG_PITCH 4978#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 4979#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 4980//UVD_JPEG_UV_PITCH 4981#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 4982#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 4983//JPEG_DEC_Y_GFX8_TILING_SURFACE 4984#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 4985#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 4986#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 4987#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 4988#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 4989#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 4990#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 4991#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 4992#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 4993#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 4994#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 4995#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 4996#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 4997#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 4998//JPEG_DEC_UV_GFX8_TILING_SURFACE 4999#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 5000#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 5001#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 5002#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 5003#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 5004#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 5005#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 5006#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 5007#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 5008#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 5009#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 5010#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 5011#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 5012#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 5013//JPEG_DEC_GFX8_ADDR_CONFIG 5014#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 5015#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 5016//JPEG_DEC_Y_GFX10_TILING_SURFACE 5017#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 5018#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 5019//JPEG_DEC_UV_GFX10_TILING_SURFACE 5020#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 5021#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 5022//JPEG_DEC_GFX10_ADDR_CONFIG 5023#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 5024#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 5025#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 5026#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 5027#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 5028#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 5029#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 5030#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 5031#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 5032#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 5033//JPEG_DEC_ADDR_MODE 5034#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 5035#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 5036#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 5037#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 5038#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 5039#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 5040//UVD_JPEG_OUTPUT_XY 5041#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 5042#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 5043#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 5044#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 5045//UVD_JPEG_GPCOM_CMD 5046#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 5047#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 5048//UVD_JPEG_GPCOM_DATA0 5049#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 5050#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 5051//UVD_JPEG_GPCOM_DATA1 5052#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 5053#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 5054//UVD_JPEG_INDEX 5055#define UVD_JPEG_INDEX__INDEX__SHIFT 0x0 5056#define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL 5057//UVD_JPEG_DATA 5058#define UVD_JPEG_DATA__DATA__SHIFT 0x0 5059#define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL 5060//UVD_JPEG_SCRATCH1 5061#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 5062#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 5063 5064 5065// addressBlock: uvd_uvd_jrbc_dec 5066//UVD_JRBC_RB_WPTR 5067#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 5068#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5069//UVD_JRBC_RB_CNTL 5070#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 5071#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 5072#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 5073#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 5074#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 5075#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 5076//UVD_JRBC_IB_SIZE 5077#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 5078#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 5079//UVD_JRBC_URGENT_CNTL 5080#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 5081#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 5082//UVD_JRBC_RB_REF_DATA 5083#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 5084#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 5085//UVD_JRBC_RB_COND_RD_TIMER 5086#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 5087#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 5088#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 5089#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 5090#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 5091#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 5092#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 5093#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 5094//UVD_JRBC_SOFT_RESET 5095#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 5096#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 5097#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 5098#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 5099//UVD_JRBC_STATUS 5100#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 5101#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 5102#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 5103#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 5104#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 5105#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 5106#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 5107#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 5108#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 5109#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 5110#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 5111#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 5112#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 5113#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 5114#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 5115#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 5116#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 5117#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 5118#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 5119#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 5120#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 5121#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 5122#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 5123#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 5124#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 5125#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 5126#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 5127#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 5128#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 5129#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 5130//UVD_JRBC_RB_RPTR 5131#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 5132#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5133//UVD_JRBC_RB_BUF_STATUS 5134#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 5135#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 5136#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 5137#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 5138#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 5139#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 5140//UVD_JRBC_IB_BUF_STATUS 5141#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 5142#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 5143#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 5144#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 5145#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 5146#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 5147//UVD_JRBC_IB_SIZE_UPDATE 5148#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 5149#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 5150//UVD_JRBC_IB_COND_RD_TIMER 5151#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 5152#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 5153#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 5154#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 5155#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 5156#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 5157#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 5158#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 5159//UVD_JRBC_IB_REF_DATA 5160#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 5161#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 5162//UVD_JPEG_PREEMPT_CMD 5163#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 5164#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 5165#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 5166#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 5167#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 5168#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 5169//UVD_JPEG_PREEMPT_FENCE_DATA0 5170#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 5171#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 5172//UVD_JPEG_PREEMPT_FENCE_DATA1 5173#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 5174#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 5175//UVD_JRBC_RB_SIZE 5176#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 5177#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 5178//UVD_JRBC_SCRATCH0 5179#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 5180#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 5181 5182 5183// addressBlock: uvd_uvd_jmi_dec 5184//UVD_JADP_MCIF_URGENT_CTRL 5185#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 5186#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 5187#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 5188#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 5189#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 5190#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 5191#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 5192#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 5193#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 5194#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 5195#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 5196#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 5197#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 5198#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 5199//UVD_JMI_URGENT_CTRL 5200#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 5201#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 5202#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 5203#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 5204#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 5205#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 5206#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 5207#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 5208//UVD_JPEG_ENC_PF_CTRL 5209#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0 5210#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1 5211#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L 5212#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L 5213//UVD_JMI_CTRL 5214#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 5215#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 5216#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 5217#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 5218#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 5219#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 5220#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 5221#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 5222#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 5223#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 5224#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 5225#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 5226#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 5227#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 5228//UVD_LMI_JRBC_CTRL 5229#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5230#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5231#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 5232#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 5233#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 5234#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 5235#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5236#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5237#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5238#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5239#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 5240#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 5241//UVD_LMI_JPEG_CTRL 5242#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5243#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5244#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 5245#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 5246#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 5247#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 5248#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5249#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5250#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5251#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5252#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 5253#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 5254//UVD_JMI_EJRBC_CTRL 5255#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5256#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5257#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 5258#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 5259#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 5260#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 5261#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5262#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5263#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5264#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5265#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 5266#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 5267//UVD_LMI_EJPEG_CTRL 5268#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5269#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5270#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 5271#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 5272#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 5273#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 5274#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5275#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5276#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5277#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5278#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 5279#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 5280//UVD_JMI_SCALER_CTRL 5281#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5282#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5283#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4 5284#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8 5285#define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14 5286#define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16 5287#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5288#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5289#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5290#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5291#define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L 5292#define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L 5293//JPEG_LMI_DROP 5294#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 5295#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 5296#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 5297#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 5298#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 5299#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 5300#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 5301#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 5302//UVD_JMI_EJPEG_DROP 5303#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0 5304#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1 5305#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2 5306#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3 5307#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4 5308#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5 5309#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L 5310#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L 5311#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L 5312#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L 5313#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L 5314#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L 5315//JPEG_MEMCHECK_CLAMPING 5316#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd 5317#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe 5318#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16 5319#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17 5320#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19 5321#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a 5322#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 5323#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L 5324#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L 5325#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L 5326#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L 5327#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L 5328#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L 5329#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 5330//UVD_JMI_EJPEG_MEMCHECK_CLAMPING 5331#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0 5332#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1 5333#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2 5334#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3 5335#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4 5336#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5 5337#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f 5338#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L 5339#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L 5340#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L 5341#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L 5342#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L 5343#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L 5344#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L 5345//UVD_LMI_JRBC_IB_VMID 5346#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 5347#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 5348#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 5349#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 5350#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 5351#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5352//UVD_LMI_JRBC_RB_VMID 5353#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 5354#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 5355#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 5356#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 5357#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 5358#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5359//UVD_LMI_JPEG_VMID 5360#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 5361#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 5362#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 5363#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 5364#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 5365#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 5366//UVD_JMI_ENC_JRBC_IB_VMID 5367#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 5368#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 5369#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 5370#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 5371#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 5372#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5373//UVD_JMI_ENC_JRBC_RB_VMID 5374#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 5375#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 5376#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 5377#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 5378#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 5379#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5380//UVD_JMI_ENC_JPEG_VMID 5381#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 5382#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 5383#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 5384#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 5385#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 5386#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 5387#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 5388#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 5389#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 5390#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 5391#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 5392#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 5393//JPEG_MEMCHECK_SAFE_ADDR 5394#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 5395#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 5396//JPEG_MEMCHECK_SAFE_ADDR_64BIT 5397#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 5398#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 5399//UVD_JMI_LAT_CTRL 5400#define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 5401#define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 5402#define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 5403#define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 5404#define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 5405#define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 5406#define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 5407#define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 5408#define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 5409#define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 5410#define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 5411#define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 5412//UVD_JMI_LAT_CNTR 5413#define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 5414#define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 5415#define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 5416#define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 5417//UVD_JMI_AVG_LAT_CNTR 5418#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 5419#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 5420#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 5421#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 5422#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 5423#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 5424//UVD_JMI_PERFMON_CTRL 5425#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 5426#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 5427#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 5428#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 5429//UVD_JMI_PERFMON_COUNT_LO 5430#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 5431#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 5432//UVD_JMI_PERFMON_COUNT_HI 5433#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 5434#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 5435//UVD_JMI_CLEAN_STATUS 5436#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 5437#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 5438#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 5439#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 5440#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4 5441#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5 5442#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6 5443#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7 5444#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8 5445#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9 5446#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa 5447#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb 5448#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc 5449#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd 5450#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe 5451#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf 5452#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10 5453#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 5454#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 5455#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 5456#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 5457#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L 5458#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L 5459#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L 5460#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L 5461#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L 5462#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L 5463#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L 5464#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L 5465#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L 5466#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L 5467#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L 5468#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L 5469#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L 5470//UVD_LMI_JPEG_READ_64BIT_BAR_LOW 5471#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5472#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5473//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 5474#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5475#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5476//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 5477#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5478#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5479//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 5480#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5481#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5482//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 5483#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5484#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5485//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 5486#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5487#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5488//UVD_LMI_JRBC_RB_64BIT_BAR_LOW 5489#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5490#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5491//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 5492#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5493#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5494//UVD_LMI_JRBC_IB_64BIT_BAR_LOW 5495#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5496#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5497//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 5498#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5499#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5500//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 5501#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5502#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5503//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 5504#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5505#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5506//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 5507#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5508#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5509//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 5510#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5511#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5512//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 5513#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5514#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5515//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 5516#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5517#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5518//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 5519#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5520#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5521//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 5522#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5523#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5524//UVD_JMI_PEL_RD_64BIT_BAR_LOW 5525#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5526#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5527//UVD_JMI_PEL_RD_64BIT_BAR_HIGH 5528#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5529#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5530//UVD_JMI_BS_WR_64BIT_BAR_LOW 5531#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5532#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5533//UVD_JMI_BS_WR_64BIT_BAR_HIGH 5534#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5535#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5536//UVD_JMI_SCALAR_RD_64BIT_BAR_LOW 5537#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5538#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5539//UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 5540#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5541#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5542//UVD_JMI_SCALAR_WR_64BIT_BAR_LOW 5543#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5544#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5545//UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 5546#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5547#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5548//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 5549#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5550#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5551//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 5552#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5553#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5554//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 5555#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5556#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5557//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 5558#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5559#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5560//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 5561#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5562#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5563//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 5564#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5565#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5566//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 5567#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5568#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5569//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 5570#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5571#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5572//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 5573#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5574#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5575//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 5576#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5577#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5578//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 5579#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5580#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5581//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 5582#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5583#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5584//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 5585#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5586#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5587//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 5588#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5589#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5590//UVD_LMI_JPEG_PREEMPT_VMID 5591#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 5592#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 5593//UVD_LMI_ENC_JPEG_PREEMPT_VMID 5594#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 5595#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 5596//UVD_LMI_JPEG2_VMID 5597#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 5598#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 5599#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 5600#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 5601//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 5602#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5603#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5604//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 5605#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5606#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5607//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 5608#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5609#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5610//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 5611#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5612#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5613//UVD_LMI_JPEG_CTRL2 5614#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 5615#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 5616#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 5617#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 5618#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 5619#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 5620#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 5621#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 5622#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 5623#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 5624#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 5625#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 5626//UVD_JMI_DEC_SWAP_CNTL 5627#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 5628#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 5629#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 5630#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 5631#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 5632#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 5633#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 5634#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 5635#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 5636#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 5637#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 5638#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 5639#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 5640#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 5641#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 5642#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 5643#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 5644#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 5645//UVD_JMI_ENC_SWAP_CNTL 5646#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 5647#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 5648#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 5649#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 5650#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 5651#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 5652#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 5653#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 5654#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 5655#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 5656#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 5657#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 5658#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 5659#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 5660#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 5661#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 5662#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 5663#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 5664#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 5665#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 5666#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 5667#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 5668#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 5669#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 5670//UVD_JMI_CNTL 5671#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 5672#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 5673#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 5674#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 5675//UVD_JMI_ATOMIC_CNTL 5676#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 5677#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 5678#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 5679#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 5680#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 5681#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 5682#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 5683#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 5684#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 5685#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 5686#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 5687#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 5688//UVD_JMI_ATOMIC_CNTL2 5689#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 5690#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 5691#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 5692#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 5693//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 5694#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5695#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5696//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 5697#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5698#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5699//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 5700#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5701#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5702//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 5703#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5704#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5705//JPEG2_LMI_DROP 5706#define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0 5707#define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1 5708#define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L 5709#define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L 5710//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 5711#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5712#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5713//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 5714#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5715#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5716//UVD_JMI_DEC_SWAP_CNTL2 5717#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 5718#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 5719#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 5720#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 5721//UVD_JMI_DJPEG_RAS_CNTL 5722#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0 5723#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1 5724#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2 5725#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3 5726#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4 5727#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L 5728#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L 5729#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L 5730#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L 5731#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L 5732//UVD_JMI_EJPEG_RAS_CNTL 5733#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0 5734#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1 5735#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2 5736#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3 5737#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4 5738#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L 5739#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L 5740#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L 5741#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L 5742#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L 5743//UVD_JPEG_DEC2_PF_CTRL 5744#define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS__SHIFT 0x0 5745#define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING__SHIFT 0x1 5746#define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_HANDLING_DIS_MASK 0x00000001L 5747#define UVD_JPEG_DEC2_PF_CTRL__DEC2_PF_SW_GATING_MASK 0x00000002L 5748 5749 5750// addressBlock: uvd_uvd_jpeg_common_dec 5751//JPEG_SOFT_RESET_STATUS 5752#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 5753#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 5754#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 5755#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 5756#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 5757#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 5758#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 5759#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 5760#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 5761#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 5762#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 5763#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 5764//JPEG_SYS_INT_EN 5765#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 5766#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 5767#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 5768#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 5769#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 5770#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 5771#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 5772#define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x7 5773#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x8 5774#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x9 5775#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 5776#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 5777#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 5778#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 5779#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 5780#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 5781#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 5782#define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00000080L 5783#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000100L 5784#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000200L 5785//JPEG_SYS_INT_STATUS 5786#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 5787#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 5788#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 5789#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 5790#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 5791#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 5792#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 5793#define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x7 5794#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x8 5795#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x9 5796#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 5797#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 5798#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 5799#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 5800#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 5801#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 5802#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 5803#define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00000080L 5804#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000100L 5805#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000200L 5806//JPEG_SYS_INT_ACK 5807#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 5808#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 5809#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 5810#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 5811#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 5812#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 5813#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 5814#define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x7 5815#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x8 5816#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x9 5817#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 5818#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 5819#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 5820#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 5821#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 5822#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 5823#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 5824#define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00000080L 5825#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000100L 5826#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000200L 5827//JPEG_MEMCHECK_SYS_INT_EN 5828#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0 5829#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1 5830#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2 5831#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3 5832#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4 5833#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5 5834#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6 5835#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7 5836#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8 5837#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9 5838#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa 5839#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb 5840#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L 5841#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L 5842#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L 5843#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L 5844#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L 5845#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L 5846#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L 5847#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L 5848#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L 5849#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L 5850#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L 5851#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L 5852//JPEG_MEMCHECK_SYS_INT_STAT 5853#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0 5854#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1 5855#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2 5856#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3 5857#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4 5858#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5 5859#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6 5860#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7 5861#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8 5862#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9 5863#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa 5864#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb 5865#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc 5866#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd 5867#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe 5868#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf 5869#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10 5870#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11 5871#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12 5872#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13 5873#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14 5874#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15 5875#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16 5876#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17 5877#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L 5878#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L 5879#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L 5880#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L 5881#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L 5882#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L 5883#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L 5884#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L 5885#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L 5886#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L 5887#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L 5888#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L 5889#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L 5890#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L 5891#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L 5892#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L 5893#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L 5894#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L 5895#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L 5896#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L 5897#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L 5898#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L 5899#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L 5900#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L 5901//JPEG_MEMCHECK_SYS_INT_ACK 5902#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0 5903#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1 5904#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2 5905#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3 5906#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4 5907#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5 5908#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6 5909#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7 5910#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8 5911#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9 5912#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa 5913#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb 5914#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc 5915#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd 5916#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe 5917#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf 5918#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10 5919#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11 5920#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12 5921#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13 5922#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14 5923#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15 5924#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16 5925#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17 5926#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L 5927#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L 5928#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L 5929#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L 5930#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L 5931#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L 5932#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L 5933#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L 5934#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L 5935#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L 5936#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L 5937#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L 5938#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L 5939#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L 5940#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L 5941#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L 5942#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L 5943#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L 5944#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L 5945#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L 5946#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L 5947#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L 5948#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L 5949#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L 5950//UVD_JPEG_IOV_ACTIVE_FCN_ID 5951#define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 5952#define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 5953#define UVD_JPEG_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 5954#define UVD_JPEG_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 5955//JPEG_MASTINT_EN 5956#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 5957#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 5958#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 5959#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 5960//JPEG_IH_CTRL 5961#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 5962#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 5963#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 5964#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 5965#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 5966#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 5967#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 5968#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 5969#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 5970#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 5971#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 5972#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 5973//JRBBM_ARB_CTRL 5974#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 5975#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 5976#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 5977#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 5978#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 5979#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 5980 5981 5982// addressBlock: uvd_uvd_jpeg_common_sclk_dec 5983//JPEG_CGC_GATE 5984#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 5985#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 5986#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 5987#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 5988#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 5989#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 5990#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 5991#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 5992#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 5993#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 5994//JPEG_CGC_CTRL 5995#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 5996#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 5997#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 5998#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 5999#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 6000#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 6001#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 6002#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 6003#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 6004#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 6005#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00001FE0L 6006#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 6007#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 6008#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 6009#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 6010#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 6011//JPEG_CGC_STATUS 6012#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 6013#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 6014#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 6015#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 6016#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 6017#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 6018#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 6019#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 6020#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 6021#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 6022#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 6023#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 6024#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 6025#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 6026#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 6027#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 6028#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 6029#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 6030//JPEG_COMN_CGC_MEM_CTRL 6031#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 6032#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 6033#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 6034#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN__SHIFT 0x3 6035#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 6036#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 6037#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 6038#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 6039#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 6040#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN_MASK 0x00000008L 6041#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 6042#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 6043//JPEG_DEC_CGC_MEM_CTRL 6044#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 6045#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 6046#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 6047#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_SW_EN__SHIFT 0x3 6048#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 6049#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 6050#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 6051#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_SW_EN_MASK 0x00000008L 6052//JPEG2_DEC_CGC_MEM_CTRL 6053#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 6054#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 6055#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 6056#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN__SHIFT 0x3 6057#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 6058#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 6059#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 6060#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN_MASK 0x00000008L 6061//JPEG_ENC_CGC_MEM_CTRL 6062#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 6063#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 6064#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 6065#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN__SHIFT 0x3 6066#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 6067#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 6068#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 6069#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN_MASK 0x00000008L 6070//JPEG_SOFT_RESET2 6071#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 6072#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 6073//JPEG_PERF_BANK_CONF 6074#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 6075#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 6076#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 6077#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 6078#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 6079#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 6080//JPEG_PERF_BANK_EVENT_SEL 6081#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 6082#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 6083#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 6084#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 6085#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 6086#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 6087#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 6088#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 6089//JPEG_PERF_BANK_COUNT0 6090#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 6091#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 6092//JPEG_PERF_BANK_COUNT1 6093#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 6094#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 6095//JPEG_PERF_BANK_COUNT2 6096#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 6097#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 6098//JPEG_PERF_BANK_COUNT3 6099#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 6100#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 6101 6102 6103// addressBlock: uvd_uvd_pg_dec 6104//UVD_PGFSM_CONFIG 6105#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 6106#define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 0x2 6107#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 6108#define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 0x6 6109#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 6110#define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 0xa 6111#define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 0xc 6112#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 6113#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 6114#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 6115#define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 0x14 6116#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 6117#define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 0x18 6118#define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 0x1a 6119#define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT 0x1c 6120#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 6121#define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG_MASK 0x0000000CL 6122#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 6123#define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG_MASK 0x000000C0L 6124#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 6125#define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG_MASK 0x00000C00L 6126#define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG_MASK 0x00003000L 6127#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 6128#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 6129#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 6130#define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG_MASK 0x00300000L 6131#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 6132#define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG_MASK 0x03000000L 6133#define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG_MASK 0x0C000000L 6134#define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG_MASK 0x30000000L 6135//UVD_PGFSM_STATUS 6136#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 6137#define UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 0x2 6138#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 6139#define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 0x6 6140#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 6141#define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 0xa 6142#define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 0xc 6143#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 6144#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 6145#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 6146#define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 0x14 6147#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 6148#define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 0x18 6149#define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 0x1a 6150#define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT 0x1c 6151#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 6152#define UVD_PGFSM_STATUS__UVDS_PWR_STATUS_MASK 0x0000000CL 6153#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 6154#define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS_MASK 0x000000C0L 6155#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 6156#define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS_MASK 0x00000C00L 6157#define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS_MASK 0x00003000L 6158#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 6159#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 6160#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 6161#define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS_MASK 0x00300000L 6162#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 6163#define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS_MASK 0x03000000L 6164#define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS_MASK 0x0C000000L 6165#define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS_MASK 0x30000000L 6166//UVD_POWER_STATUS 6167#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 6168#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 6169#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 6170#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 6171#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 6172#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 6173#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 6174#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 6175#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 6176#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 6177#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 6178#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 6179#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 6180#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 6181//UVD_JPEG_POWER_STATUS 6182#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 6183#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 6184#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 6185#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 6186#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 6187#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 6188#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 6189#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 6190#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 6191#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 6192//UVD_MC_DJPEG_RD_SPACE 6193#define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 6194#define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL 6195//UVD_MC_DJPEG_WR_SPACE 6196#define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 6197#define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL 6198//UVD_PG_IND_INDEX 6199#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 6200#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 6201//UVD_PG_IND_DATA 6202#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 6203#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 6204//CC_UVD_HARVESTING 6205#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 6206#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 6207#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 6208#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 6209//UVD_DPG_LMA_CTL 6210#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 6211#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 6212#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 6213#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 6214#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe 6215#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 6216#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 6217#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 6218#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 6219#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFFC000L 6220//UVD_DPG_LMA_DATA 6221#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 6222#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 6223//UVD_DPG_LMA_MASK 6224#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 6225#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 6226//UVD_DPG_PAUSE 6227#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 6228#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 6229#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 6230#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 6231#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 6232#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 6233#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 6234#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 6235//UVD_SCRATCH1 6236#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 6237#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 6238//UVD_SCRATCH2 6239#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 6240#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 6241//UVD_SCRATCH3 6242#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 6243#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 6244//UVD_SCRATCH4 6245#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 6246#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 6247//UVD_SCRATCH5 6248#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 6249#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 6250//UVD_SCRATCH6 6251#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 6252#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 6253//UVD_SCRATCH7 6254#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 6255#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 6256//UVD_SCRATCH8 6257#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 6258#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 6259//UVD_SCRATCH9 6260#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 6261#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 6262//UVD_SCRATCH10 6263#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 6264#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 6265//UVD_SCRATCH11 6266#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 6267#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 6268//UVD_SCRATCH12 6269#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 6270#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 6271//UVD_SCRATCH13 6272#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 6273#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 6274//UVD_SCRATCH14 6275#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 6276#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 6277//UVD_FREE_COUNTER_REG 6278#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 6279#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 6280//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 6281#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6282#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6283//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 6284#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6285#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6286//UVD_DPG_VCPU_CACHE_OFFSET0 6287#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 6288#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 6289//UVD_DPG_LMI_VCPU_CACHE_VMID 6290#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 6291#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 6292//UVD_REG_FILTER_EN 6293#define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 6294#define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 6295#define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 6296#define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 6297#define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L 6298#define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L 6299#define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L 6300#define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L 6301//UVD_PF_STATUS 6302#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 6303#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 6304#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 6305#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 6306#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 6307#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 6308#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 6309#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 6310#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 6311#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 6312#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 6313#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 6314#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 6315#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 6316#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 6317#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 6318#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 6319#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 6320#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 6321#define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 6322#define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 6323#define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 6324#define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 6325#define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 6326#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 6327#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 6328#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 6329#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 6330#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 6331#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 6332#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 6333#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 6334#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 6335#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 6336#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 6337#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 6338#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 6339#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 6340#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 6341#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 6342#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 6343#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 6344#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 6345#define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L 6346#define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L 6347#define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L 6348#define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L 6349#define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L 6350//UVD_DPG_CLK_EN_VCPU_REPORT 6351#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 6352#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 6353#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 6354#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 6355//CC_UVD_VCPU_ERR_DETECT_BOT_LO 6356#define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc 6357#define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L 6358//CC_UVD_VCPU_ERR_DETECT_BOT_HI 6359#define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 6360#define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0x0000FFFFL 6361//CC_UVD_VCPU_ERR_DETECT_TOP_LO 6362#define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc 6363#define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L 6364//CC_UVD_VCPU_ERR_DETECT_TOP_HI 6365#define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 6366#define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0x0000FFFFL 6367//CC_UVD_VCPU_ERR 6368#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 6369#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 6370#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 6371#define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 6372#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L 6373#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L 6374#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L 6375#define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L 6376//CC_UVD_VCPU_ERR_INST_ADDR_LO 6377#define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 6378#define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL 6379//CC_UVD_VCPU_ERR_INST_ADDR_HI 6380#define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 6381#define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0x0000FFFFL 6382//UVD_LMI_MMSCH_NC_SPACE 6383#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE__SHIFT 0x0 6384#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE__SHIFT 0x3 6385#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE__SHIFT 0x6 6386#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE__SHIFT 0x9 6387#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE__SHIFT 0xc 6388#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE__SHIFT 0xf 6389#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE__SHIFT 0x12 6390#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE__SHIFT 0x15 6391#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE_MASK 0x00000007L 6392#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE_MASK 0x00000038L 6393#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE_MASK 0x000001C0L 6394#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE_MASK 0x00000E00L 6395#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE_MASK 0x00007000L 6396#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE_MASK 0x00038000L 6397#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE_MASK 0x001C0000L 6398#define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE_MASK 0x00E00000L 6399//UVD_LMI_ATOMIC_SPACE 6400#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE__SHIFT 0x0 6401#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE__SHIFT 0x3 6402#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE__SHIFT 0x6 6403#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE__SHIFT 0x9 6404#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE_MASK 0x00000007L 6405#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE_MASK 0x00000038L 6406#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE_MASK 0x000001C0L 6407#define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE_MASK 0x00000E00L 6408//UVD_GFX8_ADDR_CONFIG 6409#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 6410#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6411//UVD_GFX10_ADDR_CONFIG 6412#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 6413#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 6414#define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 6415#define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 6416#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 6417#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 6418#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 6419#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 6420#define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 6421#define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 6422#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 6423#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 6424//UVD_GPCNT2_CNTL 6425#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 6426#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 6427#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 6428#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 6429#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 6430#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 6431//UVD_GPCNT2_TARGET_LOWER 6432#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 6433#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 6434//UVD_GPCNT2_STATUS_LOWER 6435#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 6436#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 6437//UVD_GPCNT2_TARGET_UPPER 6438#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 6439#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 6440//UVD_GPCNT2_STATUS_UPPER 6441#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 6442#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 6443//UVD_GPCNT3_CNTL 6444#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 6445#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 6446#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 6447#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 6448#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 6449#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 6450#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 6451#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 6452#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 6453#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 6454//UVD_GPCNT3_TARGET_LOWER 6455#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 6456#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 6457//UVD_GPCNT3_STATUS_LOWER 6458#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 6459#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 6460//UVD_GPCNT3_TARGET_UPPER 6461#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 6462#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 6463//UVD_GPCNT3_STATUS_UPPER 6464#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 6465#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 6466//UVD_VCLK_DS_CNTL 6467#define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 6468#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 6469#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 6470#define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 6471#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 6472#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 6473//UVD_DCLK_DS_CNTL 6474#define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 6475#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 6476#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 6477#define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 6478#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 6479#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 6480//UVD_TSC_LOWER 6481#define UVD_TSC_LOWER__COUNT__SHIFT 0x0 6482#define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 6483//UVD_TSC_UPPER 6484#define UVD_TSC_UPPER__COUNT__SHIFT 0x0 6485#define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 6486//VCN_FEATURES 6487#define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 6488#define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 6489#define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 6490#define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 6491#define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 6492#define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 6493#define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 6494#define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 6495#define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 6496#define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 6497#define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa 6498#define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb 6499#define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc 6500#define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd 6501#define VCN_FEATURES__HAS_AV1_ENC__SHIFT 0xe 6502#define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c 6503#define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L 6504#define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L 6505#define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L 6506#define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L 6507#define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L 6508#define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L 6509#define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L 6510#define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L 6511#define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L 6512#define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L 6513#define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L 6514#define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L 6515#define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L 6516#define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L 6517#define VCN_FEATURES__HAS_AV1_ENC_MASK 0x00004000L 6518#define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L 6519//UVD_GPUIOV_STATUS 6520#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 6521#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L 6522//UVD_SCRATCH15 6523#define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT 0x0 6524#define UVD_SCRATCH15__SCRATCH15_DATA_MASK 0xFFFFFFFFL 6525//UVD_IPX_DLDO_CONFIG 6526#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x2 6527#define UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT 0x4 6528#define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT 0x6 6529#define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT 0x8 6530#define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT 0xa 6531#define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT 0xc 6532#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000CL 6533#define UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG_MASK 0x00000030L 6534#define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG_MASK 0x000000C0L 6535#define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG_MASK 0x00000300L 6536#define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG_MASK 0x00000C00L 6537#define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG_MASK 0x00003000L 6538//UVD_IPX_DLDO_STATUS 6539#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x1 6540#define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT 0x2 6541#define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT 0x3 6542#define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT 0x4 6543#define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT 0x5 6544#define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT 0x6 6545#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002L 6546#define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK 0x00000004L 6547#define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK 0x00000008L 6548#define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK 0x00000010L 6549#define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK 0x00000020L 6550#define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK 0x00000040L 6551//UVD_SCRATCH32 6552#define UVD_SCRATCH32__SCRATCH32_DATA__SHIFT 0x0 6553#define UVD_SCRATCH32__SCRATCH32_DATA_MASK 0xFFFFFFFFL 6554//UVD_VERSION 6555#define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 6556#define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 6557#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 6558#define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 6559#define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL 6560#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L 6561#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 6562#define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 6563//VCN_UMSCH_CNTL 6564#define VCN_UMSCH_CNTL__umsch_fw_en__SHIFT 0x0 6565#define VCN_UMSCH_CNTL__umsch_fw_en_MASK 0x00000001L 6566//VCN_RB_DB_CTRL 6567#define VCN_RB_DB_CTRL__OFFSET__SHIFT 0x2 6568#define VCN_RB_DB_CTRL__EN__SHIFT 0x1e 6569#define VCN_RB_DB_CTRL__HIT__SHIFT 0x1f 6570#define VCN_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6571#define VCN_RB_DB_CTRL__EN_MASK 0x40000000L 6572#define VCN_RB_DB_CTRL__HIT_MASK 0x80000000L 6573//VCN_JPEG_DB_CTRL 6574#define VCN_JPEG_DB_CTRL__OFFSET__SHIFT 0x2 6575#define VCN_JPEG_DB_CTRL__EN__SHIFT 0x1e 6576#define VCN_JPEG_DB_CTRL__HIT__SHIFT 0x1f 6577#define VCN_JPEG_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6578#define VCN_JPEG_DB_CTRL__EN_MASK 0x40000000L 6579#define VCN_JPEG_DB_CTRL__HIT_MASK 0x80000000L 6580//VCN_RB1_DB_CTRL 6581#define VCN_RB1_DB_CTRL__OFFSET__SHIFT 0x2 6582#define VCN_RB1_DB_CTRL__EN__SHIFT 0x1e 6583#define VCN_RB1_DB_CTRL__HIT__SHIFT 0x1f 6584#define VCN_RB1_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6585#define VCN_RB1_DB_CTRL__EN_MASK 0x40000000L 6586#define VCN_RB1_DB_CTRL__HIT_MASK 0x80000000L 6587//VCN_RB2_DB_CTRL 6588#define VCN_RB2_DB_CTRL__OFFSET__SHIFT 0x2 6589#define VCN_RB2_DB_CTRL__EN__SHIFT 0x1e 6590#define VCN_RB2_DB_CTRL__HIT__SHIFT 0x1f 6591#define VCN_RB2_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6592#define VCN_RB2_DB_CTRL__EN_MASK 0x40000000L 6593#define VCN_RB2_DB_CTRL__HIT_MASK 0x80000000L 6594//VCN_RB3_DB_CTRL 6595#define VCN_RB3_DB_CTRL__OFFSET__SHIFT 0x2 6596#define VCN_RB3_DB_CTRL__EN__SHIFT 0x1e 6597#define VCN_RB3_DB_CTRL__HIT__SHIFT 0x1f 6598#define VCN_RB3_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6599#define VCN_RB3_DB_CTRL__EN_MASK 0x40000000L 6600#define VCN_RB3_DB_CTRL__HIT_MASK 0x80000000L 6601//VCN_RB4_DB_CTRL 6602#define VCN_RB4_DB_CTRL__OFFSET__SHIFT 0x2 6603#define VCN_RB4_DB_CTRL__EN__SHIFT 0x1e 6604#define VCN_RB4_DB_CTRL__HIT__SHIFT 0x1f 6605#define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6606#define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L 6607#define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L 6608//VCN_UMSCH_RB_DB_CTRL 6609#define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2 6610#define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e 6611#define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f 6612#define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6613#define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L 6614#define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L 6615//VCN_AGDB_CTRL0 6616#define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2 6617#define VCN_AGDB_CTRL0__EN__SHIFT 0x1e 6618#define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f 6619#define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL 6620#define VCN_AGDB_CTRL0__EN_MASK 0x40000000L 6621#define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L 6622//VCN_AGDB_CTRL1 6623#define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2 6624#define VCN_AGDB_CTRL1__EN__SHIFT 0x1e 6625#define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f 6626#define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL 6627#define VCN_AGDB_CTRL1__EN_MASK 0x40000000L 6628#define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L 6629//VCN_AGDB_CTRL2 6630#define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2 6631#define VCN_AGDB_CTRL2__EN__SHIFT 0x1e 6632#define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f 6633#define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL 6634#define VCN_AGDB_CTRL2__EN_MASK 0x40000000L 6635#define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L 6636//VCN_AGDB_CTRL3 6637#define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2 6638#define VCN_AGDB_CTRL3__EN__SHIFT 0x1e 6639#define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f 6640#define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL 6641#define VCN_AGDB_CTRL3__EN_MASK 0x40000000L 6642#define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L 6643//VCN_AGDB_CTRL4 6644#define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2 6645#define VCN_AGDB_CTRL4__EN__SHIFT 0x1e 6646#define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f 6647#define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL 6648#define VCN_AGDB_CTRL4__EN_MASK 0x40000000L 6649#define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L 6650//VCN_AGDB_CTRL5 6651#define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2 6652#define VCN_AGDB_CTRL5__EN__SHIFT 0x1e 6653#define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f 6654#define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL 6655#define VCN_AGDB_CTRL5__EN_MASK 0x40000000L 6656#define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L 6657//VCN_AGDB_MASK0 6658#define VCN_AGDB_MASK0__MASK__SHIFT 0x2 6659#define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL 6660//VCN_AGDB_MASK1 6661#define VCN_AGDB_MASK1__MASK__SHIFT 0x2 6662#define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL 6663//VCN_AGDB_MASK2 6664#define VCN_AGDB_MASK2__MASK__SHIFT 0x2 6665#define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL 6666//VCN_AGDB_MASK3 6667#define VCN_AGDB_MASK3__MASK__SHIFT 0x2 6668#define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL 6669//VCN_AGDB_MASK4 6670#define VCN_AGDB_MASK4__MASK__SHIFT 0x2 6671#define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL 6672//VCN_AGDB_MASK5 6673#define VCN_AGDB_MASK5__MASK__SHIFT 0x2 6674#define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL 6675//VCN_RB_ENABLE 6676#define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 6677#define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 6678#define VCN_RB_ENABLE__RB1_EN__SHIFT 0x2 6679#define VCN_RB_ENABLE__RB2_EN__SHIFT 0x3 6680#define VCN_RB_ENABLE__RB3_EN__SHIFT 0x4 6681#define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5 6682#define VCN_RB_ENABLE__UMSCH_RB_EN__SHIFT 0x6 6683#define VCN_RB_ENABLE__EJPEG_RB_EN__SHIFT 0x7 6684#define VCN_RB_ENABLE__AUDIO_RB_EN__SHIFT 0x8 6685#define VCN_RB_ENABLE__RB_EN_MASK 0x00000001L 6686#define VCN_RB_ENABLE__JPEG_RB_EN_MASK 0x00000002L 6687#define VCN_RB_ENABLE__RB1_EN_MASK 0x00000004L 6688#define VCN_RB_ENABLE__RB2_EN_MASK 0x00000008L 6689#define VCN_RB_ENABLE__RB3_EN_MASK 0x00000010L 6690#define VCN_RB_ENABLE__RB4_EN_MASK 0x00000020L 6691#define VCN_RB_ENABLE__UMSCH_RB_EN_MASK 0x00000040L 6692#define VCN_RB_ENABLE__EJPEG_RB_EN_MASK 0x00000080L 6693#define VCN_RB_ENABLE__AUDIO_RB_EN_MASK 0x00000100L 6694//VCN_RB_WPTR_CTRL 6695#define VCN_RB_WPTR_CTRL__RB_CS_EN__SHIFT 0x0 6696#define VCN_RB_WPTR_CTRL__JPEG_CS_EN__SHIFT 0x1 6697#define VCN_RB_WPTR_CTRL__RB1_CS_EN__SHIFT 0x2 6698#define VCN_RB_WPTR_CTRL__RB2_CS_EN__SHIFT 0x3 6699#define VCN_RB_WPTR_CTRL__RB3_CS_EN__SHIFT 0x4 6700#define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5 6701#define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN__SHIFT 0x6 6702#define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN__SHIFT 0x7 6703#define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN__SHIFT 0x8 6704#define VCN_RB_WPTR_CTRL__RB_CS_EN_MASK 0x00000001L 6705#define VCN_RB_WPTR_CTRL__JPEG_CS_EN_MASK 0x00000002L 6706#define VCN_RB_WPTR_CTRL__RB1_CS_EN_MASK 0x00000004L 6707#define VCN_RB_WPTR_CTRL__RB2_CS_EN_MASK 0x00000008L 6708#define VCN_RB_WPTR_CTRL__RB3_CS_EN_MASK 0x00000010L 6709#define VCN_RB_WPTR_CTRL__RB4_CS_EN_MASK 0x00000020L 6710#define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN_MASK 0x00000040L 6711#define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN_MASK 0x00000080L 6712#define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN_MASK 0x00000100L 6713//UVD_RB_RPTR 6714#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 6715#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 6716//UVD_RB_WPTR 6717#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 6718#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 6719//UVD_RB_RPTR2 6720#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 6721#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 6722//UVD_RB_WPTR2 6723#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 6724#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 6725//UVD_RB_RPTR3 6726#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 6727#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 6728//UVD_RB_WPTR3 6729#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 6730#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 6731//UVD_RB_RPTR4 6732#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 6733#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 6734//UVD_RB_WPTR4 6735#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 6736#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 6737//UVD_OUT_RB_RPTR 6738#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 6739#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 6740//UVD_OUT_RB_WPTR 6741#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 6742#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 6743//UVD_AUDIO_RB_RPTR 6744#define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 6745#define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 6746//UVD_AUDIO_RB_WPTR 6747#define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 6748#define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 6749//UVD_RBC_RB_RPTR 6750#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 6751#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 6752//UVD_RBC_RB_WPTR 6753#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 6754#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 6755//UVD_DPG_LMA_CTL2 6756#define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL__SHIFT 0x0 6757#define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN__SHIFT 0x1 6758#define UVD_DPG_LMA_CTL2__VID_WRITE_PTR__SHIFT 0x2 6759#define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR__SHIFT 0x9 6760#define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL_MASK 0x00000001L 6761#define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN_MASK 0x00000002L 6762#define UVD_DPG_LMA_CTL2__VID_WRITE_PTR_MASK 0x000001FCL 6763#define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L 6764 6765 6766// addressBlock: uvd_vcn_umsch_dec 6767//VCN_UMSCH_MES_CNTL 6768#define VCN_UMSCH_MES_CNTL__PIPE_ID__SHIFT 0x0 6769#define VCN_UMSCH_MES_CNTL__PerfPipeSel__SHIFT 0x2 6770#define VCN_UMSCH_MES_CNTL__RamClkGatingDisable__SHIFT 0x4 6771#define VCN_UMSCH_MES_CNTL__InterruptChickenBit__SHIFT 0x5 6772#define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis__SHIFT 0x6 6773#define VCN_UMSCH_MES_CNTL__PIPE_ID_MASK 0x00000003L 6774#define VCN_UMSCH_MES_CNTL__PerfPipeSel_MASK 0x0000000CL 6775#define VCN_UMSCH_MES_CNTL__RamClkGatingDisable_MASK 0x00000010L 6776#define VCN_UMSCH_MES_CNTL__InterruptChickenBit_MASK 0x00000020L 6777#define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis_MASK 0x00000040L 6778//UMSCH_CTL 6779#define UMSCH_CTL__P_RESET__SHIFT 0x0 6780#define UMSCH_CTL__UTCL2_CLIENT_ID__SHIFT 0x1 6781#define UMSCH_CTL__UMSCH_BUSY__SHIFT 0xa 6782#define UMSCH_CTL__IllegalRegReadAckLatency__SHIFT 0xd 6783#define UMSCH_CTL__P_RESET_MASK 0x00000001L 6784#define UMSCH_CTL__UTCL2_CLIENT_ID_MASK 0x000003FEL 6785#define UMSCH_CTL__UMSCH_BUSY_MASK 0x00000400L 6786#define UMSCH_CTL__IllegalRegReadAckLatency_MASK 0x0000E000L 6787//UMSCH_CTL2 6788#define UMSCH_CTL2__Spare__SHIFT 0x0 6789#define UMSCH_CTL2__Spare_MASK 0xFFFFFFFFL 6790//VCN_UMSCH_AGDB_WPTR0 6791#define VCN_UMSCH_AGDB_WPTR0__WPTR__SHIFT 0x4 6792#define VCN_UMSCH_AGDB_WPTR0__WPTR_MASK 0x007FFFF0L 6793//VCN_UMSCH_AGDB_WPTR1 6794#define VCN_UMSCH_AGDB_WPTR1__WPTR__SHIFT 0x4 6795#define VCN_UMSCH_AGDB_WPTR1__WPTR_MASK 0x007FFFF0L 6796//VCN_UMSCH_AGDB_WPTR2 6797#define VCN_UMSCH_AGDB_WPTR2__WPTR__SHIFT 0x4 6798#define VCN_UMSCH_AGDB_WPTR2__WPTR_MASK 0x007FFFF0L 6799//VCN_UMSCH_AGDB_WPTR3 6800#define VCN_UMSCH_AGDB_WPTR3__WPTR__SHIFT 0x4 6801#define VCN_UMSCH_AGDB_WPTR3__WPTR_MASK 0x007FFFF0L 6802//VCN_UMSCH_AGDB_WPTR4 6803#define VCN_UMSCH_AGDB_WPTR4__WPTR__SHIFT 0x4 6804#define VCN_UMSCH_AGDB_WPTR4__WPTR_MASK 0x007FFFF0L 6805//VCN_UMSCH_AGDB_WPTR5 6806#define VCN_UMSCH_AGDB_WPTR5__WPTR__SHIFT 0x4 6807#define VCN_UMSCH_AGDB_WPTR5__WPTR_MASK 0x007FFFF0L 6808//VCN_UMSCH_MAILBOX0 6809#define VCN_UMSCH_MAILBOX0__DATA__SHIFT 0x0 6810#define VCN_UMSCH_MAILBOX0__DATA_MASK 0xFFFFFFFFL 6811//VCN_UMSCH_MAILBOX_RESP0 6812#define VCN_UMSCH_MAILBOX_RESP0__DATA__SHIFT 0x0 6813#define VCN_UMSCH_MAILBOX_RESP0__DATA_MASK 0xFFFFFFFFL 6814//VCN_UMSCH_MAILBOX1 6815#define VCN_UMSCH_MAILBOX1__DATA__SHIFT 0x0 6816#define VCN_UMSCH_MAILBOX1__DATA_MASK 0xFFFFFFFFL 6817//VCN_UMSCH_MAILBOX_RESP1 6818#define VCN_UMSCH_MAILBOX_RESP1__DATA__SHIFT 0x0 6819#define VCN_UMSCH_MAILBOX_RESP1__DATA_MASK 0xFFFFFFFFL 6820//VCN_UMSCH_MAILBOX2 6821#define VCN_UMSCH_MAILBOX2__DATA__SHIFT 0x0 6822#define VCN_UMSCH_MAILBOX2__DATA_MASK 0xFFFFFFFFL 6823//VCN_UMSCH_MAILBOX_RESP2 6824#define VCN_UMSCH_MAILBOX_RESP2__DATA__SHIFT 0x0 6825#define VCN_UMSCH_MAILBOX_RESP2__DATA_MASK 0xFFFFFFFFL 6826//VCN_UMSCH_MAILBOX3 6827#define VCN_UMSCH_MAILBOX3__DATA__SHIFT 0x0 6828#define VCN_UMSCH_MAILBOX3__DATA_MASK 0xFFFFFFFFL 6829//VCN_UMSCH_MAILBOX_RESP3 6830#define VCN_UMSCH_MAILBOX_RESP3__DATA__SHIFT 0x0 6831#define VCN_UMSCH_MAILBOX_RESP3__DATA_MASK 0xFFFFFFFFL 6832//VCN_UMSCH_SPARE_REGISTER0 6833#define VCN_UMSCH_SPARE_REGISTER0__DATA__SHIFT 0x0 6834#define VCN_UMSCH_SPARE_REGISTER0__DATA_MASK 0xFFFFFFFFL 6835//VCN_UMSCH_SPARE_REGISTER1 6836#define VCN_UMSCH_SPARE_REGISTER1__DATA__SHIFT 0x0 6837#define VCN_UMSCH_SPARE_REGISTER1__DATA_MASK 0xFFFFFFFFL 6838//VCN_UMSCH_SPARE_REGISTER2 6839#define VCN_UMSCH_SPARE_REGISTER2__DATA__SHIFT 0x0 6840#define VCN_UMSCH_SPARE_REGISTER2__DATA_MASK 0xFFFFFFFFL 6841//VCN_UMSCH_SPARE_REGISTER3 6842#define VCN_UMSCH_SPARE_REGISTER3__DATA__SHIFT 0x0 6843#define VCN_UMSCH_SPARE_REGISTER3__DATA_MASK 0xFFFFFFFFL 6844//VCN_UMSCH_SPARE_REGISTER4 6845#define VCN_UMSCH_SPARE_REGISTER4__DATA__SHIFT 0x0 6846#define VCN_UMSCH_SPARE_REGISTER4__DATA_MASK 0xFFFFFFFFL 6847//VCN_UMSCH_SPARE_REGISTER5 6848#define VCN_UMSCH_SPARE_REGISTER5__DATA__SHIFT 0x0 6849#define VCN_UMSCH_SPARE_REGISTER5__DATA_MASK 0xFFFFFFFFL 6850//VCN_UMSCH_SPARE_REGISTER6 6851#define VCN_UMSCH_SPARE_REGISTER6__DATA__SHIFT 0x0 6852#define VCN_UMSCH_SPARE_REGISTER6__DATA_MASK 0xFFFFFFFFL 6853//VCN_UMSCH_SPARE_REGISTER7 6854#define VCN_UMSCH_SPARE_REGISTER7__DATA__SHIFT 0x0 6855#define VCN_UMSCH_SPARE_REGISTER7__DATA_MASK 0xFFFFFFFFL 6856//VCN_UMSCH_MES_UTCL1_CNTL 6857#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0 6858#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14 6859#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15 6860#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16 6861#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17 6862#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL 6863#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L 6864#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L 6865#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L 6866#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L 6867//VCN_UMSCH_MES_BUSY 6868#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0 6869#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1 6870#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2 6871#define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3 6872#define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4 6873#define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5 6874#define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6 6875#define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8 6876#define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa 6877#define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc 6878#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L 6879#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L 6880#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L 6881#define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L 6882#define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L 6883#define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L 6884#define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L 6885#define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L 6886#define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L 6887#define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L 6888//VCN_UMSCH_RB_BASE_LO 6889#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 6890#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 6891//VCN_UMSCH_RB_BASE_HI 6892#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 6893#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 6894//VCN_UMSCH_RB_SIZE 6895#define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4 6896#define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L 6897//VCN_UMSCH_RB_RPTR 6898#define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4 6899#define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L 6900//VCN_UMSCH_RB_WPTR 6901#define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4 6902#define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L 6903//VCN_UMSCH_MASTINT_EN 6904#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 6905#define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2 6906#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 6907#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 6908#define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L 6909#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 6910//VCN_UMSCH_IH_CTRL 6911#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 6912#define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1 6913#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 6914#define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3 6915#define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7 6916#define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13 6917#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 6918#define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 6919#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 6920#define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L 6921#define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 6922#define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L 6923//VCN_UMSCH_SYS_INT_EN 6924#define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0 6925#define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1 6926#define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2 6927#define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3 6928#define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4 6929#define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5 6930#define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6 6931#define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7 6932#define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L 6933#define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L 6934#define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L 6935#define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L 6936#define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L 6937#define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L 6938#define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L 6939#define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L 6940//VCN_UMSCH_SYS_INT_STATUS 6941#define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0 6942#define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1 6943#define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2 6944#define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3 6945#define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4 6946#define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5 6947#define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6 6948#define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7 6949#define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L 6950#define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L 6951#define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L 6952#define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L 6953#define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L 6954#define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L 6955#define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L 6956#define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L 6957//VCN_UMSCH_SYS_INT_ACK 6958#define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0 6959#define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1 6960#define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2 6961#define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3 6962#define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4 6963#define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5 6964#define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6 6965#define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7 6966#define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L 6967#define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L 6968#define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L 6969#define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L 6970#define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L 6971#define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L 6972#define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L 6973#define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L 6974//VCN_UMSCH_SYS_INT_SRC 6975#define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0 6976#define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1 6977#define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2 6978#define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3 6979#define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4 6980#define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5 6981#define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6 6982#define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7 6983#define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L 6984#define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L 6985#define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L 6986#define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L 6987#define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L 6988#define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L 6989#define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L 6990#define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L 6991//VCN_UMSCH_IH_CTX_CTRL 6992#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0 6993#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL 6994//UVD_UMSCH_FORCE 6995#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0 6996#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1 6997#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2 6998#define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE__SHIFT 0x3 6999#define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP__SHIFT 0x4 7000#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L 7001#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L 7002#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L 7003#define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE_MASK 0x00000008L 7004#define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP_MASK 0x00000010L 7005//UMSCH_MES_RESET_CTRL 7006#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0 7007#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L 7008 7009 7010// addressBlock: uvd_vcn_cprs64dec 7011//VCN_MES_PRGRM_CNTR_START 7012#define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 7013#define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL 7014//VCN_MES_INTR_ROUTINE_START 7015#define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 7016#define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL 7017//VCN_MES_MTVEC_LO 7018#define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 7019#define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL 7020//VCN_MES_INTR_ROUTINE_START_HI 7021#define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 7022#define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL 7023//VCN_MES_MTVEC_HI 7024#define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 7025#define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL 7026//VCN_MES_CNTL 7027#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 7028#define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 7029#define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 7030#define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 7031#define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 7032#define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a 7033#define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b 7034#define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c 7035#define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d 7036#define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e 7037#define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f 7038#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L 7039#define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L 7040#define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L 7041#define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L 7042#define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L 7043#define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L 7044#define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L 7045#define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L 7046#define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L 7047#define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L 7048#define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L 7049//VCN_MES_PIPE_PRIORITY_CNTS 7050#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 7051#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 7052#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 7053#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 7054#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 7055#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 7056#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 7057#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 7058//VCN_MES_PIPE0_PRIORITY 7059#define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 7060#define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 7061//VCN_MES_PIPE1_PRIORITY 7062#define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 7063#define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 7064//VCN_MES_PIPE2_PRIORITY 7065#define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 7066#define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 7067//VCN_MES_PIPE3_PRIORITY 7068#define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 7069#define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L 7070//VCN_MES_HEADER_DUMP 7071#define VCN_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 7072#define VCN_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL 7073//VCN_MES_MIE_LO 7074#define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0 7075#define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL 7076//VCN_MES_MIE_HI 7077#define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0 7078#define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL 7079//VCN_MES_INTERRUPT 7080#define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0 7081#define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL 7082//VCN_MES_SCRATCH_INDEX 7083#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 7084#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f 7085#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL 7086#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L 7087//VCN_MES_SCRATCH_DATA 7088#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 7089#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL 7090//VCN_MES_INSTR_PNTR 7091#define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 7092#define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL 7093//VCN_MES_MSCRATCH_HI 7094#define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0 7095#define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL 7096//VCN_MES_MSCRATCH_LO 7097#define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0 7098#define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL 7099//VCN_MES_MSTATUS_LO 7100#define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 7101#define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL 7102//VCN_MES_MSTATUS_HI 7103#define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 7104#define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL 7105//VCN_MES_MEPC_LO 7106#define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 7107#define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL 7108//VCN_MES_MEPC_HI 7109#define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 7110#define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL 7111//VCN_MES_MCAUSE_LO 7112#define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 7113#define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL 7114//VCN_MES_MCAUSE_HI 7115#define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 7116#define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL 7117//VCN_MES_MBADADDR_LO 7118#define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 7119#define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL 7120//VCN_MES_MBADADDR_HI 7121#define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 7122#define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL 7123//VCN_MES_MIP_LO 7124#define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0 7125#define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL 7126//VCN_MES_MIP_HI 7127#define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0 7128#define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL 7129//VCN_MES_IC_OP_CNTL 7130#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 7131#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 7132#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 7133#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L 7134#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L 7135#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L 7136//VCN_MES_MCYCLE_LO 7137#define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 7138#define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL 7139//VCN_MES_MCYCLE_HI 7140#define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 7141#define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL 7142//VCN_MES_MTIME_LO 7143#define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0 7144#define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL 7145//VCN_MES_MTIME_HI 7146#define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0 7147#define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL 7148//VCN_MES_MINSTRET_LO 7149#define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 7150#define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL 7151//VCN_MES_MINSTRET_HI 7152#define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 7153#define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL 7154//VCN_MES_MISA_LO 7155#define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0 7156#define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL 7157//VCN_MES_MISA_HI 7158#define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0 7159#define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL 7160//VCN_MES_MVENDORID_LO 7161#define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 7162#define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL 7163//VCN_MES_MVENDORID_HI 7164#define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 7165#define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL 7166//VCN_MES_MARCHID_LO 7167#define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 7168#define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL 7169//VCN_MES_MARCHID_HI 7170#define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 7171#define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL 7172//VCN_MES_MIMPID_LO 7173#define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 7174#define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL 7175//VCN_MES_MIMPID_HI 7176#define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 7177#define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL 7178//VCN_MES_MHARTID_LO 7179#define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 7180#define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL 7181//VCN_MES_MHARTID_HI 7182#define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 7183#define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL 7184//VCN_MES_DC_BASE_CNTL 7185#define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 7186#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 7187#define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL 7188#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 7189//VCN_MES_DC_OP_CNTL 7190#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 7191#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 7192#define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 7193#define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 7194#define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4 7195#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L 7196#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L 7197#define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L 7198#define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L 7199#define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L 7200//VCN_MES_MTIMECMP_LO 7201#define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 7202#define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL 7203//VCN_MES_MTIMECMP_HI 7204#define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 7205#define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL 7206//VCN_MES_GP0_LO 7207#define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 7208#define VCN_MES_GP0_LO__DATA__SHIFT 0x1 7209#define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L 7210#define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL 7211//VCN_MES_GP0_HI 7212#define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 7213#define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 7214//VCN_MES_GP1_LO 7215#define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 7216#define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 7217//VCN_MES_GP1_HI 7218#define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 7219#define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 7220//VCN_MES_GP2_LO 7221#define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 7222#define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 7223//VCN_MES_GP2_HI 7224#define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 7225#define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 7226//VCN_MES_GP3_LO 7227#define VCN_MES_GP3_LO__DATA__SHIFT 0x0 7228#define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL 7229//VCN_MES_GP3_HI 7230#define VCN_MES_GP3_HI__DATA__SHIFT 0x0 7231#define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL 7232//VCN_MES_GP4_LO 7233#define VCN_MES_GP4_LO__DATA__SHIFT 0x0 7234#define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL 7235//VCN_MES_GP4_HI 7236#define VCN_MES_GP4_HI__DATA__SHIFT 0x0 7237#define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL 7238//VCN_MES_GP5_LO 7239#define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 7240#define VCN_MES_GP5_LO__DATA__SHIFT 0x1 7241#define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L 7242#define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL 7243//VCN_MES_GP5_HI 7244#define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 7245#define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 7246//VCN_MES_GP6_LO 7247#define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 7248#define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 7249//VCN_MES_GP6_HI 7250#define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 7251#define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 7252//VCN_MES_GP7_LO 7253#define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 7254#define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 7255//VCN_MES_GP7_HI 7256#define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 7257#define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 7258//VCN_MES_GP8_LO 7259#define VCN_MES_GP8_LO__DATA__SHIFT 0x0 7260#define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL 7261//VCN_MES_GP8_HI 7262#define VCN_MES_GP8_HI__DATA__SHIFT 0x0 7263#define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL 7264//VCN_MES_GP9_LO 7265#define VCN_MES_GP9_LO__DATA__SHIFT 0x0 7266#define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL 7267//VCN_MES_GP9_HI 7268#define VCN_MES_GP9_HI__DATA__SHIFT 0x0 7269#define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL 7270//VCN_MES_DM_INDEX_ADDR 7271#define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 7272#define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL 7273//VCN_MES_DM_INDEX_DATA 7274#define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 7275#define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL 7276//VCN_MES_LOCAL_BASE0_LO 7277#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 7278#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L 7279//VCN_MES_LOCAL_BASE0_HI 7280#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 7281#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL 7282//VCN_MES_LOCAL_MASK0_LO 7283#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 7284#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L 7285//VCN_MES_LOCAL_MASK0_HI 7286#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 7287#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL 7288//VCN_MES_LOCAL_APERTURE 7289#define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 7290#define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L 7291//VCN_MES_LOCAL_INSTR_BASE_LO 7292#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 7293#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L 7294//VCN_MES_LOCAL_INSTR_BASE_HI 7295#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 7296#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL 7297//VCN_MES_LOCAL_INSTR_MASK_LO 7298#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 7299#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L 7300//VCN_MES_LOCAL_INSTR_MASK_HI 7301#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 7302#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL 7303//VCN_MES_LOCAL_INSTR_APERTURE 7304#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 7305#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L 7306//VCN_MES_LOCAL_SCRATCH_APERTURE 7307#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 7308#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L 7309//VCN_MES_LOCAL_SCRATCH_BASE_LO 7310#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 7311#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L 7312//VCN_MES_LOCAL_SCRATCH_BASE_HI 7313#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 7314#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL 7315//VCN_MES_PERFCOUNT_CNTL 7316#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 7317#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL 7318//VCN_MES_PENDING_INTERRUPT 7319#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 7320#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL 7321//VCN_MES_PRGRM_CNTR_START_HI 7322#define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 7323#define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL 7324//VCN_MES_INTERRUPT_DATA_16 7325#define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 7326#define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL 7327//VCN_MES_INTERRUPT_DATA_17 7328#define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 7329#define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL 7330//VCN_MES_INTERRUPT_DATA_18 7331#define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 7332#define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL 7333//VCN_MES_INTERRUPT_DATA_19 7334#define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 7335#define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL 7336//VCN_MES_INTERRUPT_DATA_20 7337#define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 7338#define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL 7339//VCN_MES_INTERRUPT_DATA_21 7340#define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 7341#define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL 7342//VCN_MES_INTERRUPT_DATA_22 7343#define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 7344#define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL 7345//VCN_MES_INTERRUPT_DATA_23 7346#define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 7347#define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL 7348//VCN_MES_INTERRUPT_DATA_24 7349#define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 7350#define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL 7351//VCN_MES_INTERRUPT_DATA_25 7352#define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 7353#define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL 7354//VCN_MES_INTERRUPT_DATA_26 7355#define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 7356#define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL 7357//VCN_MES_INTERRUPT_DATA_27 7358#define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 7359#define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL 7360//VCN_MES_INTERRUPT_DATA_28 7361#define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 7362#define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL 7363//VCN_MES_INTERRUPT_DATA_29 7364#define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 7365#define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL 7366//VCN_MES_INTERRUPT_DATA_30 7367#define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 7368#define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL 7369//VCN_MES_INTERRUPT_DATA_31 7370#define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 7371#define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL 7372//VCN_MES_DC_APERTURE0_BASE 7373#define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 7374#define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL 7375//VCN_MES_DC_APERTURE0_MASK 7376#define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 7377#define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL 7378//VCN_MES_DC_APERTURE0_CNTL 7379#define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 7380#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 7381#define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL 7382#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L 7383//VCN_MES_DC_APERTURE1_BASE 7384#define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 7385#define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL 7386//VCN_MES_DC_APERTURE1_MASK 7387#define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 7388#define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL 7389//VCN_MES_DC_APERTURE1_CNTL 7390#define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 7391#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 7392#define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL 7393#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L 7394//VCN_MES_DC_APERTURE2_BASE 7395#define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 7396#define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL 7397//VCN_MES_DC_APERTURE2_MASK 7398#define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 7399#define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL 7400//VCN_MES_DC_APERTURE2_CNTL 7401#define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 7402#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 7403#define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL 7404#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L 7405//VCN_MES_DC_APERTURE3_BASE 7406#define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 7407#define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL 7408//VCN_MES_DC_APERTURE3_MASK 7409#define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 7410#define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL 7411//VCN_MES_DC_APERTURE3_CNTL 7412#define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 7413#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 7414#define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL 7415#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L 7416//VCN_MES_DC_APERTURE4_BASE 7417#define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 7418#define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL 7419//VCN_MES_DC_APERTURE4_MASK 7420#define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 7421#define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL 7422//VCN_MES_DC_APERTURE4_CNTL 7423#define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 7424#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 7425#define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL 7426#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L 7427//VCN_MES_DC_APERTURE5_BASE 7428#define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 7429#define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL 7430//VCN_MES_DC_APERTURE5_MASK 7431#define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 7432#define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL 7433//VCN_MES_DC_APERTURE5_CNTL 7434#define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 7435#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 7436#define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL 7437#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L 7438//VCN_MES_DC_APERTURE6_BASE 7439#define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 7440#define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL 7441//VCN_MES_DC_APERTURE6_MASK 7442#define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 7443#define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL 7444//VCN_MES_DC_APERTURE6_CNTL 7445#define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 7446#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 7447#define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL 7448#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L 7449//VCN_MES_DC_APERTURE7_BASE 7450#define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 7451#define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL 7452//VCN_MES_DC_APERTURE7_MASK 7453#define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 7454#define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL 7455//VCN_MES_DC_APERTURE7_CNTL 7456#define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 7457#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 7458#define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL 7459#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L 7460//VCN_MES_DC_APERTURE8_BASE 7461#define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 7462#define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL 7463//VCN_MES_DC_APERTURE8_MASK 7464#define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 7465#define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL 7466//VCN_MES_DC_APERTURE8_CNTL 7467#define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 7468#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 7469#define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL 7470#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L 7471//VCN_MES_DC_APERTURE9_BASE 7472#define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 7473#define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL 7474//VCN_MES_DC_APERTURE9_MASK 7475#define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 7476#define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL 7477//VCN_MES_DC_APERTURE9_CNTL 7478#define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 7479#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 7480#define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL 7481#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L 7482//VCN_MES_DC_APERTURE10_BASE 7483#define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 7484#define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL 7485//VCN_MES_DC_APERTURE10_MASK 7486#define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 7487#define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL 7488//VCN_MES_DC_APERTURE10_CNTL 7489#define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 7490#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 7491#define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL 7492#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L 7493//VCN_MES_DC_APERTURE11_BASE 7494#define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 7495#define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL 7496//VCN_MES_DC_APERTURE11_MASK 7497#define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 7498#define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL 7499//VCN_MES_DC_APERTURE11_CNTL 7500#define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 7501#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 7502#define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL 7503#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L 7504//VCN_MES_DC_APERTURE12_BASE 7505#define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 7506#define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL 7507//VCN_MES_DC_APERTURE12_MASK 7508#define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 7509#define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL 7510//VCN_MES_DC_APERTURE12_CNTL 7511#define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 7512#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 7513#define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL 7514#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L 7515//VCN_MES_DC_APERTURE13_BASE 7516#define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 7517#define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL 7518//VCN_MES_DC_APERTURE13_MASK 7519#define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 7520#define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL 7521//VCN_MES_DC_APERTURE13_CNTL 7522#define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 7523#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 7524#define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL 7525#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L 7526//VCN_MES_DC_APERTURE14_BASE 7527#define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 7528#define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL 7529//VCN_MES_DC_APERTURE14_MASK 7530#define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 7531#define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL 7532//VCN_MES_DC_APERTURE14_CNTL 7533#define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 7534#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 7535#define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL 7536#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L 7537//VCN_MES_DC_APERTURE15_BASE 7538#define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 7539#define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL 7540//VCN_MES_DC_APERTURE15_MASK 7541#define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 7542#define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL 7543//VCN_MES_DC_APERTURE15_CNTL 7544#define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 7545#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 7546#define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL 7547#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L 7548 7549 7550// addressBlock: uvd_vcn_hypdec 7551//VCN_MES_IC_BASE_LO 7552#define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc 7553#define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 7554//VCN_MES_MIBASE_LO 7555#define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc 7556#define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 7557//VCN_MES_IC_BASE_HI 7558#define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 7559#define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 7560//VCN_MES_MIBASE_HI 7561#define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 7562#define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 7563//VCN_MES_IC_BASE_CNTL 7564#define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 7565#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 7566#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 7567#define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL 7568#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L 7569#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 7570//VCN_MES_DC_BASE_LO 7571#define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 7572#define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L 7573//VCN_MES_MDBASE_LO 7574#define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 7575#define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L 7576//VCN_MES_DC_BASE_HI 7577#define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 7578#define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL 7579//VCN_MES_MDBASE_HI 7580#define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 7581#define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL 7582//VCN_MES_MIBOUND_LO 7583#define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 7584#define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 7585//VCN_MES_MIBOUND_HI 7586#define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 7587#define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 7588//VCN_MES_MDBOUND_LO 7589#define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 7590#define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 7591//VCN_MES_MDBOUND_HI 7592#define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 7593#define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 7594 7595 7596// addressBlock: uvd_slmi_adpdec 7597//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 7598#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7599#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7600//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 7601#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7602#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7603//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 7604#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7605#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7606//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 7607#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7608#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7609//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 7610#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7611#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7612//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 7613#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7614#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7615//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 7616#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7617#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7618//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 7619#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7620#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7621//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 7622#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7623#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7624//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 7625#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7626#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7627//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 7628#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7629#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7630//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 7631#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7632#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7633//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 7634#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7635#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7636//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 7637#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7638#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7639//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 7640#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7641#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7642//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 7643#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7644#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7645//UVD_LMI_MMSCH_NC_VMID 7646#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 7647#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 7648#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 7649#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 7650#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 7651#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 7652#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 7653#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 7654#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 7655#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 7656#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 7657#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 7658#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 7659#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 7660#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 7661#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 7662//UVD_LMI_MMSCH_CTRL 7663#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 7664#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 7665#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 7666#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 7667#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 7668#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 7669#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 7670#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 7671#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 7672#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 7673#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 7674#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 7675#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 7676#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 7677#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 7678#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 7679#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 7680#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 7681//UVD_MMSCH_LMI_STATUS 7682#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT__SHIFT 0x0 7683#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0x1 7684#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 7685#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN__SHIFT 0x4 7686#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS__SHIFT 0x8 7687#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE__SHIFT 0xc 7688#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 7689#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 7690#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT_MASK 0x00000001L 7691#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00000002L 7692#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 7693#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN_MASK 0x000000F0L 7694#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS_MASK 0x00000700L 7695#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE_MASK 0x00001000L 7696#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 7697#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 7698//UMSCH_IOV_ACTIVE_FCN_ID 7699#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 7700#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 7701#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000003FL 7702#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 7703//UVD_UMSCH_LMI_STATUS 7704#define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN__SHIFT 0x0 7705#define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN__SHIFT 0x1 7706#define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN__SHIFT 0x2 7707#define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN_MASK 0x00000001L 7708#define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN_MASK 0x00000002L 7709#define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN_MASK 0x00000004L 7710 7711 7712// addressBlock: uvdctxind 7713//UVD_CGC_MEM_CTRL 7714#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 7715#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 7716#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 7717#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 7718#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 7719#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 7720#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 7721#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 7722#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 7723#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 7724#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 7725#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 7726#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 7727#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe 7728#define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf 7729#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 7730#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 7731#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L 7732#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L 7733#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L 7734#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L 7735#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L 7736#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L 7737#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L 7738#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L 7739#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L 7740#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L 7741#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L 7742#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L 7743#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L 7744#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L 7745#define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L 7746#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 7747#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 7748//UVD_CGC_CTRL2 7749#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 7750#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 7751#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 7752#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 7753#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 7754#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL 7755//UVD_CGC_MEM_DS_CTRL 7756#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 7757#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 7758#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 7759#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 7760#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 7761#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 7762#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 7763#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 7764#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 7765#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 7766#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa 7767#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc 7768#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd 7769#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe 7770#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf 7771#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L 7772#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L 7773#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L 7774#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L 7775#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L 7776#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L 7777#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L 7778#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L 7779#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L 7780#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L 7781#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L 7782#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L 7783#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L 7784#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L 7785#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L 7786//UVD_CGC_MEM_SD_CTRL 7787#define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 7788#define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 7789#define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 7790#define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 7791#define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 7792#define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 7793#define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 7794#define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 7795#define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 7796#define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 7797#define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa 7798#define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc 7799#define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd 7800#define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe 7801#define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf 7802#define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L 7803#define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L 7804#define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L 7805#define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L 7806#define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L 7807#define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L 7808#define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L 7809#define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L 7810#define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L 7811#define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L 7812#define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L 7813#define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L 7814#define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L 7815#define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L 7816#define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L 7817//UVD_SW_SCRATCH_00 7818#define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 7819#define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL 7820//UVD_SW_SCRATCH_01 7821#define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 7822#define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL 7823//UVD_SW_SCRATCH_02 7824#define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 7825#define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL 7826//UVD_SW_SCRATCH_03 7827#define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 7828#define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL 7829//UVD_SW_SCRATCH_04 7830#define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 7831#define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL 7832//UVD_SW_SCRATCH_05 7833#define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 7834#define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL 7835//UVD_SW_SCRATCH_06 7836#define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 7837#define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL 7838//UVD_SW_SCRATCH_07 7839#define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 7840#define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL 7841//UVD_SW_SCRATCH_08 7842#define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 7843#define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL 7844//UVD_SW_SCRATCH_09 7845#define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 7846#define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL 7847//UVD_SW_SCRATCH_10 7848#define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 7849#define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL 7850//UVD_SW_SCRATCH_11 7851#define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 7852#define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL 7853//UVD_SW_SCRATCH_12 7854#define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 7855#define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL 7856//UVD_SW_SCRATCH_13 7857#define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 7858#define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL 7859//UVD_SW_SCRATCH_14 7860#define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 7861#define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL 7862//UVD_SW_SCRATCH_15 7863#define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 7864#define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL 7865//UVD_IH_SEM_CTRL 7866#define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 7867#define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 7868#define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 7869#define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 7870#define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 7871#define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 7872#define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 7873#define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L 7874#define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L 7875#define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 7876#define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L 7877#define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L 7878#define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L 7879#define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L 7880//UVD_MISC_FEATURE_CTL 7881#define UVD_MISC_FEATURE_CTL__ROW_PREEMPT_EN__SHIFT 0x0 7882#define UVD_MISC_FEATURE_CTL__PREEMPT_BLOCKIF_DIS_EN__SHIFT 0x1 7883#define UVD_MISC_FEATURE_CTL__ROW_PREEMPT_EN_MASK 0x00000001L 7884#define UVD_MISC_FEATURE_CTL__PREEMPT_BLOCKIF_DIS_EN_MASK 0x00000002L 7885 7886 7887// addressBlock: uvd_pg_indirect 7888//UVD_GPCNT0_CNTL 7889#define UVD_GPCNT0_CNTL__CLR__SHIFT 0x0 7890#define UVD_GPCNT0_CNTL__START__SHIFT 0x1 7891#define UVD_GPCNT0_CNTL__COUNTUP__SHIFT 0x2 7892//UVD_GPCNT0_TARGET_LOWER 7893#define UVD_GPCNT0_TARGET_LOWER__TARGET__SHIFT 0x0 7894//UVD_GPCNT0_STATUS_LOWER 7895#define UVD_GPCNT0_STATUS_LOWER__COUNT__SHIFT 0x0 7896//UVD_GPCNT0_TARGET_UPPER 7897#define UVD_GPCNT0_TARGET_UPPER__TARGET__SHIFT 0x0 7898//UVD_GPCNT0_STATUS_UPPER 7899#define UVD_GPCNT0_STATUS_UPPER__COUNT__SHIFT 0x0 7900//UVD_GPCNT1_CNTL 7901#define UVD_GPCNT1_CNTL__CLR__SHIFT 0x0 7902#define UVD_GPCNT1_CNTL__START__SHIFT 0x1 7903#define UVD_GPCNT1_CNTL__COUNTUP__SHIFT 0x2 7904//UVD_GPCNT1_TARGET_LOWER 7905#define UVD_GPCNT1_TARGET_LOWER__TARGET__SHIFT 0x0 7906//UVD_GPCNT1_STATUS_LOWER 7907#define UVD_GPCNT1_STATUS_LOWER__COUNT__SHIFT 0x0 7908//UVD_GPCNT1_TARGET_UPPER 7909#define UVD_GPCNT1_TARGET_UPPER__TARGET__SHIFT 0x0 7910//UVD_GPCNT1_STATUS_UPPER 7911#define UVD_GPCNT1_STATUS_UPPER__COUNT__SHIFT 0x0 7912 7913 7914// addressBlock: ecpu_indirect 7915//UVD_VCPU_CACHE_MISS_COUNTER_CTL 7916#define UVD_VCPU_CACHE_MISS_COUNTER_CTL__CNT_EN__SHIFT 0x0 7917#define UVD_VCPU_CACHE_MISS_COUNTER_CTL__CNT_CLR__SHIFT 0x1 7918//UVD_VCPU_ICACHE_MISS_COUNTER 7919#define UVD_VCPU_ICACHE_MISS_COUNTER__ICACHE_MISS_CNT__SHIFT 0x0 7920//UVD_VCPU_DCACHE_MISS_COUNTER 7921#define UVD_VCPU_DCACHE_MISS_COUNTER__DCACHE_MISS_CNT__SHIFT 0x0 7922//UVD_VCPU_ICMISS_ADDR 7923#define UVD_VCPU_ICMISS_ADDR__ICM_INSTR_ADDR__SHIFT 0x0 7924//UVD_VCPU_DCMISS_ADDR 7925#define UVD_VCPU_DCMISS_ADDR__DCM_DATA_ADDR__SHIFT 0x0 7926//UVD_VCPU_CACHE_MISS_CTRL1 7927#define UVD_VCPU_CACHE_MISS_CTRL1__CACHE_MISS_VALUE_TO_READ__SHIFT 0x0 7928#define UVD_VCPU_CACHE_MISS_CTRL1__CACHE_MISS_GRP_SEL_INSTR0_DATA1__SHIFT 0x4 7929#define UVD_VCPU_CACHE_MISS_CTRL1__REG_READ_ADDR_MASK_REG_SELECT__SHIFT 0x5 7930#define UVD_VCPU_CACHE_MISS_CTRL1__WR_EN_REG_READ_ADDR_MASK_VALUE__SHIFT 0x6 7931#define UVD_VCPU_CACHE_MISS_CTRL1__CACHE_MISS_COLLECT_EN__SHIFT 0x8 7932#define UVD_VCPU_CACHE_MISS_CTRL1__CACHE_MISS_REPEAT_TRACK_EN__SHIFT 0x9 7933#define UVD_VCPU_CACHE_MISS_CTRL1__EXCLUDE_REG_READS_FROM_DATA_CACHE_MISS__SHIFT 0xa 7934#define UVD_VCPU_CACHE_MISS_CTRL1__RESET_CACHE_MISS_INSTR_VALUES__SHIFT 0xc 7935#define UVD_VCPU_CACHE_MISS_CTRL1__RESET_CACHE_MISS_DATA_VALUES__SHIFT 0xd 7936#define UVD_VCPU_CACHE_MISS_CTRL1__REG_READ_ADDR_MASK_VALUE__SHIFT 0x10 7937//UVD_VCPU_CACHE_MISS_CTRL2 7938#define UVD_VCPU_CACHE_MISS_CTRL2__ICM_LAST_VALUE_UPDATED__SHIFT 0x0 7939#define UVD_VCPU_CACHE_MISS_CTRL2__DCM_LAST_VALUE_UPDATED__SHIFT 0x8 7940//UVD_VCPU_INSTR_CACHE_MISS_COUNT 7941#define UVD_VCPU_INSTR_CACHE_MISS_COUNT__TOTAL_INSTR_CACHE_MISSES__SHIFT 0x0 7942//UVD_VCPU_CACHE_MISS1 7943#define UVD_VCPU_CACHE_MISS1__CM_START_ADDR__SHIFT 0x0 7944//UVD_VCPU_CACHE_MISS2 7945#define UVD_VCPU_CACHE_MISS2__CM_CURRENT_LOOP_LAST_ADDR_16LSB__SHIFT 0x0 7946#define UVD_VCPU_CACHE_MISS2__CM_PREVIOUS_LOOP_LAST_ADDR_16LSB__SHIFT 0x10 7947//UVD_VCPU_CACHE_MISS3 7948#define UVD_VCPU_CACHE_MISS3__CM_CURRENT_LOOP_TOTAL_LENGTH__SHIFT 0x0 7949#define UVD_VCPU_CACHE_MISS3__CM_NUM_LOOPS_FROM_SAME_START_ADDR__SHIFT 0x14 7950//UVD_VCPU_DATA_CACHE_MISS_COUNT 7951#define UVD_VCPU_DATA_CACHE_MISS_COUNT__TOTAL_DATA_CACHE_MISSES__SHIFT 0x0 7952//UVD_LMI_VCPU_EXT40_MODE 7953#define UVD_LMI_VCPU_EXT40_MODE__MODE__SHIFT 0x0 7954 7955 7956// addressBlock: lmi_adp_indirect 7957//UVD_LMI_CRC0 7958#define UVD_LMI_CRC0__CRC32__SHIFT 0x0 7959#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 7960//UVD_LMI_CRC1 7961#define UVD_LMI_CRC1__CRC32__SHIFT 0x0 7962#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 7963//UVD_LMI_CRC2 7964#define UVD_LMI_CRC2__CRC32__SHIFT 0x0 7965#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 7966//UVD_LMI_CRC3 7967#define UVD_LMI_CRC3__CRC32__SHIFT 0x0 7968#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 7969//UVD_LMI_CRC4 7970#define UVD_LMI_CRC4__CRC32__SHIFT 0x0 7971//UVD_LMI_CRC5 7972#define UVD_LMI_CRC5__CRC32__SHIFT 0x0 7973//UVD_LMI_CRC6 7974#define UVD_LMI_CRC6__CRC32__SHIFT 0x0 7975//UVD_LMI_CRC7 7976#define UVD_LMI_CRC7__CRC32__SHIFT 0x0 7977//UVD_LMI_CRC8 7978#define UVD_LMI_CRC8__CRC32__SHIFT 0x0 7979//UVD_LMI_CRC9 7980#define UVD_LMI_CRC9__CRC32__SHIFT 0x0 7981//UVD_LMI_CRC10 7982#define UVD_LMI_CRC10__CRC32__SHIFT 0x0 7983#define UVD_LMI_CRC10__CRC32_MASK 0xFFFFFFFFL 7984//UVD_LMI_CRC11 7985#define UVD_LMI_CRC11__CRC32__SHIFT 0x0 7986#define UVD_LMI_CRC11__CRC32_MASK 0xFFFFFFFFL 7987//UVD_LMI_CRC12 7988#define UVD_LMI_CRC12__CRC32__SHIFT 0x0 7989#define UVD_LMI_CRC12__CRC32_MASK 0xFFFFFFFFL 7990//UVD_LMI_CRC13 7991#define UVD_LMI_CRC13__CRC32__SHIFT 0x0 7992#define UVD_LMI_CRC13__CRC32_MASK 0xFFFFFFFFL 7993//UVD_LMI_CRC14 7994#define UVD_LMI_CRC14__CRC32__SHIFT 0x0 7995#define UVD_LMI_CRC14__CRC32_MASK 0xFFFFFFFFL 7996//UVD_LMI_CRC15 7997#define UVD_LMI_CRC15__CRC32__SHIFT 0x0 7998#define UVD_LMI_CRC15__CRC32_MASK 0xFFFFFFFFL 7999//UVD_LMI_UVD_SWAP_RD 8000#define UVD_LMI_UVD_SWAP_RD__IT_RD__SHIFT 0x0 8001#define UVD_LMI_UVD_SWAP_RD__CM_RD__SHIFT 0x2 8002#define UVD_LMI_UVD_SWAP_RD__DB_RD__SHIFT 0x4 8003#define UVD_LMI_UVD_SWAP_RD__IDCT_RD__SHIFT 0x6 8004#define UVD_LMI_UVD_SWAP_RD__MPC_RD__SHIFT 0x8 8005#define UVD_LMI_UVD_SWAP_RD__LBSI_RD__SHIFT 0xa 8006#define UVD_LMI_UVD_SWAP_RD__RBC_RD__SHIFT 0xc 8007#define UVD_LMI_UVD_SWAP_RD__VCPU_RD__SHIFT 0xe 8008#define UVD_LMI_UVD_SWAP_RD__SCPU_RD__SHIFT 0x12 8009#define UVD_LMI_UVD_SWAP_RD__CENC_RD__SHIFT 0x16 8010//UVD_LMI_VMID_INTERNAL 8011#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 8012#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 8013#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 8014#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 8015#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 8016#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 8017#define UVD_LMI_VMID_INTERNAL__PREF_VMID__SHIFT 0x18 8018#define UVD_LMI_VMID_INTERNAL__CENC_VMID__SHIFT 0x1c 8019//UVD_LMI_VMID_INTERNAL2 8020#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 8021#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 8022#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 8023#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 8024#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 8025#define UVD_LMI_VMID_INTERNAL2__MIF_BSD0_VMID__SHIFT 0x14 8026#define UVD_LMI_VMID_INTERNAL2__MIF_BSP0_VMID__SHIFT 0x18 8027#define UVD_LMI_VMID_INTERNAL2__MIF_PRIVACY_CHROMA_VMID__SHIFT 0x1c 8028//UVD_LMI_CACHE_CTRL 8029#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 8030#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 8031#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 8032#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 8033#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 8034#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 8035//UVD_LMI_ARB_CTRL 8036#define UVD_LMI_ARB_CTRL__RD_WAIT_TIMER__SHIFT 0x0 8037#define UVD_LMI_ARB_CTRL__IT_RD_WAIT_EN__SHIFT 0x8 8038#define UVD_LMI_ARB_CTRL__CM_RD_WAIT_EN__SHIFT 0x9 8039#define UVD_LMI_ARB_CTRL__DB_RD_WAIT_EN__SHIFT 0xa 8040#define UVD_LMI_ARB_CTRL__IDCT_RD_WAIT_EN__SHIFT 0xb 8041#define UVD_LMI_ARB_CTRL__MPC_RD_WAIT_EN__SHIFT 0xc 8042#define UVD_LMI_ARB_CTRL__LBSI_RD_WAIT_EN__SHIFT 0xd 8043#define UVD_LMI_ARB_CTRL__RBC_RD_WAIT_EN__SHIFT 0xe 8044#define UVD_LMI_ARB_CTRL__MIF_RD_WAIT_EN__SHIFT 0xf 8045#define UVD_LMI_ARB_CTRL__WR_WAIT_TIMER__SHIFT 0x10 8046#define UVD_LMI_ARB_CTRL__IT_WR_WAIT_EN__SHIFT 0x18 8047#define UVD_LMI_ARB_CTRL__CM_WR_WAIT_EN__SHIFT 0x19 8048#define UVD_LMI_ARB_CTRL__DB_WR_WAIT_EN__SHIFT 0x1a 8049#define UVD_LMI_ARB_CTRL__DBW_WR_WAIT_EN__SHIFT 0x1b 8050#define UVD_LMI_ARB_CTRL__RE_WR_WAIT_EN__SHIFT 0x1c 8051#define UVD_LMI_ARB_CTRL__MP_WR_WAIT_EN__SHIFT 0x1d 8052#define UVD_LMI_ARB_CTRL__PREF_WR_WAIT_EN__SHIFT 0x1e 8053#define UVD_LMI_ARB_CTRL__LMI_WON_DEFAULT_EN__SHIFT 0x1f 8054//UVD_LMI_RD_BURST_CTRL 8055#define UVD_LMI_RD_BURST_CTRL__IT__SHIFT 0x0 8056#define UVD_LMI_RD_BURST_CTRL__CM__SHIFT 0x4 8057#define UVD_LMI_RD_BURST_CTRL__DB__SHIFT 0x8 8058#define UVD_LMI_RD_BURST_CTRL__IDCT__SHIFT 0xc 8059#define UVD_LMI_RD_BURST_CTRL__MPC__SHIFT 0x10 8060#define UVD_LMI_RD_BURST_CTRL__LBSI__SHIFT 0x14 8061#define UVD_LMI_RD_BURST_CTRL__RBC__SHIFT 0x18 8062#define UVD_LMI_RD_BURST_CTRL__MIF__SHIFT 0x1c 8063//UVD_LMI_WR_BURST_CTRL 8064#define UVD_LMI_WR_BURST_CTRL__IT__SHIFT 0x0 8065#define UVD_LMI_WR_BURST_CTRL__CM__SHIFT 0x4 8066#define UVD_LMI_WR_BURST_CTRL__DB__SHIFT 0x8 8067#define UVD_LMI_WR_BURST_CTRL__DBW__SHIFT 0xc 8068#define UVD_LMI_WR_BURST_CTRL__RE__SHIFT 0x10 8069#define UVD_LMI_WR_BURST_CTRL__MP__SHIFT 0x14 8070#define UVD_LMI_WR_BURST_CTRL__MIF__SHIFT 0x18 8071#define UVD_LMI_WR_BURST_CTRL__PREF__SHIFT 0x1c 8072//UVD_LMI_WR_COMB_CTRL 8073#define UVD_LMI_WR_COMB_CTRL__IT_TIMER__SHIFT 0x0 8074#define UVD_LMI_WR_COMB_CTRL__IT_MAX__SHIFT 0x4 8075#define UVD_LMI_WR_COMB_CTRL__CM_TIMER__SHIFT 0x8 8076#define UVD_LMI_WR_COMB_CTRL__CM_MAX__SHIFT 0xc 8077#define UVD_LMI_WR_COMB_CTRL__DB_TIMER__SHIFT 0x10 8078#define UVD_LMI_WR_COMB_CTRL__DB_MAX__SHIFT 0x14 8079#define UVD_LMI_WR_COMB_CTRL__DBW_TIMER__SHIFT 0x18 8080#define UVD_LMI_WR_COMB_CTRL__DBW_MAX__SHIFT 0x1c 8081//UVD_LMI_ISOC_CTRL 8082#define UVD_LMI_ISOC_CTRL__RANGE1_EN__SHIFT 0x0 8083#define UVD_LMI_ISOC_CTRL__RANGE2_EN__SHIFT 0x1 8084#define UVD_LMI_ISOC_CTRL__IT_EN__SHIFT 0x4 8085#define UVD_LMI_ISOC_CTRL__CM_EN__SHIFT 0x5 8086#define UVD_LMI_ISOC_CTRL__DB_EN__SHIFT 0x6 8087#define UVD_LMI_ISOC_CTRL__IDCT_EN__SHIFT 0x7 8088#define UVD_LMI_ISOC_CTRL__MPC_EN__SHIFT 0x8 8089#define UVD_LMI_ISOC_CTRL__LBSI_EN__SHIFT 0x9 8090#define UVD_LMI_ISOC_CTRL__RBC_EN__SHIFT 0xa 8091#define UVD_LMI_ISOC_CTRL__VCPU_EN__SHIFT 0xb 8092#define UVD_LMI_ISOC_CTRL__SCPU_EN__SHIFT 0xd 8093#define UVD_LMI_ISOC_CTRL__MIF_EN__SHIFT 0xf 8094//UVD_LMI_ISOC_PREF_BASE1 8095#define UVD_LMI_ISOC_PREF_BASE1__ADDR__SHIFT 0x0 8096//UVD_LMI_ISOC_PREF_LIMIT1 8097#define UVD_LMI_ISOC_PREF_LIMIT1__ADDR__SHIFT 0x0 8098//UVD_LMI_ISOC_PREF_BASE2 8099#define UVD_LMI_ISOC_PREF_BASE2__ADDR__SHIFT 0x0 8100//UVD_LMI_ISOC_PREF_LIMIT2 8101#define UVD_LMI_ISOC_PREF_LIMIT2__ADDR__SHIFT 0x0 8102//UVD_LMI_CLEAN_STATUS 8103#define UVD_LMI_CLEAN_STATUS__IT_RD__SHIFT 0x0 8104#define UVD_LMI_CLEAN_STATUS__CM_RD__SHIFT 0x1 8105#define UVD_LMI_CLEAN_STATUS__DB_RD__SHIFT 0x2 8106#define UVD_LMI_CLEAN_STATUS__IDCT_RD__SHIFT 0x3 8107#define UVD_LMI_CLEAN_STATUS__MPC_RD__SHIFT 0x4 8108#define UVD_LMI_CLEAN_STATUS__LBSI_RD__SHIFT 0x5 8109#define UVD_LMI_CLEAN_STATUS__RBC_RD__SHIFT 0x6 8110#define UVD_LMI_CLEAN_STATUS__VCPU_RD__SHIFT 0x7 8111#define UVD_LMI_CLEAN_STATUS__SCPU_RD__SHIFT 0x9 8112#define UVD_LMI_CLEAN_STATUS__ECPU_RD__SHIFT 0xb 8113#define UVD_LMI_CLEAN_STATUS__MIF_RD__SHIFT 0xc 8114#define UVD_LMI_CLEAN_STATUS__MPC2_RD__SHIFT 0xd 8115#define UVD_LMI_CLEAN_STATUS__PREF_WR__SHIFT 0xe 8116#define UVD_LMI_CLEAN_STATUS__IT_WR__SHIFT 0x10 8117#define UVD_LMI_CLEAN_STATUS__CM_WR__SHIFT 0x11 8118#define UVD_LMI_CLEAN_STATUS__DB_WR__SHIFT 0x12 8119#define UVD_LMI_CLEAN_STATUS__DBW_WR__SHIFT 0x13 8120#define UVD_LMI_CLEAN_STATUS__VCPU_WR__SHIFT 0x14 8121#define UVD_LMI_CLEAN_STATUS__SPH_WR__SHIFT 0x15 8122#define UVD_LMI_CLEAN_STATUS__RE_WR__SHIFT 0x16 8123#define UVD_LMI_CLEAN_STATUS__MP_WR__SHIFT 0x17 8124#define UVD_LMI_CLEAN_STATUS__SCPU_WR__SHIFT 0x18 8125#define UVD_LMI_CLEAN_STATUS__ECPU_WR__SHIFT 0x19 8126#define UVD_LMI_CLEAN_STATUS__MIF_WR__SHIFT 0x1a 8127#define UVD_LMI_CLEAN_STATUS__SRE_WR__SHIFT 0x1f 8128//UVD_LMI_CLEAN_STATUS2 8129#define UVD_LMI_CLEAN_STATUS2__BSP0_WR__SHIFT 0x0 8130#define UVD_LMI_CLEAN_STATUS2__BSP1_WR__SHIFT 0x1 8131#define UVD_LMI_CLEAN_STATUS2__BSP2_WR__SHIFT 0x2 8132#define UVD_LMI_CLEAN_STATUS2__BSP3_WR__SHIFT 0x3 8133#define UVD_LMI_CLEAN_STATUS2__SCLR2_WR__SHIFT 0x4 8134#define UVD_LMI_CLEAN_STATUS2__CENC_RD__SHIFT 0x5 8135#define UVD_LMI_CLEAN_STATUS2__ATOMIC_WR__SHIFT 0x7 8136//UVD_LMI_WR_COMB_CTRL2 8137#define UVD_LMI_WR_COMB_CTRL2__RE_TIMER__SHIFT 0x0 8138#define UVD_LMI_WR_COMB_CTRL2__RE_MAX__SHIFT 0x4 8139#define UVD_LMI_WR_COMB_CTRL2__MP_TIMER__SHIFT 0x8 8140#define UVD_LMI_WR_COMB_CTRL2__MP_MAX__SHIFT 0xc 8141#define UVD_LMI_WR_COMB_CTRL2__PREF_TIMER__SHIFT 0x10 8142#define UVD_LMI_WR_COMB_CTRL2__PREF_MAX__SHIFT 0x14 8143//UVD_LMI_UVD_SWAP_WR 8144#define UVD_LMI_UVD_SWAP_WR__IT_WR__SHIFT 0x0 8145#define UVD_LMI_UVD_SWAP_WR__CM_WR__SHIFT 0x2 8146#define UVD_LMI_UVD_SWAP_WR__DB_WR__SHIFT 0x4 8147#define UVD_LMI_UVD_SWAP_WR__DBW_WR__SHIFT 0x6 8148#define UVD_LMI_UVD_SWAP_WR__VCPU_WR__SHIFT 0x8 8149#define UVD_LMI_UVD_SWAP_WR__RE_WR__SHIFT 0xa 8150#define UVD_LMI_UVD_SWAP_WR__MP_WR__SHIFT 0xc 8151#define UVD_LMI_UVD_SWAP_WR__SCPU_WR__SHIFT 0xe 8152#define UVD_LMI_UVD_SWAP_WR__PREF_WR__SHIFT 0x10 8153#define UVD_LMI_UVD_SWAP_WR__ATOMIC_WR__SHIFT 0x12 8154//UVD_LMI_SCPU_VM0 8155#define UVD_LMI_SCPU_VM0__LOWER_RANGE__SHIFT 0x0 8156#define UVD_LMI_SCPU_VM0__UPPER_RANGE__SHIFT 0xc 8157#define UVD_LMI_SCPU_VM0__ENABLE__SHIFT 0x1f 8158//UVD_LMI_SCPU_VM1 8159#define UVD_LMI_SCPU_VM1__LOWER_RANGE__SHIFT 0x0 8160#define UVD_LMI_SCPU_VM1__UPPER_RANGE__SHIFT 0xc 8161#define UVD_LMI_SCPU_VM1__ENABLE__SHIFT 0x1f 8162//UVD_LMI_SWAP_CNTL2 8163#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 8164#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 8165#define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x4 8166#define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP__SHIFT 0xc 8167#define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP__SHIFT 0xe 8168#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L 8169#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000CL 8170#define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP_MASK 0x00000FF0L 8171#define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP_MASK 0x00003000L 8172//UVD_LMI_ADDR_EXT2 8173#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 8174#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 8175#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 8176#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 8177//UVD_LMI_MIF_BSP0_40BIT_BAR 8178#define UVD_LMI_MIF_BSP0_40BIT_BAR__DATA__SHIFT 0x0 8179//UVD_LMI_MIF_BSP1_40BIT_BAR 8180#define UVD_LMI_MIF_BSP1_40BIT_BAR__DATA__SHIFT 0x0 8181//UVD_LMI_MIF_BSP2_40BIT_BAR 8182#define UVD_LMI_MIF_BSP2_40BIT_BAR__DATA__SHIFT 0x0 8183//UVD_LMI_MIF_BSP3_40BIT_BAR 8184#define UVD_LMI_MIF_BSP3_40BIT_BAR__DATA__SHIFT 0x0 8185//UVD_LMI_MIF_BSP4_40BIT_BAR 8186#define UVD_LMI_MIF_BSP4_40BIT_BAR__DATA__SHIFT 0x0 8187//UVD_LMI_MIF_BSD0_40BIT_BAR 8188#define UVD_LMI_MIF_BSD0_40BIT_BAR__DATA__SHIFT 0x0 8189//UVD_LMI_MIF_BSD1_40BIT_BAR 8190#define UVD_LMI_MIF_BSD1_40BIT_BAR__DATA__SHIFT 0x0 8191//UVD_LMI_MIF_REF_40BIT_BAR 8192#define UVD_LMI_MIF_REF_40BIT_BAR__DATA__SHIFT 0x0 8193//UVD_LMI_MIF_GPGPU_40BIT_BAR 8194#define UVD_LMI_MIF_GPGPU_40BIT_BAR__DATA__SHIFT 0x0 8195//UVD_LMI_MIF_RD_SWAP_CNTL 8196#define UVD_LMI_MIF_RD_SWAP_CNTL__MIF_RD_SWAP__SHIFT 0x0 8197#define UVD_LMI_MIF_RD_SWAP_CNTL__MIF_RD_PRIV__SHIFT 0xc 8198#define UVD_LMI_MIF_RD_SWAP_CNTL__MIF_RD_TRAN__SHIFT 0x12 8199#define UVD_LMI_MIF_RD_SWAP_CNTL__MIF_RD_URG__SHIFT 0x18 8200//UVD_LMI_MIF_RD_SWAP_CNTL2 8201#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_SCLR2_SWAP__SHIFT 0x0 8202#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_SWAP2__SHIFT 0x2 8203#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_SCLR2_PRIV__SHIFT 0xc 8204#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_SCLR2_TRAN__SHIFT 0x12 8205#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_SCLR2_URG__SHIFT 0x18 8206#define UVD_LMI_MIF_RD_SWAP_CNTL2__MIF_RD_URG2__SHIFT 0x19 8207//UVD_LMI_MIF_WR_SWAP_CNTL 8208#define UVD_LMI_MIF_WR_SWAP_CNTL__MIF_WR_SWAP__SHIFT 0x0 8209#define UVD_LMI_MIF_WR_SWAP_CNTL__MIF_WR_SCLR2_SWAP__SHIFT 0x10 8210//UVD_LMI_MIF_WR_SWAP_CNTL2 8211#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_PRIV__SHIFT 0x0 8212#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_TRAN__SHIFT 0x8 8213#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_URG__SHIFT 0x10 8214#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_SCLR2_PRIV__SHIFT 0x18 8215#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_SCLR2_TRAN__SHIFT 0x1a 8216#define UVD_LMI_MIF_WR_SWAP_CNTL2__MIF_WR_SCLR2_URG__SHIFT 0x1c 8217//UVD_LMI_VCPU_CACHE_40BIT_BAR 8218#define UVD_LMI_VCPU_CACHE_40BIT_BAR__DATA__SHIFT 0x0 8219//UVD_LMI_MIF_CURR_LUMA_40BIT_BAR 8220#define UVD_LMI_MIF_CURR_LUMA_40BIT_BAR__DATA__SHIFT 0x0 8221//UVD_LMI_VCPU_NONCACHE_40BIT_BAR0 8222#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR0__DATA__SHIFT 0x0 8223//UVD_LMI_VCPU_NONCACHE_40BIT_BAR1 8224#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR1__DATA__SHIFT 0x0 8225//UVD_LMI_VCPU_NONCACHE_40BIT_BAR2 8226#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR2__DATA__SHIFT 0x0 8227//UVD_LMI_VCPU_NONCACHE_40BIT_BAR3 8228#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR3__DATA__SHIFT 0x0 8229//UVD_LMI_VCPU_NONCACHE_40BIT_BAR4 8230#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR4__DATA__SHIFT 0x0 8231//UVD_LMI_VCPU_NONCACHE_40BIT_BAR5 8232#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR5__DATA__SHIFT 0x0 8233//UVD_LMI_MIF_CURR_CHROMA_40BIT_BAR 8234#define UVD_LMI_MIF_CURR_CHROMA_40BIT_BAR__DATA__SHIFT 0x0 8235//UVD_LMI_VCPU_NONCACHE_40BIT_BAR6 8236#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR6__DATA__SHIFT 0x0 8237//UVD_LMI_VCPU_NONCACHE_40BIT_BAR7 8238#define UVD_LMI_VCPU_NONCACHE_40BIT_BAR7__DATA__SHIFT 0x0 8239//UVD_LMI_MIF_SWAP_WR 8240#define UVD_LMI_MIF_SWAP_WR__MIF_WR__SHIFT 0x0 8241#define UVD_LMI_MIF_SWAP_WR__MIF_WR_SCLR2__SHIFT 0x10 8242//UVD_LMI_MIF_SWAP_RD 8243#define UVD_LMI_MIF_SWAP_RD__MIF_RD__SHIFT 0x0 8244#define UVD_LMI_MIF_SWAP_RD__MIF_RD_SCLR2__SHIFT 0xc 8245#define UVD_LMI_MIF_SWAP_RD__MIF_RD_SWAP2__SHIFT 0xe 8246//UVD_LMI_MIF_RD_COMB_EN 8247#define UVD_LMI_MIF_RD_COMB_EN__MIF_RD__SHIFT 0x0 8248//UVD_LMI_MIF_DBW_40BIT_BAR 8249#define UVD_LMI_MIF_DBW_40BIT_BAR__DATA__SHIFT 0x0 8250//UVD_LMI_DROP 8251#define UVD_LMI_DROP__PREF_WR_DROP__SHIFT 0x1 8252#define UVD_LMI_DROP__IT_WR_DROP__SHIFT 0x2 8253#define UVD_LMI_DROP__CM_WR_DROP__SHIFT 0x3 8254#define UVD_LMI_DROP__DB_WR_DROP__SHIFT 0x4 8255#define UVD_LMI_DROP__DBW_WR_DROP__SHIFT 0x5 8256#define UVD_LMI_DROP__RE_WR_DROP__SHIFT 0x6 8257#define UVD_LMI_DROP__MP_WR_DROP__SHIFT 0x7 8258#define UVD_LMI_DROP__MIF_WR_DROP__SHIFT 0x8 8259#define UVD_LMI_DROP__VCPU_WR_DROP__SHIFT 0x9 8260#define UVD_LMI_DROP__ATOMIC_WR_DROP__SHIFT 0xa 8261#define UVD_LMI_DROP__ECPU_WR_DROP__SHIFT 0xb 8262#define UVD_LMI_DROP__IT_RD_DROP__SHIFT 0x10 8263#define UVD_LMI_DROP__CM_RD_DROP__SHIFT 0x11 8264#define UVD_LMI_DROP__DB_RD_DROP__SHIFT 0x12 8265#define UVD_LMI_DROP__MIF_RD_DROP__SHIFT 0x13 8266#define UVD_LMI_DROP__IDCT_RD_DROP__SHIFT 0x14 8267#define UVD_LMI_DROP__MPC_RD_DROP__SHIFT 0x15 8268#define UVD_LMI_DROP__LBSI_RD_DROP__SHIFT 0x16 8269#define UVD_LMI_DROP__RBC_RD_DROP__SHIFT 0x19 8270#define UVD_LMI_DROP__VCPU_RD_DROP__SHIFT 0x1a 8271#define UVD_LMI_DROP__CENC_RD_DROP__SHIFT 0x1b 8272#define UVD_LMI_DROP__ECPU_RD_DROP__SHIFT 0x1c 8273//UVD_LMI_VMID_INTERNAL3 8274#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 8275#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 8276#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 8277#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 8278#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10 8279#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR2_VMID__SHIFT 0x14 8280#define UVD_LMI_VMID_INTERNAL3__MIF_IMAGEPASTE_LUMA_VMID__SHIFT 0x18 8281#define UVD_LMI_VMID_INTERNAL3__MIF_IMAGEPASTE_CHROMA_VMID__SHIFT 0x1c 8282//UVD_LMI_MIF_RD_COHERENCY 8283#define UVD_LMI_MIF_RD_COHERENCY__MIF_GPGPU_RD_COHERENCY_DIS__SHIFT 0x0 8284#define UVD_LMI_MIF_RD_COHERENCY__MIF_CURR_RD_COHERENCY_DIS__SHIFT 0x1 8285#define UVD_LMI_MIF_RD_COHERENCY__MIF_REF_RD_COHERENCY_DIS__SHIFT 0x2 8286#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_COHERENCY_DIS__SHIFT 0x3 8287#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN1_RD_COHERENCY_DIS__SHIFT 0x4 8288#define UVD_LMI_MIF_RD_COHERENCY__MIF_BSD0_RD_COHERENCY_DIS__SHIFT 0x5 8289#define UVD_LMI_MIF_RD_COHERENCY__MIF_BSD1_RD_COHERENCY_DIS__SHIFT 0x6 8290#define UVD_LMI_MIF_RD_COHERENCY__MIF_BSD2_RD_COHERENCY_DIS__SHIFT 0x7 8291#define UVD_LMI_MIF_RD_COHERENCY__MIF_BSD3_RD_COHERENCY_DIS__SHIFT 0x8 8292#define UVD_LMI_MIF_RD_COHERENCY__MIF_BSD4_RD_COHERENCY_DIS__SHIFT 0x9 8293#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_CLEAN_SEL__SHIFT 0xf 8294#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR1_CLEAN_SEL__SHIFT 0x10 8295#define UVD_LMI_MIF_RD_COHERENCY__MIF_SCLR2_RD_COHERENCY_DIS__SHIFT 0x11 8296#define UVD_LMI_MIF_RD_COHERENCY__MIF_IMAGEPASTE_LUMA_RD_COHERENCY_DIS__SHIFT 0x12 8297#define UVD_LMI_MIF_RD_COHERENCY__MIF_IMAGEPASTE_CHROMA_RD_COHERENCY_DIS__SHIFT 0x13 8298#define UVD_LMI_MIF_RD_COHERENCY__MIF_PRIVACY_LUMA_RD_COHERENCY_DIS__SHIFT 0x14 8299#define UVD_LMI_MIF_RD_COHERENCY__MIF_PRIVACY_CHROMA_RD_COHERENCY_DIS__SHIFT 0x15 8300#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_SUBCLI1_CLEAN_SEL__SHIFT 0x16 8301#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_SUBCLI2_CLEAN_SEL__SHIFT 0x17 8302#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_SUBCLI3_CLEAN_SEL__SHIFT 0x18 8303#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_SUBCLI4_CLEAN_SEL__SHIFT 0x19 8304#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN_WR0_SUBCLI5_CLEAN_SEL__SHIFT 0x1a 8305#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_SUBCLIENT_1_COHERENCY_DIS__SHIFT 0x1b 8306#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_SUBCLIENT_2_COHERENCY_DIS__SHIFT 0x1c 8307#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_SUBCLIENT_3_COHERENCY_DIS__SHIFT 0x1d 8308#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_SUBCLIENT_4_COHERENCY_DIS__SHIFT 0x1e 8309#define UVD_LMI_MIF_RD_COHERENCY__MIF_GEN0_RD_SUBCLIENT_5_COHERENCY_DIS__SHIFT 0x1f 8310//UVD_LMI_ISOC_PREF_BASE1_64BIT 8311#define UVD_LMI_ISOC_PREF_BASE1_64BIT__ADDR_64BIT__SHIFT 0x0 8312//UVD_LMI_ISOC_PREF_LIMIT1_64BIT 8313#define UVD_LMI_ISOC_PREF_LIMIT1_64BIT__ADDR_64BIT__SHIFT 0x0 8314//UVD_LMI_ISOC_PREF_BASE2_64BIT 8315#define UVD_LMI_ISOC_PREF_BASE2_64BIT__ADDR_64BIT__SHIFT 0x0 8316//UVD_LMI_ISOC_PREF_LIMIT2_64BIT 8317#define UVD_LMI_ISOC_PREF_LIMIT2_64BIT__ADDR_64BIT__SHIFT 0x0 8318//UVD_LMI_PREF_64BIT_BAR_LOW 8319#define UVD_LMI_PREF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8320//UVD_LMI_PREF_64BIT_BAR_HIGH 8321#define UVD_LMI_PREF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8322//UVD_LMI_RDCOMB 8323#define UVD_LMI_RDCOMB__RDCOMB_EN__SHIFT 0x0 8324#define UVD_LMI_RDCOMB__RDCOMB_REPEAT_EN__SHIFT 0x1 8325#define UVD_LMI_RDCOMB__RDCOMB_SWITCH_DONE__SHIFT 0x2 8326#define UVD_LMI_RDCOMB__RDCOMB_WTIME__SHIFT 0x4 8327#define UVD_LMI_RDCOMB__RDCOMB_MAX__SHIFT 0xc 8328#define UVD_LMI_RDCOMB__RDCOMB_BW_MIF__SHIFT 0x10 8329//UVD_LMI_MC_LAT_MON0 8330#define UVD_LMI_MC_LAT_MON0__HIST_BIN0__SHIFT 0x0 8331#define UVD_LMI_MC_LAT_MON0__HIST_BIN1__SHIFT 0x10 8332//UVD_LMI_MC_LAT_MON1 8333#define UVD_LMI_MC_LAT_MON1__HIST_BIN2__SHIFT 0x0 8334#define UVD_LMI_MC_LAT_MON1__HIST_BIN3__SHIFT 0x10 8335//UVD_LMI_MC_LAT_MON2 8336#define UVD_LMI_MC_LAT_MON2__HIST_BIN4__SHIFT 0x0 8337#define UVD_LMI_MC_LAT_MON2__HIST_SAT_FLAG__SHIFT 0x10 8338//UVD_LMI_MC_LAT_MON3 8339#define UVD_LMI_MC_LAT_MON3__HIST_LAT_MAX__SHIFT 0x0 8340//UVD_LMI_MC_LAT_MON4 8341#define UVD_LMI_MC_LAT_MON4__HIST_AVG_ACC__SHIFT 0x0 8342//UVD_LMI_MC_LAT_MON5 8343#define UVD_LMI_MC_LAT_MON5__HIST_AVG_CNT__SHIFT 0x0 8344//UVD_LMI_MC_LAT_MON6 8345#define UVD_LMI_MC_LAT_MON6__HIST_LAT_AVG__SHIFT 0x0 8346//UVD_LMI_MC_LAT_MON7 8347#define UVD_LMI_MC_LAT_MON7__HIST_LAT_AVG_NO__SHIFT 0x0 8348//UVD_LMI_MC_LAT_CFG0 8349#define UVD_LMI_MC_LAT_CFG0__HIST_LAT_INIT__SHIFT 0x0 8350#define UVD_LMI_MC_LAT_CFG0__HIST_BIN_MASK__SHIFT 0x4 8351#define UVD_LMI_MC_LAT_CFG0__HIST_INPUT_SEL__SHIFT 0xc 8352//UVD_LMI_MC_LAT_CFG1 8353#define UVD_LMI_MC_LAT_CFG1__HIST_LIM0__SHIFT 0x0 8354#define UVD_LMI_MC_LAT_CFG1__HIST_LIM1__SHIFT 0x10 8355//UVD_LMI_MC_LAT_CFG2 8356#define UVD_LMI_MC_LAT_CFG2__HIST_LIM2__SHIFT 0x0 8357#define UVD_LMI_MC_LAT_CFG2__HIST_LIM3__SHIFT 0x10 8358//UVD_LMI_MC_LAT_CFG3 8359#define UVD_LMI_MC_LAT_CFG3__HIST_CLID_SEL__SHIFT 0x0 8360#define UVD_LMI_MC_LAT_CFG3__HIST_CLID_ALL__SHIFT 0x4 8361#define UVD_LMI_MC_LAT_CFG3__HIST_START_LAPSE_SCALE__SHIFT 0x8 8362//UVD_LMI_VMID_INTERNAL4 8363#define UVD_LMI_VMID_INTERNAL4__MIF_BSD1_VMID__SHIFT 0x0 8364#define UVD_LMI_VMID_INTERNAL4__MIF_BSD2_VMID__SHIFT 0x4 8365#define UVD_LMI_VMID_INTERNAL4__MIF_BSD3_VMID__SHIFT 0x8 8366#define UVD_LMI_VMID_INTERNAL4__MIF_BSD4_VMID__SHIFT 0xc 8367#define UVD_LMI_VMID_INTERNAL4__MIF_BSP1_VMID__SHIFT 0x10 8368#define UVD_LMI_VMID_INTERNAL4__MIF_BSP2_VMID__SHIFT 0x14 8369#define UVD_LMI_VMID_INTERNAL4__MIF_BSP3_VMID__SHIFT 0x18 8370#define UVD_LMI_VMID_INTERNAL4__MIF_PRIVACY_LUMA_VMID__SHIFT 0x1c 8371//UVD_LMI_VCPU_NC2_64BIT_BAR_LOW 8372#define UVD_LMI_VCPU_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8373//UVD_LMI_VCPU_NC2_64BIT_BAR_HIGH 8374#define UVD_LMI_VCPU_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8375//UVD_LMI_VCPU_NC3_64BIT_BAR_LOW 8376#define UVD_LMI_VCPU_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8377//UVD_LMI_VCPU_NC3_64BIT_BAR_HIGH 8378#define UVD_LMI_VCPU_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8379//UVD_LMI_VCPU_NC4_64BIT_BAR_LOW 8380#define UVD_LMI_VCPU_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8381//UVD_LMI_VCPU_NC4_64BIT_BAR_HIGH 8382#define UVD_LMI_VCPU_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8383//UVD_LMI_VCPU_NC5_64BIT_BAR_LOW 8384#define UVD_LMI_VCPU_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8385//UVD_LMI_VCPU_NC5_64BIT_BAR_HIGH 8386#define UVD_LMI_VCPU_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8387//UVD_LMI_VCPU_NC6_64BIT_BAR_LOW 8388#define UVD_LMI_VCPU_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8389//UVD_LMI_VCPU_NC6_64BIT_BAR_HIGH 8390#define UVD_LMI_VCPU_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8391//UVD_LMI_VCPU_NC7_64BIT_BAR_LOW 8392#define UVD_LMI_VCPU_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8393//UVD_LMI_VCPU_NC7_64BIT_BAR_HIGH 8394#define UVD_LMI_VCPU_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8395//UVD_LMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 8396#define UVD_LMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8397//UVD_LMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 8398#define UVD_LMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8399//UVD_LMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 8400#define UVD_LMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8401//UVD_LMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 8402#define UVD_LMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8403//UVD_LMI_ATOMIC_USER2_WRITE_64BIT_BAR_LOW 8404#define UVD_LMI_ATOMIC_USER2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8405//UVD_LMI_ATOMIC_USER2_WRITE_64BIT_BAR_HIGH 8406#define UVD_LMI_ATOMIC_USER2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8407//UVD_LMI_ATOMIC_USER3_WRITE_64BIT_BAR_LOW 8408#define UVD_LMI_ATOMIC_USER3_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8409//UVD_LMI_ATOMIC_USER3_WRITE_64BIT_BAR_HIGH 8410#define UVD_LMI_ATOMIC_USER3_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8411//UVD_LMI_EXT40_MODE 8412#define UVD_LMI_EXT40_MODE__VCPU_EXT40_MODE__SHIFT 0x0 8413//UVD_MEMCHECK2_SYS_INT_STAT 8414#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 8415#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 8416#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 8417#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 8418#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 8419#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 8420#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 8421#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 8422#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 8423#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 8424#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 8425#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 8426#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 8427#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 8428#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 8429#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 8430#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 8431#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 8432#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a 8433#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b 8434#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c 8435#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d 8436#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e 8437#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f 8438#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 8439#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 8440#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 8441#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 8442#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 8443#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 8444#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 8445#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 8446#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 8447#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 8448#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 8449#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 8450#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 8451#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 8452#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L 8453#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L 8454#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L 8455#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L 8456#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L 8457#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L 8458#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L 8459#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L 8460#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L 8461#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L 8462//UVD_MEMCHECK2_SYS_INT_ACK 8463#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 8464#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 8465#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 8466#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 8467#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 8468#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 8469#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 8470#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 8471#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 8472#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 8473#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 8474#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 8475#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 8476#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 8477#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 8478#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 8479#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 8480#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 8481#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a 8482#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b 8483#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c 8484#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d 8485#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e 8486#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f 8487#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 8488#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 8489#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 8490#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 8491#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 8492#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 8493#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 8494#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 8495#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 8496#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 8497#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 8498#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 8499#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 8500#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 8501#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L 8502#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L 8503#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L 8504#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L 8505#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L 8506#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L 8507#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L 8508#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L 8509#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L 8510#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L 8511//UVD_MEMCHECK2_VCPU_INT_STAT 8512#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 8513#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 8514#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 8515#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 8516#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 8517#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 8518#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 8519#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 8520#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 8521#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 8522#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 8523#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 8524#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 8525#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 8526#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 8527#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 8528#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 8529#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 8530#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 8531#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 8532#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 8533#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 8534#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a 8535#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b 8536#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 8537#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 8538#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 8539#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 8540#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 8541#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 8542#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 8543#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 8544#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 8545#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 8546#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 8547#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 8548#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 8549#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 8550#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L 8551#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L 8552#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L 8553#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L 8554#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L 8555#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L 8556#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L 8557#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L 8558#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L 8559#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L 8560//UVD_MEMCHECK2_VCPU_INT_ACK 8561#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 8562#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 8563#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 8564#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 8565#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 8566#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 8567#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 8568#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 8569#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 8570#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 8571#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 8572#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 8573#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 8574#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 8575#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 8576#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 8577#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 8578#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 8579#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 8580#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 8581#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 8582#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 8583#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a 8584#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b 8585#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 8586#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 8587#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 8588#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 8589#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 8590#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 8591#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 8592#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 8593#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 8594#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 8595#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 8596#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 8597#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 8598#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 8599#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L 8600#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L 8601#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L 8602#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L 8603#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L 8604#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L 8605#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L 8606#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L 8607#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 8608#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 8609 8610 8611 8612 8613 8614#endif 8615