| /freebsd-11-stable/sys/dev/bxe/ |
| H A D | ecore_init_ops.h | 54 REG_WR(sc, addr + i*4, data[i]);
284 REG_WR(sc, addr, op->write.val);
526 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
527 REG_WR(sc, read_arb_addr[i].add,
529 REG_WR(sc, read_arb_addr[i].ubound,
537 REG_WR(sc, write_arb_addr[i].l,
540 REG_WR(sc, write_arb_addr[i].add,
543 REG_WR(sc, write_arb_addr[i].ubound,
548 REG_WR(sc, write_arb_addr[i].l,
552 REG_WR(s
[all...] |
| H A D | bxe.c | 1047 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1091 REG_WR(sc, hw_lock_control_reg, resource_bit);
1136 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1172 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1205 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1217 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1235 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1238 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1242 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1348 REG_WR(s
[all...] |
| H A D | bxe_elink.c | 956 REG_WR(sc, reg, val);
965 REG_WR(sc, reg, val);
993 REG_WR(sc, params->lfa_base +
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1200 REG_WR(s
[all...] |
| H A D | ecore_init.h | 274 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
279 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));
284 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);
295 REG_WR(sc, reg_addr, reg_bit_map);
644 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
646 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
649 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
650 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
757 REG_WR(s
[all...] |
| H A D | bxe.h | 1923 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) macro
1979 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1987 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1993 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
2313 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2383 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2410 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
|
| H A D | ecore_sp.c | 920 REG_WR(sc, (ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
3595 REG_WR(sc, ECORE_MC_HASH_OFFSET(sc, i), mc_filter[i]);
|
| /freebsd-11-stable/sys/dev/bce/ |
| H A D | if_bce.c | 1678 REG_WR(sc, offset, val);
1798 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1814 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1850 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1851 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1866 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1867 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1903 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1913 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1942 REG_WR(s
[all...] |
| H A D | if_bcereg.h | 1087 #define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val) macro
1091 #define REG_WR(sc, offset, val) \ macro
1105 REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1107 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
|
| /freebsd-11-stable/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_hw.c | 213 REG_WR(p_hwfn,
286 REG_WR(p_hwfn, bar_addr, val);
408 REG_WR(p_hwfn,
424 REG_WR(p_hwfn,
441 REG_WR(p_hwfn,
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| H A D | ecore_vf.c | 153 REG_WR(p_hwfn,
157 REG_WR(p_hwfn,
166 REG_WR(p_hwfn, (osal_uintptr_t)&zone_data->trigger, *((u32 *)&trigger));
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| H A D | bcm_osal.h | 218 #define REG_WR(hwfn, addr, val) qlnx_reg_wr32(hwfn, addr, val) macro
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| H A D | ecore_init_ops.c | 628 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
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| H A D | ecore_sriov.c | 1458 REG_WR(p_hwfn,
2401 REG_WR(p_hwfn,
3969 REG_WR(p_hwfn,
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| H A D | ecore_dev.c | 2728 REG_WR(p_hwfn, addr, 0);
2747 REG_WR(p_hwfn, addr, 0);
|