Lines Matching refs:REG_WR
956 REG_WR(sc, reg, val);
965 REG_WR(sc, reg, val);
993 REG_WR(sc, params->lfa_base +
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1200 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1204 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1205 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1206 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1208 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1209 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1210 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1212 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1216 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1217 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1219 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1220 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1222 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1270 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1272 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1274 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1276 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1278 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1280 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1284 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1286 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1312 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1313 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1315 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1316 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1328 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1329 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1332 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1334 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1345 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1347 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1349 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1358 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1360 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1362 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1364 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1366 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1368 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1371 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1372 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1373 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1406 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1432 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1435 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1440 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1443 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1445 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1449 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1452 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1466 REG_WR(sc, base_weight + (0x4 * i), 0);
1533 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1536 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1539 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1543 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1616 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1618 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1840 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1843 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1849 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1851 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1854 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1974 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1981 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1983 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1985 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1989 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1992 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
2000 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
2003 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
2005 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
2034 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2035 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2037 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2038 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2055 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2059 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2061 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2063 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2066 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2076 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2119 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2120 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2121 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2127 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2128 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2129 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2133 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2138 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2224 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2263 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2266 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2304 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2306 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2308 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2328 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2338 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2342 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2348 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2381 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2387 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2389 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2391 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2395 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2400 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2408 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2417 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2422 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2457 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2463 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2466 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2469 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2474 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2479 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2483 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2487 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2506 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2508 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2516 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2544 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2547 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2548 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2553 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2556 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2563 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2564 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2566 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2581 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2601 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2605 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2611 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2612 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2622 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2623 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2634 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2636 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2641 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2720 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2728 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2731 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2732 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2733 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2736 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2743 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2744 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2749 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2753 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2756 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2920 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2928 REG_WR(sc, params->shmem_base +
2982 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2984 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2986 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2988 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2991 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2994 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2997 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
3001 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
3005 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
3016 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
3020 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3024 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3078 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3231 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3236 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3240 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3247 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3248 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3249 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3255 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3256 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3257 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3258 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3259 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3260 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3301 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3325 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3327 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3334 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3336 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3348 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3353 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3355 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3358 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3443 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3457 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3464 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3482 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3509 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3531 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3587 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3608 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3736 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3786 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3803 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3827 REG_WR(sc, params->shmem2_base +
3928 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3932 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3939 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3963 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
4140 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4141 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4143 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4146 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4158 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4160 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4164 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4176 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4177 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4194 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4196 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4456 REG_WR(sc, params->shmem2_base +
6976 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
7124 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7145 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7192 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7193 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7223 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7224 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7244 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7249 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7251 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7256 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7270 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7274 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7277 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7280 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7282 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7294 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7296 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7298 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7487 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7528 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7532 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7542 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7544 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7593 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7595 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7596 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7632 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7663 REG_WR(sc, addr, val);
7722 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7877 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7970 REG_WR(sc, ver_addr, spirom_ver);
9140 REG_WR(sc, sync_offset, media_types);
9501 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9504 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9505 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9506 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
12248 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
12253 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
13475 REG_WR(sc, sync_offset, media_types);
13600 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13662 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13686 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13705 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13731 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13746 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13796 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13809 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13812 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13816 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13855 REG_WR(sc, GRCBASE_MISC +
13859 REG_WR(sc, GRCBASE_MISC +
13883 REG_WR(sc, params->lfa_base +
13887 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13906 REG_WR(sc, params->lfa_base +
13910 REG_WR(sc, params->lfa_base +
13914 REG_WR(sc, params->lfa_base +
13919 REG_WR(sc, params->lfa_base +
13930 REG_WR(sc, params->lfa_base +
13949 REG_WR(sc, params->lfa_base +
14090 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
14094 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
14095 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
14117 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
14159 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
14161 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
14162 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
14168 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
14188 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14223 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14369 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14639 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14741 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14754 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14804 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14805 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
15098 REG_WR(sc, sync_offset, vars->aeu_int_mask);
15111 REG_WR(sc, offset, aeu_mask);
15116 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);