1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#ifndef __BXE_H__ 28#define __BXE_H__ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/bxe/bxe.h 339881 2018-10-29 21:09:39Z davidcs $"); 32 33#include <sys/param.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/sx.h> 39#include <sys/module.h> 40#include <sys/endian.h> 41#include <sys/types.h> 42#include <sys/malloc.h> 43#include <sys/kobj.h> 44#include <sys/bus.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49#include <sys/smp.h> 50#include <sys/bitstring.h> 51#include <sys/limits.h> 52#include <sys/queue.h> 53#include <sys/taskqueue.h> 54#include <sys/zlib.h> 55 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_arp.h> 59#include <net/ethernet.h> 60#include <net/if_dl.h> 61#include <net/if_var.h> 62#include <net/if_media.h> 63#include <net/if_vlan_var.h> 64#include <net/bpf.h> 65 66#include <netinet/in.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/udp.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/atomic.h> 76#include <machine/resource.h> 77#include <machine/endian.h> 78#include <machine/bus.h> 79#include <machine/in_cksum.h> 80 81#include "device_if.h" 82#include "bus_if.h" 83#include "pci_if.h" 84 85#if _BYTE_ORDER == _LITTLE_ENDIAN 86#ifndef LITTLE_ENDIAN 87#define LITTLE_ENDIAN 88#endif 89#ifndef __LITTLE_ENDIAN 90#define __LITTLE_ENDIAN 91#endif 92#undef BIG_ENDIAN 93#undef __BIG_ENDIAN 94#else /* _BIG_ENDIAN */ 95#ifndef BIG_ENDIAN 96#define BIG_ENDIAN 97#endif 98#ifndef __BIG_ENDIAN 99#define __BIG_ENDIAN 100#endif 101#undef LITTLE_ENDIAN 102#undef __LITTLE_ENDIAN 103#endif 104 105#include "ecore_mfw_req.h" 106#include "ecore_fw_defs.h" 107#include "ecore_hsi.h" 108#include "ecore_reg.h" 109#include "bxe_dcb.h" 110#include "bxe_stats.h" 111 112#include "bxe_elink.h" 113 114#define VF_MAC_CREDIT_CNT 0 115#define VF_VLAN_CREDIT_CNT (0) 116 117#if __FreeBSD_version < 800054 118#if defined(__i386__) || defined(__amd64__) 119#define mb() __asm volatile("mfence;" : : : "memory") 120#define wmb() __asm volatile("sfence;" : : : "memory") 121#define rmb() __asm volatile("lfence;" : : : "memory") 122static __inline void prefetch(void *x) 123{ 124 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 125} 126#else 127#define mb() 128#define rmb() 129#define wmb() 130#define prefetch(x) 131#endif 132#endif 133 134#if __FreeBSD_version >= 1000000 135#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 136#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 137#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 138#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 139#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 140#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 141#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 142#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 143#endif 144 145#ifndef ARRAY_SIZE 146#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147#endif 148#ifndef ARRSIZE 149#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 150#endif 151#ifndef DIV_ROUND_UP 152#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 153#endif 154#ifndef roundup 155#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 156#endif 157#ifndef ilog2 158static inline 159int bxe_ilog2(int x) 160{ 161 int log = 0; 162 while (x >>= 1) log++; 163 return (log); 164} 165#define ilog2(x) bxe_ilog2(x) 166#endif 167 168#include "ecore_sp.h" 169 170#define BRCM_VENDORID 0x14e4 171#define QLOGIC_VENDORID 0x1077 172#define PCI_ANY_ID (uint16_t)(~0U) 173 174struct bxe_device_type 175{ 176 uint16_t bxe_vid; 177 uint16_t bxe_did; 178 uint16_t bxe_svid; 179 uint16_t bxe_sdid; 180 char *bxe_name; 181}; 182 183#define BCM_PAGE_SHIFT 12 184#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 185#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 186#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 187 188#if BCM_PAGE_SIZE != 4096 189#error Page sizes other than 4KB are unsupported! 190#endif 191 192#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 193#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 194#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 195#else 196#define U64_LO(addr) ((uint32_t)(addr)) 197#define U64_HI(addr) (0) 198#endif 199#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 200 201#define SET_FLAG(value, mask, flag) \ 202 do { \ 203 (value) &= ~(mask); \ 204 (value) |= ((flag) << (mask##_SHIFT)); \ 205 } while (0) 206 207#define GET_FLAG(value, mask) \ 208 (((value) & (mask)) >> (mask##_SHIFT)) 209 210#define GET_FIELD(value, fname) \ 211 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 212 213#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 214#define BXE_TSO_MAX_SEGMENTS 32 215#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 216#define BXE_TSO_MAX_SEG_SIZE 4096 217 218/* dropless fc FW/HW related params */ 219#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 220#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 221 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 222 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 223#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 224#define FW_PREFETCH_CNT 16 225#define DROPLESS_FC_HEADROOM 100 226 227/******************/ 228/* RX SGE defines */ 229/******************/ 230 231#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 232#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 233#define RX_SGE_NEXT_PAGE_DESC_CNT 2 234#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 235#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 236#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 237#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 238#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 239#define RX_SGE(x) ((x) & RX_SGE_MAX) 240 241#define RX_SGE_NEXT(x) \ 242 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 243 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 244 245#define RX_SGE_MASK_ELEM_SZ 64 246#define RX_SGE_MASK_ELEM_SHIFT 6 247#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 248 249/* 250 * Creates a bitmask of all ones in less significant bits. 251 * idx - index of the most significant bit in the created mask. 252 */ 253#define RX_SGE_ONES_MASK(idx) \ 254 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 255#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 256 257/* Number of uint64_t elements in SGE mask array. */ 258#define RX_SGE_MASK_LEN \ 259 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 260#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 261#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 262 263/* 264 * dropless fc calculations for SGEs 265 * Number of required SGEs is the sum of two: 266 * 1. Number of possible opened aggregations (next packet for 267 * these aggregations will probably consume SGE immidiatelly) 268 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 269 * after placement on BD for new TPA aggregation) 270 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 271 */ 272#define NUM_SGE_REQ(sc) \ 273 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 274#define NUM_SGE_PG_REQ(sc) \ 275 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 276#define SGE_TH_LO(sc) \ 277 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 278#define SGE_TH_HI(sc) \ 279 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 280 281#define PAGES_PER_SGE_SHIFT 0 282#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 283#define SGE_PAGE_SIZE BCM_PAGE_SIZE 284#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 285#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 286#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 287#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 288 289/*****************/ 290/* TX BD defines */ 291/*****************/ 292 293#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 294#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 295#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 296#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 297#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 298#define TX_BD_MAX (TX_BD_TOTAL - 1) 299 300#define TX_BD_NEXT(x) \ 301 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 302 ((x) + 2) : ((x) + 1)) 303#define TX_BD(x) ((x) & TX_BD_MAX) 304#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 305#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 306 307/* 308 * Trigger pending transmits when the number of available BDs is greater 309 * than 1/8 of the total number of usable BDs. 310 */ 311#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 312#define BXE_TX_TIMEOUT 5 313 314/*****************/ 315/* RX BD defines */ 316/*****************/ 317 318#define RX_BD_NUM_PAGES 8 /* power of 2 */ 319#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 320#define RX_BD_NEXT_PAGE_DESC_CNT 2 321#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 322#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 323#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 324#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 325#define RX_BD_MAX (RX_BD_TOTAL - 1) 326 327#define RX_BD_NEXT(x) \ 328 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 329 ((x) + 3) : ((x) + 1)) 330#define RX_BD(x) ((x) & RX_BD_MAX) 331#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 332#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 333 334/* 335 * dropless fc calculations for BDs 336 * Number of BDs should be as number of buffers in BRB: 337 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 338 * "next" elements on each page 339 */ 340#define NUM_BD_REQ(sc) \ 341 BRB_SIZE(sc) 342#define NUM_BD_PG_REQ(sc) \ 343 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 344#define BD_TH_LO(sc) \ 345 (NUM_BD_REQ(sc) + \ 346 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 347 FW_DROP_LEVEL(sc)) 348#define BD_TH_HI(sc) \ 349 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 350#define MIN_RX_AVAIL(sc) \ 351 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 352#define MIN_RX_SIZE_TPA_HW(sc) \ 353 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 354 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 355#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 356#define MIN_RX_SIZE_TPA(sc) \ 357 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 358#define MIN_RX_SIZE_NONTPA(sc) \ 359 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 360 361/***************/ 362/* RCQ defines */ 363/***************/ 364 365/* 366 * As long as CQE is X times bigger than BD entry we have to allocate X times 367 * more pages for CQ ring in order to keep it balanced with BD ring 368 */ 369#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 370 sizeof(struct eth_rx_bd)) 371#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 372#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 373#define RCQ_NEXT_PAGE_DESC_CNT 1 374#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 375#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 376#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 377#define RCQ_MAX (RCQ_TOTAL - 1) 378 379#define RCQ_NEXT(x) \ 380 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 381 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 382#define RCQ(x) ((x) & RCQ_MAX) 383#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 384#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 385 386/* 387 * dropless fc calculations for RCQs 388 * Number of RCQs should be as number of buffers in BRB: 389 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 390 * "next" elements on each page 391 */ 392#define NUM_RCQ_REQ(sc) \ 393 BRB_SIZE(sc) 394#define NUM_RCQ_PG_REQ(sc) \ 395 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 396#define RCQ_TH_LO(sc) \ 397 (NUM_RCQ_REQ(sc) + \ 398 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 399 FW_DROP_LEVEL(sc)) 400#define RCQ_TH_HI(sc) \ 401 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 402 403/* This is needed for determening of last_max */ 404#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 405 406#define __SGE_MASK_SET_BIT(el, bit) \ 407 do { \ 408 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 409 } while (0) 410 411#define __SGE_MASK_CLEAR_BIT(el, bit) \ 412 do { \ 413 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 414 } while (0) 415 416#define SGE_MASK_SET_BIT(fp, idx) \ 417 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 418 ((idx) & RX_SGE_MASK_ELEM_MASK)) 419 420#define SGE_MASK_CLEAR_BIT(fp, idx) \ 421 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 422 ((idx) & RX_SGE_MASK_ELEM_MASK)) 423 424/* Load / Unload modes */ 425#define LOAD_NORMAL 0 426#define LOAD_OPEN 1 427#define LOAD_DIAG 2 428#define LOAD_LOOPBACK_EXT 3 429#define UNLOAD_NORMAL 0 430#define UNLOAD_CLOSE 1 431#define UNLOAD_RECOVERY 2 432 433/* Some constants... */ 434//#define MAX_PATH_NUM 2 435//#define E2_MAX_NUM_OF_VFS 64 436//#define E1H_FUNC_MAX 8 437//#define E2_FUNC_MAX 4 /* per path */ 438#define MAX_VNIC_NUM 4 439#define MAX_FUNC_NUM 8 /* common to all chips */ 440//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 441#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 442#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 443 444#define ILT_NUM_PAGE_ENTRIES 3072 445/* 446 * 57710/11 we use whole table since we have 8 functions. 447 * 57712 we have only 4 functions, but use same size per func, so only half 448 * of the table is used. 449 */ 450#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 451#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 452/* 453 * the phys address is shifted right 12 bits and has an added 454 * 1=valid bit added to the 53rd bit 455 * then since this is a wide register(TM) 456 * we split it into two 32 bit writes 457 */ 458#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 459#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 460 461/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 462#define ETH_HLEN 14 463#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 464#define ETH_MIN_PACKET_SIZE 60 465#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 466#define ETH_MAX_JUMBO_PACKET_SIZE 9600 467/* TCP with Timestamp Option (32) + IPv6 (40) */ 468#define ETH_MAX_TPA_HEADER_SIZE 72 469 470/* max supported alignment is 256 (8 shift) */ 471//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 472#define BXE_RX_ALIGN_SHIFT 8 473/* FW uses 2 cache lines alignment for start packet and size */ 474#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 475#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 476 477#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 478#define BXE_SET_ERROR_BIT(sc, error) \ 479{ \ 480 (sc)->error_status |= (error); \ 481} 482 483struct bxe_bar { 484 struct resource *resource; 485 int rid; 486 bus_space_tag_t tag; 487 bus_space_handle_t handle; 488 vm_offset_t kva; 489}; 490 491struct bxe_intr { 492 struct resource *resource; 493 int rid; 494 void *tag; 495}; 496 497/* Used to manage DMA allocations. */ 498struct bxe_dma { 499 struct bxe_softc *sc; 500 bus_addr_t paddr; 501 void *vaddr; 502 bus_dma_tag_t tag; 503 bus_dmamap_t map; 504 bus_dma_segment_t seg; 505 bus_size_t size; 506 int nseg; 507 char msg[32]; 508}; 509 510/* attn group wiring */ 511#define MAX_DYNAMIC_ATTN_GRPS 8 512 513struct attn_route { 514 uint32_t sig[5]; 515}; 516 517struct iro { 518 uint32_t base; 519 uint16_t m1; 520 uint16_t m2; 521 uint16_t m3; 522 uint16_t size; 523}; 524 525union bxe_host_hc_status_block { 526 /* pointer to fp status block e2 */ 527 struct host_hc_status_block_e2 *e2_sb; 528 /* pointer to fp status block e1x */ 529 struct host_hc_status_block_e1x *e1x_sb; 530}; 531 532union bxe_db_prod { 533 struct doorbell_set_prod data; 534 uint32_t raw; 535}; 536 537struct bxe_sw_tx_bd { 538 struct mbuf *m; 539 bus_dmamap_t m_map; 540 uint16_t first_bd; 541 uint8_t flags; 542/* set on the first BD descriptor when there is a split BD */ 543#define BXE_TSO_SPLIT_BD (1 << 0) 544}; 545 546struct bxe_sw_rx_bd { 547 struct mbuf *m; 548 bus_dmamap_t m_map; 549}; 550 551struct bxe_sw_tpa_info { 552 struct bxe_sw_rx_bd bd; 553 bus_dma_segment_t seg; 554 uint8_t state; 555#define BXE_TPA_STATE_START 1 556#define BXE_TPA_STATE_STOP 2 557 uint8_t placement_offset; 558 uint16_t parsing_flags; 559 uint16_t vlan_tag; 560 uint16_t len_on_bd; 561}; 562 563/* 564 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 565 * instances of the fastpath structure when using multiple queues. 566 */ 567struct bxe_fastpath { 568 /* pointer back to parent structure */ 569 struct bxe_softc *sc; 570 571 struct mtx tx_mtx; 572 char tx_mtx_name[32]; 573 struct mtx rx_mtx; 574 char rx_mtx_name[32]; 575 576#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 577#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 578#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 579#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 580 581#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 582#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 583#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 584 585 /* status block */ 586 struct bxe_dma sb_dma; 587 union bxe_host_hc_status_block status_block; 588 589 /* transmit chain (tx bds) */ 590 struct bxe_dma tx_dma; 591 union eth_tx_bd_types *tx_chain; 592 593 /* receive chain (rx bds) */ 594 struct bxe_dma rx_dma; 595 struct eth_rx_bd *rx_chain; 596 597 /* receive completion queue chain (rcq bds) */ 598 struct bxe_dma rcq_dma; 599 union eth_rx_cqe *rcq_chain; 600 601 /* receive scatter/gather entry chain (for TPA) */ 602 struct bxe_dma rx_sge_dma; 603 struct eth_rx_sge *rx_sge_chain; 604 605 /* tx mbufs */ 606 bus_dma_tag_t tx_mbuf_tag; 607 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 608 609 /* rx mbufs */ 610 bus_dma_tag_t rx_mbuf_tag; 611 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 612 bus_dmamap_t rx_mbuf_spare_map; 613 614 /* rx sge mbufs */ 615 bus_dma_tag_t rx_sge_mbuf_tag; 616 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 617 bus_dmamap_t rx_sge_mbuf_spare_map; 618 619 /* rx tpa mbufs (use the larger size for TPA queue length) */ 620 int tpa_enable; /* disabled per fastpath upon error */ 621 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 622 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 623 uint64_t rx_tpa_queue_used; 624 625 uint16_t *sb_index_values; 626 uint16_t *sb_running_index; 627 uint32_t ustorm_rx_prods_offset; 628 629 uint8_t igu_sb_id; /* status block number in HW */ 630 uint8_t fw_sb_id; /* status block number in FW */ 631 632 uint32_t rx_buf_size; 633 int mbuf_alloc_size; 634 635 int state; 636#define BXE_FP_STATE_CLOSED 0x01 637#define BXE_FP_STATE_IRQ 0x02 638#define BXE_FP_STATE_OPENING 0x04 639#define BXE_FP_STATE_OPEN 0x08 640#define BXE_FP_STATE_HALTING 0x10 641#define BXE_FP_STATE_HALTED 0x20 642 643 /* reference back to this fastpath queue number */ 644 uint8_t index; /* this is also the 'cid' */ 645#define FP_IDX(fp) (fp->index) 646 647 /* interrupt taskqueue (fast) */ 648 struct task tq_task; 649 struct taskqueue *tq; 650 char tq_name[32]; 651 652 struct task tx_task; 653 struct timeout_task tx_timeout_task; 654 655 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 656 uint8_t cl_id; 657#define FP_CL_ID(fp) (fp->cl_id) 658 uint8_t cl_qzone_id; 659 660 uint16_t fp_hc_idx; 661 662 /* driver copy of the receive buffer descriptor prod/cons indices */ 663 uint16_t rx_bd_prod; 664 uint16_t rx_bd_cons; 665 666 /* driver copy of the receive completion queue prod/cons indices */ 667 uint16_t rx_cq_prod; 668 uint16_t rx_cq_cons; 669 670 union bxe_db_prod tx_db; 671 672 /* Transmit packet producer index (used in eth_tx_bd). */ 673 uint16_t tx_pkt_prod; 674 uint16_t tx_pkt_cons; 675 676 /* Transmit buffer descriptor producer index. */ 677 uint16_t tx_bd_prod; 678 uint16_t tx_bd_cons; 679 680 uint64_t sge_mask[RX_SGE_MASK_LEN]; 681 uint16_t rx_sge_prod; 682 683 struct tstorm_per_queue_stats old_tclient; 684 struct ustorm_per_queue_stats old_uclient; 685 struct xstorm_per_queue_stats old_xclient; 686 struct bxe_eth_q_stats eth_q_stats; 687 struct bxe_eth_q_stats_old eth_q_stats_old; 688 689 /* Pointer to the receive consumer in the status block */ 690 uint16_t *rx_cq_cons_sb; 691 692 /* Pointer to the transmit consumer in the status block */ 693 uint16_t *tx_cons_sb; 694 695 /* transmit timeout until chip reset */ 696 int watchdog_timer; 697 698 /* Free/used buffer descriptor counters. */ 699 //uint16_t used_tx_bd; 700 701 /* Last maximal completed SGE */ 702 uint16_t last_max_sge; 703 704 //uint16_t rx_sge_free_idx; 705 706 //uint8_t segs; 707 708#if __FreeBSD_version >= 800000 709#define BXE_BR_SIZE 4096 710 struct buf_ring *tx_br; 711#endif 712}; /* struct bxe_fastpath */ 713 714/* sriov XXX */ 715#define BXE_MAX_NUM_OF_VFS 64 716#define BXE_VF_CID_WND 0 717#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 718#define BXE_CLIENTS_PER_VF 1 719#define BXE_FIRST_VF_CID 256 720#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 721#define BXE_VF_ID_INVALID 0xFF 722#define IS_SRIOV(sc) 0 723 724#define GET_NUM_VFS_PER_PATH(sc) 0 725#define GET_NUM_VFS_PER_PF(sc) 0 726 727/* maximum number of fast-path interrupt contexts */ 728#define FP_SB_MAX_E1x 16 729#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 730 731union cdu_context { 732 struct eth_context eth; 733 char pad[1024]; 734}; 735 736/* CDU host DB constants */ 737#define CDU_ILT_PAGE_SZ_HW 2 738#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 739#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 740 741#define CNIC_ISCSI_CID_MAX 256 742#define CNIC_FCOE_CID_MAX 2048 743#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 744#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 745 746#define QM_ILT_PAGE_SZ_HW 0 747#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 748#define QM_CID_ROUND 1024 749 750/* TM (timers) host DB constants */ 751#define TM_ILT_PAGE_SZ_HW 0 752#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 753/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 754#define TM_CONN_NUM 1024 755#define TM_ILT_SZ (8 * TM_CONN_NUM) 756#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 757 758/* SRC (Searcher) host DB constants */ 759#define SRC_ILT_PAGE_SZ_HW 0 760#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 761#define SRC_HASH_BITS 10 762#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 763#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 764#define SRC_T2_SZ SRC_ILT_SZ 765#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 766 767struct hw_context { 768 struct bxe_dma vcxt_dma; 769 union cdu_context *vcxt; 770 //bus_addr_t cxt_mapping; 771 size_t size; 772}; 773 774#define SM_RX_ID 0 775#define SM_TX_ID 1 776 777/* defines for multiple tx priority indices */ 778#define FIRST_TX_ONLY_COS_INDEX 1 779#define FIRST_TX_COS_INDEX 0 780 781#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 782 783#define HC_INDEX_ETH_RX_CQ_CONS 1 784#define HC_INDEX_OOO_TX_CQ_CONS 4 785#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 786#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 787#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 788#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 789 790/* congestion management fairness mode */ 791#define CMNG_FNS_NONE 0 792#define CMNG_FNS_MINMAX 1 793 794/* CMNG constants, as derived from system spec calculations */ 795/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 796#define DEF_MIN_RATE 100 797/* resolution of the rate shaping timer - 400 usec */ 798#define RS_PERIODIC_TIMEOUT_USEC 400 799/* number of bytes in single QM arbitration cycle - 800 * coefficient for calculating the fairness timer */ 801#define QM_ARB_BYTES 160000 802/* resolution of Min algorithm 1:100 */ 803#define MIN_RES 100 804/* how many bytes above threshold for the minimal credit of Min algorithm*/ 805#define MIN_ABOVE_THRESH 32768 806/* fairness algorithm integration time coefficient - 807 * for calculating the actual Tfair */ 808#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 809/* memory of fairness algorithm - 2 cycles */ 810#define FAIR_MEM 2 811 812#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 813#define HC_SEG_ACCESS_ATTN 4 814#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 815 816/* 817 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 818 * control by the number of fast-path status blocks supported by the 819 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 820 * status block represents an independent interrupts context that can 821 * serve a regular L2 networking queue. However special L2 queues such 822 * as the FCoE queue do not require a FP-SB and other components like 823 * the CNIC may consume FP-SB reducing the number of possible L2 queues 824 * 825 * If the maximum number of FP-SB available is X then: 826 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 827 * regular L2 queues is Y=X-1 828 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 829 * c. If the FCoE L2 queue is supported the actual number of L2 queues 830 * is Y+1 831 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 832 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 833 * FP interrupt context for the CNIC). 834 * e. The number of HW context (CID count) is always X or X+1 if FCoE 835 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 836 * 837 * So this is quite simple for now as no ULPs are supported yet. :-) 838 */ 839#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 840#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 841#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 842#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 843 844#define FOR_EACH_QUEUE(sc, var) \ 845 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 846 847#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 848 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 849 850#define FOR_EACH_ETH_QUEUE(sc, var) \ 851 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 852 853#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 854 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 855 856#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 857 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 858 859#define FOR_EACH_CNIC_QUEUE(sc, var) \ 860 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 861 (var) < BXE_NUM_QUEUES(sc); \ 862 (var)++) 863 864enum { 865 OOO_IDX_OFFSET, 866 FCOE_IDX_OFFSET, 867 FWD_IDX_OFFSET, 868}; 869 870#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 871#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 872#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 873#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 874#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 875#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 876 877#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 878#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 879#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 880#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 881#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 882 883#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 884#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 885#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 886#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 887#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 888#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 889 890#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 891#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 892#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 893#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 894#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 895#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 896#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 897 898enum { 899 BXE_PORT_QUERY_IDX, 900 BXE_PF_QUERY_IDX, 901 BXE_FCOE_QUERY_IDX, 902 BXE_FIRST_QUEUE_QUERY_IDX, 903}; 904 905struct bxe_fw_stats_req { 906 struct stats_query_header hdr; 907 struct stats_query_entry query[FP_SB_MAX_E1x + 908 BXE_FIRST_QUEUE_QUERY_IDX]; 909}; 910 911struct bxe_fw_stats_data { 912 struct stats_counter storm_counters; 913 struct per_port_stats port; 914 struct per_pf_stats pf; 915 //struct fcoe_statistics_params fcoe; 916 struct per_queue_stats queue_stats[1]; 917}; 918 919/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 920#define BXE_IGU_STAS_MSG_VF_CNT 64 921#define BXE_IGU_STAS_MSG_PF_CNT 4 922 923#define MAX_DMAE_C 8 924 925/* 926 * For the main interface up/down code paths, a not-so-fine-grained CORE 927 * mutex lock is used. Inside this code are various calls to kernel routines 928 * that can cause a sleep to occur. Namely memory allocations and taskqueue 929 * handling. If using an MTX lock we are *not* allowed to sleep but we can 930 * with an SX lock. This define forces the CORE lock to use and SX lock. 931 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 932 * path can cause problems since it's called by a non-sleepable thread. To 933 * alleviate a potential sleep, any IOCTL processing that results in the 934 * chip/interface being started/stopped/reinitialized, the actual work is 935 * offloaded to a taskqueue. 936 */ 937#define BXE_CORE_LOCK_SX 938 939/* 940 * This is the slowpath data structure. It is mapped into non-paged memory 941 * so that the hardware can access it's contents directly and must be page 942 * aligned. 943 */ 944struct bxe_slowpath { 945 946 /* used by the DMAE command executer */ 947 struct dmae_cmd dmae[MAX_DMAE_C]; 948 949 /* statistics completion */ 950 uint32_t stats_comp; 951 952 /* firmware defined statistics blocks */ 953 union mac_stats mac_stats; 954 struct nig_stats nig_stats; 955 struct host_port_stats port_stats; 956 struct host_func_stats func_stats; 957 //struct host_func_stats func_stats_base; 958 959 /* DMAE completion value and data source/sink */ 960 uint32_t wb_comp; 961 uint32_t wb_data[4]; 962 963 union { 964 struct mac_configuration_cmd e1x; 965 struct eth_classify_rules_ramrod_data e2; 966 } mac_rdata; 967 968 union { 969 struct tstorm_eth_mac_filter_config e1x; 970 struct eth_filter_rules_ramrod_data e2; 971 } rx_mode_rdata; 972 973 struct eth_rss_update_ramrod_data rss_rdata; 974 975 union { 976 struct mac_configuration_cmd e1; 977 struct eth_multicast_rules_ramrod_data e2; 978 } mcast_rdata; 979 980 union { 981 struct function_start_data func_start; 982 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 983 } func_rdata; 984 985 /* Queue State related ramrods */ 986 union { 987 struct client_init_ramrod_data init_data; 988 struct client_update_ramrod_data update_data; 989 } q_rdata; 990 991 /* 992 * AFEX ramrod can not be a part of func_rdata union because these 993 * events might arrive in parallel to other events from func_rdata. 994 * If they were defined in the same union the data can get corrupted. 995 */ 996 struct afex_vif_list_ramrod_data func_afex_rdata; 997 998 union drv_info_to_mcp drv_info_to_mcp; 999}; /* struct bxe_slowpath */ 1000 1001/* 1002 * Port specifc data structure. 1003 */ 1004struct bxe_port { 1005 /* 1006 * Port Management Function (for 57711E only). 1007 * When this field is set the driver instance is 1008 * responsible for managing port specifc 1009 * configurations such as handling link attentions. 1010 */ 1011 uint32_t pmf; 1012 1013 /* Ethernet maximum transmission unit. */ 1014 uint16_t ether_mtu; 1015 1016 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1017 1018 uint32_t ext_phy_config; 1019 1020 /* Port feature config.*/ 1021 uint32_t config; 1022 1023 /* Defines the features supported by the PHY. */ 1024 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1025 1026 /* Defines the features advertised by the PHY. */ 1027 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1028#define ADVERTISED_10baseT_Half (1 << 1) 1029#define ADVERTISED_10baseT_Full (1 << 2) 1030#define ADVERTISED_100baseT_Half (1 << 3) 1031#define ADVERTISED_100baseT_Full (1 << 4) 1032#define ADVERTISED_1000baseT_Half (1 << 5) 1033#define ADVERTISED_1000baseT_Full (1 << 6) 1034#define ADVERTISED_TP (1 << 7) 1035#define ADVERTISED_FIBRE (1 << 8) 1036#define ADVERTISED_Autoneg (1 << 9) 1037#define ADVERTISED_Asym_Pause (1 << 10) 1038#define ADVERTISED_Pause (1 << 11) 1039#define ADVERTISED_2500baseX_Full (1 << 15) 1040#define ADVERTISED_10000baseT_Full (1 << 16) 1041 1042 uint32_t phy_addr; 1043 1044 /* Used to synchronize phy accesses. */ 1045 struct mtx phy_mtx; 1046 char phy_mtx_name[32]; 1047 1048#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1049#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1050#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1051 1052 /* 1053 * MCP scratchpad address for port specific statistics. 1054 * The device is responsible for writing statistcss 1055 * back to the MCP for use with management firmware such 1056 * as UMP/NC-SI. 1057 */ 1058 uint32_t port_stx; 1059 1060 struct nig_stats old_nig_stats; 1061}; /* struct bxe_port */ 1062 1063struct bxe_mf_info { 1064 uint32_t mf_config[E1HVN_MAX]; 1065 1066 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1067 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1068 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1069 1070#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1071#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1072#define VNICS_PER_PATH(sc) \ 1073 ((sc)->devinfo.mf_info.vnics_per_port * \ 1074 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1075 1076 uint8_t min_bw[MAX_VNIC_NUM]; 1077 uint8_t max_bw[MAX_VNIC_NUM]; 1078 1079 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1080#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1081#define INVALID_VIF_ID 0xFFFF 1082#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1083#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1084 1085 uint16_t default_vlan; 1086#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1087 1088 uint8_t niv_allowed_priorities; 1089#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1090 1091 uint8_t niv_default_cos; 1092#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1093 1094 uint8_t niv_mba_enabled; 1095 1096 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1097#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1098 int afex_def_vlan_tag; 1099 uint32_t pending_max; 1100 1101 uint16_t flags; 1102#define MF_INFO_VALID_MAC 0x0001 1103 1104 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1105#define IS_MF(sc) \ 1106 (IS_MULTI_VNIC(sc) && \ 1107 ((sc)->devinfo.mf_info.mf_mode != 0)) 1108#define IS_MF_SD(sc) \ 1109 (IS_MULTI_VNIC(sc) && \ 1110 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1111#define IS_MF_SI(sc) \ 1112 (IS_MULTI_VNIC(sc) && \ 1113 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1114#define IS_MF_AFEX(sc) \ 1115 (IS_MULTI_VNIC(sc) && \ 1116 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1117#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1118#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1119#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1120 1121 uint32_t mf_protos_supported; 1122 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1123 #define MF_PROTO_SUPPORT_ISCSI 0x2 1124 #define MF_PROTO_SUPPORT_FCOE 0x4 1125}; /* struct bxe_mf_info */ 1126 1127/* Device information data structure. */ 1128struct bxe_devinfo { 1129 /* PCIe info */ 1130 uint16_t vendor_id; 1131 uint16_t device_id; 1132 uint16_t subvendor_id; 1133 uint16_t subdevice_id; 1134 1135 /* 1136 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1137 * C = Chip Number (bits 16-31) 1138 * R = Chip Revision (bits 12-15) 1139 * M = Chip Metal (bits 4-11) 1140 * B = Chip Bond ID (bits 0-3) 1141 */ 1142 uint32_t chip_id; 1143#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1144#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1145/* device ids */ 1146#define CHIP_NUM_57710 0x164e 1147#define CHIP_NUM_57711 0x164f 1148#define CHIP_NUM_57711E 0x1650 1149#define CHIP_NUM_57712 0x1662 1150#define CHIP_NUM_57712_MF 0x1663 1151#define CHIP_NUM_57712_VF 0x166f 1152#define CHIP_NUM_57800 0x168a 1153#define CHIP_NUM_57800_MF 0x16a5 1154#define CHIP_NUM_57800_VF 0x16a9 1155#define CHIP_NUM_57810 0x168e 1156#define CHIP_NUM_57810_MF 0x16ae 1157#define CHIP_NUM_57810_VF 0x16af 1158#define CHIP_NUM_57811 0x163d 1159#define CHIP_NUM_57811_MF 0x163e 1160#define CHIP_NUM_57811_VF 0x163f 1161#define CHIP_NUM_57840_OBS 0x168d 1162#define CHIP_NUM_57840_OBS_MF 0x16ab 1163#define CHIP_NUM_57840_4_10 0x16a1 1164#define CHIP_NUM_57840_2_20 0x16a2 1165#define CHIP_NUM_57840_MF 0x16a4 1166#define CHIP_NUM_57840_VF 0x16ad 1167 1168#define CHIP_REV_SHIFT 12 1169#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1170#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1171 1172#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1173#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1174#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1175 1176#define CHIP_REV_IS_SLOW(sc) \ 1177 (CHIP_REV(sc) > 0x00005000) 1178#define CHIP_REV_IS_FPGA(sc) \ 1179 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1180#define CHIP_REV_IS_EMUL(sc) \ 1181 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1182#define CHIP_REV_IS_ASIC(sc) \ 1183 (!CHIP_REV_IS_SLOW(sc)) 1184 1185#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1186#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1187 1188#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1189#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1190#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1191#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1192#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1193 (CHIP_IS_57711E(sc))) 1194#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1195 CHIP_IS_E1H((sc))) 1196 1197#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1198#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1199#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1200#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1201 CHIP_IS_57712_MF(sc)) 1202 1203#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1204#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1205#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1206#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1207#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1208#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1209#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1210#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1211#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1212#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1213 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1214 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1215#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1216 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1217#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1218 1219#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1220 CHIP_IS_57800_MF(sc) || \ 1221 CHIP_IS_57800_VF(sc) || \ 1222 CHIP_IS_57810(sc) || \ 1223 CHIP_IS_57810_MF(sc) || \ 1224 CHIP_IS_57810_VF(sc) || \ 1225 CHIP_IS_57811(sc) || \ 1226 CHIP_IS_57811_MF(sc) || \ 1227 CHIP_IS_57811_VF(sc) || \ 1228 CHIP_IS_57840(sc) || \ 1229 CHIP_IS_57840_MF(sc) || \ 1230 CHIP_IS_57840_VF(sc)) 1231#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1232 (CHIP_REV(sc) == CHIP_REV_Ax)) 1233#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1234 (CHIP_REV(sc) == CHIP_REV_Bx)) 1235 1236#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1237#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1238 CHIP_IS_E3(sc)) 1239 1240#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1241 CHIP_IS_57712_MF(sc) || \ 1242 CHIP_IS_E3(sc)) 1243 1244#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1245 CHIP_IS_57800_VF(sc) || \ 1246 CHIP_IS_57810_VF(sc) || \ 1247 CHIP_IS_57840_VF(sc)) 1248#define IS_PF(sc) (!IS_VF(sc)) 1249 1250/* 1251 * This define is used in two main places: 1252 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1253 * to nic-only mode or to offload mode. Offload mode is configured if either 1254 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1255 * already registered for this port (which means that the user wants storage 1256 * services). 1257 * 2. During cnic-related load, to know if offload mode is already configured 1258 * in the HW or needs to be configrued. Since the transition from nic-mode to 1259 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1260 * in ports on which storage services where never requested. 1261 */ 1262#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1263 1264 uint8_t chip_port_mode; 1265#define CHIP_4_PORT_MODE 0x0 1266#define CHIP_2_PORT_MODE 0x1 1267#define CHIP_PORT_MODE_NONE 0x2 1268#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1269#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1270 1271 uint8_t int_block; 1272#define INT_BLOCK_HC 0 1273#define INT_BLOCK_IGU 1 1274#define INT_BLOCK_MODE_NORMAL 0 1275#define INT_BLOCK_MODE_BW_COMP 2 1276#define CHIP_INT_MODE_IS_NBC(sc) \ 1277 (!CHIP_IS_E1x(sc) && \ 1278 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1279#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1280 1281 uint32_t shmem_base; 1282 uint32_t shmem2_base; 1283 uint32_t bc_ver; 1284 char bc_ver_str[32]; 1285 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1286 struct bxe_mf_info mf_info; 1287 1288 int flash_size; 1289#define NVRAM_1MB_SIZE 0x20000 1290#define NVRAM_TIMEOUT_COUNT 30000 1291#define NVRAM_PAGE_SIZE 256 1292 1293 /* PCIe capability information */ 1294 uint32_t pcie_cap_flags; 1295#define BXE_PM_CAPABLE_FLAG 0x00000001 1296#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1297#define BXE_MSI_CAPABLE_FLAG 0x00000004 1298#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1299 uint16_t pcie_pm_cap_reg; 1300 uint16_t pcie_pcie_cap_reg; 1301 //uint16_t pcie_devctl; 1302 uint16_t pcie_link_width; 1303 uint16_t pcie_link_speed; 1304 uint16_t pcie_msi_cap_reg; 1305 uint16_t pcie_msix_cap_reg; 1306 1307 /* device configuration read from bootcode shared memory */ 1308 uint32_t hw_config; 1309 uint32_t hw_config2; 1310}; /* struct bxe_devinfo */ 1311 1312struct bxe_sp_objs { 1313 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1314 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1315}; /* struct bxe_sp_objs */ 1316 1317/* 1318 * Data that will be used to create a link report message. We will keep the 1319 * data used for the last link report in order to prevent reporting the same 1320 * link parameters twice. 1321 */ 1322struct bxe_link_report_data { 1323 uint16_t line_speed; /* Effective line speed */ 1324 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1325}; 1326enum { 1327 BXE_LINK_REPORT_FULL_DUPLEX, 1328 BXE_LINK_REPORT_LINK_DOWN, 1329 BXE_LINK_REPORT_RX_FC_ON, 1330 BXE_LINK_REPORT_TX_FC_ON 1331}; 1332 1333/* Top level device private data structure. */ 1334struct bxe_softc { 1335 /* 1336 * First entry must be a pointer to the BSD ifnet struct which 1337 * has a first element of 'void *if_softc' (which is us). XXX 1338 */ 1339 if_t ifp; 1340 struct ifmedia ifmedia; /* network interface media structure */ 1341 int media; 1342 1343 volatile int state; /* device state */ 1344#define BXE_STATE_CLOSED 0x0000 1345#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1346#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1347#define BXE_STATE_OPEN 0x3000 1348#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1349#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1350#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1351#define BXE_STATE_DISABLED 0xD000 1352#define BXE_STATE_DIAG 0xE000 1353#define BXE_STATE_ERROR 0xF000 1354 1355 int flags; 1356#define BXE_ONE_PORT_FLAG 0x00000001 1357#define BXE_NO_ISCSI 0x00000002 1358#define BXE_NO_FCOE 0x00000004 1359#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1360//#define BXE_NO_WOL_FLAG 0x00000008 1361//#define BXE_USING_DAC_FLAG 0x00000010 1362//#define BXE_USING_MSIX_FLAG 0x00000020 1363//#define BXE_USING_MSI_FLAG 0x00000040 1364//#define BXE_DISABLE_MSI_FLAG 0x00000080 1365#define BXE_NO_MCP_FLAG 0x00000200 1366#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1367//#define BXE_SAFC_TX_FLAG 0x00000400 1368#define BXE_MF_FUNC_DIS 0x00000800 1369#define BXE_TX_SWITCHING 0x00001000 1370#define BXE_NO_PULSE 0x00002000 1371 1372 unsigned long debug; /* per-instance debug logging config */ 1373 1374#define MAX_BARS 5 1375 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1376 1377 uint16_t doorbell_size; 1378 1379 /* periodic timer callout */ 1380#define PERIODIC_STOP 0 1381#define PERIODIC_GO 1 1382 volatile unsigned long periodic_flags; 1383 struct callout periodic_callout; 1384 1385 /* chip start/stop/reset taskqueue */ 1386#define CHIP_TQ_NONE 0 1387#define CHIP_TQ_START 1 1388#define CHIP_TQ_STOP 2 1389#define CHIP_TQ_REINIT 3 1390 volatile unsigned long chip_tq_flags; 1391 struct task chip_tq_task; 1392 struct taskqueue *chip_tq; 1393 char chip_tq_name[32]; 1394 1395 struct timeout_task sp_err_timeout_task; 1396 1397 /* slowpath interrupt taskqueue */ 1398 struct task sp_tq_task; 1399 struct taskqueue *sp_tq; 1400 char sp_tq_name[32]; 1401 1402 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1403 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1404 1405 device_t dev; /* parent device handle */ 1406 uint8_t unit; /* driver instance number */ 1407 1408 int pcie_bus; /* PCIe bus number */ 1409 int pcie_device; /* PCIe device/slot number */ 1410 int pcie_func; /* PCIe function number */ 1411 1412 uint8_t pfunc_rel; /* function relative */ 1413 uint8_t pfunc_abs; /* function absolute */ 1414 uint8_t path_id; /* function absolute */ 1415#define SC_PATH(sc) (sc->path_id) 1416#define SC_PORT(sc) (sc->pfunc_rel & 1) 1417#define SC_FUNC(sc) (sc->pfunc_rel) 1418#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1419#define SC_VN(sc) (sc->pfunc_rel >> 1) 1420#define SC_L_ID(sc) (SC_VN(sc) << 2) 1421#define PORT_ID(sc) SC_PORT(sc) 1422#define PATH_ID(sc) SC_PATH(sc) 1423#define VNIC_ID(sc) SC_VN(sc) 1424#define FUNC_ID(sc) SC_FUNC(sc) 1425#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1426#define SC_FW_MB_IDX_VN(sc, vn) \ 1427 (SC_PORT(sc) + (vn) * \ 1428 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1429#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1430 1431 int if_capen; /* enabled interface capabilities */ 1432 1433 struct bxe_devinfo devinfo; 1434 char fw_ver_str[32]; 1435 char mf_mode_str[32]; 1436 char pci_link_str[32]; 1437 1438 const struct iro *iro_array; 1439 1440#ifdef BXE_CORE_LOCK_SX 1441 struct sx core_sx; 1442 char core_sx_name[32]; 1443#else 1444 struct mtx core_mtx; 1445 char core_mtx_name[32]; 1446#endif 1447 struct mtx sp_mtx; 1448 char sp_mtx_name[32]; 1449 struct mtx dmae_mtx; 1450 char dmae_mtx_name[32]; 1451 struct mtx fwmb_mtx; 1452 char fwmb_mtx_name[32]; 1453 struct mtx print_mtx; 1454 char print_mtx_name[32]; 1455 struct mtx stats_mtx; 1456 char stats_mtx_name[32]; 1457 struct mtx mcast_mtx; 1458 char mcast_mtx_name[32]; 1459 1460#ifdef BXE_CORE_LOCK_SX 1461#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1462#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1463#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1464#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1465#else 1466#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1467#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1468#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1469#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1470#endif 1471 1472#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1473#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1474#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1475 1476#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1477#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1478#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1479 1480#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1481#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1482#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1483 1484#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1485#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1486#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1487 1488#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1489#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1490#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1491 1492#if __FreeBSD_version < 800000 1493#define BXE_MCAST_LOCK(sc) \ 1494 do { \ 1495 mtx_lock(&sc->mcast_mtx); \ 1496 IF_ADDR_LOCK(sc->ifp); \ 1497 } while (0) 1498#define BXE_MCAST_UNLOCK(sc) \ 1499 do { \ 1500 IF_ADDR_UNLOCK(sc->ifp); \ 1501 mtx_unlock(&sc->mcast_mtx); \ 1502 } while (0) 1503#else 1504#define BXE_MCAST_LOCK(sc) \ 1505 do { \ 1506 mtx_lock(&sc->mcast_mtx); \ 1507 if_maddr_rlock(sc->ifp); \ 1508 } while (0) 1509#define BXE_MCAST_UNLOCK(sc) \ 1510 do { \ 1511 if_maddr_runlock(sc->ifp); \ 1512 mtx_unlock(&sc->mcast_mtx); \ 1513 } while (0) 1514#endif 1515#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1516 1517 int dmae_ready; 1518#define DMAE_READY(sc) (sc->dmae_ready) 1519 1520 struct ecore_credit_pool_obj vlans_pool; 1521 struct ecore_credit_pool_obj macs_pool; 1522 struct ecore_rx_mode_obj rx_mode_obj; 1523 struct ecore_mcast_obj mcast_obj; 1524 struct ecore_rss_config_obj rss_conf_obj; 1525 struct ecore_func_sp_obj func_obj; 1526 1527 uint16_t fw_seq; 1528 uint16_t fw_drv_pulse_wr_seq; 1529 uint32_t func_stx; 1530 1531 struct elink_params link_params; 1532 struct elink_vars link_vars; 1533 uint32_t link_cnt; 1534 struct bxe_link_report_data last_reported_link; 1535 char mac_addr_str[32]; 1536 1537 int last_reported_link_state; 1538 1539 int tx_ring_size; 1540 int rx_ring_size; 1541 int wol; 1542 1543 int is_leader; 1544 int recovery_state; 1545#define BXE_RECOVERY_DONE 1 1546#define BXE_RECOVERY_INIT 2 1547#define BXE_RECOVERY_WAIT 3 1548#define BXE_RECOVERY_FAILED 4 1549#define BXE_RECOVERY_NIC_LOADING 5 1550 1551#define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1552#define BXE_ERR_MISC 0x2 /* MISC ERR */ 1553#define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1554#define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1555#define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1556#define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1557#define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1558#define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1559 uint32_t error_status; 1560 1561 uint32_t rx_mode; 1562#define BXE_RX_MODE_NONE 0 1563#define BXE_RX_MODE_NORMAL 1 1564#define BXE_RX_MODE_ALLMULTI 2 1565#define BXE_RX_MODE_PROMISC 3 1566#define BXE_MAX_MULTICAST 64 1567 1568 struct bxe_port port; 1569 1570 struct cmng_init cmng; 1571 1572 /* user configs */ 1573 int num_queues; 1574 int max_rx_bufs; 1575 int hc_rx_ticks; 1576 int hc_tx_ticks; 1577 int rx_budget; 1578 int max_aggregation_size; 1579 int mrrs; 1580 int autogreeen; 1581#define AUTO_GREEN_HW_DEFAULT 0 1582#define AUTO_GREEN_FORCE_ON 1 1583#define AUTO_GREEN_FORCE_OFF 2 1584 int interrupt_mode; 1585#define INTR_MODE_INTX 0 1586#define INTR_MODE_MSI 1 1587#define INTR_MODE_MSIX 2 1588 int udp_rss; 1589 1590 /* interrupt allocations */ 1591 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1592 int intr_count; 1593 uint8_t igu_dsb_id; 1594 uint8_t igu_base_sb; 1595 uint8_t igu_sb_cnt; 1596 //uint8_t min_msix_vec_cnt; 1597 uint32_t igu_base_addr; 1598 //bus_addr_t def_status_blk_mapping; 1599 uint8_t base_fw_ndsb; 1600#define DEF_SB_IGU_ID 16 1601#define DEF_SB_ID HC_SP_SB_ID 1602 1603 /* parent bus DMA tag */ 1604 bus_dma_tag_t parent_dma_tag; 1605 1606 /* default status block */ 1607 struct bxe_dma def_sb_dma; 1608 struct host_sp_status_block *def_sb; 1609 uint16_t def_idx; 1610 uint16_t def_att_idx; 1611 uint32_t attn_state; 1612 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1613 1614/* general SP events - stats query, cfc delete, etc */ 1615#define HC_SP_INDEX_ETH_DEF_CONS 3 1616/* EQ completions */ 1617#define HC_SP_INDEX_EQ_CONS 7 1618/* FCoE L2 connection completions */ 1619#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1620#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1621/* iSCSI L2 */ 1622#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1623#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1624 1625 /* event queue */ 1626 struct bxe_dma eq_dma; 1627 union event_ring_elem *eq; 1628 uint16_t eq_prod; 1629 uint16_t eq_cons; 1630 uint16_t *eq_cons_sb; 1631#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1632#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1633#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1634#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1635#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1636#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1637/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1638#define NEXT_EQ_IDX(x) \ 1639 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1640 ((x) + 2) : ((x) + 1)) 1641/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1642#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1643 1644 /* slow path */ 1645 struct bxe_dma sp_dma; 1646 struct bxe_slowpath *sp; 1647 unsigned long sp_state; 1648 1649 /* slow path queue */ 1650 struct bxe_dma spq_dma; 1651 struct eth_spe *spq; 1652#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1653#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1654#define MAX_SPQ_PENDING 8 1655 1656 uint16_t spq_prod_idx; 1657 struct eth_spe *spq_prod_bd; 1658 struct eth_spe *spq_last_bd; 1659 uint16_t *dsb_sp_prod; 1660 //uint16_t *spq_hw_con; 1661 //uint16_t spq_left; 1662 1663 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1664 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1665 1666 /* fw decompression buffer */ 1667 struct bxe_dma gz_buf_dma; 1668 void *gz_buf; 1669 z_streamp gz_strm; 1670 uint32_t gz_outlen; 1671#define GUNZIP_BUF(sc) (sc->gz_buf) 1672#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1673#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1674#define FW_BUF_SIZE 0x40000 1675 1676 const struct raw_op *init_ops; 1677 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1678 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1679 uint32_t init_mode_flags; 1680#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1681 /* PRAM blobs - raw data */ 1682 const uint8_t *tsem_int_table_data; 1683 const uint8_t *tsem_pram_data; 1684 const uint8_t *usem_int_table_data; 1685 const uint8_t *usem_pram_data; 1686 const uint8_t *xsem_int_table_data; 1687 const uint8_t *xsem_pram_data; 1688 const uint8_t *csem_int_table_data; 1689 const uint8_t *csem_pram_data; 1690#define INIT_OPS(sc) (sc->init_ops) 1691#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1692#define INIT_DATA(sc) (sc->init_data) 1693#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1694#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1695#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1696#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1697#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1698#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1699#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1700#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1701 1702 /* ILT 1703 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1704 * context size we need 8 ILT entries. 1705 */ 1706#define ILT_MAX_L2_LINES 8 1707 struct hw_context context[ILT_MAX_L2_LINES]; 1708 struct ecore_ilt *ilt; 1709#define ILT_MAX_LINES 256 1710 1711/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1712#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1713/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1714#if 1 1715#define BXE_L2_MAX_CID(sc) \ 1716 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1717#else 1718#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1719 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1720#endif 1721#if 1 1722#define BXE_L2_CID_COUNT(sc) \ 1723 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1724#else 1725#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1726 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1727#endif 1728#define L2_ILT_LINES(sc) \ 1729 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1730 1731 int qm_cid_count; 1732 1733 uint8_t dropless_fc; 1734 1735 /* total number of FW statistics requests */ 1736 uint8_t fw_stats_num; 1737 /* 1738 * This is a memory buffer that will contain both statistics ramrod 1739 * request and data. 1740 */ 1741 struct bxe_dma fw_stats_dma; 1742 /* 1743 * FW statistics request shortcut (points at the beginning of fw_stats 1744 * buffer). 1745 */ 1746 int fw_stats_req_size; 1747 struct bxe_fw_stats_req *fw_stats_req; 1748 bus_addr_t fw_stats_req_mapping; 1749 /* 1750 * FW statistics data shortcut (points at the beginning of fw_stats 1751 * buffer + fw_stats_req_size). 1752 */ 1753 int fw_stats_data_size; 1754 struct bxe_fw_stats_data *fw_stats_data; 1755 bus_addr_t fw_stats_data_mapping; 1756 1757 /* tracking a pending STAT_QUERY ramrod */ 1758 uint16_t stats_pending; 1759 /* number of completed statistics ramrods */ 1760 uint16_t stats_comp; 1761 uint16_t stats_counter; 1762 uint8_t stats_init; 1763 int stats_state; 1764 1765 struct bxe_eth_stats eth_stats; 1766 struct host_func_stats func_stats; 1767 struct bxe_eth_stats_old eth_stats_old; 1768 struct bxe_net_stats_old net_stats_old; 1769 struct bxe_fw_port_stats_old fw_stats_old; 1770 1771 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1772 int executer_idx; 1773 1774 int mtu; 1775 1776 /* LLDP params */ 1777 struct bxe_config_lldp_params lldp_config_params; 1778 /* DCB support on/off */ 1779 int dcb_state; 1780#define BXE_DCB_STATE_OFF 0 1781#define BXE_DCB_STATE_ON 1 1782 /* DCBX engine mode */ 1783 int dcbx_enabled; 1784#define BXE_DCBX_ENABLED_OFF 0 1785#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1786#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1787#define BXE_DCBX_ENABLED_INVALID -1 1788 uint8_t dcbx_mode_uset; 1789 struct bxe_config_dcbx_params dcbx_config_params; 1790 struct bxe_dcbx_port_params dcbx_port_params; 1791 int dcb_version; 1792 1793 uint8_t cnic_support; 1794 uint8_t cnic_enabled; 1795 uint8_t cnic_loaded; 1796#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1797#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1798#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1799 1800 /* multiple tx classes of service */ 1801 uint8_t max_cos; 1802#define BXE_MAX_PRIORITY 8 1803 /* priority to cos mapping */ 1804 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1805 1806 int panic; 1807 1808 struct cdev *ioctl_dev; 1809 1810 void *grc_dump; 1811 unsigned int trigger_grcdump; 1812 unsigned int grcdump_done; 1813 unsigned int grcdump_started; 1814 int bxe_pause_param; 1815 void *eeprom; 1816}; /* struct bxe_softc */ 1817 1818/* IOCTL sub-commands for edebug and firmware upgrade */ 1819#define BXE_IOC_RD_NVRAM 1 1820#define BXE_IOC_WR_NVRAM 2 1821#define BXE_IOC_STATS_SHOW_NUM 3 1822#define BXE_IOC_STATS_SHOW_STR 4 1823#define BXE_IOC_STATS_SHOW_CNT 5 1824 1825struct bxe_nvram_data { 1826 uint32_t op; /* ioctl sub-command */ 1827 uint32_t offset; 1828 uint32_t len; 1829 uint32_t value[1]; /* variable */ 1830}; 1831 1832union bxe_stats_show_data { 1833 uint32_t op; /* ioctl sub-command */ 1834 1835 struct { 1836 uint32_t num; /* return number of stats */ 1837 uint32_t len; /* length of each string item */ 1838 } desc; 1839 1840 /* variable length... */ 1841 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1842 1843 /* variable length... */ 1844 uint64_t stats[1]; /* holds all stats */ 1845}; 1846 1847/* function init flags */ 1848#define FUNC_FLG_RSS 0x0001 1849#define FUNC_FLG_STATS 0x0002 1850/* FUNC_FLG_UNMATCHED 0x0004 */ 1851#define FUNC_FLG_TPA 0x0008 1852#define FUNC_FLG_SPQ 0x0010 1853#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1854 1855struct bxe_func_init_params { 1856 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1857 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1858 uint16_t func_flgs; 1859 uint16_t func_id; /* abs function id */ 1860 uint16_t pf_id; 1861 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1862}; 1863 1864/* memory resources reside at BARs 0, 2, 4 */ 1865/* Run `pciconf -lb` to see mappings */ 1866#define BAR0 0 1867#define BAR1 2 1868#define BAR2 4 1869 1870#ifdef BXE_REG_NO_INLINE 1871 1872uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1873uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1874uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1875 1876void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1877void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1878void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1879 1880#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1881#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1882#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1883 1884#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1885#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1886#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1887 1888#else /* not BXE_REG_NO_INLINE */ 1889 1890#define REG_WR8(sc, offset, val) \ 1891 bus_space_write_1(sc->bar[BAR0].tag, \ 1892 sc->bar[BAR0].handle, \ 1893 offset, val) 1894 1895#define REG_WR16(sc, offset, val) \ 1896 bus_space_write_2(sc->bar[BAR0].tag, \ 1897 sc->bar[BAR0].handle, \ 1898 offset, val) 1899 1900#define REG_WR32(sc, offset, val) \ 1901 bus_space_write_4(sc->bar[BAR0].tag, \ 1902 sc->bar[BAR0].handle, \ 1903 offset, val) 1904 1905#define REG_RD8(sc, offset) \ 1906 bus_space_read_1(sc->bar[BAR0].tag, \ 1907 sc->bar[BAR0].handle, \ 1908 offset) 1909 1910#define REG_RD16(sc, offset) \ 1911 bus_space_read_2(sc->bar[BAR0].tag, \ 1912 sc->bar[BAR0].handle, \ 1913 offset) 1914 1915#define REG_RD32(sc, offset) \ 1916 bus_space_read_4(sc->bar[BAR0].tag, \ 1917 sc->bar[BAR0].handle, \ 1918 offset) 1919 1920#endif /* BXE_REG_NO_INLINE */ 1921 1922#define REG_RD(sc, offset) REG_RD32(sc, offset) 1923#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1924 1925#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1926#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1927 1928#define BXE_SP(sc, var) (&(sc)->sp->var) 1929#define BXE_SP_MAPPING(sc, var) \ 1930 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1931 1932#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1933#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1934 1935#define REG_RD_DMAE(sc, offset, valp, len32) \ 1936 do { \ 1937 bxe_read_dmae(sc, offset, len32); \ 1938 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1939 } while (0) 1940 1941#define REG_WR_DMAE(sc, offset, valp, len32) \ 1942 do { \ 1943 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1944 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1945 } while (0) 1946 1947#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1948 REG_WR_DMAE(sc, offset, valp, len32) 1949 1950#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1951 REG_RD_DMAE(sc, offset, valp, len32) 1952 1953#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1954 do { \ 1955 /* if (le32_swap) { */ \ 1956 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1957 /* } */ \ 1958 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1959 ecore_write_big_buf_wb(sc, addr, len32); \ 1960 } while (0) 1961 1962#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1963#define BXE_DB_SHIFT 7 /* 128 bytes */ 1964#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1965#error "Minimum DB doorbell stride is 8" 1966#endif 1967#define DPM_TRIGGER_TYPE 0x40 1968#define DOORBELL(sc, cid, val) \ 1969 do { \ 1970 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1971 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1972 (uint32_t)val); \ 1973 } while(0) 1974 1975#define SHMEM_ADDR(sc, field) \ 1976 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1977#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1978#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1979#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1980 1981#define SHMEM2_ADDR(sc, field) \ 1982 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1983#define SHMEM2_HAS(sc, field) \ 1984 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1985 offsetof(struct shmem2_region, field))) 1986#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1987#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1988 1989#define MFCFG_ADDR(sc, field) \ 1990 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1991#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1992#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1993#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1994 1995/* DMAE command defines */ 1996 1997#define DMAE_TIMEOUT -1 1998#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1999#define DMAE_NOT_RDY -3 2000#define DMAE_PCI_ERR_FLAG 0x80000000 2001 2002#define DMAE_SRC_PCI 0 2003#define DMAE_SRC_GRC 1 2004 2005#define DMAE_DST_NONE 0 2006#define DMAE_DST_PCI 1 2007#define DMAE_DST_GRC 2 2008 2009#define DMAE_COMP_PCI 0 2010#define DMAE_COMP_GRC 1 2011 2012#define DMAE_COMP_REGULAR 0 2013#define DMAE_COM_SET_ERR 1 2014 2015#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 2016#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 2017#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 2018#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 2019 2020#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 2021#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 2022 2023#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 2024#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 2025#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 2026#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 2027 2028#define DMAE_CMD_PORT_0 0 2029#define DMAE_CMD_PORT_1 DMAE_CMD_PORT 2030 2031#define DMAE_SRC_PF 0 2032#define DMAE_SRC_VF 1 2033 2034#define DMAE_DST_PF 0 2035#define DMAE_DST_VF 1 2036 2037#define DMAE_C_SRC 0 2038#define DMAE_C_DST 1 2039 2040#define DMAE_LEN32_RD_MAX 0x80 2041#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2042 2043#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2044 2045#define MAX_DMAE_C_PER_PORT 8 2046#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2047#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2048 2049static const uint32_t dmae_reg_go_c[] = { 2050 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2051 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2052 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2053 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2054}; 2055 2056#define ATTN_NIG_FOR_FUNC (1L << 8) 2057#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2058#define GPIO_2_FUNC (1L << 10) 2059#define GPIO_3_FUNC (1L << 11) 2060#define GPIO_4_FUNC (1L << 12) 2061#define ATTN_GENERAL_ATTN_1 (1L << 13) 2062#define ATTN_GENERAL_ATTN_2 (1L << 14) 2063#define ATTN_GENERAL_ATTN_3 (1L << 15) 2064#define ATTN_GENERAL_ATTN_4 (1L << 13) 2065#define ATTN_GENERAL_ATTN_5 (1L << 14) 2066#define ATTN_GENERAL_ATTN_6 (1L << 15) 2067#define ATTN_HARD_WIRED_MASK 0xff00 2068#define ATTENTION_ID 4 2069 2070#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2071 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2072 2073#define MAX_IGU_ATTN_ACK_TO 100 2074 2075#define STORM_ASSERT_ARRAY_SIZE 50 2076 2077#define BXE_PMF_LINK_ASSERT(sc) \ 2078 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2079 2080#define BXE_MC_ASSERT_BITS \ 2081 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2082 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2083 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2084 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2085 2086#define BXE_MCP_ASSERT \ 2087 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2088 2089#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2090#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2091 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2092 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2093 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2094 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2095 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2096 2097#define MULTI_MASK 0x7f 2098 2099#define PFS_PER_PORT(sc) \ 2100 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2101#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2102 2103#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2104 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2105 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2106 2107#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2108 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2109 (i) < MAX_FUNC_NUM; \ 2110 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2111 2112#define BXE_SWCID_SHIFT 17 2113#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2114 2115#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2116#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2117 2118#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2119#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2120#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2121#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2122#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2123 2124/* must be used on a CID before placing it on a HW ring */ 2125#define HW_CID(sc, x) \ 2126 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2127 2128#define SPEED_10 10 2129#define SPEED_100 100 2130#define SPEED_1000 1000 2131#define SPEED_2500 2500 2132#define SPEED_10000 10000 2133 2134#define PCI_PM_D0 1 2135#define PCI_PM_D3hot 2 2136 2137#ifndef DUPLEX_UNKNOWN 2138#define DUPLEX_UNKNOWN (0xff) 2139#endif 2140 2141#ifndef SPEED_UNKNOWN 2142#define SPEED_UNKNOWN (-1) 2143#endif 2144 2145/* Enable or disable autonegotiation. */ 2146#define AUTONEG_DISABLE 0x00 2147#define AUTONEG_ENABLE 0x01 2148 2149/* Which connector port. */ 2150#define PORT_TP 0x00 2151#define PORT_AUI 0x01 2152#define PORT_MII 0x02 2153#define PORT_FIBRE 0x03 2154#define PORT_BNC 0x04 2155#define PORT_DA 0x05 2156#define PORT_NONE 0xef 2157#define PORT_OTHER 0xff 2158 2159int bxe_test_bit(int nr, volatile unsigned long * addr); 2160void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2161void bxe_clear_bit(int nr, volatile unsigned long * addr); 2162int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2163int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2164int bxe_cmpxchg(volatile int *addr, int old, int new); 2165 2166void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2167 uint32_t val); 2168uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2169 2170 2171int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2172 struct bxe_dma *dma, const char *msg); 2173void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2174 2175uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2176uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2177uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2178 uint8_t dst_type, uint8_t with_comp, 2179 uint8_t comp_type); 2180void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2181void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2182void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2183 uint32_t dst_addr, uint32_t len32); 2184void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2185 uint32_t addr, uint32_t len); 2186 2187void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2188 uint32_t cid); 2189void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2190 uint8_t sb_index, uint8_t disable, 2191 uint16_t usec); 2192 2193int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2194 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2195 2196void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2197 uint8_t segment, uint16_t index, uint8_t op, 2198 uint8_t update); 2199 2200void ecore_init_e1_firmware(struct bxe_softc *sc); 2201void ecore_init_e1h_firmware(struct bxe_softc *sc); 2202void ecore_init_e2_firmware(struct bxe_softc *sc); 2203 2204void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2205 size_t size, uint32_t *data); 2206 2207/*********************/ 2208/* LOGGING AND DEBUG */ 2209/*********************/ 2210 2211/* debug logging codepaths */ 2212#define DBG_LOAD 0x00000001 /* load and unload */ 2213#define DBG_INTR 0x00000002 /* interrupt handling */ 2214#define DBG_SP 0x00000004 /* slowpath handling */ 2215#define DBG_STATS 0x00000008 /* stats updates */ 2216#define DBG_TX 0x00000010 /* packet transmit */ 2217#define DBG_RX 0x00000020 /* packet receive */ 2218#define DBG_PHY 0x00000040 /* phy/link handling */ 2219#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2220#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2221#define DBG_REGS 0x00000200 /* register access */ 2222#define DBG_LRO 0x00000400 /* lro processing */ 2223#define DBG_ASSERT 0x80000000 /* debug assert */ 2224#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2225 2226#define DBASSERT(sc, exp, msg) \ 2227 do { \ 2228 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2229 if (__predict_false(!(exp))) { \ 2230 panic msg; \ 2231 } \ 2232 } \ 2233 } while (0) 2234 2235/* log a debug message */ 2236#define BLOGD(sc, codepath, format, args...) \ 2237 do { \ 2238 if (__predict_false(sc->debug & (codepath))) { \ 2239 device_printf((sc)->dev, \ 2240 "%s(%s:%d) " format, \ 2241 __FUNCTION__, \ 2242 __FILE__, \ 2243 __LINE__, \ 2244 ## args); \ 2245 } \ 2246 } while(0) 2247 2248/* log a info message */ 2249#define BLOGI(sc, format, args...) \ 2250 do { \ 2251 if (__predict_false(sc->debug)) { \ 2252 device_printf((sc)->dev, \ 2253 "%s(%s:%d) " format, \ 2254 __FUNCTION__, \ 2255 __FILE__, \ 2256 __LINE__, \ 2257 ## args); \ 2258 } else { \ 2259 device_printf((sc)->dev, \ 2260 format, \ 2261 ## args); \ 2262 } \ 2263 } while(0) 2264 2265/* log a warning message */ 2266#define BLOGW(sc, format, args...) \ 2267 do { \ 2268 if (__predict_false(sc->debug)) { \ 2269 device_printf((sc)->dev, \ 2270 "%s(%s:%d) WARNING: " format, \ 2271 __FUNCTION__, \ 2272 __FILE__, \ 2273 __LINE__, \ 2274 ## args); \ 2275 } else { \ 2276 device_printf((sc)->dev, \ 2277 "WARNING: " format, \ 2278 ## args); \ 2279 } \ 2280 } while(0) 2281 2282/* log a error message */ 2283#define BLOGE(sc, format, args...) \ 2284 do { \ 2285 if (__predict_false(sc->debug)) { \ 2286 device_printf((sc)->dev, \ 2287 "%s(%s:%d) ERROR: " format, \ 2288 __FUNCTION__, \ 2289 __FILE__, \ 2290 __LINE__, \ 2291 ## args); \ 2292 } else { \ 2293 device_printf((sc)->dev, \ 2294 "ERROR: " format, \ 2295 ## args); \ 2296 } \ 2297 } while(0) 2298 2299#ifdef ECORE_STOP_ON_ERROR 2300 2301#define bxe_panic(sc, msg) \ 2302 do { \ 2303 panic msg; \ 2304 } while (0) 2305 2306#else 2307 2308#define bxe_panic(sc, msg) \ 2309 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2310 2311#endif 2312 2313#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2314#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2315 2316void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2317 uint8_t *mem, uint32_t len); 2318void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2319 struct mbuf *m, uint8_t contents); 2320 2321#if __FreeBSD_version >= 800000 2322#if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) ||\ 2323 __FreeBSD_version >= 1100048 2324#define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2325#define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2326#else 2327#define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0) 2328#define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID 2329#endif 2330#endif /* #if __FreeBSD_version >= 800000 */ 2331 2332/***********/ 2333/* INLINES */ 2334/***********/ 2335 2336static inline uint32_t 2337reg_poll(struct bxe_softc *sc, 2338 uint32_t reg, 2339 uint32_t expected, 2340 int ms, 2341 int wait) 2342{ 2343 uint32_t val; 2344 2345 do { 2346 val = REG_RD(sc, reg); 2347 if (val == expected) { 2348 break; 2349 } 2350 ms -= wait; 2351 DELAY(wait * 1000); 2352 } while (ms > 0); 2353 2354 return (val); 2355} 2356 2357static inline void 2358bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2359{ 2360 mb(); /* status block is written to by the chip */ 2361 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2362} 2363 2364static inline void 2365bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2366 uint8_t igu_sb_id, 2367 uint8_t segment, 2368 uint16_t index, 2369 uint8_t op, 2370 uint8_t update, 2371 uint32_t igu_addr) 2372{ 2373 struct igu_regular cmd_data = {0}; 2374 2375 cmd_data.sb_id_and_flags = 2376 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2377 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2378 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2379 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2380 2381 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2382 cmd_data.sb_id_and_flags, igu_addr); 2383 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2384 2385 /* Make sure that ACK is written */ 2386 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2387 BUS_SPACE_BARRIER_WRITE); 2388 mb(); 2389} 2390 2391static inline void 2392bxe_hc_ack_sb(struct bxe_softc *sc, 2393 uint8_t sb_id, 2394 uint8_t storm, 2395 uint16_t index, 2396 uint8_t op, 2397 uint8_t update) 2398{ 2399 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2400 COMMAND_REG_INT_ACK); 2401 struct igu_ack_register igu_ack; 2402 2403 igu_ack.status_block_index = index; 2404 igu_ack.sb_id_and_flags = 2405 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2406 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2407 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2408 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2409 2410 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2411 2412 /* Make sure that ACK is written */ 2413 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2414 BUS_SPACE_BARRIER_WRITE); 2415 mb(); 2416} 2417 2418static inline void 2419bxe_ack_sb(struct bxe_softc *sc, 2420 uint8_t igu_sb_id, 2421 uint8_t storm, 2422 uint16_t index, 2423 uint8_t op, 2424 uint8_t update) 2425{ 2426 if (sc->devinfo.int_block == INT_BLOCK_HC) 2427 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2428 else { 2429 uint8_t segment; 2430 if (CHIP_INT_MODE_IS_BC(sc)) { 2431 segment = storm; 2432 } else if (igu_sb_id != sc->igu_dsb_id) { 2433 segment = IGU_SEG_ACCESS_DEF; 2434 } else if (storm == ATTENTION_ID) { 2435 segment = IGU_SEG_ACCESS_ATTN; 2436 } else { 2437 segment = IGU_SEG_ACCESS_DEF; 2438 } 2439 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2440 } 2441} 2442 2443static inline uint16_t 2444bxe_hc_ack_int(struct bxe_softc *sc) 2445{ 2446 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2447 COMMAND_REG_SIMD_MASK); 2448 uint32_t result = REG_RD(sc, hc_addr); 2449 2450 mb(); 2451 return (result); 2452} 2453 2454static inline uint16_t 2455bxe_igu_ack_int(struct bxe_softc *sc) 2456{ 2457 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2458 uint32_t result = REG_RD(sc, igu_addr); 2459 2460 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2461 result, igu_addr); 2462 2463 mb(); 2464 return (result); 2465} 2466 2467static inline uint16_t 2468bxe_ack_int(struct bxe_softc *sc) 2469{ 2470 mb(); 2471 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2472 return (bxe_hc_ack_int(sc)); 2473 } else { 2474 return (bxe_igu_ack_int(sc)); 2475 } 2476} 2477 2478static inline int 2479func_by_vn(struct bxe_softc *sc, 2480 int vn) 2481{ 2482 return (2 * vn + SC_PORT(sc)); 2483} 2484 2485/* 2486 * Statistics ID are global per chip/path, while Client IDs for E1x 2487 * are per port. 2488 */ 2489static inline uint8_t 2490bxe_stats_id(struct bxe_fastpath *fp) 2491{ 2492 struct bxe_softc *sc = fp->sc; 2493 2494 if (!CHIP_IS_E1x(sc)) { 2495 return (fp->cl_id); 2496 } 2497 2498 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2499} 2500 2501#endif /* __BXE_H__ */ 2502 2503