dev/bxe/ecore_init_ops.h

54 		REG_WR(sc, addr + i*4, data[i]);
284 			REG_WR(sc, addr, op->write.val);
526 		REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
527 		REG_WR(sc, read_arb_addr[i].add,
529 		REG_WR(sc, read_arb_addr[i].ubound,
537 			REG_WR(sc, write_arb_addr[i].l,
540 			REG_WR(sc, write_arb_addr[i].add,
543 			REG_WR(sc, write_arb_addr[i].ubound,
548 			REG_WR(sc, write_arb_addr[i].l,
552 			REG_WR(sc, write_arb_addr[i].add,
556 			REG_WR(sc, write_arb_addr[i].ubound,
564 	REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
569 	REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
571 	REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
572 	REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
573 	REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
574 	REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
577 		REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
580 		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
582 		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
584 		REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
596 			REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
599 			REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
602 		REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
603 		REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
604 		REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
605 		REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
606 		REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
607 		REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
608 		REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
609 		REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
610 		REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
611 		REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
619 		REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
764 		REG_WR(sc, start_reg + SC_FUNC(sc)*4,
786 		REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
787 		REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
853 		REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
894 			REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
909 		REG_WR(sc, base_reg + i*4,
956 	REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);