1255736Sdavidch/*- 2265411Sdavidcs * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3255736Sdavidch * 4255736Sdavidch * Redistribution and use in source and binary forms, with or without 5255736Sdavidch * modification, are permitted provided that the following conditions 6255736Sdavidch * are met: 7255736Sdavidch * 8255736Sdavidch * 1. Redistributions of source code must retain the above copyright 9255736Sdavidch * notice, this list of conditions and the following disclaimer. 10255736Sdavidch * 2. Redistributions in binary form must reproduce the above copyright 11255736Sdavidch * notice, this list of conditions and the following disclaimer in the 12255736Sdavidch * documentation and/or other materials provided with the distribution. 13255736Sdavidch * 14255736Sdavidch * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15255736Sdavidch * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16255736Sdavidch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17255736Sdavidch * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18255736Sdavidch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19255736Sdavidch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20255736Sdavidch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21255736Sdavidch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22255736Sdavidch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23255736Sdavidch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24255736Sdavidch * THE POSSIBILITY OF SUCH DAMAGE. 25255736Sdavidch */ 26255736Sdavidch 27255736Sdavidch#ifndef __BXE_H__ 28255736Sdavidch#define __BXE_H__ 29255736Sdavidch 30255736Sdavidch#include <sys/cdefs.h> 31255736Sdavidch__FBSDID("$FreeBSD: stable/11/sys/dev/bxe/bxe.h 339881 2018-10-29 21:09:39Z davidcs $"); 32255736Sdavidch 33255736Sdavidch#include <sys/param.h> 34255736Sdavidch#include <sys/kernel.h> 35255736Sdavidch#include <sys/systm.h> 36255736Sdavidch#include <sys/lock.h> 37255736Sdavidch#include <sys/mutex.h> 38255736Sdavidch#include <sys/sx.h> 39255736Sdavidch#include <sys/module.h> 40255736Sdavidch#include <sys/endian.h> 41255736Sdavidch#include <sys/types.h> 42255736Sdavidch#include <sys/malloc.h> 43255736Sdavidch#include <sys/kobj.h> 44255736Sdavidch#include <sys/bus.h> 45255736Sdavidch#include <sys/rman.h> 46255736Sdavidch#include <sys/socket.h> 47255736Sdavidch#include <sys/sockio.h> 48255736Sdavidch#include <sys/sysctl.h> 49255736Sdavidch#include <sys/smp.h> 50255736Sdavidch#include <sys/bitstring.h> 51255736Sdavidch#include <sys/limits.h> 52255736Sdavidch#include <sys/queue.h> 53255736Sdavidch#include <sys/taskqueue.h> 54281855Srodrigc#include <sys/zlib.h> 55255736Sdavidch 56255736Sdavidch#include <net/if.h> 57255736Sdavidch#include <net/if_types.h> 58255736Sdavidch#include <net/if_arp.h> 59255736Sdavidch#include <net/ethernet.h> 60255736Sdavidch#include <net/if_dl.h> 61266979Smarcel#include <net/if_var.h> 62255736Sdavidch#include <net/if_media.h> 63255736Sdavidch#include <net/if_vlan_var.h> 64255736Sdavidch#include <net/bpf.h> 65255736Sdavidch 66255736Sdavidch#include <netinet/in.h> 67255736Sdavidch#include <netinet/ip.h> 68255736Sdavidch#include <netinet/ip6.h> 69255736Sdavidch#include <netinet/tcp.h> 70255736Sdavidch#include <netinet/udp.h> 71255736Sdavidch 72255736Sdavidch#include <dev/pci/pcireg.h> 73255736Sdavidch#include <dev/pci/pcivar.h> 74255736Sdavidch 75255736Sdavidch#include <machine/atomic.h> 76255736Sdavidch#include <machine/resource.h> 77255736Sdavidch#include <machine/endian.h> 78255736Sdavidch#include <machine/bus.h> 79255736Sdavidch#include <machine/in_cksum.h> 80255736Sdavidch 81255736Sdavidch#include "device_if.h" 82255736Sdavidch#include "bus_if.h" 83255736Sdavidch#include "pci_if.h" 84255736Sdavidch 85255736Sdavidch#if _BYTE_ORDER == _LITTLE_ENDIAN 86255736Sdavidch#ifndef LITTLE_ENDIAN 87255736Sdavidch#define LITTLE_ENDIAN 88255736Sdavidch#endif 89255736Sdavidch#ifndef __LITTLE_ENDIAN 90255736Sdavidch#define __LITTLE_ENDIAN 91255736Sdavidch#endif 92255736Sdavidch#undef BIG_ENDIAN 93255736Sdavidch#undef __BIG_ENDIAN 94255736Sdavidch#else /* _BIG_ENDIAN */ 95255736Sdavidch#ifndef BIG_ENDIAN 96255736Sdavidch#define BIG_ENDIAN 97255736Sdavidch#endif 98255736Sdavidch#ifndef __BIG_ENDIAN 99255736Sdavidch#define __BIG_ENDIAN 100255736Sdavidch#endif 101255736Sdavidch#undef LITTLE_ENDIAN 102255736Sdavidch#undef __LITTLE_ENDIAN 103255736Sdavidch#endif 104255736Sdavidch 105255736Sdavidch#include "ecore_mfw_req.h" 106255736Sdavidch#include "ecore_fw_defs.h" 107255736Sdavidch#include "ecore_hsi.h" 108255736Sdavidch#include "ecore_reg.h" 109255736Sdavidch#include "bxe_dcb.h" 110255736Sdavidch#include "bxe_stats.h" 111255736Sdavidch 112255736Sdavidch#include "bxe_elink.h" 113255736Sdavidch 114296071Sdavidcs#define VF_MAC_CREDIT_CNT 0 115296071Sdavidcs#define VF_VLAN_CREDIT_CNT (0) 116296071Sdavidcs 117255736Sdavidch#if __FreeBSD_version < 800054 118255736Sdavidch#if defined(__i386__) || defined(__amd64__) 119255736Sdavidch#define mb() __asm volatile("mfence;" : : : "memory") 120255736Sdavidch#define wmb() __asm volatile("sfence;" : : : "memory") 121255736Sdavidch#define rmb() __asm volatile("lfence;" : : : "memory") 122255736Sdavidchstatic __inline void prefetch(void *x) 123255736Sdavidch{ 124255736Sdavidch __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 125255736Sdavidch} 126255736Sdavidch#else 127255736Sdavidch#define mb() 128255736Sdavidch#define rmb() 129255736Sdavidch#define wmb() 130255736Sdavidch#define prefetch(x) 131255736Sdavidch#endif 132255736Sdavidch#endif 133255736Sdavidch 134255736Sdavidch#if __FreeBSD_version >= 1000000 135255736Sdavidch#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 136255736Sdavidch#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 137255736Sdavidch#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 138255736Sdavidch#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 139255736Sdavidch#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 140255736Sdavidch#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 141255736Sdavidch#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 142255736Sdavidch#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 143255736Sdavidch#endif 144255736Sdavidch 145255736Sdavidch#ifndef ARRAY_SIZE 146255736Sdavidch#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147255736Sdavidch#endif 148255736Sdavidch#ifndef ARRSIZE 149255736Sdavidch#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 150255736Sdavidch#endif 151255736Sdavidch#ifndef DIV_ROUND_UP 152255736Sdavidch#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 153255736Sdavidch#endif 154255736Sdavidch#ifndef roundup 155255736Sdavidch#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 156255736Sdavidch#endif 157255736Sdavidch#ifndef ilog2 158255736Sdavidchstatic inline 159255736Sdavidchint bxe_ilog2(int x) 160255736Sdavidch{ 161255736Sdavidch int log = 0; 162255736Sdavidch while (x >>= 1) log++; 163255736Sdavidch return (log); 164255736Sdavidch} 165255736Sdavidch#define ilog2(x) bxe_ilog2(x) 166255736Sdavidch#endif 167255736Sdavidch 168255736Sdavidch#include "ecore_sp.h" 169255736Sdavidch 170255736Sdavidch#define BRCM_VENDORID 0x14e4 171321517Sae#define QLOGIC_VENDORID 0x1077 172255736Sdavidch#define PCI_ANY_ID (uint16_t)(~0U) 173255736Sdavidch 174255736Sdavidchstruct bxe_device_type 175255736Sdavidch{ 176255736Sdavidch uint16_t bxe_vid; 177255736Sdavidch uint16_t bxe_did; 178255736Sdavidch uint16_t bxe_svid; 179255736Sdavidch uint16_t bxe_sdid; 180255736Sdavidch char *bxe_name; 181255736Sdavidch}; 182255736Sdavidch 183255736Sdavidch#define BCM_PAGE_SHIFT 12 184255736Sdavidch#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 185255736Sdavidch#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 186255736Sdavidch#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 187255736Sdavidch 188255736Sdavidch#if BCM_PAGE_SIZE != 4096 189255736Sdavidch#error Page sizes other than 4KB are unsupported! 190255736Sdavidch#endif 191255736Sdavidch 192255736Sdavidch#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 193255736Sdavidch#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 194255736Sdavidch#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 195255736Sdavidch#else 196255736Sdavidch#define U64_LO(addr) ((uint32_t)(addr)) 197255736Sdavidch#define U64_HI(addr) (0) 198255736Sdavidch#endif 199255736Sdavidch#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 200255736Sdavidch 201255736Sdavidch#define SET_FLAG(value, mask, flag) \ 202255736Sdavidch do { \ 203255736Sdavidch (value) &= ~(mask); \ 204255736Sdavidch (value) |= ((flag) << (mask##_SHIFT)); \ 205255736Sdavidch } while (0) 206255736Sdavidch 207255736Sdavidch#define GET_FLAG(value, mask) \ 208255736Sdavidch (((value) & (mask)) >> (mask##_SHIFT)) 209255736Sdavidch 210255736Sdavidch#define GET_FIELD(value, fname) \ 211255736Sdavidch (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 212255736Sdavidch 213255736Sdavidch#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 214255736Sdavidch#define BXE_TSO_MAX_SEGMENTS 32 215255736Sdavidch#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 216255736Sdavidch#define BXE_TSO_MAX_SEG_SIZE 4096 217255736Sdavidch 218255736Sdavidch/* dropless fc FW/HW related params */ 219255736Sdavidch#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 220255736Sdavidch#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 221255736Sdavidch ETH_MAX_AGGREGATION_QUEUES_E1 : \ 222255736Sdavidch ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 223255736Sdavidch#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 224255736Sdavidch#define FW_PREFETCH_CNT 16 225255736Sdavidch#define DROPLESS_FC_HEADROOM 100 226255736Sdavidch 227255736Sdavidch/******************/ 228255736Sdavidch/* RX SGE defines */ 229255736Sdavidch/******************/ 230255736Sdavidch 231255736Sdavidch#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 232255736Sdavidch#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 233255736Sdavidch#define RX_SGE_NEXT_PAGE_DESC_CNT 2 234255736Sdavidch#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 235255736Sdavidch#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 236255736Sdavidch#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 237255736Sdavidch#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 238255736Sdavidch#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 239255736Sdavidch#define RX_SGE(x) ((x) & RX_SGE_MAX) 240255736Sdavidch 241255736Sdavidch#define RX_SGE_NEXT(x) \ 242255736Sdavidch ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 243255736Sdavidch ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 244255736Sdavidch 245255736Sdavidch#define RX_SGE_MASK_ELEM_SZ 64 246255736Sdavidch#define RX_SGE_MASK_ELEM_SHIFT 6 247255736Sdavidch#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 248255736Sdavidch 249255736Sdavidch/* 250255736Sdavidch * Creates a bitmask of all ones in less significant bits. 251255736Sdavidch * idx - index of the most significant bit in the created mask. 252255736Sdavidch */ 253255736Sdavidch#define RX_SGE_ONES_MASK(idx) \ 254255736Sdavidch (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 255255736Sdavidch#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 256255736Sdavidch 257255736Sdavidch/* Number of uint64_t elements in SGE mask array. */ 258255736Sdavidch#define RX_SGE_MASK_LEN \ 259255736Sdavidch ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 260255736Sdavidch#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 261255736Sdavidch#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 262255736Sdavidch 263255736Sdavidch/* 264255736Sdavidch * dropless fc calculations for SGEs 265255736Sdavidch * Number of required SGEs is the sum of two: 266255736Sdavidch * 1. Number of possible opened aggregations (next packet for 267255736Sdavidch * these aggregations will probably consume SGE immidiatelly) 268255736Sdavidch * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 269255736Sdavidch * after placement on BD for new TPA aggregation) 270255736Sdavidch * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 271255736Sdavidch */ 272255736Sdavidch#define NUM_SGE_REQ(sc) \ 273255736Sdavidch (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 274255736Sdavidch#define NUM_SGE_PG_REQ(sc) \ 275255736Sdavidch ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 276255736Sdavidch#define SGE_TH_LO(sc) \ 277255736Sdavidch (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 278255736Sdavidch#define SGE_TH_HI(sc) \ 279255736Sdavidch (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 280255736Sdavidch 281255736Sdavidch#define PAGES_PER_SGE_SHIFT 0 282255736Sdavidch#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 283255736Sdavidch#define SGE_PAGE_SIZE BCM_PAGE_SIZE 284255736Sdavidch#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 285255736Sdavidch#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 286255736Sdavidch#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 287255736Sdavidch#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 288255736Sdavidch 289255736Sdavidch/*****************/ 290255736Sdavidch/* TX BD defines */ 291255736Sdavidch/*****************/ 292255736Sdavidch 293255736Sdavidch#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 294255736Sdavidch#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 295255736Sdavidch#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 296255736Sdavidch#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 297255736Sdavidch#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 298255736Sdavidch#define TX_BD_MAX (TX_BD_TOTAL - 1) 299255736Sdavidch 300255736Sdavidch#define TX_BD_NEXT(x) \ 301255736Sdavidch ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 302255736Sdavidch ((x) + 2) : ((x) + 1)) 303255736Sdavidch#define TX_BD(x) ((x) & TX_BD_MAX) 304255736Sdavidch#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 305255736Sdavidch#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 306255736Sdavidch 307255736Sdavidch/* 308255736Sdavidch * Trigger pending transmits when the number of available BDs is greater 309255736Sdavidch * than 1/8 of the total number of usable BDs. 310255736Sdavidch */ 311255736Sdavidch#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 312255736Sdavidch#define BXE_TX_TIMEOUT 5 313255736Sdavidch 314255736Sdavidch/*****************/ 315255736Sdavidch/* RX BD defines */ 316255736Sdavidch/*****************/ 317255736Sdavidch 318255736Sdavidch#define RX_BD_NUM_PAGES 8 /* power of 2 */ 319255736Sdavidch#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 320255736Sdavidch#define RX_BD_NEXT_PAGE_DESC_CNT 2 321255736Sdavidch#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 322255736Sdavidch#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 323255736Sdavidch#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 324255736Sdavidch#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 325255736Sdavidch#define RX_BD_MAX (RX_BD_TOTAL - 1) 326255736Sdavidch 327255736Sdavidch#define RX_BD_NEXT(x) \ 328255736Sdavidch ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 329255736Sdavidch ((x) + 3) : ((x) + 1)) 330255736Sdavidch#define RX_BD(x) ((x) & RX_BD_MAX) 331255736Sdavidch#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 332255736Sdavidch#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 333255736Sdavidch 334255736Sdavidch/* 335255736Sdavidch * dropless fc calculations for BDs 336255736Sdavidch * Number of BDs should be as number of buffers in BRB: 337255736Sdavidch * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 338255736Sdavidch * "next" elements on each page 339255736Sdavidch */ 340255736Sdavidch#define NUM_BD_REQ(sc) \ 341255736Sdavidch BRB_SIZE(sc) 342255736Sdavidch#define NUM_BD_PG_REQ(sc) \ 343255736Sdavidch ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 344255736Sdavidch#define BD_TH_LO(sc) \ 345255736Sdavidch (NUM_BD_REQ(sc) + \ 346255736Sdavidch NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 347255736Sdavidch FW_DROP_LEVEL(sc)) 348255736Sdavidch#define BD_TH_HI(sc) \ 349255736Sdavidch (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 350255736Sdavidch#define MIN_RX_AVAIL(sc) \ 351255736Sdavidch ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 352255736Sdavidch#define MIN_RX_SIZE_TPA_HW(sc) \ 353255736Sdavidch (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 354255736Sdavidch ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 355255736Sdavidch#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 356255736Sdavidch#define MIN_RX_SIZE_TPA(sc) \ 357255736Sdavidch (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 358255736Sdavidch#define MIN_RX_SIZE_NONTPA(sc) \ 359255736Sdavidch (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 360255736Sdavidch 361255736Sdavidch/***************/ 362255736Sdavidch/* RCQ defines */ 363255736Sdavidch/***************/ 364255736Sdavidch 365255736Sdavidch/* 366255736Sdavidch * As long as CQE is X times bigger than BD entry we have to allocate X times 367255736Sdavidch * more pages for CQ ring in order to keep it balanced with BD ring 368255736Sdavidch */ 369255736Sdavidch#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 370255736Sdavidch sizeof(struct eth_rx_bd)) 371255736Sdavidch#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 372255736Sdavidch#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 373255736Sdavidch#define RCQ_NEXT_PAGE_DESC_CNT 1 374255736Sdavidch#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 375255736Sdavidch#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 376255736Sdavidch#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 377255736Sdavidch#define RCQ_MAX (RCQ_TOTAL - 1) 378255736Sdavidch 379255736Sdavidch#define RCQ_NEXT(x) \ 380255736Sdavidch ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 381255736Sdavidch ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 382255736Sdavidch#define RCQ(x) ((x) & RCQ_MAX) 383255736Sdavidch#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 384255736Sdavidch#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 385255736Sdavidch 386255736Sdavidch/* 387255736Sdavidch * dropless fc calculations for RCQs 388255736Sdavidch * Number of RCQs should be as number of buffers in BRB: 389255736Sdavidch * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 390255736Sdavidch * "next" elements on each page 391255736Sdavidch */ 392255736Sdavidch#define NUM_RCQ_REQ(sc) \ 393255736Sdavidch BRB_SIZE(sc) 394255736Sdavidch#define NUM_RCQ_PG_REQ(sc) \ 395255736Sdavidch ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 396255736Sdavidch#define RCQ_TH_LO(sc) \ 397255736Sdavidch (NUM_RCQ_REQ(sc) + \ 398255736Sdavidch NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 399255736Sdavidch FW_DROP_LEVEL(sc)) 400255736Sdavidch#define RCQ_TH_HI(sc) \ 401255736Sdavidch (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 402255736Sdavidch 403255736Sdavidch/* This is needed for determening of last_max */ 404255736Sdavidch#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 405255736Sdavidch 406255736Sdavidch#define __SGE_MASK_SET_BIT(el, bit) \ 407255736Sdavidch do { \ 408255736Sdavidch (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 409255736Sdavidch } while (0) 410255736Sdavidch 411255736Sdavidch#define __SGE_MASK_CLEAR_BIT(el, bit) \ 412255736Sdavidch do { \ 413255736Sdavidch (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 414255736Sdavidch } while (0) 415255736Sdavidch 416255736Sdavidch#define SGE_MASK_SET_BIT(fp, idx) \ 417255736Sdavidch __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 418255736Sdavidch ((idx) & RX_SGE_MASK_ELEM_MASK)) 419255736Sdavidch 420255736Sdavidch#define SGE_MASK_CLEAR_BIT(fp, idx) \ 421255736Sdavidch __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 422255736Sdavidch ((idx) & RX_SGE_MASK_ELEM_MASK)) 423255736Sdavidch 424255736Sdavidch/* Load / Unload modes */ 425255736Sdavidch#define LOAD_NORMAL 0 426255736Sdavidch#define LOAD_OPEN 1 427255736Sdavidch#define LOAD_DIAG 2 428255736Sdavidch#define LOAD_LOOPBACK_EXT 3 429255736Sdavidch#define UNLOAD_NORMAL 0 430255736Sdavidch#define UNLOAD_CLOSE 1 431255736Sdavidch#define UNLOAD_RECOVERY 2 432255736Sdavidch 433255736Sdavidch/* Some constants... */ 434255736Sdavidch//#define MAX_PATH_NUM 2 435255736Sdavidch//#define E2_MAX_NUM_OF_VFS 64 436255736Sdavidch//#define E1H_FUNC_MAX 8 437255736Sdavidch//#define E2_FUNC_MAX 4 /* per path */ 438255736Sdavidch#define MAX_VNIC_NUM 4 439255736Sdavidch#define MAX_FUNC_NUM 8 /* common to all chips */ 440255736Sdavidch//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 441255736Sdavidch#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 442255736Sdavidch#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 443255736Sdavidch 444255736Sdavidch#define ILT_NUM_PAGE_ENTRIES 3072 445255736Sdavidch/* 446255736Sdavidch * 57710/11 we use whole table since we have 8 functions. 447255736Sdavidch * 57712 we have only 4 functions, but use same size per func, so only half 448255736Sdavidch * of the table is used. 449255736Sdavidch */ 450255736Sdavidch#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 451255736Sdavidch#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 452255736Sdavidch/* 453255736Sdavidch * the phys address is shifted right 12 bits and has an added 454255736Sdavidch * 1=valid bit added to the 53rd bit 455255736Sdavidch * then since this is a wide register(TM) 456255736Sdavidch * we split it into two 32 bit writes 457255736Sdavidch */ 458255736Sdavidch#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 459255736Sdavidch#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 460255736Sdavidch 461255736Sdavidch/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 462255736Sdavidch#define ETH_HLEN 14 463255736Sdavidch#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 464255736Sdavidch#define ETH_MIN_PACKET_SIZE 60 465255736Sdavidch#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 466255736Sdavidch#define ETH_MAX_JUMBO_PACKET_SIZE 9600 467255736Sdavidch/* TCP with Timestamp Option (32) + IPv6 (40) */ 468255736Sdavidch#define ETH_MAX_TPA_HEADER_SIZE 72 469255736Sdavidch 470255736Sdavidch/* max supported alignment is 256 (8 shift) */ 471255736Sdavidch//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 472255736Sdavidch#define BXE_RX_ALIGN_SHIFT 8 473255736Sdavidch/* FW uses 2 cache lines alignment for start packet and size */ 474255736Sdavidch#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 475255736Sdavidch#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 476255736Sdavidch 477255736Sdavidch#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 478339881Sdavidcs#define BXE_SET_ERROR_BIT(sc, error) \ 479339881Sdavidcs{ \ 480339881Sdavidcs (sc)->error_status |= (error); \ 481339881Sdavidcs} 482255736Sdavidch 483255736Sdavidchstruct bxe_bar { 484255736Sdavidch struct resource *resource; 485255736Sdavidch int rid; 486255736Sdavidch bus_space_tag_t tag; 487255736Sdavidch bus_space_handle_t handle; 488255736Sdavidch vm_offset_t kva; 489255736Sdavidch}; 490255736Sdavidch 491255736Sdavidchstruct bxe_intr { 492255736Sdavidch struct resource *resource; 493255736Sdavidch int rid; 494255736Sdavidch void *tag; 495255736Sdavidch}; 496255736Sdavidch 497255736Sdavidch/* Used to manage DMA allocations. */ 498255736Sdavidchstruct bxe_dma { 499255736Sdavidch struct bxe_softc *sc; 500255736Sdavidch bus_addr_t paddr; 501255736Sdavidch void *vaddr; 502255736Sdavidch bus_dma_tag_t tag; 503255736Sdavidch bus_dmamap_t map; 504255736Sdavidch bus_dma_segment_t seg; 505255736Sdavidch bus_size_t size; 506255736Sdavidch int nseg; 507255736Sdavidch char msg[32]; 508255736Sdavidch}; 509255736Sdavidch 510255736Sdavidch/* attn group wiring */ 511255736Sdavidch#define MAX_DYNAMIC_ATTN_GRPS 8 512255736Sdavidch 513255736Sdavidchstruct attn_route { 514255736Sdavidch uint32_t sig[5]; 515255736Sdavidch}; 516255736Sdavidch 517255736Sdavidchstruct iro { 518255736Sdavidch uint32_t base; 519255736Sdavidch uint16_t m1; 520255736Sdavidch uint16_t m2; 521255736Sdavidch uint16_t m3; 522255736Sdavidch uint16_t size; 523255736Sdavidch}; 524255736Sdavidch 525255736Sdavidchunion bxe_host_hc_status_block { 526255736Sdavidch /* pointer to fp status block e2 */ 527255736Sdavidch struct host_hc_status_block_e2 *e2_sb; 528255736Sdavidch /* pointer to fp status block e1x */ 529255736Sdavidch struct host_hc_status_block_e1x *e1x_sb; 530255736Sdavidch}; 531255736Sdavidch 532255736Sdavidchunion bxe_db_prod { 533255736Sdavidch struct doorbell_set_prod data; 534255736Sdavidch uint32_t raw; 535255736Sdavidch}; 536255736Sdavidch 537255736Sdavidchstruct bxe_sw_tx_bd { 538255736Sdavidch struct mbuf *m; 539255736Sdavidch bus_dmamap_t m_map; 540255736Sdavidch uint16_t first_bd; 541255736Sdavidch uint8_t flags; 542255736Sdavidch/* set on the first BD descriptor when there is a split BD */ 543255736Sdavidch#define BXE_TSO_SPLIT_BD (1 << 0) 544255736Sdavidch}; 545255736Sdavidch 546255736Sdavidchstruct bxe_sw_rx_bd { 547255736Sdavidch struct mbuf *m; 548255736Sdavidch bus_dmamap_t m_map; 549255736Sdavidch}; 550255736Sdavidch 551255736Sdavidchstruct bxe_sw_tpa_info { 552255736Sdavidch struct bxe_sw_rx_bd bd; 553255736Sdavidch bus_dma_segment_t seg; 554255736Sdavidch uint8_t state; 555255736Sdavidch#define BXE_TPA_STATE_START 1 556255736Sdavidch#define BXE_TPA_STATE_STOP 2 557255736Sdavidch uint8_t placement_offset; 558255736Sdavidch uint16_t parsing_flags; 559255736Sdavidch uint16_t vlan_tag; 560255736Sdavidch uint16_t len_on_bd; 561255736Sdavidch}; 562255736Sdavidch 563255736Sdavidch/* 564255736Sdavidch * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 565255736Sdavidch * instances of the fastpath structure when using multiple queues. 566255736Sdavidch */ 567255736Sdavidchstruct bxe_fastpath { 568255736Sdavidch /* pointer back to parent structure */ 569255736Sdavidch struct bxe_softc *sc; 570255736Sdavidch 571255736Sdavidch struct mtx tx_mtx; 572255736Sdavidch char tx_mtx_name[32]; 573255736Sdavidch struct mtx rx_mtx; 574255736Sdavidch char rx_mtx_name[32]; 575255736Sdavidch 576255736Sdavidch#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 577255736Sdavidch#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 578255736Sdavidch#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 579285973Sdavidcs#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 580255736Sdavidch 581255736Sdavidch#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 582255736Sdavidch#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 583255736Sdavidch#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 584255736Sdavidch 585255736Sdavidch /* status block */ 586255736Sdavidch struct bxe_dma sb_dma; 587255736Sdavidch union bxe_host_hc_status_block status_block; 588255736Sdavidch 589255736Sdavidch /* transmit chain (tx bds) */ 590255736Sdavidch struct bxe_dma tx_dma; 591255736Sdavidch union eth_tx_bd_types *tx_chain; 592255736Sdavidch 593255736Sdavidch /* receive chain (rx bds) */ 594255736Sdavidch struct bxe_dma rx_dma; 595255736Sdavidch struct eth_rx_bd *rx_chain; 596255736Sdavidch 597255736Sdavidch /* receive completion queue chain (rcq bds) */ 598255736Sdavidch struct bxe_dma rcq_dma; 599255736Sdavidch union eth_rx_cqe *rcq_chain; 600255736Sdavidch 601255736Sdavidch /* receive scatter/gather entry chain (for TPA) */ 602255736Sdavidch struct bxe_dma rx_sge_dma; 603255736Sdavidch struct eth_rx_sge *rx_sge_chain; 604255736Sdavidch 605255736Sdavidch /* tx mbufs */ 606255736Sdavidch bus_dma_tag_t tx_mbuf_tag; 607255736Sdavidch struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 608255736Sdavidch 609255736Sdavidch /* rx mbufs */ 610255736Sdavidch bus_dma_tag_t rx_mbuf_tag; 611255736Sdavidch struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 612255736Sdavidch bus_dmamap_t rx_mbuf_spare_map; 613255736Sdavidch 614255736Sdavidch /* rx sge mbufs */ 615255736Sdavidch bus_dma_tag_t rx_sge_mbuf_tag; 616255736Sdavidch struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 617255736Sdavidch bus_dmamap_t rx_sge_mbuf_spare_map; 618255736Sdavidch 619255736Sdavidch /* rx tpa mbufs (use the larger size for TPA queue length) */ 620255736Sdavidch int tpa_enable; /* disabled per fastpath upon error */ 621255736Sdavidch struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 622255736Sdavidch bus_dmamap_t rx_tpa_info_mbuf_spare_map; 623255736Sdavidch uint64_t rx_tpa_queue_used; 624255736Sdavidch 625255736Sdavidch uint16_t *sb_index_values; 626255736Sdavidch uint16_t *sb_running_index; 627255736Sdavidch uint32_t ustorm_rx_prods_offset; 628255736Sdavidch 629255736Sdavidch uint8_t igu_sb_id; /* status block number in HW */ 630255736Sdavidch uint8_t fw_sb_id; /* status block number in FW */ 631255736Sdavidch 632255736Sdavidch uint32_t rx_buf_size; 633255736Sdavidch int mbuf_alloc_size; 634255736Sdavidch 635255736Sdavidch int state; 636255736Sdavidch#define BXE_FP_STATE_CLOSED 0x01 637255736Sdavidch#define BXE_FP_STATE_IRQ 0x02 638255736Sdavidch#define BXE_FP_STATE_OPENING 0x04 639255736Sdavidch#define BXE_FP_STATE_OPEN 0x08 640255736Sdavidch#define BXE_FP_STATE_HALTING 0x10 641255736Sdavidch#define BXE_FP_STATE_HALTED 0x20 642255736Sdavidch 643255736Sdavidch /* reference back to this fastpath queue number */ 644255736Sdavidch uint8_t index; /* this is also the 'cid' */ 645255736Sdavidch#define FP_IDX(fp) (fp->index) 646255736Sdavidch 647255736Sdavidch /* interrupt taskqueue (fast) */ 648255736Sdavidch struct task tq_task; 649255736Sdavidch struct taskqueue *tq; 650255736Sdavidch char tq_name[32]; 651255736Sdavidch 652307972Sdavidcs struct task tx_task; 653307972Sdavidcs struct timeout_task tx_timeout_task; 654307972Sdavidcs 655255736Sdavidch /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 656255736Sdavidch uint8_t cl_id; 657255736Sdavidch#define FP_CL_ID(fp) (fp->cl_id) 658255736Sdavidch uint8_t cl_qzone_id; 659255736Sdavidch 660255736Sdavidch uint16_t fp_hc_idx; 661255736Sdavidch 662255736Sdavidch /* driver copy of the receive buffer descriptor prod/cons indices */ 663255736Sdavidch uint16_t rx_bd_prod; 664255736Sdavidch uint16_t rx_bd_cons; 665255736Sdavidch 666255736Sdavidch /* driver copy of the receive completion queue prod/cons indices */ 667255736Sdavidch uint16_t rx_cq_prod; 668255736Sdavidch uint16_t rx_cq_cons; 669255736Sdavidch 670255736Sdavidch union bxe_db_prod tx_db; 671255736Sdavidch 672255736Sdavidch /* Transmit packet producer index (used in eth_tx_bd). */ 673255736Sdavidch uint16_t tx_pkt_prod; 674255736Sdavidch uint16_t tx_pkt_cons; 675255736Sdavidch 676255736Sdavidch /* Transmit buffer descriptor producer index. */ 677255736Sdavidch uint16_t tx_bd_prod; 678255736Sdavidch uint16_t tx_bd_cons; 679255736Sdavidch 680255736Sdavidch uint64_t sge_mask[RX_SGE_MASK_LEN]; 681255736Sdavidch uint16_t rx_sge_prod; 682255736Sdavidch 683255736Sdavidch struct tstorm_per_queue_stats old_tclient; 684255736Sdavidch struct ustorm_per_queue_stats old_uclient; 685255736Sdavidch struct xstorm_per_queue_stats old_xclient; 686255736Sdavidch struct bxe_eth_q_stats eth_q_stats; 687255736Sdavidch struct bxe_eth_q_stats_old eth_q_stats_old; 688255736Sdavidch 689255736Sdavidch /* Pointer to the receive consumer in the status block */ 690255736Sdavidch uint16_t *rx_cq_cons_sb; 691255736Sdavidch 692255736Sdavidch /* Pointer to the transmit consumer in the status block */ 693255736Sdavidch uint16_t *tx_cons_sb; 694255736Sdavidch 695255736Sdavidch /* transmit timeout until chip reset */ 696255736Sdavidch int watchdog_timer; 697255736Sdavidch 698255736Sdavidch /* Free/used buffer descriptor counters. */ 699255736Sdavidch //uint16_t used_tx_bd; 700255736Sdavidch 701255736Sdavidch /* Last maximal completed SGE */ 702255736Sdavidch uint16_t last_max_sge; 703255736Sdavidch 704255736Sdavidch //uint16_t rx_sge_free_idx; 705255736Sdavidch 706255736Sdavidch //uint8_t segs; 707255736Sdavidch 708255736Sdavidch#if __FreeBSD_version >= 800000 709255736Sdavidch#define BXE_BR_SIZE 4096 710255736Sdavidch struct buf_ring *tx_br; 711255736Sdavidch#endif 712255736Sdavidch}; /* struct bxe_fastpath */ 713255736Sdavidch 714255736Sdavidch/* sriov XXX */ 715255736Sdavidch#define BXE_MAX_NUM_OF_VFS 64 716255736Sdavidch#define BXE_VF_CID_WND 0 717255736Sdavidch#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 718255736Sdavidch#define BXE_CLIENTS_PER_VF 1 719255736Sdavidch#define BXE_FIRST_VF_CID 256 720255736Sdavidch#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 721255736Sdavidch#define BXE_VF_ID_INVALID 0xFF 722255736Sdavidch#define IS_SRIOV(sc) 0 723255736Sdavidch 724258187Sedavis#define GET_NUM_VFS_PER_PATH(sc) 0 725258187Sedavis#define GET_NUM_VFS_PER_PF(sc) 0 726258187Sedavis 727255736Sdavidch/* maximum number of fast-path interrupt contexts */ 728255736Sdavidch#define FP_SB_MAX_E1x 16 729255736Sdavidch#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 730255736Sdavidch 731255736Sdavidchunion cdu_context { 732255736Sdavidch struct eth_context eth; 733255736Sdavidch char pad[1024]; 734255736Sdavidch}; 735255736Sdavidch 736255736Sdavidch/* CDU host DB constants */ 737255736Sdavidch#define CDU_ILT_PAGE_SZ_HW 2 738255736Sdavidch#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 739255736Sdavidch#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 740255736Sdavidch 741255736Sdavidch#define CNIC_ISCSI_CID_MAX 256 742255736Sdavidch#define CNIC_FCOE_CID_MAX 2048 743255736Sdavidch#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 744255736Sdavidch#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 745255736Sdavidch 746255736Sdavidch#define QM_ILT_PAGE_SZ_HW 0 747255736Sdavidch#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 748255736Sdavidch#define QM_CID_ROUND 1024 749255736Sdavidch 750255736Sdavidch/* TM (timers) host DB constants */ 751255736Sdavidch#define TM_ILT_PAGE_SZ_HW 0 752255736Sdavidch#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 753255736Sdavidch/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 754255736Sdavidch#define TM_CONN_NUM 1024 755255736Sdavidch#define TM_ILT_SZ (8 * TM_CONN_NUM) 756255736Sdavidch#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 757255736Sdavidch 758255736Sdavidch/* SRC (Searcher) host DB constants */ 759255736Sdavidch#define SRC_ILT_PAGE_SZ_HW 0 760255736Sdavidch#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 761255736Sdavidch#define SRC_HASH_BITS 10 762255736Sdavidch#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 763255736Sdavidch#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 764255736Sdavidch#define SRC_T2_SZ SRC_ILT_SZ 765255736Sdavidch#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 766255736Sdavidch 767255736Sdavidchstruct hw_context { 768255736Sdavidch struct bxe_dma vcxt_dma; 769255736Sdavidch union cdu_context *vcxt; 770255736Sdavidch //bus_addr_t cxt_mapping; 771255736Sdavidch size_t size; 772255736Sdavidch}; 773255736Sdavidch 774255736Sdavidch#define SM_RX_ID 0 775255736Sdavidch#define SM_TX_ID 1 776255736Sdavidch 777255736Sdavidch/* defines for multiple tx priority indices */ 778255736Sdavidch#define FIRST_TX_ONLY_COS_INDEX 1 779255736Sdavidch#define FIRST_TX_COS_INDEX 0 780255736Sdavidch 781255736Sdavidch#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 782255736Sdavidch 783255736Sdavidch#define HC_INDEX_ETH_RX_CQ_CONS 1 784255736Sdavidch#define HC_INDEX_OOO_TX_CQ_CONS 4 785255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 786255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 787255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 788255736Sdavidch#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 789255736Sdavidch 790255736Sdavidch/* congestion management fairness mode */ 791255736Sdavidch#define CMNG_FNS_NONE 0 792255736Sdavidch#define CMNG_FNS_MINMAX 1 793255736Sdavidch 794255736Sdavidch/* CMNG constants, as derived from system spec calculations */ 795255736Sdavidch/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 796255736Sdavidch#define DEF_MIN_RATE 100 797255736Sdavidch/* resolution of the rate shaping timer - 400 usec */ 798255736Sdavidch#define RS_PERIODIC_TIMEOUT_USEC 400 799255736Sdavidch/* number of bytes in single QM arbitration cycle - 800255736Sdavidch * coefficient for calculating the fairness timer */ 801255736Sdavidch#define QM_ARB_BYTES 160000 802255736Sdavidch/* resolution of Min algorithm 1:100 */ 803255736Sdavidch#define MIN_RES 100 804255736Sdavidch/* how many bytes above threshold for the minimal credit of Min algorithm*/ 805255736Sdavidch#define MIN_ABOVE_THRESH 32768 806255736Sdavidch/* fairness algorithm integration time coefficient - 807255736Sdavidch * for calculating the actual Tfair */ 808255736Sdavidch#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 809255736Sdavidch/* memory of fairness algorithm - 2 cycles */ 810255736Sdavidch#define FAIR_MEM 2 811255736Sdavidch 812255736Sdavidch#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 813255736Sdavidch#define HC_SEG_ACCESS_ATTN 4 814255736Sdavidch#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 815255736Sdavidch 816255736Sdavidch/* 817255736Sdavidch * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 818255736Sdavidch * control by the number of fast-path status blocks supported by the 819255736Sdavidch * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 820255736Sdavidch * status block represents an independent interrupts context that can 821255736Sdavidch * serve a regular L2 networking queue. However special L2 queues such 822255736Sdavidch * as the FCoE queue do not require a FP-SB and other components like 823255736Sdavidch * the CNIC may consume FP-SB reducing the number of possible L2 queues 824255736Sdavidch * 825255736Sdavidch * If the maximum number of FP-SB available is X then: 826255736Sdavidch * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 827255736Sdavidch * regular L2 queues is Y=X-1 828255736Sdavidch * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 829255736Sdavidch * c. If the FCoE L2 queue is supported the actual number of L2 queues 830255736Sdavidch * is Y+1 831255736Sdavidch * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 832255736Sdavidch * slow-path interrupts) or Y+2 if CNIC is supported (one additional 833255736Sdavidch * FP interrupt context for the CNIC). 834255736Sdavidch * e. The number of HW context (CID count) is always X or X+1 if FCoE 835255736Sdavidch * L2 queue is supported. the cid for the FCoE L2 queue is always X. 836255736Sdavidch * 837255736Sdavidch * So this is quite simple for now as no ULPs are supported yet. :-) 838255736Sdavidch */ 839255736Sdavidch#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 840255736Sdavidch#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 841255736Sdavidch#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 842255736Sdavidch#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 843255736Sdavidch 844255736Sdavidch#define FOR_EACH_QUEUE(sc, var) \ 845255736Sdavidch for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 846255736Sdavidch 847255736Sdavidch#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 848255736Sdavidch for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 849255736Sdavidch 850255736Sdavidch#define FOR_EACH_ETH_QUEUE(sc, var) \ 851255736Sdavidch for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 852255736Sdavidch 853255736Sdavidch#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 854255736Sdavidch for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 855255736Sdavidch 856255736Sdavidch#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 857255736Sdavidch for ((var) = 0; (var) < (sc)->max_cos; (var)++) 858255736Sdavidch 859255736Sdavidch#define FOR_EACH_CNIC_QUEUE(sc, var) \ 860255736Sdavidch for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 861255736Sdavidch (var) < BXE_NUM_QUEUES(sc); \ 862255736Sdavidch (var)++) 863255736Sdavidch 864255736Sdavidchenum { 865255736Sdavidch OOO_IDX_OFFSET, 866255736Sdavidch FCOE_IDX_OFFSET, 867255736Sdavidch FWD_IDX_OFFSET, 868255736Sdavidch}; 869255736Sdavidch 870255736Sdavidch#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 871255736Sdavidch#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 872255736Sdavidch#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 873255736Sdavidch#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 874255736Sdavidch#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 875255736Sdavidch#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 876255736Sdavidch 877255736Sdavidch#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 878255736Sdavidch#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 879255736Sdavidch#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 880255736Sdavidch#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 881255736Sdavidch#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 882255736Sdavidch 883255736Sdavidch#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 884255736Sdavidch#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 885255736Sdavidch#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 886255736Sdavidch#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 887255736Sdavidch#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 888255736Sdavidch#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 889255736Sdavidch 890255736Sdavidch#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 891255736Sdavidch#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 892255736Sdavidch#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 893255736Sdavidch#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 894255736Sdavidch#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 895255736Sdavidch#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 896255736Sdavidch#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 897255736Sdavidch 898255736Sdavidchenum { 899255736Sdavidch BXE_PORT_QUERY_IDX, 900255736Sdavidch BXE_PF_QUERY_IDX, 901255736Sdavidch BXE_FCOE_QUERY_IDX, 902255736Sdavidch BXE_FIRST_QUEUE_QUERY_IDX, 903255736Sdavidch}; 904255736Sdavidch 905255736Sdavidchstruct bxe_fw_stats_req { 906255736Sdavidch struct stats_query_header hdr; 907255736Sdavidch struct stats_query_entry query[FP_SB_MAX_E1x + 908255736Sdavidch BXE_FIRST_QUEUE_QUERY_IDX]; 909255736Sdavidch}; 910255736Sdavidch 911255736Sdavidchstruct bxe_fw_stats_data { 912255736Sdavidch struct stats_counter storm_counters; 913255736Sdavidch struct per_port_stats port; 914255736Sdavidch struct per_pf_stats pf; 915255736Sdavidch //struct fcoe_statistics_params fcoe; 916255736Sdavidch struct per_queue_stats queue_stats[1]; 917255736Sdavidch}; 918255736Sdavidch 919255736Sdavidch/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 920255736Sdavidch#define BXE_IGU_STAS_MSG_VF_CNT 64 921255736Sdavidch#define BXE_IGU_STAS_MSG_PF_CNT 4 922255736Sdavidch 923255736Sdavidch#define MAX_DMAE_C 8 924255736Sdavidch 925255736Sdavidch/* 926255736Sdavidch * For the main interface up/down code paths, a not-so-fine-grained CORE 927255736Sdavidch * mutex lock is used. Inside this code are various calls to kernel routines 928255736Sdavidch * that can cause a sleep to occur. Namely memory allocations and taskqueue 929255736Sdavidch * handling. If using an MTX lock we are *not* allowed to sleep but we can 930255736Sdavidch * with an SX lock. This define forces the CORE lock to use and SX lock. 931255736Sdavidch * Undefine this and an MTX lock will be used instead. Note that the IOCTL 932255736Sdavidch * path can cause problems since it's called by a non-sleepable thread. To 933255736Sdavidch * alleviate a potential sleep, any IOCTL processing that results in the 934255736Sdavidch * chip/interface being started/stopped/reinitialized, the actual work is 935255736Sdavidch * offloaded to a taskqueue. 936255736Sdavidch */ 937255736Sdavidch#define BXE_CORE_LOCK_SX 938255736Sdavidch 939255736Sdavidch/* 940255736Sdavidch * This is the slowpath data structure. It is mapped into non-paged memory 941255736Sdavidch * so that the hardware can access it's contents directly and must be page 942255736Sdavidch * aligned. 943255736Sdavidch */ 944255736Sdavidchstruct bxe_slowpath { 945255736Sdavidch 946255736Sdavidch /* used by the DMAE command executer */ 947296071Sdavidcs struct dmae_cmd dmae[MAX_DMAE_C]; 948255736Sdavidch 949255736Sdavidch /* statistics completion */ 950255736Sdavidch uint32_t stats_comp; 951255736Sdavidch 952255736Sdavidch /* firmware defined statistics blocks */ 953255736Sdavidch union mac_stats mac_stats; 954255736Sdavidch struct nig_stats nig_stats; 955255736Sdavidch struct host_port_stats port_stats; 956255736Sdavidch struct host_func_stats func_stats; 957255736Sdavidch //struct host_func_stats func_stats_base; 958255736Sdavidch 959255736Sdavidch /* DMAE completion value and data source/sink */ 960255736Sdavidch uint32_t wb_comp; 961255736Sdavidch uint32_t wb_data[4]; 962255736Sdavidch 963255736Sdavidch union { 964255736Sdavidch struct mac_configuration_cmd e1x; 965255736Sdavidch struct eth_classify_rules_ramrod_data e2; 966255736Sdavidch } mac_rdata; 967255736Sdavidch 968255736Sdavidch union { 969255736Sdavidch struct tstorm_eth_mac_filter_config e1x; 970255736Sdavidch struct eth_filter_rules_ramrod_data e2; 971255736Sdavidch } rx_mode_rdata; 972255736Sdavidch 973255736Sdavidch struct eth_rss_update_ramrod_data rss_rdata; 974255736Sdavidch 975255736Sdavidch union { 976255736Sdavidch struct mac_configuration_cmd e1; 977255736Sdavidch struct eth_multicast_rules_ramrod_data e2; 978255736Sdavidch } mcast_rdata; 979255736Sdavidch 980255736Sdavidch union { 981255736Sdavidch struct function_start_data func_start; 982255736Sdavidch struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 983255736Sdavidch } func_rdata; 984255736Sdavidch 985255736Sdavidch /* Queue State related ramrods */ 986255736Sdavidch union { 987255736Sdavidch struct client_init_ramrod_data init_data; 988255736Sdavidch struct client_update_ramrod_data update_data; 989255736Sdavidch } q_rdata; 990255736Sdavidch 991255736Sdavidch /* 992255736Sdavidch * AFEX ramrod can not be a part of func_rdata union because these 993255736Sdavidch * events might arrive in parallel to other events from func_rdata. 994255736Sdavidch * If they were defined in the same union the data can get corrupted. 995255736Sdavidch */ 996255736Sdavidch struct afex_vif_list_ramrod_data func_afex_rdata; 997255736Sdavidch 998255736Sdavidch union drv_info_to_mcp drv_info_to_mcp; 999255736Sdavidch}; /* struct bxe_slowpath */ 1000255736Sdavidch 1001255736Sdavidch/* 1002255736Sdavidch * Port specifc data structure. 1003255736Sdavidch */ 1004255736Sdavidchstruct bxe_port { 1005255736Sdavidch /* 1006255736Sdavidch * Port Management Function (for 57711E only). 1007255736Sdavidch * When this field is set the driver instance is 1008255736Sdavidch * responsible for managing port specifc 1009255736Sdavidch * configurations such as handling link attentions. 1010255736Sdavidch */ 1011255736Sdavidch uint32_t pmf; 1012255736Sdavidch 1013255736Sdavidch /* Ethernet maximum transmission unit. */ 1014255736Sdavidch uint16_t ether_mtu; 1015255736Sdavidch 1016255736Sdavidch uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1017255736Sdavidch 1018255736Sdavidch uint32_t ext_phy_config; 1019255736Sdavidch 1020255736Sdavidch /* Port feature config.*/ 1021255736Sdavidch uint32_t config; 1022255736Sdavidch 1023255736Sdavidch /* Defines the features supported by the PHY. */ 1024255736Sdavidch uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1025255736Sdavidch 1026255736Sdavidch /* Defines the features advertised by the PHY. */ 1027255736Sdavidch uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1028255736Sdavidch#define ADVERTISED_10baseT_Half (1 << 1) 1029255736Sdavidch#define ADVERTISED_10baseT_Full (1 << 2) 1030255736Sdavidch#define ADVERTISED_100baseT_Half (1 << 3) 1031255736Sdavidch#define ADVERTISED_100baseT_Full (1 << 4) 1032255736Sdavidch#define ADVERTISED_1000baseT_Half (1 << 5) 1033255736Sdavidch#define ADVERTISED_1000baseT_Full (1 << 6) 1034255736Sdavidch#define ADVERTISED_TP (1 << 7) 1035255736Sdavidch#define ADVERTISED_FIBRE (1 << 8) 1036255736Sdavidch#define ADVERTISED_Autoneg (1 << 9) 1037255736Sdavidch#define ADVERTISED_Asym_Pause (1 << 10) 1038255736Sdavidch#define ADVERTISED_Pause (1 << 11) 1039255736Sdavidch#define ADVERTISED_2500baseX_Full (1 << 15) 1040255736Sdavidch#define ADVERTISED_10000baseT_Full (1 << 16) 1041255736Sdavidch 1042255736Sdavidch uint32_t phy_addr; 1043255736Sdavidch 1044255736Sdavidch /* Used to synchronize phy accesses. */ 1045255736Sdavidch struct mtx phy_mtx; 1046255736Sdavidch char phy_mtx_name[32]; 1047255736Sdavidch 1048255736Sdavidch#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1049255736Sdavidch#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1050255736Sdavidch#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1051255736Sdavidch 1052255736Sdavidch /* 1053255736Sdavidch * MCP scratchpad address for port specific statistics. 1054255736Sdavidch * The device is responsible for writing statistcss 1055255736Sdavidch * back to the MCP for use with management firmware such 1056255736Sdavidch * as UMP/NC-SI. 1057255736Sdavidch */ 1058255736Sdavidch uint32_t port_stx; 1059255736Sdavidch 1060255736Sdavidch struct nig_stats old_nig_stats; 1061255736Sdavidch}; /* struct bxe_port */ 1062255736Sdavidch 1063255736Sdavidchstruct bxe_mf_info { 1064255736Sdavidch uint32_t mf_config[E1HVN_MAX]; 1065255736Sdavidch 1066255736Sdavidch uint32_t vnics_per_port; /* 1, 2 or 4 */ 1067255736Sdavidch uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1068255736Sdavidch uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1069255736Sdavidch 1070255736Sdavidch#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1071255736Sdavidch#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1072255736Sdavidch#define VNICS_PER_PATH(sc) \ 1073255736Sdavidch ((sc)->devinfo.mf_info.vnics_per_port * \ 1074255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1075255736Sdavidch 1076255736Sdavidch uint8_t min_bw[MAX_VNIC_NUM]; 1077255736Sdavidch uint8_t max_bw[MAX_VNIC_NUM]; 1078255736Sdavidch 1079255736Sdavidch uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1080255736Sdavidch#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1081255736Sdavidch#define INVALID_VIF_ID 0xFFFF 1082255736Sdavidch#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1083255736Sdavidch#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1084255736Sdavidch 1085255736Sdavidch uint16_t default_vlan; 1086255736Sdavidch#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1087255736Sdavidch 1088255736Sdavidch uint8_t niv_allowed_priorities; 1089255736Sdavidch#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1090255736Sdavidch 1091255736Sdavidch uint8_t niv_default_cos; 1092255736Sdavidch#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1093255736Sdavidch 1094255736Sdavidch uint8_t niv_mba_enabled; 1095255736Sdavidch 1096255736Sdavidch enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1097255736Sdavidch#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1098255736Sdavidch int afex_def_vlan_tag; 1099255736Sdavidch uint32_t pending_max; 1100255736Sdavidch 1101255736Sdavidch uint16_t flags; 1102255736Sdavidch#define MF_INFO_VALID_MAC 0x0001 1103255736Sdavidch 1104255736Sdavidch uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1105255736Sdavidch#define IS_MF(sc) \ 1106255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1107255736Sdavidch ((sc)->devinfo.mf_info.mf_mode != 0)) 1108255736Sdavidch#define IS_MF_SD(sc) \ 1109255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1110255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1111255736Sdavidch#define IS_MF_SI(sc) \ 1112255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1113255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1114255736Sdavidch#define IS_MF_AFEX(sc) \ 1115255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1116255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1117255736Sdavidch#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1118255736Sdavidch#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1119255736Sdavidch#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1120255736Sdavidch 1121255736Sdavidch uint32_t mf_protos_supported; 1122255736Sdavidch #define MF_PROTO_SUPPORT_ETHERNET 0x1 1123255736Sdavidch #define MF_PROTO_SUPPORT_ISCSI 0x2 1124255736Sdavidch #define MF_PROTO_SUPPORT_FCOE 0x4 1125255736Sdavidch}; /* struct bxe_mf_info */ 1126255736Sdavidch 1127255736Sdavidch/* Device information data structure. */ 1128255736Sdavidchstruct bxe_devinfo { 1129255736Sdavidch /* PCIe info */ 1130255736Sdavidch uint16_t vendor_id; 1131255736Sdavidch uint16_t device_id; 1132255736Sdavidch uint16_t subvendor_id; 1133255736Sdavidch uint16_t subdevice_id; 1134255736Sdavidch 1135255736Sdavidch /* 1136255736Sdavidch * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1137255736Sdavidch * C = Chip Number (bits 16-31) 1138255736Sdavidch * R = Chip Revision (bits 12-15) 1139255736Sdavidch * M = Chip Metal (bits 4-11) 1140255736Sdavidch * B = Chip Bond ID (bits 0-3) 1141255736Sdavidch */ 1142255736Sdavidch uint32_t chip_id; 1143255736Sdavidch#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1144255736Sdavidch#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1145255736Sdavidch/* device ids */ 1146255736Sdavidch#define CHIP_NUM_57710 0x164e 1147255736Sdavidch#define CHIP_NUM_57711 0x164f 1148255736Sdavidch#define CHIP_NUM_57711E 0x1650 1149255736Sdavidch#define CHIP_NUM_57712 0x1662 1150255736Sdavidch#define CHIP_NUM_57712_MF 0x1663 1151255736Sdavidch#define CHIP_NUM_57712_VF 0x166f 1152255736Sdavidch#define CHIP_NUM_57800 0x168a 1153255736Sdavidch#define CHIP_NUM_57800_MF 0x16a5 1154255736Sdavidch#define CHIP_NUM_57800_VF 0x16a9 1155255736Sdavidch#define CHIP_NUM_57810 0x168e 1156255736Sdavidch#define CHIP_NUM_57810_MF 0x16ae 1157255736Sdavidch#define CHIP_NUM_57810_VF 0x16af 1158255736Sdavidch#define CHIP_NUM_57811 0x163d 1159255736Sdavidch#define CHIP_NUM_57811_MF 0x163e 1160255736Sdavidch#define CHIP_NUM_57811_VF 0x163f 1161255736Sdavidch#define CHIP_NUM_57840_OBS 0x168d 1162255736Sdavidch#define CHIP_NUM_57840_OBS_MF 0x16ab 1163255736Sdavidch#define CHIP_NUM_57840_4_10 0x16a1 1164255736Sdavidch#define CHIP_NUM_57840_2_20 0x16a2 1165255736Sdavidch#define CHIP_NUM_57840_MF 0x16a4 1166255736Sdavidch#define CHIP_NUM_57840_VF 0x16ad 1167255736Sdavidch 1168255736Sdavidch#define CHIP_REV_SHIFT 12 1169255736Sdavidch#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1170255736Sdavidch#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1171255736Sdavidch 1172255736Sdavidch#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1173255736Sdavidch#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1174255736Sdavidch#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1175255736Sdavidch 1176255736Sdavidch#define CHIP_REV_IS_SLOW(sc) \ 1177255736Sdavidch (CHIP_REV(sc) > 0x00005000) 1178255736Sdavidch#define CHIP_REV_IS_FPGA(sc) \ 1179255736Sdavidch (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1180255736Sdavidch#define CHIP_REV_IS_EMUL(sc) \ 1181255736Sdavidch (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1182255736Sdavidch#define CHIP_REV_IS_ASIC(sc) \ 1183255736Sdavidch (!CHIP_REV_IS_SLOW(sc)) 1184255736Sdavidch 1185255736Sdavidch#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1186255736Sdavidch#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1187255736Sdavidch 1188255736Sdavidch#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1189255736Sdavidch#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1190255736Sdavidch#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1191255736Sdavidch#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1192255736Sdavidch#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1193255736Sdavidch (CHIP_IS_57711E(sc))) 1194255736Sdavidch#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1195255736Sdavidch CHIP_IS_E1H((sc))) 1196255736Sdavidch 1197255736Sdavidch#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1198255736Sdavidch#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1199255736Sdavidch#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1200255736Sdavidch#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1201255736Sdavidch CHIP_IS_57712_MF(sc)) 1202255736Sdavidch 1203255736Sdavidch#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1204255736Sdavidch#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1205255736Sdavidch#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1206255736Sdavidch#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1207255736Sdavidch#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1208255736Sdavidch#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1209255736Sdavidch#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1210255736Sdavidch#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1211255736Sdavidch#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1212255736Sdavidch#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1213255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1214255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1215255736Sdavidch#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1216255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1217255736Sdavidch#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1218255736Sdavidch 1219255736Sdavidch#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1220255736Sdavidch CHIP_IS_57800_MF(sc) || \ 1221255736Sdavidch CHIP_IS_57800_VF(sc) || \ 1222255736Sdavidch CHIP_IS_57810(sc) || \ 1223255736Sdavidch CHIP_IS_57810_MF(sc) || \ 1224255736Sdavidch CHIP_IS_57810_VF(sc) || \ 1225255736Sdavidch CHIP_IS_57811(sc) || \ 1226255736Sdavidch CHIP_IS_57811_MF(sc) || \ 1227255736Sdavidch CHIP_IS_57811_VF(sc) || \ 1228255736Sdavidch CHIP_IS_57840(sc) || \ 1229255736Sdavidch CHIP_IS_57840_MF(sc) || \ 1230255736Sdavidch CHIP_IS_57840_VF(sc)) 1231255736Sdavidch#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1232255736Sdavidch (CHIP_REV(sc) == CHIP_REV_Ax)) 1233255736Sdavidch#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1234255736Sdavidch (CHIP_REV(sc) == CHIP_REV_Bx)) 1235255736Sdavidch 1236255736Sdavidch#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1237255736Sdavidch#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1238255736Sdavidch CHIP_IS_E3(sc)) 1239255736Sdavidch 1240255736Sdavidch#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1241255736Sdavidch CHIP_IS_57712_MF(sc) || \ 1242255736Sdavidch CHIP_IS_E3(sc)) 1243255736Sdavidch 1244255736Sdavidch#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1245255736Sdavidch CHIP_IS_57800_VF(sc) || \ 1246255736Sdavidch CHIP_IS_57810_VF(sc) || \ 1247255736Sdavidch CHIP_IS_57840_VF(sc)) 1248255736Sdavidch#define IS_PF(sc) (!IS_VF(sc)) 1249255736Sdavidch 1250255736Sdavidch/* 1251255736Sdavidch * This define is used in two main places: 1252255736Sdavidch * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1253255736Sdavidch * to nic-only mode or to offload mode. Offload mode is configured if either 1254255736Sdavidch * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1255255736Sdavidch * already registered for this port (which means that the user wants storage 1256255736Sdavidch * services). 1257255736Sdavidch * 2. During cnic-related load, to know if offload mode is already configured 1258255736Sdavidch * in the HW or needs to be configrued. Since the transition from nic-mode to 1259255736Sdavidch * offload-mode in HW causes traffic coruption, nic-mode is configured only 1260255736Sdavidch * in ports on which storage services where never requested. 1261255736Sdavidch */ 1262255736Sdavidch#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1263255736Sdavidch 1264255736Sdavidch uint8_t chip_port_mode; 1265255736Sdavidch#define CHIP_4_PORT_MODE 0x0 1266255736Sdavidch#define CHIP_2_PORT_MODE 0x1 1267255736Sdavidch#define CHIP_PORT_MODE_NONE 0x2 1268255736Sdavidch#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1269255736Sdavidch#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1270255736Sdavidch 1271255736Sdavidch uint8_t int_block; 1272255736Sdavidch#define INT_BLOCK_HC 0 1273255736Sdavidch#define INT_BLOCK_IGU 1 1274255736Sdavidch#define INT_BLOCK_MODE_NORMAL 0 1275255736Sdavidch#define INT_BLOCK_MODE_BW_COMP 2 1276255736Sdavidch#define CHIP_INT_MODE_IS_NBC(sc) \ 1277255736Sdavidch (!CHIP_IS_E1x(sc) && \ 1278255736Sdavidch !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1279255736Sdavidch#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1280255736Sdavidch 1281255736Sdavidch uint32_t shmem_base; 1282255736Sdavidch uint32_t shmem2_base; 1283255736Sdavidch uint32_t bc_ver; 1284255736Sdavidch char bc_ver_str[32]; 1285255736Sdavidch uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1286255736Sdavidch struct bxe_mf_info mf_info; 1287255736Sdavidch 1288255736Sdavidch int flash_size; 1289255736Sdavidch#define NVRAM_1MB_SIZE 0x20000 1290255736Sdavidch#define NVRAM_TIMEOUT_COUNT 30000 1291255736Sdavidch#define NVRAM_PAGE_SIZE 256 1292255736Sdavidch 1293255736Sdavidch /* PCIe capability information */ 1294255736Sdavidch uint32_t pcie_cap_flags; 1295255736Sdavidch#define BXE_PM_CAPABLE_FLAG 0x00000001 1296255736Sdavidch#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1297255736Sdavidch#define BXE_MSI_CAPABLE_FLAG 0x00000004 1298255736Sdavidch#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1299255736Sdavidch uint16_t pcie_pm_cap_reg; 1300255736Sdavidch uint16_t pcie_pcie_cap_reg; 1301255736Sdavidch //uint16_t pcie_devctl; 1302255736Sdavidch uint16_t pcie_link_width; 1303255736Sdavidch uint16_t pcie_link_speed; 1304255736Sdavidch uint16_t pcie_msi_cap_reg; 1305255736Sdavidch uint16_t pcie_msix_cap_reg; 1306255736Sdavidch 1307255736Sdavidch /* device configuration read from bootcode shared memory */ 1308255736Sdavidch uint32_t hw_config; 1309255736Sdavidch uint32_t hw_config2; 1310255736Sdavidch}; /* struct bxe_devinfo */ 1311255736Sdavidch 1312255736Sdavidchstruct bxe_sp_objs { 1313255736Sdavidch struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1314255736Sdavidch struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1315255736Sdavidch}; /* struct bxe_sp_objs */ 1316255736Sdavidch 1317255736Sdavidch/* 1318255736Sdavidch * Data that will be used to create a link report message. We will keep the 1319255736Sdavidch * data used for the last link report in order to prevent reporting the same 1320255736Sdavidch * link parameters twice. 1321255736Sdavidch */ 1322255736Sdavidchstruct bxe_link_report_data { 1323255736Sdavidch uint16_t line_speed; /* Effective line speed */ 1324255736Sdavidch unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1325255736Sdavidch}; 1326255736Sdavidchenum { 1327255736Sdavidch BXE_LINK_REPORT_FULL_DUPLEX, 1328255736Sdavidch BXE_LINK_REPORT_LINK_DOWN, 1329255736Sdavidch BXE_LINK_REPORT_RX_FC_ON, 1330255736Sdavidch BXE_LINK_REPORT_TX_FC_ON 1331255736Sdavidch}; 1332255736Sdavidch 1333255736Sdavidch/* Top level device private data structure. */ 1334255736Sdavidchstruct bxe_softc { 1335255736Sdavidch /* 1336255736Sdavidch * First entry must be a pointer to the BSD ifnet struct which 1337266979Smarcel * has a first element of 'void *if_softc' (which is us). XXX 1338255736Sdavidch */ 1339266979Smarcel if_t ifp; 1340255736Sdavidch struct ifmedia ifmedia; /* network interface media structure */ 1341255736Sdavidch int media; 1342255736Sdavidch 1343315881Sdavidcs volatile int state; /* device state */ 1344255736Sdavidch#define BXE_STATE_CLOSED 0x0000 1345255736Sdavidch#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1346255736Sdavidch#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1347255736Sdavidch#define BXE_STATE_OPEN 0x3000 1348255736Sdavidch#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1349255736Sdavidch#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1350255736Sdavidch#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1351255736Sdavidch#define BXE_STATE_DISABLED 0xD000 1352255736Sdavidch#define BXE_STATE_DIAG 0xE000 1353255736Sdavidch#define BXE_STATE_ERROR 0xF000 1354255736Sdavidch 1355255736Sdavidch int flags; 1356255736Sdavidch#define BXE_ONE_PORT_FLAG 0x00000001 1357255736Sdavidch#define BXE_NO_ISCSI 0x00000002 1358255736Sdavidch#define BXE_NO_FCOE 0x00000004 1359255736Sdavidch#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1360255736Sdavidch//#define BXE_NO_WOL_FLAG 0x00000008 1361255736Sdavidch//#define BXE_USING_DAC_FLAG 0x00000010 1362255736Sdavidch//#define BXE_USING_MSIX_FLAG 0x00000020 1363255736Sdavidch//#define BXE_USING_MSI_FLAG 0x00000040 1364255736Sdavidch//#define BXE_DISABLE_MSI_FLAG 0x00000080 1365255736Sdavidch#define BXE_NO_MCP_FLAG 0x00000200 1366255736Sdavidch#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1367255736Sdavidch//#define BXE_SAFC_TX_FLAG 0x00000400 1368255736Sdavidch#define BXE_MF_FUNC_DIS 0x00000800 1369255736Sdavidch#define BXE_TX_SWITCHING 0x00001000 1370284335Sdavidcs#define BXE_NO_PULSE 0x00002000 1371255736Sdavidch 1372258187Sedavis unsigned long debug; /* per-instance debug logging config */ 1373255736Sdavidch 1374255736Sdavidch#define MAX_BARS 5 1375255736Sdavidch struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1376255736Sdavidch 1377255736Sdavidch uint16_t doorbell_size; 1378255736Sdavidch 1379255736Sdavidch /* periodic timer callout */ 1380255736Sdavidch#define PERIODIC_STOP 0 1381255736Sdavidch#define PERIODIC_GO 1 1382255736Sdavidch volatile unsigned long periodic_flags; 1383255736Sdavidch struct callout periodic_callout; 1384255736Sdavidch 1385255736Sdavidch /* chip start/stop/reset taskqueue */ 1386255736Sdavidch#define CHIP_TQ_NONE 0 1387255736Sdavidch#define CHIP_TQ_START 1 1388255736Sdavidch#define CHIP_TQ_STOP 2 1389255736Sdavidch#define CHIP_TQ_REINIT 3 1390255736Sdavidch volatile unsigned long chip_tq_flags; 1391255736Sdavidch struct task chip_tq_task; 1392255736Sdavidch struct taskqueue *chip_tq; 1393255736Sdavidch char chip_tq_name[32]; 1394255736Sdavidch 1395339881Sdavidcs struct timeout_task sp_err_timeout_task; 1396339881Sdavidcs 1397255736Sdavidch /* slowpath interrupt taskqueue */ 1398255736Sdavidch struct task sp_tq_task; 1399255736Sdavidch struct taskqueue *sp_tq; 1400255736Sdavidch char sp_tq_name[32]; 1401255736Sdavidch 1402255736Sdavidch struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1403255736Sdavidch struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1404255736Sdavidch 1405255736Sdavidch device_t dev; /* parent device handle */ 1406255736Sdavidch uint8_t unit; /* driver instance number */ 1407255736Sdavidch 1408255736Sdavidch int pcie_bus; /* PCIe bus number */ 1409255736Sdavidch int pcie_device; /* PCIe device/slot number */ 1410255736Sdavidch int pcie_func; /* PCIe function number */ 1411255736Sdavidch 1412255736Sdavidch uint8_t pfunc_rel; /* function relative */ 1413255736Sdavidch uint8_t pfunc_abs; /* function absolute */ 1414255736Sdavidch uint8_t path_id; /* function absolute */ 1415255736Sdavidch#define SC_PATH(sc) (sc->path_id) 1416255736Sdavidch#define SC_PORT(sc) (sc->pfunc_rel & 1) 1417255736Sdavidch#define SC_FUNC(sc) (sc->pfunc_rel) 1418255736Sdavidch#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1419255736Sdavidch#define SC_VN(sc) (sc->pfunc_rel >> 1) 1420255736Sdavidch#define SC_L_ID(sc) (SC_VN(sc) << 2) 1421255736Sdavidch#define PORT_ID(sc) SC_PORT(sc) 1422255736Sdavidch#define PATH_ID(sc) SC_PATH(sc) 1423255736Sdavidch#define VNIC_ID(sc) SC_VN(sc) 1424255736Sdavidch#define FUNC_ID(sc) SC_FUNC(sc) 1425255736Sdavidch#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1426255736Sdavidch#define SC_FW_MB_IDX_VN(sc, vn) \ 1427255736Sdavidch (SC_PORT(sc) + (vn) * \ 1428255736Sdavidch ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1429255736Sdavidch#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1430255736Sdavidch 1431255736Sdavidch int if_capen; /* enabled interface capabilities */ 1432255736Sdavidch 1433255736Sdavidch struct bxe_devinfo devinfo; 1434255736Sdavidch char fw_ver_str[32]; 1435255736Sdavidch char mf_mode_str[32]; 1436255736Sdavidch char pci_link_str[32]; 1437255736Sdavidch 1438255736Sdavidch const struct iro *iro_array; 1439255736Sdavidch 1440255736Sdavidch#ifdef BXE_CORE_LOCK_SX 1441255736Sdavidch struct sx core_sx; 1442255736Sdavidch char core_sx_name[32]; 1443255736Sdavidch#else 1444255736Sdavidch struct mtx core_mtx; 1445255736Sdavidch char core_mtx_name[32]; 1446255736Sdavidch#endif 1447255736Sdavidch struct mtx sp_mtx; 1448255736Sdavidch char sp_mtx_name[32]; 1449255736Sdavidch struct mtx dmae_mtx; 1450255736Sdavidch char dmae_mtx_name[32]; 1451255736Sdavidch struct mtx fwmb_mtx; 1452255736Sdavidch char fwmb_mtx_name[32]; 1453255736Sdavidch struct mtx print_mtx; 1454255736Sdavidch char print_mtx_name[32]; 1455255736Sdavidch struct mtx stats_mtx; 1456255736Sdavidch char stats_mtx_name[32]; 1457255736Sdavidch struct mtx mcast_mtx; 1458255736Sdavidch char mcast_mtx_name[32]; 1459255736Sdavidch 1460255736Sdavidch#ifdef BXE_CORE_LOCK_SX 1461255736Sdavidch#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1462255736Sdavidch#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1463255736Sdavidch#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1464255736Sdavidch#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1465255736Sdavidch#else 1466255736Sdavidch#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1467255736Sdavidch#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1468255736Sdavidch#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1469255736Sdavidch#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1470255736Sdavidch#endif 1471255736Sdavidch 1472255736Sdavidch#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1473255736Sdavidch#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1474255736Sdavidch#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1475255736Sdavidch 1476255736Sdavidch#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1477255736Sdavidch#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1478255736Sdavidch#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1479255736Sdavidch 1480255736Sdavidch#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1481255736Sdavidch#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1482255736Sdavidch#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1483255736Sdavidch 1484255736Sdavidch#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1485255736Sdavidch#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1486255736Sdavidch#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1487255736Sdavidch 1488255736Sdavidch#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1489255736Sdavidch#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1490255736Sdavidch#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1491255736Sdavidch 1492255736Sdavidch#if __FreeBSD_version < 800000 1493255736Sdavidch#define BXE_MCAST_LOCK(sc) \ 1494255736Sdavidch do { \ 1495255736Sdavidch mtx_lock(&sc->mcast_mtx); \ 1496266979Smarcel IF_ADDR_LOCK(sc->ifp); \ 1497255736Sdavidch } while (0) 1498255736Sdavidch#define BXE_MCAST_UNLOCK(sc) \ 1499255736Sdavidch do { \ 1500266979Smarcel IF_ADDR_UNLOCK(sc->ifp); \ 1501255736Sdavidch mtx_unlock(&sc->mcast_mtx); \ 1502255736Sdavidch } while (0) 1503255736Sdavidch#else 1504255736Sdavidch#define BXE_MCAST_LOCK(sc) \ 1505255736Sdavidch do { \ 1506255736Sdavidch mtx_lock(&sc->mcast_mtx); \ 1507266979Smarcel if_maddr_rlock(sc->ifp); \ 1508255736Sdavidch } while (0) 1509255736Sdavidch#define BXE_MCAST_UNLOCK(sc) \ 1510255736Sdavidch do { \ 1511266979Smarcel if_maddr_runlock(sc->ifp); \ 1512255736Sdavidch mtx_unlock(&sc->mcast_mtx); \ 1513255736Sdavidch } while (0) 1514255736Sdavidch#endif 1515255736Sdavidch#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1516255736Sdavidch 1517255736Sdavidch int dmae_ready; 1518255736Sdavidch#define DMAE_READY(sc) (sc->dmae_ready) 1519255736Sdavidch 1520255736Sdavidch struct ecore_credit_pool_obj vlans_pool; 1521255736Sdavidch struct ecore_credit_pool_obj macs_pool; 1522255736Sdavidch struct ecore_rx_mode_obj rx_mode_obj; 1523255736Sdavidch struct ecore_mcast_obj mcast_obj; 1524255736Sdavidch struct ecore_rss_config_obj rss_conf_obj; 1525255736Sdavidch struct ecore_func_sp_obj func_obj; 1526255736Sdavidch 1527255736Sdavidch uint16_t fw_seq; 1528255736Sdavidch uint16_t fw_drv_pulse_wr_seq; 1529255736Sdavidch uint32_t func_stx; 1530255736Sdavidch 1531255736Sdavidch struct elink_params link_params; 1532255736Sdavidch struct elink_vars link_vars; 1533255736Sdavidch uint32_t link_cnt; 1534255736Sdavidch struct bxe_link_report_data last_reported_link; 1535255736Sdavidch char mac_addr_str[32]; 1536255736Sdavidch 1537255736Sdavidch int last_reported_link_state; 1538255736Sdavidch 1539255736Sdavidch int tx_ring_size; 1540255736Sdavidch int rx_ring_size; 1541255736Sdavidch int wol; 1542255736Sdavidch 1543255736Sdavidch int is_leader; 1544255736Sdavidch int recovery_state; 1545255736Sdavidch#define BXE_RECOVERY_DONE 1 1546255736Sdavidch#define BXE_RECOVERY_INIT 2 1547255736Sdavidch#define BXE_RECOVERY_WAIT 3 1548255736Sdavidch#define BXE_RECOVERY_FAILED 4 1549255736Sdavidch#define BXE_RECOVERY_NIC_LOADING 5 1550255736Sdavidch 1551339881Sdavidcs#define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1552339881Sdavidcs#define BXE_ERR_MISC 0x2 /* MISC ERR */ 1553339881Sdavidcs#define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1554339881Sdavidcs#define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1555339881Sdavidcs#define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1556339881Sdavidcs#define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1557339881Sdavidcs#define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1558339881Sdavidcs#define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1559339881Sdavidcs uint32_t error_status; 1560339881Sdavidcs 1561255736Sdavidch uint32_t rx_mode; 1562255736Sdavidch#define BXE_RX_MODE_NONE 0 1563255736Sdavidch#define BXE_RX_MODE_NORMAL 1 1564255736Sdavidch#define BXE_RX_MODE_ALLMULTI 2 1565255736Sdavidch#define BXE_RX_MODE_PROMISC 3 1566255736Sdavidch#define BXE_MAX_MULTICAST 64 1567255736Sdavidch 1568255736Sdavidch struct bxe_port port; 1569255736Sdavidch 1570255736Sdavidch struct cmng_init cmng; 1571255736Sdavidch 1572255736Sdavidch /* user configs */ 1573255736Sdavidch int num_queues; 1574255736Sdavidch int max_rx_bufs; 1575255736Sdavidch int hc_rx_ticks; 1576255736Sdavidch int hc_tx_ticks; 1577258187Sedavis int rx_budget; 1578255736Sdavidch int max_aggregation_size; 1579255736Sdavidch int mrrs; 1580255736Sdavidch int autogreeen; 1581255736Sdavidch#define AUTO_GREEN_HW_DEFAULT 0 1582255736Sdavidch#define AUTO_GREEN_FORCE_ON 1 1583255736Sdavidch#define AUTO_GREEN_FORCE_OFF 2 1584255736Sdavidch int interrupt_mode; 1585255736Sdavidch#define INTR_MODE_INTX 0 1586255736Sdavidch#define INTR_MODE_MSI 1 1587255736Sdavidch#define INTR_MODE_MSIX 2 1588255736Sdavidch int udp_rss; 1589255736Sdavidch 1590255736Sdavidch /* interrupt allocations */ 1591255736Sdavidch struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1592255736Sdavidch int intr_count; 1593255736Sdavidch uint8_t igu_dsb_id; 1594255736Sdavidch uint8_t igu_base_sb; 1595255736Sdavidch uint8_t igu_sb_cnt; 1596255736Sdavidch //uint8_t min_msix_vec_cnt; 1597255736Sdavidch uint32_t igu_base_addr; 1598255736Sdavidch //bus_addr_t def_status_blk_mapping; 1599255736Sdavidch uint8_t base_fw_ndsb; 1600255736Sdavidch#define DEF_SB_IGU_ID 16 1601255736Sdavidch#define DEF_SB_ID HC_SP_SB_ID 1602255736Sdavidch 1603255736Sdavidch /* parent bus DMA tag */ 1604255736Sdavidch bus_dma_tag_t parent_dma_tag; 1605255736Sdavidch 1606255736Sdavidch /* default status block */ 1607255736Sdavidch struct bxe_dma def_sb_dma; 1608255736Sdavidch struct host_sp_status_block *def_sb; 1609255736Sdavidch uint16_t def_idx; 1610255736Sdavidch uint16_t def_att_idx; 1611255736Sdavidch uint32_t attn_state; 1612255736Sdavidch struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1613255736Sdavidch 1614255736Sdavidch/* general SP events - stats query, cfc delete, etc */ 1615255736Sdavidch#define HC_SP_INDEX_ETH_DEF_CONS 3 1616255736Sdavidch/* EQ completions */ 1617255736Sdavidch#define HC_SP_INDEX_EQ_CONS 7 1618255736Sdavidch/* FCoE L2 connection completions */ 1619255736Sdavidch#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1620255736Sdavidch#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1621255736Sdavidch/* iSCSI L2 */ 1622255736Sdavidch#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1623255736Sdavidch#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1624255736Sdavidch 1625255736Sdavidch /* event queue */ 1626255736Sdavidch struct bxe_dma eq_dma; 1627255736Sdavidch union event_ring_elem *eq; 1628255736Sdavidch uint16_t eq_prod; 1629255736Sdavidch uint16_t eq_cons; 1630255736Sdavidch uint16_t *eq_cons_sb; 1631255736Sdavidch#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1632255736Sdavidch#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1633255736Sdavidch#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1634255736Sdavidch#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1635255736Sdavidch#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1636255736Sdavidch#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1637255736Sdavidch/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1638255736Sdavidch#define NEXT_EQ_IDX(x) \ 1639255736Sdavidch ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1640255736Sdavidch ((x) + 2) : ((x) + 1)) 1641255736Sdavidch/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1642255736Sdavidch#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1643255736Sdavidch 1644255736Sdavidch /* slow path */ 1645255736Sdavidch struct bxe_dma sp_dma; 1646255736Sdavidch struct bxe_slowpath *sp; 1647255736Sdavidch unsigned long sp_state; 1648255736Sdavidch 1649255736Sdavidch /* slow path queue */ 1650255736Sdavidch struct bxe_dma spq_dma; 1651255736Sdavidch struct eth_spe *spq; 1652255736Sdavidch#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1653255736Sdavidch#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1654255736Sdavidch#define MAX_SPQ_PENDING 8 1655255736Sdavidch 1656255736Sdavidch uint16_t spq_prod_idx; 1657255736Sdavidch struct eth_spe *spq_prod_bd; 1658255736Sdavidch struct eth_spe *spq_last_bd; 1659255736Sdavidch uint16_t *dsb_sp_prod; 1660255736Sdavidch //uint16_t *spq_hw_con; 1661255736Sdavidch //uint16_t spq_left; 1662255736Sdavidch 1663255736Sdavidch volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1664255736Sdavidch volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1665255736Sdavidch 1666255736Sdavidch /* fw decompression buffer */ 1667255736Sdavidch struct bxe_dma gz_buf_dma; 1668255736Sdavidch void *gz_buf; 1669255736Sdavidch z_streamp gz_strm; 1670255736Sdavidch uint32_t gz_outlen; 1671255736Sdavidch#define GUNZIP_BUF(sc) (sc->gz_buf) 1672255736Sdavidch#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1673255736Sdavidch#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1674255736Sdavidch#define FW_BUF_SIZE 0x40000 1675255736Sdavidch 1676255736Sdavidch const struct raw_op *init_ops; 1677255736Sdavidch const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1678255736Sdavidch const uint32_t *init_data; /* data blob, 32 bit granularity */ 1679255736Sdavidch uint32_t init_mode_flags; 1680255736Sdavidch#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1681255736Sdavidch /* PRAM blobs - raw data */ 1682255736Sdavidch const uint8_t *tsem_int_table_data; 1683255736Sdavidch const uint8_t *tsem_pram_data; 1684255736Sdavidch const uint8_t *usem_int_table_data; 1685255736Sdavidch const uint8_t *usem_pram_data; 1686255736Sdavidch const uint8_t *xsem_int_table_data; 1687255736Sdavidch const uint8_t *xsem_pram_data; 1688255736Sdavidch const uint8_t *csem_int_table_data; 1689255736Sdavidch const uint8_t *csem_pram_data; 1690255736Sdavidch#define INIT_OPS(sc) (sc->init_ops) 1691255736Sdavidch#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1692255736Sdavidch#define INIT_DATA(sc) (sc->init_data) 1693255736Sdavidch#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1694255736Sdavidch#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1695255736Sdavidch#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1696255736Sdavidch#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1697255736Sdavidch#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1698255736Sdavidch#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1699255736Sdavidch#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1700255736Sdavidch#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1701255736Sdavidch 1702255736Sdavidch /* ILT 1703255736Sdavidch * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1704255736Sdavidch * context size we need 8 ILT entries. 1705255736Sdavidch */ 1706255736Sdavidch#define ILT_MAX_L2_LINES 8 1707255736Sdavidch struct hw_context context[ILT_MAX_L2_LINES]; 1708255736Sdavidch struct ecore_ilt *ilt; 1709255736Sdavidch#define ILT_MAX_LINES 256 1710255736Sdavidch 1711255736Sdavidch/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1712255736Sdavidch#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1713255736Sdavidch/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1714255736Sdavidch#if 1 1715255736Sdavidch#define BXE_L2_MAX_CID(sc) \ 1716255736Sdavidch (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1717255736Sdavidch#else 1718255736Sdavidch#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1719255736Sdavidch (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1720255736Sdavidch#endif 1721255736Sdavidch#if 1 1722255736Sdavidch#define BXE_L2_CID_COUNT(sc) \ 1723255736Sdavidch (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1724255736Sdavidch#else 1725255736Sdavidch#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1726255736Sdavidch (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1727255736Sdavidch#endif 1728255736Sdavidch#define L2_ILT_LINES(sc) \ 1729255736Sdavidch (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1730255736Sdavidch 1731255736Sdavidch int qm_cid_count; 1732255736Sdavidch 1733255736Sdavidch uint8_t dropless_fc; 1734255736Sdavidch 1735255736Sdavidch /* total number of FW statistics requests */ 1736255736Sdavidch uint8_t fw_stats_num; 1737255736Sdavidch /* 1738255736Sdavidch * This is a memory buffer that will contain both statistics ramrod 1739255736Sdavidch * request and data. 1740255736Sdavidch */ 1741255736Sdavidch struct bxe_dma fw_stats_dma; 1742255736Sdavidch /* 1743255736Sdavidch * FW statistics request shortcut (points at the beginning of fw_stats 1744255736Sdavidch * buffer). 1745255736Sdavidch */ 1746255736Sdavidch int fw_stats_req_size; 1747255736Sdavidch struct bxe_fw_stats_req *fw_stats_req; 1748255736Sdavidch bus_addr_t fw_stats_req_mapping; 1749255736Sdavidch /* 1750255736Sdavidch * FW statistics data shortcut (points at the beginning of fw_stats 1751255736Sdavidch * buffer + fw_stats_req_size). 1752255736Sdavidch */ 1753255736Sdavidch int fw_stats_data_size; 1754255736Sdavidch struct bxe_fw_stats_data *fw_stats_data; 1755255736Sdavidch bus_addr_t fw_stats_data_mapping; 1756255736Sdavidch 1757255736Sdavidch /* tracking a pending STAT_QUERY ramrod */ 1758255736Sdavidch uint16_t stats_pending; 1759255736Sdavidch /* number of completed statistics ramrods */ 1760255736Sdavidch uint16_t stats_comp; 1761255736Sdavidch uint16_t stats_counter; 1762255736Sdavidch uint8_t stats_init; 1763255736Sdavidch int stats_state; 1764255736Sdavidch 1765255736Sdavidch struct bxe_eth_stats eth_stats; 1766255736Sdavidch struct host_func_stats func_stats; 1767255736Sdavidch struct bxe_eth_stats_old eth_stats_old; 1768255736Sdavidch struct bxe_net_stats_old net_stats_old; 1769255736Sdavidch struct bxe_fw_port_stats_old fw_stats_old; 1770255736Sdavidch 1771296071Sdavidcs struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1772255736Sdavidch int executer_idx; 1773255736Sdavidch 1774255736Sdavidch int mtu; 1775255736Sdavidch 1776255736Sdavidch /* LLDP params */ 1777255736Sdavidch struct bxe_config_lldp_params lldp_config_params; 1778255736Sdavidch /* DCB support on/off */ 1779255736Sdavidch int dcb_state; 1780255736Sdavidch#define BXE_DCB_STATE_OFF 0 1781255736Sdavidch#define BXE_DCB_STATE_ON 1 1782255736Sdavidch /* DCBX engine mode */ 1783255736Sdavidch int dcbx_enabled; 1784255736Sdavidch#define BXE_DCBX_ENABLED_OFF 0 1785255736Sdavidch#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1786255736Sdavidch#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1787255736Sdavidch#define BXE_DCBX_ENABLED_INVALID -1 1788255736Sdavidch uint8_t dcbx_mode_uset; 1789255736Sdavidch struct bxe_config_dcbx_params dcbx_config_params; 1790255736Sdavidch struct bxe_dcbx_port_params dcbx_port_params; 1791255736Sdavidch int dcb_version; 1792255736Sdavidch 1793255736Sdavidch uint8_t cnic_support; 1794255736Sdavidch uint8_t cnic_enabled; 1795255736Sdavidch uint8_t cnic_loaded; 1796255736Sdavidch#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1797255736Sdavidch#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1798255736Sdavidch#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1799255736Sdavidch 1800255736Sdavidch /* multiple tx classes of service */ 1801255736Sdavidch uint8_t max_cos; 1802255736Sdavidch#define BXE_MAX_PRIORITY 8 1803255736Sdavidch /* priority to cos mapping */ 1804255736Sdavidch uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1805255736Sdavidch 1806255736Sdavidch int panic; 1807292639Sdavidcs 1808292639Sdavidcs struct cdev *ioctl_dev; 1809298294Sdavidcs 1810292639Sdavidcs void *grc_dump; 1811298294Sdavidcs unsigned int trigger_grcdump; 1812298294Sdavidcs unsigned int grcdump_done; 1813298294Sdavidcs unsigned int grcdump_started; 1814315881Sdavidcs int bxe_pause_param; 1815297884Sdavidcs void *eeprom; 1816255736Sdavidch}; /* struct bxe_softc */ 1817255736Sdavidch 1818255736Sdavidch/* IOCTL sub-commands for edebug and firmware upgrade */ 1819255736Sdavidch#define BXE_IOC_RD_NVRAM 1 1820255736Sdavidch#define BXE_IOC_WR_NVRAM 2 1821255736Sdavidch#define BXE_IOC_STATS_SHOW_NUM 3 1822255736Sdavidch#define BXE_IOC_STATS_SHOW_STR 4 1823255736Sdavidch#define BXE_IOC_STATS_SHOW_CNT 5 1824255736Sdavidch 1825255736Sdavidchstruct bxe_nvram_data { 1826255736Sdavidch uint32_t op; /* ioctl sub-command */ 1827255736Sdavidch uint32_t offset; 1828255736Sdavidch uint32_t len; 1829255736Sdavidch uint32_t value[1]; /* variable */ 1830255736Sdavidch}; 1831255736Sdavidch 1832255736Sdavidchunion bxe_stats_show_data { 1833255736Sdavidch uint32_t op; /* ioctl sub-command */ 1834255736Sdavidch 1835255736Sdavidch struct { 1836255736Sdavidch uint32_t num; /* return number of stats */ 1837255736Sdavidch uint32_t len; /* length of each string item */ 1838255736Sdavidch } desc; 1839255736Sdavidch 1840255736Sdavidch /* variable length... */ 1841255736Sdavidch char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1842255736Sdavidch 1843255736Sdavidch /* variable length... */ 1844255736Sdavidch uint64_t stats[1]; /* holds all stats */ 1845255736Sdavidch}; 1846255736Sdavidch 1847255736Sdavidch/* function init flags */ 1848255736Sdavidch#define FUNC_FLG_RSS 0x0001 1849255736Sdavidch#define FUNC_FLG_STATS 0x0002 1850255736Sdavidch/* FUNC_FLG_UNMATCHED 0x0004 */ 1851255736Sdavidch#define FUNC_FLG_TPA 0x0008 1852255736Sdavidch#define FUNC_FLG_SPQ 0x0010 1853255736Sdavidch#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1854255736Sdavidch 1855255736Sdavidchstruct bxe_func_init_params { 1856255736Sdavidch bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1857255736Sdavidch bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1858255736Sdavidch uint16_t func_flgs; 1859255736Sdavidch uint16_t func_id; /* abs function id */ 1860255736Sdavidch uint16_t pf_id; 1861255736Sdavidch uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1862255736Sdavidch}; 1863255736Sdavidch 1864255736Sdavidch/* memory resources reside at BARs 0, 2, 4 */ 1865255736Sdavidch/* Run `pciconf -lb` to see mappings */ 1866255736Sdavidch#define BAR0 0 1867255736Sdavidch#define BAR1 2 1868255736Sdavidch#define BAR2 4 1869255736Sdavidch 1870255736Sdavidch#ifdef BXE_REG_NO_INLINE 1871255736Sdavidch 1872255736Sdavidchuint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1873255736Sdavidchuint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1874255736Sdavidchuint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1875255736Sdavidch 1876255736Sdavidchvoid bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1877255736Sdavidchvoid bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1878255736Sdavidchvoid bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1879255736Sdavidch 1880255736Sdavidch#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1881255736Sdavidch#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1882255736Sdavidch#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1883255736Sdavidch 1884255736Sdavidch#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1885255736Sdavidch#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1886255736Sdavidch#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1887255736Sdavidch 1888255736Sdavidch#else /* not BXE_REG_NO_INLINE */ 1889255736Sdavidch 1890255736Sdavidch#define REG_WR8(sc, offset, val) \ 1891255736Sdavidch bus_space_write_1(sc->bar[BAR0].tag, \ 1892255736Sdavidch sc->bar[BAR0].handle, \ 1893255736Sdavidch offset, val) 1894255736Sdavidch 1895255736Sdavidch#define REG_WR16(sc, offset, val) \ 1896255736Sdavidch bus_space_write_2(sc->bar[BAR0].tag, \ 1897255736Sdavidch sc->bar[BAR0].handle, \ 1898255736Sdavidch offset, val) 1899255736Sdavidch 1900255736Sdavidch#define REG_WR32(sc, offset, val) \ 1901255736Sdavidch bus_space_write_4(sc->bar[BAR0].tag, \ 1902255736Sdavidch sc->bar[BAR0].handle, \ 1903255736Sdavidch offset, val) 1904255736Sdavidch 1905255736Sdavidch#define REG_RD8(sc, offset) \ 1906255736Sdavidch bus_space_read_1(sc->bar[BAR0].tag, \ 1907255736Sdavidch sc->bar[BAR0].handle, \ 1908255736Sdavidch offset) 1909255736Sdavidch 1910255736Sdavidch#define REG_RD16(sc, offset) \ 1911255736Sdavidch bus_space_read_2(sc->bar[BAR0].tag, \ 1912255736Sdavidch sc->bar[BAR0].handle, \ 1913255736Sdavidch offset) 1914255736Sdavidch 1915255736Sdavidch#define REG_RD32(sc, offset) \ 1916255736Sdavidch bus_space_read_4(sc->bar[BAR0].tag, \ 1917255736Sdavidch sc->bar[BAR0].handle, \ 1918255736Sdavidch offset) 1919255736Sdavidch 1920255736Sdavidch#endif /* BXE_REG_NO_INLINE */ 1921255736Sdavidch 1922255736Sdavidch#define REG_RD(sc, offset) REG_RD32(sc, offset) 1923255736Sdavidch#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1924255736Sdavidch 1925255736Sdavidch#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1926255736Sdavidch#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1927255736Sdavidch 1928255736Sdavidch#define BXE_SP(sc, var) (&(sc)->sp->var) 1929255736Sdavidch#define BXE_SP_MAPPING(sc, var) \ 1930255736Sdavidch (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1931255736Sdavidch 1932255736Sdavidch#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1933255736Sdavidch#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1934255736Sdavidch 1935255736Sdavidch#define REG_RD_DMAE(sc, offset, valp, len32) \ 1936255736Sdavidch do { \ 1937255736Sdavidch bxe_read_dmae(sc, offset, len32); \ 1938255736Sdavidch memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1939255736Sdavidch } while (0) 1940255736Sdavidch 1941255736Sdavidch#define REG_WR_DMAE(sc, offset, valp, len32) \ 1942255736Sdavidch do { \ 1943255736Sdavidch memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1944255736Sdavidch bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1945255736Sdavidch } while (0) 1946255736Sdavidch 1947255736Sdavidch#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1948255736Sdavidch REG_WR_DMAE(sc, offset, valp, len32) 1949255736Sdavidch 1950255736Sdavidch#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1951255736Sdavidch REG_RD_DMAE(sc, offset, valp, len32) 1952255736Sdavidch 1953255736Sdavidch#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1954255736Sdavidch do { \ 1955255736Sdavidch /* if (le32_swap) { */ \ 1956255736Sdavidch /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1957255736Sdavidch /* } */ \ 1958255736Sdavidch memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1959255736Sdavidch ecore_write_big_buf_wb(sc, addr, len32); \ 1960255736Sdavidch } while (0) 1961255736Sdavidch 1962255736Sdavidch#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1963255736Sdavidch#define BXE_DB_SHIFT 7 /* 128 bytes */ 1964255736Sdavidch#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1965255736Sdavidch#error "Minimum DB doorbell stride is 8" 1966255736Sdavidch#endif 1967255736Sdavidch#define DPM_TRIGGER_TYPE 0x40 1968255736Sdavidch#define DOORBELL(sc, cid, val) \ 1969255736Sdavidch do { \ 1970255736Sdavidch bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1971255736Sdavidch ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1972255736Sdavidch (uint32_t)val); \ 1973255736Sdavidch } while(0) 1974255736Sdavidch 1975255736Sdavidch#define SHMEM_ADDR(sc, field) \ 1976255736Sdavidch (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1977255736Sdavidch#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1978255736Sdavidch#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1979255736Sdavidch#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1980255736Sdavidch 1981255736Sdavidch#define SHMEM2_ADDR(sc, field) \ 1982255736Sdavidch (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1983255736Sdavidch#define SHMEM2_HAS(sc, field) \ 1984255736Sdavidch (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1985255736Sdavidch offsetof(struct shmem2_region, field))) 1986255736Sdavidch#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1987255736Sdavidch#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1988255736Sdavidch 1989255736Sdavidch#define MFCFG_ADDR(sc, field) \ 1990255736Sdavidch (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1991255736Sdavidch#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1992255736Sdavidch#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1993255736Sdavidch#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1994255736Sdavidch 1995255736Sdavidch/* DMAE command defines */ 1996255736Sdavidch 1997255736Sdavidch#define DMAE_TIMEOUT -1 1998255736Sdavidch#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1999255736Sdavidch#define DMAE_NOT_RDY -3 2000255736Sdavidch#define DMAE_PCI_ERR_FLAG 0x80000000 2001255736Sdavidch 2002255736Sdavidch#define DMAE_SRC_PCI 0 2003255736Sdavidch#define DMAE_SRC_GRC 1 2004255736Sdavidch 2005255736Sdavidch#define DMAE_DST_NONE 0 2006255736Sdavidch#define DMAE_DST_PCI 1 2007255736Sdavidch#define DMAE_DST_GRC 2 2008255736Sdavidch 2009255736Sdavidch#define DMAE_COMP_PCI 0 2010255736Sdavidch#define DMAE_COMP_GRC 1 2011255736Sdavidch 2012255736Sdavidch#define DMAE_COMP_REGULAR 0 2013255736Sdavidch#define DMAE_COM_SET_ERR 1 2014255736Sdavidch 2015296071Sdavidcs#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 2016296071Sdavidcs#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 2017296071Sdavidcs#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 2018296071Sdavidcs#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 2019255736Sdavidch 2020296071Sdavidcs#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 2021296071Sdavidcs#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 2022255736Sdavidch 2023296071Sdavidcs#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 2024296071Sdavidcs#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 2025296071Sdavidcs#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 2026296071Sdavidcs#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 2027255736Sdavidch 2028255736Sdavidch#define DMAE_CMD_PORT_0 0 2029296071Sdavidcs#define DMAE_CMD_PORT_1 DMAE_CMD_PORT 2030255736Sdavidch 2031255736Sdavidch#define DMAE_SRC_PF 0 2032255736Sdavidch#define DMAE_SRC_VF 1 2033255736Sdavidch 2034255736Sdavidch#define DMAE_DST_PF 0 2035255736Sdavidch#define DMAE_DST_VF 1 2036255736Sdavidch 2037255736Sdavidch#define DMAE_C_SRC 0 2038255736Sdavidch#define DMAE_C_DST 1 2039255736Sdavidch 2040255736Sdavidch#define DMAE_LEN32_RD_MAX 0x80 2041255736Sdavidch#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2042255736Sdavidch 2043255736Sdavidch#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2044255736Sdavidch 2045255736Sdavidch#define MAX_DMAE_C_PER_PORT 8 2046255736Sdavidch#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2047255736Sdavidch#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2048255736Sdavidch 2049255736Sdavidchstatic const uint32_t dmae_reg_go_c[] = { 2050255736Sdavidch DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2051255736Sdavidch DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2052255736Sdavidch DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2053255736Sdavidch DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2054255736Sdavidch}; 2055255736Sdavidch 2056255736Sdavidch#define ATTN_NIG_FOR_FUNC (1L << 8) 2057255736Sdavidch#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2058255736Sdavidch#define GPIO_2_FUNC (1L << 10) 2059255736Sdavidch#define GPIO_3_FUNC (1L << 11) 2060255736Sdavidch#define GPIO_4_FUNC (1L << 12) 2061255736Sdavidch#define ATTN_GENERAL_ATTN_1 (1L << 13) 2062255736Sdavidch#define ATTN_GENERAL_ATTN_2 (1L << 14) 2063255736Sdavidch#define ATTN_GENERAL_ATTN_3 (1L << 15) 2064255736Sdavidch#define ATTN_GENERAL_ATTN_4 (1L << 13) 2065255736Sdavidch#define ATTN_GENERAL_ATTN_5 (1L << 14) 2066255736Sdavidch#define ATTN_GENERAL_ATTN_6 (1L << 15) 2067255736Sdavidch#define ATTN_HARD_WIRED_MASK 0xff00 2068255736Sdavidch#define ATTENTION_ID 4 2069255736Sdavidch 2070255736Sdavidch#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2071255736Sdavidch AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2072255736Sdavidch 2073255736Sdavidch#define MAX_IGU_ATTN_ACK_TO 100 2074255736Sdavidch 2075255736Sdavidch#define STORM_ASSERT_ARRAY_SIZE 50 2076255736Sdavidch 2077255736Sdavidch#define BXE_PMF_LINK_ASSERT(sc) \ 2078255736Sdavidch GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2079255736Sdavidch 2080255736Sdavidch#define BXE_MC_ASSERT_BITS \ 2081255736Sdavidch (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2082255736Sdavidch GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2083255736Sdavidch GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2084255736Sdavidch GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2085255736Sdavidch 2086255736Sdavidch#define BXE_MCP_ASSERT \ 2087255736Sdavidch GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2088255736Sdavidch 2089255736Sdavidch#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2090255736Sdavidch#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2091255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2092255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2093255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2094255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2095255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2096255736Sdavidch 2097255736Sdavidch#define MULTI_MASK 0x7f 2098255736Sdavidch 2099255736Sdavidch#define PFS_PER_PORT(sc) \ 2100255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2101255736Sdavidch#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2102255736Sdavidch 2103255736Sdavidch#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2104255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2105255736Sdavidch PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2106255736Sdavidch 2107255736Sdavidch#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2108255736Sdavidch for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2109255736Sdavidch (i) < MAX_FUNC_NUM; \ 2110255736Sdavidch (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2111255736Sdavidch 2112255736Sdavidch#define BXE_SWCID_SHIFT 17 2113255736Sdavidch#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2114255736Sdavidch 2115255736Sdavidch#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2116255736Sdavidch#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2117255736Sdavidch 2118255736Sdavidch#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2119255736Sdavidch#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2120255736Sdavidch#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2121255736Sdavidch#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2122255736Sdavidch#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2123255736Sdavidch 2124255736Sdavidch/* must be used on a CID before placing it on a HW ring */ 2125255736Sdavidch#define HW_CID(sc, x) \ 2126255736Sdavidch ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2127255736Sdavidch 2128255736Sdavidch#define SPEED_10 10 2129255736Sdavidch#define SPEED_100 100 2130255736Sdavidch#define SPEED_1000 1000 2131255736Sdavidch#define SPEED_2500 2500 2132255736Sdavidch#define SPEED_10000 10000 2133255736Sdavidch 2134255736Sdavidch#define PCI_PM_D0 1 2135255736Sdavidch#define PCI_PM_D3hot 2 2136255736Sdavidch 2137297884Sdavidcs#ifndef DUPLEX_UNKNOWN 2138297884Sdavidcs#define DUPLEX_UNKNOWN (0xff) 2139297884Sdavidcs#endif 2140297884Sdavidcs 2141297884Sdavidcs#ifndef SPEED_UNKNOWN 2142297884Sdavidcs#define SPEED_UNKNOWN (-1) 2143297884Sdavidcs#endif 2144297884Sdavidcs 2145297884Sdavidcs/* Enable or disable autonegotiation. */ 2146297884Sdavidcs#define AUTONEG_DISABLE 0x00 2147297884Sdavidcs#define AUTONEG_ENABLE 0x01 2148297884Sdavidcs 2149297884Sdavidcs/* Which connector port. */ 2150297884Sdavidcs#define PORT_TP 0x00 2151297884Sdavidcs#define PORT_AUI 0x01 2152297884Sdavidcs#define PORT_MII 0x02 2153297884Sdavidcs#define PORT_FIBRE 0x03 2154297884Sdavidcs#define PORT_BNC 0x04 2155297884Sdavidcs#define PORT_DA 0x05 2156297884Sdavidcs#define PORT_NONE 0xef 2157297884Sdavidcs#define PORT_OTHER 0xff 2158297884Sdavidcs 2159255736Sdavidchint bxe_test_bit(int nr, volatile unsigned long * addr); 2160255736Sdavidchvoid bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2161255736Sdavidchvoid bxe_clear_bit(int nr, volatile unsigned long * addr); 2162255736Sdavidchint bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2163255736Sdavidchint bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2164255736Sdavidchint bxe_cmpxchg(volatile int *addr, int old, int new); 2165255736Sdavidch 2166255736Sdavidchvoid bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2167255736Sdavidch uint32_t val); 2168255736Sdavidchuint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2169255736Sdavidch 2170255736Sdavidch 2171255736Sdavidchint bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2172255736Sdavidch struct bxe_dma *dma, const char *msg); 2173255736Sdavidchvoid bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2174255736Sdavidch 2175255736Sdavidchuint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2176255736Sdavidchuint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2177255736Sdavidchuint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2178255736Sdavidch uint8_t dst_type, uint8_t with_comp, 2179255736Sdavidch uint8_t comp_type); 2180296071Sdavidcsvoid bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2181255736Sdavidchvoid bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2182255736Sdavidchvoid bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2183255736Sdavidch uint32_t dst_addr, uint32_t len32); 2184255736Sdavidchvoid bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2185255736Sdavidch uint32_t addr, uint32_t len); 2186255736Sdavidch 2187255736Sdavidchvoid bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2188255736Sdavidch uint32_t cid); 2189255736Sdavidchvoid bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2190255736Sdavidch uint8_t sb_index, uint8_t disable, 2191255736Sdavidch uint16_t usec); 2192255736Sdavidch 2193255736Sdavidchint bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2194255736Sdavidch uint32_t data_hi, uint32_t data_lo, int cmd_type); 2195255736Sdavidch 2196255736Sdavidchvoid bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2197255736Sdavidch uint8_t segment, uint16_t index, uint8_t op, 2198255736Sdavidch uint8_t update); 2199255736Sdavidch 2200255736Sdavidchvoid ecore_init_e1_firmware(struct bxe_softc *sc); 2201255736Sdavidchvoid ecore_init_e1h_firmware(struct bxe_softc *sc); 2202255736Sdavidchvoid ecore_init_e2_firmware(struct bxe_softc *sc); 2203255736Sdavidch 2204255736Sdavidchvoid ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2205255736Sdavidch size_t size, uint32_t *data); 2206255736Sdavidch 2207255736Sdavidch/*********************/ 2208255736Sdavidch/* LOGGING AND DEBUG */ 2209255736Sdavidch/*********************/ 2210255736Sdavidch 2211255736Sdavidch/* debug logging codepaths */ 2212255736Sdavidch#define DBG_LOAD 0x00000001 /* load and unload */ 2213255736Sdavidch#define DBG_INTR 0x00000002 /* interrupt handling */ 2214255736Sdavidch#define DBG_SP 0x00000004 /* slowpath handling */ 2215255736Sdavidch#define DBG_STATS 0x00000008 /* stats updates */ 2216255736Sdavidch#define DBG_TX 0x00000010 /* packet transmit */ 2217255736Sdavidch#define DBG_RX 0x00000020 /* packet receive */ 2218255736Sdavidch#define DBG_PHY 0x00000040 /* phy/link handling */ 2219255736Sdavidch#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2220255736Sdavidch#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2221255736Sdavidch#define DBG_REGS 0x00000200 /* register access */ 2222255736Sdavidch#define DBG_LRO 0x00000400 /* lro processing */ 2223255736Sdavidch#define DBG_ASSERT 0x80000000 /* debug assert */ 2224255736Sdavidch#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2225255736Sdavidch 2226255736Sdavidch#define DBASSERT(sc, exp, msg) \ 2227255736Sdavidch do { \ 2228255736Sdavidch if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2229255736Sdavidch if (__predict_false(!(exp))) { \ 2230255736Sdavidch panic msg; \ 2231255736Sdavidch } \ 2232255736Sdavidch } \ 2233255736Sdavidch } while (0) 2234255736Sdavidch 2235255736Sdavidch/* log a debug message */ 2236255736Sdavidch#define BLOGD(sc, codepath, format, args...) \ 2237255736Sdavidch do { \ 2238255736Sdavidch if (__predict_false(sc->debug & (codepath))) { \ 2239255736Sdavidch device_printf((sc)->dev, \ 2240255736Sdavidch "%s(%s:%d) " format, \ 2241255736Sdavidch __FUNCTION__, \ 2242255736Sdavidch __FILE__, \ 2243255736Sdavidch __LINE__, \ 2244255736Sdavidch ## args); \ 2245255736Sdavidch } \ 2246255736Sdavidch } while(0) 2247255736Sdavidch 2248255736Sdavidch/* log a info message */ 2249255736Sdavidch#define BLOGI(sc, format, args...) \ 2250255736Sdavidch do { \ 2251255736Sdavidch if (__predict_false(sc->debug)) { \ 2252255736Sdavidch device_printf((sc)->dev, \ 2253255736Sdavidch "%s(%s:%d) " format, \ 2254255736Sdavidch __FUNCTION__, \ 2255255736Sdavidch __FILE__, \ 2256255736Sdavidch __LINE__, \ 2257255736Sdavidch ## args); \ 2258255736Sdavidch } else { \ 2259255736Sdavidch device_printf((sc)->dev, \ 2260255736Sdavidch format, \ 2261255736Sdavidch ## args); \ 2262255736Sdavidch } \ 2263255736Sdavidch } while(0) 2264255736Sdavidch 2265255736Sdavidch/* log a warning message */ 2266255736Sdavidch#define BLOGW(sc, format, args...) \ 2267255736Sdavidch do { \ 2268255736Sdavidch if (__predict_false(sc->debug)) { \ 2269255736Sdavidch device_printf((sc)->dev, \ 2270255736Sdavidch "%s(%s:%d) WARNING: " format, \ 2271255736Sdavidch __FUNCTION__, \ 2272255736Sdavidch __FILE__, \ 2273255736Sdavidch __LINE__, \ 2274255736Sdavidch ## args); \ 2275255736Sdavidch } else { \ 2276255736Sdavidch device_printf((sc)->dev, \ 2277255736Sdavidch "WARNING: " format, \ 2278255736Sdavidch ## args); \ 2279255736Sdavidch } \ 2280255736Sdavidch } while(0) 2281255736Sdavidch 2282255736Sdavidch/* log a error message */ 2283255736Sdavidch#define BLOGE(sc, format, args...) \ 2284255736Sdavidch do { \ 2285255736Sdavidch if (__predict_false(sc->debug)) { \ 2286255736Sdavidch device_printf((sc)->dev, \ 2287255736Sdavidch "%s(%s:%d) ERROR: " format, \ 2288255736Sdavidch __FUNCTION__, \ 2289255736Sdavidch __FILE__, \ 2290255736Sdavidch __LINE__, \ 2291255736Sdavidch ## args); \ 2292255736Sdavidch } else { \ 2293255736Sdavidch device_printf((sc)->dev, \ 2294255736Sdavidch "ERROR: " format, \ 2295255736Sdavidch ## args); \ 2296255736Sdavidch } \ 2297255736Sdavidch } while(0) 2298255736Sdavidch 2299268854Sdavidcs#ifdef ECORE_STOP_ON_ERROR 2300268854Sdavidcs 2301255736Sdavidch#define bxe_panic(sc, msg) \ 2302255736Sdavidch do { \ 2303255736Sdavidch panic msg; \ 2304255736Sdavidch } while (0) 2305255736Sdavidch 2306268854Sdavidcs#else 2307268854Sdavidcs 2308268854Sdavidcs#define bxe_panic(sc, msg) \ 2309268854Sdavidcs device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2310268854Sdavidcs 2311268854Sdavidcs#endif 2312268854Sdavidcs 2313255736Sdavidch#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2314255736Sdavidch#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2315255736Sdavidch 2316255736Sdavidchvoid bxe_dump_mem(struct bxe_softc *sc, char *tag, 2317255736Sdavidch uint8_t *mem, uint32_t len); 2318255736Sdavidchvoid bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2319255736Sdavidch struct mbuf *m, uint8_t contents); 2320255736Sdavidch 2321297155Sdavidcs#if __FreeBSD_version >= 800000 2322307972Sdavidcs#if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) ||\ 2323307972Sdavidcs __FreeBSD_version >= 1100048 2324297155Sdavidcs#define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2325297155Sdavidcs#define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2326297155Sdavidcs#else 2327297155Sdavidcs#define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0) 2328297155Sdavidcs#define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID 2329297155Sdavidcs#endif 2330297155Sdavidcs#endif /* #if __FreeBSD_version >= 800000 */ 2331297155Sdavidcs 2332255736Sdavidch/***********/ 2333255736Sdavidch/* INLINES */ 2334255736Sdavidch/***********/ 2335255736Sdavidch 2336255736Sdavidchstatic inline uint32_t 2337255736Sdavidchreg_poll(struct bxe_softc *sc, 2338255736Sdavidch uint32_t reg, 2339255736Sdavidch uint32_t expected, 2340255736Sdavidch int ms, 2341255736Sdavidch int wait) 2342255736Sdavidch{ 2343255736Sdavidch uint32_t val; 2344255736Sdavidch 2345255736Sdavidch do { 2346255736Sdavidch val = REG_RD(sc, reg); 2347255736Sdavidch if (val == expected) { 2348255736Sdavidch break; 2349255736Sdavidch } 2350255736Sdavidch ms -= wait; 2351255736Sdavidch DELAY(wait * 1000); 2352255736Sdavidch } while (ms > 0); 2353255736Sdavidch 2354255736Sdavidch return (val); 2355255736Sdavidch} 2356255736Sdavidch 2357255736Sdavidchstatic inline void 2358255736Sdavidchbxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2359255736Sdavidch{ 2360255736Sdavidch mb(); /* status block is written to by the chip */ 2361255736Sdavidch fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2362255736Sdavidch} 2363255736Sdavidch 2364255736Sdavidchstatic inline void 2365255736Sdavidchbxe_igu_ack_sb_gen(struct bxe_softc *sc, 2366255736Sdavidch uint8_t igu_sb_id, 2367255736Sdavidch uint8_t segment, 2368255736Sdavidch uint16_t index, 2369255736Sdavidch uint8_t op, 2370255736Sdavidch uint8_t update, 2371255736Sdavidch uint32_t igu_addr) 2372255736Sdavidch{ 2373255736Sdavidch struct igu_regular cmd_data = {0}; 2374255736Sdavidch 2375255736Sdavidch cmd_data.sb_id_and_flags = 2376255736Sdavidch ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2377255736Sdavidch (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2378255736Sdavidch (update << IGU_REGULAR_BUPDATE_SHIFT) | 2379255736Sdavidch (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2380255736Sdavidch 2381255736Sdavidch BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2382255736Sdavidch cmd_data.sb_id_and_flags, igu_addr); 2383255736Sdavidch REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2384255736Sdavidch 2385255736Sdavidch /* Make sure that ACK is written */ 2386255736Sdavidch bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2387255736Sdavidch BUS_SPACE_BARRIER_WRITE); 2388255736Sdavidch mb(); 2389255736Sdavidch} 2390255736Sdavidch 2391255736Sdavidchstatic inline void 2392255736Sdavidchbxe_hc_ack_sb(struct bxe_softc *sc, 2393255736Sdavidch uint8_t sb_id, 2394255736Sdavidch uint8_t storm, 2395255736Sdavidch uint16_t index, 2396255736Sdavidch uint8_t op, 2397255736Sdavidch uint8_t update) 2398255736Sdavidch{ 2399255736Sdavidch uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2400255736Sdavidch COMMAND_REG_INT_ACK); 2401255736Sdavidch struct igu_ack_register igu_ack; 2402255736Sdavidch 2403255736Sdavidch igu_ack.status_block_index = index; 2404255736Sdavidch igu_ack.sb_id_and_flags = 2405255736Sdavidch ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2406255736Sdavidch (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2407255736Sdavidch (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2408255736Sdavidch (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2409255736Sdavidch 2410255736Sdavidch REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2411255736Sdavidch 2412255736Sdavidch /* Make sure that ACK is written */ 2413255736Sdavidch bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2414255736Sdavidch BUS_SPACE_BARRIER_WRITE); 2415255736Sdavidch mb(); 2416255736Sdavidch} 2417255736Sdavidch 2418255736Sdavidchstatic inline void 2419255736Sdavidchbxe_ack_sb(struct bxe_softc *sc, 2420255736Sdavidch uint8_t igu_sb_id, 2421255736Sdavidch uint8_t storm, 2422255736Sdavidch uint16_t index, 2423255736Sdavidch uint8_t op, 2424255736Sdavidch uint8_t update) 2425255736Sdavidch{ 2426255736Sdavidch if (sc->devinfo.int_block == INT_BLOCK_HC) 2427255736Sdavidch bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2428255736Sdavidch else { 2429255736Sdavidch uint8_t segment; 2430255736Sdavidch if (CHIP_INT_MODE_IS_BC(sc)) { 2431255736Sdavidch segment = storm; 2432255736Sdavidch } else if (igu_sb_id != sc->igu_dsb_id) { 2433255736Sdavidch segment = IGU_SEG_ACCESS_DEF; 2434255736Sdavidch } else if (storm == ATTENTION_ID) { 2435255736Sdavidch segment = IGU_SEG_ACCESS_ATTN; 2436255736Sdavidch } else { 2437255736Sdavidch segment = IGU_SEG_ACCESS_DEF; 2438255736Sdavidch } 2439255736Sdavidch bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2440255736Sdavidch } 2441255736Sdavidch} 2442255736Sdavidch 2443255736Sdavidchstatic inline uint16_t 2444255736Sdavidchbxe_hc_ack_int(struct bxe_softc *sc) 2445255736Sdavidch{ 2446255736Sdavidch uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2447255736Sdavidch COMMAND_REG_SIMD_MASK); 2448255736Sdavidch uint32_t result = REG_RD(sc, hc_addr); 2449255736Sdavidch 2450255736Sdavidch mb(); 2451255736Sdavidch return (result); 2452255736Sdavidch} 2453255736Sdavidch 2454255736Sdavidchstatic inline uint16_t 2455255736Sdavidchbxe_igu_ack_int(struct bxe_softc *sc) 2456255736Sdavidch{ 2457255736Sdavidch uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2458255736Sdavidch uint32_t result = REG_RD(sc, igu_addr); 2459255736Sdavidch 2460255736Sdavidch BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2461255736Sdavidch result, igu_addr); 2462255736Sdavidch 2463255736Sdavidch mb(); 2464255736Sdavidch return (result); 2465255736Sdavidch} 2466255736Sdavidch 2467255736Sdavidchstatic inline uint16_t 2468255736Sdavidchbxe_ack_int(struct bxe_softc *sc) 2469255736Sdavidch{ 2470255736Sdavidch mb(); 2471255736Sdavidch if (sc->devinfo.int_block == INT_BLOCK_HC) { 2472255736Sdavidch return (bxe_hc_ack_int(sc)); 2473255736Sdavidch } else { 2474255736Sdavidch return (bxe_igu_ack_int(sc)); 2475255736Sdavidch } 2476255736Sdavidch} 2477255736Sdavidch 2478255736Sdavidchstatic inline int 2479255736Sdavidchfunc_by_vn(struct bxe_softc *sc, 2480255736Sdavidch int vn) 2481255736Sdavidch{ 2482255736Sdavidch return (2 * vn + SC_PORT(sc)); 2483255736Sdavidch} 2484255736Sdavidch 2485255736Sdavidch/* 2486255736Sdavidch * Statistics ID are global per chip/path, while Client IDs for E1x 2487255736Sdavidch * are per port. 2488255736Sdavidch */ 2489255736Sdavidchstatic inline uint8_t 2490255736Sdavidchbxe_stats_id(struct bxe_fastpath *fp) 2491255736Sdavidch{ 2492255736Sdavidch struct bxe_softc *sc = fp->sc; 2493255736Sdavidch 2494255736Sdavidch if (!CHIP_IS_E1x(sc)) { 2495255736Sdavidch return (fp->cl_id); 2496255736Sdavidch } 2497255736Sdavidch 2498255736Sdavidch return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2499255736Sdavidch} 2500255736Sdavidch 2501255736Sdavidch#endif /* __BXE_H__ */ 2502255736Sdavidch 2503