Searched refs:REG_RD (Results 1 - 14 of 14) sorted by relevance

/freebsd-11-stable/sys/dev/bxe/
H A Dbxe.c1038 lock_status = REG_RD(sc, hw_lock_control_reg);
1048 lock_status = REG_RD(sc, hw_lock_control_reg);
1084 lock_status = REG_RD(sc, hw_lock_control_reg);
1140 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1176 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1202 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1214 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1255 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1258 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1370 val = REG_RD(s
[all...]
H A Decore_init.h251 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);
278 reg_bit_map = REG_RD(sc, reg_addr);
283 reg_bit_map = REG_RD(sc, reg_addr);
290 reg_bit_map = REG_RD(sc, reg_addr);
750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);
815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i].
826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);
H A Dbxe_elink.c953 uint32_t val = REG_RD(sc, reg);
962 uint32_t val = REG_RD(sc, reg);
985 REG_RD(sc, params->lfa_base +
1000 link_status = REG_RD(sc, params->shmem_base +
1029 saved_val = REG_RD(sc, params->lfa_base +
1038 saved_val = REG_RD(sc, params->lfa_base +
1047 saved_val = REG_RD(sc, params->lfa_base +
1057 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1070 REG_RD(sc, params->lfa_base +
1080 eee_status = REG_RD(s
[all...]
H A Decore_init_ops.h281 REG_RD(sc, addr);
547 val = REG_RD(sc, write_arb_addr[i].l);
551 val = REG_RD(sc, write_arb_addr[i].add);
555 val = REG_RD(sc, write_arb_addr[i].ubound);
616 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
H A Dbxe.h1922 #define REG_RD(sc, offset) REG_RD32(sc, offset) macro
1977 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1984 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1986 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1991 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
2346 val = REG_RD(sc, reg);
2448 uint32_t result = REG_RD(sc, hc_addr);
2458 uint32_t result = REG_RD(sc, igu_addr);
H A Dbxe_stats.c918 estats->eee_tx_lpi += REG_RD(sc, lpi_reg);
1625 REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1627 REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
/freebsd-11-stable/sys/dev/bce/
H A Dif_bce.c1186 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
1289 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1295 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1645 u32 val = REG_RD(sc, offset);
1801 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1812 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1815 val = REG_RD(sc, BCE_CTX_DATA);
1854 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1900 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1904 REG_RD(s
[all...]
H A Dif_bcereg.h1089 #define REG_RD(sc, offset) bce_reg_rd(sc, offset) macro
1095 #define REG_RD(sc, offset) \ macro
1105 REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1107 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Decore_hw.c266 is_empty = REG_RD(p_hwfn, bar_addr) == 0;
309 val = REG_RD(p_hwfn, bar_addr);
H A Dbcm_osal.h225 #define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr) macro
H A Decore_vf.c535 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
538 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
H A Decore_dev.c2725 if (REG_RD(p_hwfn, addr)) {
2738 while (!REG_RD(p_hwfn, addr) && count--)
2741 if (REG_RD(p_hwfn, addr))
4528 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
4531 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
5866 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
H A Decore_int.c2537 intr_status_lo = REG_RD(p_hwfn,
2540 intr_status_hi = REG_RD(p_hwfn,
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp666 #define REG_RD 0 macro

Completed in 844 milliseconds