Lines Matching refs:REG_RD
1038 lock_status = REG_RD(sc, hw_lock_control_reg);
1048 lock_status = REG_RD(sc, hw_lock_control_reg);
1084 lock_status = REG_RD(sc, hw_lock_control_reg);
1140 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1176 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1202 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1214 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1255 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1258 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1370 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1652 REG_RD(sc, (src_addr + (i * 4)));
1820 return (REG_RD(sc, reg_addr));
1880 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1919 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1920 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1934 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1947 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1948 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1964 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2015 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2059 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2060 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2076 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
4160 val = REG_RD(sc, addr);
4164 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
6668 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6679 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6688 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6703 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6721 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6734 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6751 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6776 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6808 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6888 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
6984 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
7127 aeu_mask = REG_RD(sc, aeu_addr);
7149 nig_mask = REG_RD(sc, nig_int_mask_addr);
7227 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7593 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7594 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7595 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7596 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7602 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
7609 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7622 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7646 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7886 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
7887 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
7888 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
7889 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
7909 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
7910 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
7911 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
7912 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
7932 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
7933 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
7934 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
7935 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
7955 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
7956 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
7957 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
7958 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
8053 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8057 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8075 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8085 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8094 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8108 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8109 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8110 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8111 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8122 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8150 val = REG_RD(sc, reg_offset);
8177 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8190 val = REG_RD(sc, reg_offset);
8219 val = REG_RD(sc, reg_offset);
8237 val = REG_RD(sc, reg_offset);
8285 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8286 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8287 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8288 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8290 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8340 aeu_mask = REG_RD(sc, reg_addr);
9873 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9883 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
10287 uint32_t val = REG_RD(sc, addr);
10363 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10433 uint32_t val = REG_RD(sc, addr);
10463 if (REG_RD(sc, addr) != val) {
10471 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10483 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10539 REG_RD(sc,
10719 lock_status = REG_RD(sc, hw_lock_control_reg);
10776 val = REG_RD(sc, HC_REG_CONFIG_1);
10781 val = REG_RD(sc, HC_REG_CONFIG_0);
10787 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
10809 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
10863 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10897 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
11059 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11060 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11061 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11062 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11063 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11065 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
13201 val = REG_RD(sc, BAR_ME_REGISTER);
13298 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
14013 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
14069 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
14070 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
14071 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
14072 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
14075 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
14094 val = (REG_RD(sc, 0x2874) & 0x55);
14113 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
14117 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
14132 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
14134 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
14195 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
14231 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
14242 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14247 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14344 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14349 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14353 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
15350 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15535 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15538 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15553 wb_data[0] = REG_RD(sc, base_addr + offset);
15554 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15565 vals->emac_val = REG_RD(sc, vals->emac_addr);
15572 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15576 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15586 vals->umac_val = REG_RD(sc, vals->umac_addr);
15608 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15643 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15658 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15665 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15670 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15674 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15789 hw_lock_val = (REG_RD(sc, hw_lock_reg));
15802 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
16665 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16669 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16740 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16798 REG_RD(sc, pretend_reg);
16886 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16941 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16953 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16960 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
16963 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
17028 val = REG_RD(sc, MISC_REG_SPIO_INT);
17033 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17204 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
17210 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
17333 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17576 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17823 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17827 val = REG_RD(sc, reg_addr);
17844 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17954 if (REG_RD(sc, comp_addr)) {
17970 (REG_RD(sc, comp_addr)));
17989 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
17990 crd = crd_start = REG_RD(sc, regs->crd);
17991 init_crd = REG_RD(sc, regs->init_crd);
18002 crd = REG_RD(sc, regs->crd);
18003 crd_freed = REG_RD(sc, regs->crd_freed);
18024 occup = to_free = REG_RD(sc, regs->lines_occup);
18025 freed = freed_start = REG_RD(sc, regs->lines_freed);
18034 occup = REG_RD(sc, regs->lines_occup);
18035 freed = REG_RD(sc, regs->lines_freed);
18120 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
18123 val = REG_RD(sc, PBF_REG_DISABLE_PF);
18126 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
18129 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
18132 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
18135 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
18138 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
18141 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
18221 val = REG_RD(sc, addr);
18462 val = REG_RD(sc, main_mem_prty_clr);
18478 REG_RD(sc, main_mem_prty_clr);
18536 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18623 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18937 *p++ = REG_RD(sc, addr);
18971 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);
18980 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4);
18988 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4);
18995 *p++ = REG_RD(sc, addr + j*4);
19184 reg_val = REG_RD(sc, reg_addr);
19488 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);