| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dimgrey_cavefish_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| H A D | aldebaran_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| H A D | vega20_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
49 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| H A D | vega10_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 51 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, variable in typeref:struct:IP_BASE
70 (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/include/ |
| H A D | cyan_skillfish_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | navi10_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega20_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | yellow_carp_offset.h | 131 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, variable in typeref:struct:IP_BASE
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| H A D | vega10_ip_offset.h | 41 static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, variable in typeref:struct:__maybe_unused
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| H A D | sienna_cichlid_ip_offset.h | 128 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, variable in typeref:struct:IP_BASE
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| H A D | beige_goby_ip_offset.h | 136 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, variable in typeref:struct:IP_BASE
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| H A D | dimgrey_cavefish_ip_offset.h | 121 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, variable in typeref:struct:IP_BASE
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| H A D | dce120_resource.c | 129 #define NBIO_BASE(seg) \ macro
493 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
494 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 282 #define NBIO_BASE(seg) \ macro
286 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 136 #define NBIO_BASE(seg) \ macro
140 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 164 #define NBIO_BASE(seg) \ macro
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 160 #define NBIO_BASE(seg) \ macro
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 202 #define NBIO_BASE(seg) \ macro
206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 185 #define NBIO_BASE(seg) \ macro
189 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
192 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 186 #define NBIO_BASE(seg) \ macro
190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 182 #define NBIO_BASE(seg) \ macro
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
190 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 129 #define NBIO_BASE(seg) \ macro
133 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 188 #define NBIO_BASE(seg) \ macro
192 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 204 #define NBIO_BASE(seg) \ macro
208 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
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